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ADS1119
SBAS925A – AUGUST 2018 – REVISED NOVEMBER 2018
ADS1119 4-Channel, 1-kSPS, 16-Bit, Delta-Sigma ADC With I2C Interface
1 Features
3 Description
•
•
•
•
The ADS1119 is a precision, 16-bit, analog-to-digital
converter (ADC) that includes all features necessary
to implement the most common system monitoring
functions, such as supply voltage, current, and
temperature monitoring. The device features two
differential or four single-ended inputs through a
flexible input multiplexer (MUX), rail-to-rail input
buffers, a programmable gain stage, a voltage
reference, and an oscillator.
1
•
•
•
•
•
•
•
•
•
•
•
Easy to Use With Only One Register to Program
Current Consumption as Low as 315 µA (typ)
Wide Supply Range: 2.3 V to 5.5 V
Rail-to-Rail Input Buffers to Achieve High Input
Impedance
Programmable Gains: 1 and 4
Programmable Data Rates: Up to 1 kSPS
16-Bit, Noise-Free Resolution at 20 SPS
Simultaneous 50-Hz and 60-Hz Rejection at
20 SPS With Single-Cycle Settling Digital Filter
Two Differential or Four Single-Ended Inputs
Internal 2.048-V Reference: 5 ppm/°C (typ) Drift
Internal 2% Accurate Oscillator
I2C-Compatible Interface
Supported I2C Bus Speed Modes:
Standard-Mode, Fast-Mode, Fast-Mode Plus
16 Pin-Configurable I2C Addresses
Package: 3.0-mm × 3.0-mm × 0.75-mm WQFN
The ADS1119 features a 2-wire, I2C-compatible
interface that supports I2C bus speeds up to 1 Mbps.
16 different I2C addresses can be selected for the
device via two address pins.
The ADS1119 is offered in a leadless 16-pin WQFN
or a 16-pin TSSOP package and is specified over a
temperature range of –40°C to +125°C.
2 Applications
•
•
•
•
•
The device includes buffers that allow highimpedance sources to be directly connected to the
device. A gain stage follows the buffers which
provides selectable gains of 1 and 4. The ADS1119
can perform conversions at data rates as high as
1000 samples per second (SPS) with single-cycle
settling. At 20 SPS, the digital filter offers
simultaneous 50-Hz and 60-Hz rejection for noisy
industrial applications.
Battery Test Equipment
Gas Detectors
Heat Meters
Optical Modules
Wearable Fitness and Activity Trackers
Device Information(1)
PART NUMBER
ADS1119
PACKAGE
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Voltage, Current, and Temperature Monitoring Application
3.3 V
3.3 V
3.3 V
0.1 PF
0.1 PF
3.3 V
0.1 PF
REFP
AVDD
RREF
REFN
DVDD
2.048-V
Reference
RF0
Reference
MUX
ADS1119
AIN0
3.3 V
Thermistor
CF0
SCL
3.3 V
SDA
0.1 PF
AIN1
Gain
1 or 4
MUX
+
RF2
RShunt
16-bit
û ADC
Digital Filter
and
I2C Interface
INA180
A0
A1
DRDY
AIN2
-
CF2
RESET
Buffers
RF3
Load
0 V to 2 V
Low Drift
Oscillator
AIN3
CF3
AGND
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1119
SBAS925A – AUGUST 2018 – REVISED NOVEMBER 2018
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
I2C Timing Requirements.......................................... 7
I2C Switching Characteristics.................................... 8
Typical Characteristics ............................................ 10
7
Parameter Measurement Information ................ 14
8
Detailed Description ............................................ 15
7.1 Noise Performance ................................................. 14
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
16
20
8.5 Programming........................................................... 22
8.6 Register Map........................................................... 27
9
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Application .................................................. 34
10 Power Supply Recommendations ..................... 37
10.1 Power-Supply Sequencing.................................... 37
10.2 Power-Supply Decoupling..................................... 37
11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
11.2 Layout Example .................................................... 39
12 Device and Documentation Support ................. 40
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
40
40
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2018) to Revision A
Page
•
Changed Internal Voltage Reference, Accuracy parameter: added TSSOP package to test conditions of first row
and added second row to Internal Voltage Reference, Accuracy parameter......................................................................... 5
•
Added TSSOP package to conditions of Internal Reference Voltage Histogram figure ...................................................... 11
2
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SBAS925A – AUGUST 2018 – REVISED NOVEMBER 2018
5 Pin Configuration and Functions
4
AIN2
SDA
A0
SCL
14
A0
1
16
SCL
A1
2
15
SDA
RESET
3
14
DRDY
DGND
4
13
DVDD
AGND
5
12
AVDD
AIN3
6
11
AIN0
AIN2
7
10
AIN1
REFN
8
9
REFP
13
12
DRDY
11
DVDD
10
AVDD
9
AIN0
8
AIN3
Pad
AIN1
3
7
AGND
PW Package
16-Pin TSSOP
Top View
Thermal
REFP
2
6
DGND
REFN
1
5
RESET
15
16
A1
RTE Package
16-Pin WQFN
Top View
Not to scale
Not to scale
Pin Functions
PIN
NO.
NAME
RTE
PW
ANALOG OR DIGITAL
INPUT/OUTPUT
DESCRIPTION (1)
2
A0
15
1
Digital input
I C slave address select pin 0. See the I2C Address section for details.
A1
16
2
Digital input
I2C slave address select pin 1. See the I2C Address section for details.
AIN0
9
11
Analog input
Analog input 0
AIN1
8
10
Analog input
Analog input 1
AIN2
5
7
Analog input
Analog input 2
AIN3
4
6
Analog input
Analog input 3
AGND
3
5
Analog supply
Negative analog power supply
AVDD
10
12
Analog supply
Positive analog power supply. Connect a 100-nF (or larger) capacitor to AGND.
DGND
2
4
Digital supply
Digital ground
DRDY
12
14
Digital output
Data ready, active low. Connect to DVDD using a pullup resistor.
DVDD
11
13
Digital supply
Positive digital power supply. Connect a 100-nF (or larger) capacitor to DGND.
REFN
6
8
Analog input
Negative reference input
REFP
7
9
Analog input
Positive reference input
RESET
1
3
Digital input
Reset, active low
SCL
14
16
Digital input
Serial clock input. Connect to DVDD using a pullup resistor.
SDA
13
15
Digital input/output
Pad
—
—
Thermal pad
(1)
Serial data input and output. Connect to DVDD using a pullup resistor.
Thermal power pad. Connect to AGND.
See the Unused Inputs and Outputs section for details on how to connect unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
see
(1)
Power-supply voltage
MIN
MAX
AVDD to AGND
–0.3
7
UNIT
DVDD to DGND
–0.3
7
AGND to DGND
–2.8
0.3
AVDD + 0.3
V
Analog input voltage
AIN0, AIN1, AIN2, AIN3, REFP, REFN
AGND – 0.3
Digital input voltage
SCL, SDA, A0, A1, DRDY, RESET
DGND – 0.3
7
V
Input current
Continuous, any pin except power-supply pins
–10
10
mA
Temperature
(1)
Junction, TJ
V
150
Storage, Tstg
–60
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Analog power supply
Digital power supply
AVDD to AGND
2.3
AGND to DGND
–0.1
5.5
DVDD to DGND
2.3
5.5
V
0
0.1
V
ANALOG INPUTS (1)
V(AINx)
Absolute input voltage
Gain = 1 and 4
AGND – 0.1
AVDD + 0.1
V
VIN
Differential input voltage
VIN = VAINP – VAINN (2)
–VREF / Gain
VREF / Gain
V
VOLTAGE REFERENCE INPUTS
VREF
Differential reference input voltage
V(REFN)
Absolute negative reference voltage
V(REFP)
Absolute positive reference voltage
VREF = V(REFP) – V(REFN)
AVDD
V
AGND – 0.1
0.75
2.5
V(REFP) – 0.75
V
V(REFN) + 0.75
AVDD + 0.1
V
SCL, SDA, A0, A1, DRDY,
2.3 V ≤ DVDD < 3.0 V
DGND
DVDD + 0.5
SCL, SDA, A0, A1, DRDY,
3.0 V ≤ DVDD ≤ 5.5 V
DGND
5.5
RESET
DGND
DVDD
–40
125
DIGITAL INPUTS
Input voltage
V
TEMPERATURE RANGE
TA
(1)
(2)
4
Operating ambient temperature
°C
AINx denotes one of the four available analog inputs. AINP and AINN denote the positive and negative inputs selected by the MUX.
Excluding the effects of offset and gain error.
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6.4 Thermal Information
ADS1119
THERMAL METRIC (1)
WQFN (RTE)
TSSOP (PW)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
57.7
90.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.0
31.7
°C/W
RθJB
Junction-to-board thermal resistance
19.9
41.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
1.8
°C/W
ψJB
Junction-to-board characterization parameter
19.8
41.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
11.8
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, DVDD = 3.3 V, all data rates, all gains, and internal reference enabled (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Absolute input current
VIN = 0 V
±5
nA
Absolute input current drift
VIN = 0 V
10
pA/°C
Differential input current
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±5
nA
Differential input current drift
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
10
pA/°C
SYSTEM PERFORMANCE
Resolution (no missing codes)
DR
16
Data rate
Noise (input-referred) (1)
Gain = 1, DR = 20 SPS
INL
Integral nonlinearity
AVDD = 3.3 V, VCM = AVDD / 2, best fit
VIO
Input offset voltage
Differential inputs
Common-mode rejection ratio
PSRR
Power-supply rejection ratio
µVRMS
15
ppmFSR
0.1
µV/°C
±4
µV
±0.01%
Gain drift vs temperature (2)
CMRR
4
0.02
Gain error (2)
Normal-mode rejection ratio
SPS
62.5
–15
Offset drift vs temperature
NMRR
Bits
20, 90, 330, 1000
0.3
50 Hz ±1 Hz, DR = 20 SPS
78
88
60 Hz ±1 Hz, DR = 20 SPS
80
88
At dc, gain = 1, AVDD = 3.3 V
2
dB
90
105
105
115
AVDD at dc, VCM = AVDD / 2
85
105
DVDD at dc, VCM = AVDD / 2
95
115
TA = 25°C, TSSOP package
–0.15%
±0.01%
0.15%
TA = 25°C, WQFN package
–0.25%
±0.04%
0.25%
5
30
fCM = 50 Hz or 60 Hz, DR = 20 SPS, AVDD = 3.3 V
ppm/°C
dB
dB
INTERNAL VOLTAGE REFERENCE
VREF
Reference voltage
Accuracy
2.048
Temperature drift
Long-term drift
V
ppm/°C
1000 hours
110
ppm
REFP = VREF, REFN = AGND, AVDD = 3.3 V
±10
nA
VOLTAGE REFERENCE INPUTS
Reference input current
INTERNAL OSCILLATOR
fCLK
Frequency
1.024
Accuracy
(1)
(2)
–2%
±1%
MHz
2%
See the Noise Performance section for more information.
Excluding error of voltage reference.
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, DVDD = 3.3 V, all data rates, all gains, and internal reference enabled (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
VIL
Logic input level, low
DGND
0.3 DVDD
2.3 V ≤ DVDD < 3.0 V,
SCL, SDA, A0, A1, DRDY
0.7 DVDD
DVDD + 0.5
3.0 V ≤ DVDD ≤ 5.5 V,
SCL, SDA, A0, A1, DRDY
0.7 DVDD
5.5
RESET
0.7 DVDD
DVDD
VIH
Logic input level, high
Vhys
Hysteresis of Schmitt-trigger
inputs
Fast-mode, fast-mode plus
VOL
Logic output level, low
IOL = 3 mA
DGND
VOL = 0.4 V, standard-mode, fast-mode
IOL
Low-level output current
0.05 DVDD
VOL = 0.4 V, fast-mode plus
VOL = 0.6 V, fast-mode
Ii
Input current
DGND + 0.1 V < VDigital Input < DVDD – 0.1 V
Ci
Capacitance
Each pin
V
V
V
0.15
0.4
V
3
20
mA
6
–10
10
µA
10
pF
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, VIN = 0 V)
IAVDD
Analog supply current
Power-down mode
0.1
Conversion mode, internal reference selected
250
Conversion mode, external reference selected
310
3
µA
DIGITAL SUPPLY CURRENT (DVDD = 3.3 V, All Data Rates, I2C Not Active)
IDVDD
Digital supply current
Power-down mode
0.3
5
Conversion mode
65
100
µA
POWER DISSIPATION (AVDD = DVDD = 3.3 V, All Data Rates, VIN = 0 V, I2C Not Active)
PD
6
Power dissipation
Conversion mode, internal reference selected
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1.04
mW
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6.6 I2C Timing Requirements
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup
resistor = 1 kΩ (unless otherwise noted)
MIN
MAX
UNIT
100
kHz
STANDARD-MODE
fSCL
SCL clock frequency
0
tHD;STA
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
4
µs
tLOW
Pulse duration, SCL low
4.7
µs
tHIGH
Pulse duration, SCL high
4.0
µs
tSU;STA
Setup time, repeated START condition
4.7
µs
tHD;DAT
Hold time, data
0
µs
tSU;DAT
Setup time, data
tr
Rise time, SCL, SDA
1000
ns
tf
Fall time, SCL, SDA
250
ns
tSU;STO
Setup time, STOP condition
4.0
tBUF
Bus free time, between STOP and START condition
4.7
tVD;DAT
Valid time, data
3.45
µs
tVD;ACK
Valid time, acknowledge
3.45
µs
400
kHz
250
ns
µs
µs
FAST-MODE
fSCL
SCL clock frequency
tHD;STA
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
0
0.6
µs
tLOW
Pulse duration, SCL low
1.3
µs
tHIGH
Pulse duration, SCL high
0.6
µs
tSU;STA
Setup time, repeated START condition
0.6
µs
tHD;DAT
Hold time, data
0
µs
tSU;DAT
Setup time, data
tr
Rise time, SCL, SDA
tf
Fall time, SCL, SDA
tSU;STO
Setup time, STOP condition
0.6
tBUF
Bus free time, between STOP and START condition
1.3
tVD;DAT
Valid time, data
0.9
µs
tVD;ACK
Valid time, acknowledge
0.9
µs
tSP
Pulse width of spikes that must be suppressed by the input filter
0
50
ns
0
1000
100
ns
20
300
ns
20 · (DVDD / 5.5 V)
250
ns
µs
µs
FAST-MODE PLUS
fSCL
SCL clock frequency
tHD;STA
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
tLOW
tHIGH
kHz
0.26
µs
Pulse duration, SCL low
0.5
µs
Pulse duration, SCL high
0.26
µs
tSU;STA
Setup time, repeated START condition
0.26
µs
tHD;DAT
Hold time, data
0
µs
tSU;DAT
Setup time, data
50
tr
Rise time, SCL, SDA
tf
Fall time, SCL, SDA
tSU;STO
Setup time, STOP condition
tBUF
Bus free time, between STOP and START condition
tVD;DAT
Valid time, data
0.45
µs
tVD;ACK
Valid time, acknowledge
0.45
µs
tSP
Pulse duration of spikes that must be suppressed by the input filter
50
ns
Pullup resistor = 350 Ω
20 · (DVDD / 5.5 V)
ns
120
ns
120
ns
0.26
µs
0.5
0
µs
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I2C Timing Requirements (continued)
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup
resistor = 1 kΩ (unless otherwise noted)
MIN
MAX
UNIT
RESET PIN
tw(RSL)
Pulse duration, RESET low
250
ns
td(RSSTA)
Delay time, START condition after RESET rising edge (1)
100
ns
0
ns
DRDY PIN
td(DRSTA)
Delay time, START condition after DRDY falling edge
TIMEOUT
Timeout (2)
(1)
(2)
14000
tMOD
No delay time is required when using the RESET command as long as all I2C timing requirements for the (repeated) START and STOP
conditions are met.
See the Timeout section for more information.
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz.
6.7 I2C Switching Characteristics
over operating ambient temperature range, DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup resistor =
1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tw(DRH)
Pulse duration, DRDY high (1)
tp(RDDR)
Propagation delay time, RDATA command latched to
DRDY rising edge
(1)
MIN
TYP
MAX
2
UNIT
tMOD
2
tMOD
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz.
tf
SDA
tSU;DAT
tr
70%
30%
...
cont.
tHD;DAT
tf
tVD;DAT
tHIGH
tr
70%
30%
70%
30%
SCL
tLOW
tHD;STA
S
...
cont.
9th clock
1 / fSCL
1st clock cycle
tBUF
SDA
tSU;STA
tHD;STA
tVD;ACK
tSP
tSU;STO
70%
30%
SCL
Sr
9th clock
P
S
Figure 1. I2C Timing Requirements
8
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tw(RSL)
RESET
ttd(RSSTA)t
SDA
ADDRESS
SCL
S
START
Condition
Figure 2. RESET Pin Timing Requirements
tw(DRH)
DRDY
td(DRSTA)
SDA
ADDRESS
ttp(RDDR)t
W
ACK
RDATA
Command
ACK
SCL
S
P
START
Condition
STOP
Condition
Figure 3. DRDY Pin Timing Requirements and Switching Characteristics
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6.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
15
20
15
Differential Input Current (nA)
Absolute Input Current (nA)
10
5
0
-5
-10
10
5
0
-5
-10
-15
-40qC
25qC
85qC
125qC
-40qC
-15
0
0.5
1
1.5
2
V(AINx) (V)
2.5
3
-20
-2.5
3.5
-2
-1.5
-1
VIN = 0 V
0
0.5
VIN (V)
85qC
1
125qC
1.5
2
2.5
80
100
VCM = 1.65 V
Figure 4. Absolute Input current vs Absolute Input Voltage
Figure 5. Differential Input Current vs
Differential Input Voltage
15
15
10
10
INL (ppm of FSR)
INL (ppm of FSR)
-0.5
25qC
5
0
-5
-10
5
0
-5
-10
-15
-100 -80
-60
-40
-20
0
20
VIN (% of FS)
40
60
80
-15
-100 -80
100
External reference, best fit
-60
-40
-20
0
20
VIN (% of FS)
40
60
Internal reference, best fit
Figure 6. INL vs Differential Input Voltage
Figure 7. INL vs Differential Input Voltage
80
10
8
60
Offset Voltage (PV)
Number of Occurrences
Gain = 1
Gain = 4
40
6
4
20
40
35
30
25
20
15
10
5
0
-5
0
-10
2
0
-50
-25
Offset Voltage ( V)
0
25
50
Temperature (qC)
75
100
125
AVDD = 5 V, gain = 1, 110 samples
Figure 8. Offset Voltage Histogram
10
Figure 9. Input Offset Voltage vs Temperature
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Typical Characteristics (continued)
300
0
250
-0.005
200
-0.01
Gain Error (%)
Number of Occurrences
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
150
100
-0.02
-0.025
50
-0.03
-50
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
Gain = 1
Gain = 4
-0.03
0
-0.015
-25
0
25
50
Temperature (qC)
75
100
125
Excluding error of voltage reference
Gain Error (%)
Gain = 1, 620 samples,
excluding error of voltage reference
Figure 10. Gain Error Histogram
Figure 11. Gain Error vs Temperature
2000
125
Number of Occurrences
CMRR (dB)
120
115
110
1500
1000
500
2.0486
2.0484
125
2.0482
100
2.048
75
2.0478
25
50
Temperature (qC)
2.0476
0
2.0474
0
-25
2.047
100
-50
2.0472
105
Internal Reference Voltage (V)
5940 samples, TSSOP package
Figure 13. Internal Reference Voltage Histogram
Figure 12. DC CMRR vs Temperature
2.0486
AVDD = 3.3 V
AVDD = 5.0 V
2.05
2.049
2.048
2.047
2.046
2.045
-50
Internal Reference Voltage (V)
Internal Reference Voltage (V)
2.051
2.0484
2.0482
2.048
2.0478
-25
0
25
50
Temperature (qC)
75
100
125
Figure 14. Internal Reference Voltage vs Temperature
2
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
Figure 15. Internal Reference Voltage vs AVDD
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
300
0
VREF = 2 V
VREF = 2.5 V
250
Number of Occurrences
-5
-10
-15
200
150
100
1.032
125
1.03
100
1.028
75
1.026
25
50
Temperature (qC)
1.024
0
1.022
-25
1.02
0
-20
-50
1.018
50
1.016
Reference Input Current (nA)
VREF = 1 V
VREF = 1.5 V
Internal Oscillator Frequency (MHz)
Figure 17. Internal Oscillator Frequency Histogram
Figure 16. External Reference Input Current vs Temperature
1.026
Internal Oscillator Frequency (MHz)
Internal Oscillator Frequency (MHz)
1.026
1.025
1.024
1.023
1.022
1.021
1.02
-50
1.025
1.024
1.023
1.022
1.021
1.02
-25
0
25
50
Temperature (qC)
75
100
125
2
Figure 18. Internal Oscillator Frequency vs Temperature
3.5
4
DVDD (V)
4.5
5
5.5
1
40°C
25°C
125°C
0.4
0.8
AVDD Current (PA)
Digital Pin Output Voltage (V)
3
Figure 19. Internal Oscillator Frequency vs DVDD
0.5
0.3
0.2
0.1
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
Sinking Current (mA)
16
18
20
0
-50
DVDD = 3.3 V
-25
0
25
50
Temperature (qC)
75
100
125
Power-down mode
Figure 20. Digital Pin Output Voltage vs Sinking Current
12
2.5
Figure 21. Analog Supply Current vs Temperature
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Typical Characteristics (continued)
600
600
500
500
AVDD Current (PA)
AVDD Current (PA)
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
400
300
200
400
300
200
100
100
0
-50
0
-25
0
25
50
Temperature (qC)
75
100
2
125
2.5
3
Conversion mode
3.5
4
AVDD (V)
4.5
5
5.5
Conversion mode
Figure 22. Analog Supply Current vs Temperature
Figure 23. Analog Supply Current vs AVDD
100
2
DVDD Current (PA)
DVDD Current (PA)
90
1.5
1
80
70
0.5
60
0
-50
-25
0
25
50
Temperature (qC)
75
100
50
-50
125
-25
0
Power-down mode
25
50
Temperature (qC)
75
100
125
Conversion mode
Figure 24. Digital Supply Current vs Temperature
Figure 25. Digital Supply Current vs Temperature
100
DVDD Current (PA)
90
80
70
60
50
2
2.5
3
3.5
4
DVDD (V)
4.5
5
5.5
Conversion mode
Figure 26. Digital Supply Current vs DVDD
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7 Parameter Measurement Information
7.1 Noise Performance
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input
signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and
decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between
modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus
reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the inputreferred noise drops when reducing the output data rate because more samples of the internal modulator are
averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is
particularly useful when measuring low-level signals.
Table 1 and Table 2 summarize the device noise performance. Data are representative of typical noise
performance at TA = 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings
from a single device over a time period of approximately 0.75 seconds and are measured with the inputs
internally shorted together. Table 1 lists the input-referred noise in units of μVRMS for the conditions shown.
Values in µVPP are shown in parenthesis. Table 2 lists the corresponding data in effective resolution calculated
from μVRMS values using Equation 1. Noise-free resolution calculated from peak-to-peak noise values using
Equation 2 are shown in parenthesis.
The input-referred noise only changes marginally when using an external low-noise reference, such as the
REF5020. Use Equation 1 and Equation 2 to calculate effective resolution numbers and noise-free resolution
when using a reference voltage other than 2.048 V:
Effective Resolution = ln [2 · VREF / (Gain · VRMS-Noise)] / ln(2)
Noise-Free Resolution = ln [2 · VREF / (Gain · VPP-Noise)] / ln(2)
(1)
(2)
Table 1. Noise in μVRMS (μVPP)
at AVDD = 3.3 V and Internal VREF = 2.048 V
GAIN
DATA RATE
(SPS)
1
4
20
62.50 (62.50)
15.63 (15.63)
90
62.50 (62.50)
15.63 (15.63)
330
62.50 (106.06)
15.63 (26.30)
1000
62.50 (221.61)
15.63 (55.07)
Table 2. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V and Internal VREF = 2.048 V
14
GAIN
DATA RATE
(SPS)
1
4
20
16 (16)
16 (16)
90
16 (16)
16 (16)
330
16 (15.24)
16 (15.25)
1000
16 (14.17)
16 (14.18)
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8 Detailed Description
8.1 Overview
The ADS1119 is a small, low-power, 16-bit, ΔΣ ADC. In addition to the ΔΣ ADC core and single-cycle settling
digital filter, the device offers a multiplexer (MUX), rail-to-rail input buffers, a programmable gain stage, an
internal 2.048-V voltage reference, and a clock oscillator. All of these features are intended to reduce the
required external circuitry in typical voltage, current, and temperature monitoring applications. The device is fully
configured through a single register and controlled by six commands through an I2C-compatible interface. The
Functional Block Diagram section shows the device functional block diagram.
The MUX selects the positive (AINP) and negative (AINN) signals that feed into the rail-to-rail input buffers. A gain
stage with selectable gains of 1 and 4 follows the input buffers. The 16-bit ADC measures the differential signal
provided after the gain stage. The converter core consists of a differential, switched-capacitor, ΔΣ modulator
followed by a digital filter. The digital filter receives a high-speed bitstream from the modulator and outputs a
code proportional to the input voltage. This architecture results in a very strong attenuation of any common-mode
signal.
The device has two available conversion modes: single-shot conversion and continuous conversion mode. In
single-shot conversion mode, the ADC performs one conversion of the input signal upon request and stores the
value in an internal data buffer. The device then enters a low-power state to save power. Single-shot conversion
mode is intended to provide significant power savings in systems that require only periodic conversions, or when
there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins
a conversion of the input signal as soon as the previous conversion is completed. New data are available at the
programmed data rate. Data can be read at any time without concern of data corruption and always reflect the
most recently completed conversion.
8.2 Functional Block Diagram
REFP
AVDD
2.048-V
Reference
AIN0
REFN
Reference
MUX
DVDD
ADS1119
SCL
AIN1
SDA
Gain
1 or 4
MUX
16-bit
û ADC
Digital Filter
and
I2C Interface
AIN2
A0
A1
DRDY
RESET
Buffers
AIN3
Low Drift
Oscillator
DGND
AGND
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8.3 Feature Description
8.3.1 Multiplexer
Figure 27 shows the flexible input multiplexer of the device. Either four single-ended signals, two differential
signals, or a combination of two single-ended signals and one differential signal can be measured. The positive
(AINP) and negative (AINN) inputs selected for measurement are configured by three bits (MUX[2:0]) in the
configuration register. When single-ended signals need to be measured, the negative ADC input (AINN) can
internally be connected to AGND by a switch within the multiplexer.
AVDD / 2
AVDD
AGND
AVDD
AGND
AVDD
AGND
AIN0
AIN1
AINP
To ADC
AIN2
AVDD
AINN
AGND
Rail-to Rail
Buffers
AIN3
AGND
Figure 27. Analog Input Multiplexer
Electrostatic discharge (ESD) diodes to AVDD and AGND protect the inputs. The absolute voltage on any input
must stay within the range provided by Equation 3 to prevent the ESD diodes from turning on:
AGND – 0.3 V < V(AINx) < AVDD + 0.3 V
(3)
If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or
series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings
table). Overdriving an unused input on the device can affect conversions taking place on other input pins.
16
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Feature Description (continued)
8.3.2 Rail-to-Rail Input Buffers and Programmable Gain Stage
The ADS1119 integrates two rail-to-rail input buffers to ensure that the effect on the input loading resulting from
the capacitor charging and discharging of the ΔΣ ADC is minimal. The buffers therefore help to increase the input
impedance of the device. See the Electrical Characteristics table for the typical values of absolute input currents
(current flowing into or out of each input) and differential input currents (difference in absolute current between
the positive and negative input).
The usable absolute input voltage range of the buffers is (AGND – 0.1 V ≤ VAINP, VAINN ≤ AVDD + 0.1 V). VIN
denotes the differential input voltage VIN = VAINP – VAINN between the buffer inputs.
A programmable gain stage follows the buffers. The GAIN bit in the configuration register is used to configure the
gain to either 1 or 4.
Equation 4 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gain
setting and the reference voltage used:
FSR = ±VREF / Gain
(4)
Table 3 shows the corresponding full-scale ranges and least significant bit (LSB) sizes when using the internal
2.048-V reference.
Table 3. Full-Scale Range and LSB Size
GAIN SETTING
FSR
LSB SIZE
1
±2.048 V
62.50 µV
4
±0.512 V
15.63 µV
In order to measure single-ended signals that are referenced to AGND (AINP = VIN, AINN = AGND), connect one
of the analog inputs to AGND externally or use the internal AGND connection of the multiplexer (MUX[2:0]
settings 011 through 110). The device only uses the code range that represents positive differential voltages
when measuring single-ended signals. See the Data Format section for more details.
For signal sources with high output impedance, external buffering may still be necessary. Active buffers can
introduce noise as well as offset and gain errors. Consider all of these factors in high-accuracy applications.
8.3.3 Voltage Reference
The device offers an integrated, low-drift, 2.048-V reference. For applications that require a different reference
voltage value or a ratiometric measurement approach, the device offers a differential reference input pair (REFP
and REFN).
The reference source is selected by the VREF bit in the configuration register. By default, the internal reference
is selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when coming
out of power-down mode, or when switching from the external reference source to the internal reference.
The differential reference input allows freedom in the reference common-mode voltage. The reference inputs are
internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required
when using an external reference. When used in ratiometric applications, the reference inputs do not load the
external circuitry; however, the analog supply current increases when using an external reference because the
reference buffers are enabled.
In most cases the conversion result is directly proportional to the stability of the reference source. Any noise and
drift of the voltage reference is reflected in the conversion result.
8.3.4 Modulator and Internal Oscillator
A ΔΣ modulator is used in the ADS1119 to convert the differential signal provided by the gain stage into a pulse
code modulated (PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 4 =
256 kHz, where fCLK is provided by the internal 1.024-MHz oscillator.
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8.3.5 Digital Filter
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and
decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the
different data rates and always settles within a single cycle. The frequency responses of the digital filter are
shown in Figure 28 to Figure 32 for different output data rates. The filter notches and output data rate scale
proportionally with the clock frequency. The internal oscillator can vary over temperature as specified in the
Electrical Characteristics table. The data rate or conversion time, respectively, and consequently also the filter
notches vary proportionally.
-60
-80
-100
-80
-100
-120
0
20
40
60
80 100 120
Frequency (Hz)
140
160
180
-120
46
200
48
50
52
D002
Figure 28. Filter Response
(DR = 20 SPS)
54
56
58
Frequency (Hz)
60
62
64
D001
Figure 29. Detailed View of the Filter Response
(DR = 20 SPS)
0
0
-10
-10
-20
-20
Magnitude (dB)
Magnitude (dB)
-60
-30
-40
-50
-30
-40
-50
-60
-60
0
100
200
300
400 500 600
Frequency (Hz)
700
800
900 1000
0
200
400
D004
Figure 30. Filter Response
(DR = 90 SPS)
600
800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
D006
Figure 31. Filter Response
(DR = 330 SPS)
0
Magnitude (dB)
-20
-40
-60
-80
0
1
2
3
4
5
6
Frequency (kHz)
7
8
9
10
D008
Figure 32. Filter Response
(DR = 1 kSPS)
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8.3.6 Conversion Times
Table 4 shows the actual conversion times for each data rate setting. The values provided are in terms of tCLK
cycles and in milliseconds.
Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge.
The first conversion starts 28.5 · tCLK after the START/SYNC command is latched.
Single-shot conversion mode data rates are timed from when the START/SYNC command is latched to the
DRDY falling edge and rounded to the next tCLK.
Commands are latched on the eighth falling edge of SCL in the command byte.
Table 4. Conversion Times
NOMINAL
DATA RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
20
90
(1)
(2)
CONTINUOUS CONVERSION MODE (1)
SINGLE-SHOT CONVERSION MODE
ACTUAL
CONVERSION TIME
(tCLK) (2)
ACTUAL
CONVERSION TIME
(ms)
ACTUAL
CONVERSION TIME
(tCLK) (2)
ACTUAL
CONVERSION TIME
(ms)
13.1
51192
49.99
51213
50.01
39.6
11532
11.26
11557
11.29
330
150.1
3116
3.04
3141
3.07
1000
483.8
1036
1.01
1061
1.04
The first conversion starts 28.5 · tCLK after the START/SYNC command is latched. The times listed in this table do not include that time.
tCLK = 1 / fCLK. fCLK = 1.024 MHz.
Although the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does not
affect the 50-Hz or 60-Hz rejection. The conversion time and filter notches vary by the amount specified in the
Electrical Characteristics table for oscillator accuracy.
8.3.7 Offset Calibration
The ADS1119 does not offer any self-calibration options. However the internal multiplexer offers the option to
short both inputs (AINP and AINN) to mid-supply AVDD / 2. This option can be used to measure and calibrate the
device offset voltage by storing the result of the shorted input voltage reading in a microcontroller and
consequently subtracting the result from each following reading. Take multiple readings with the inputs shorted
and average the result to reduce the effect of noise.
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8.4 Device Functional Modes
Figure 33 shows a flow chart of the different operating modes and how the device transitions from one mode to
another.
Power-On Reset or
RESET pin high or
RESET command(1)
Reset device to
default settings
Low-power state
No
No
START/SYNC
Command?
POWERDOWN
Command?
Yes
Yes
Conversion
Mode
Power-down Mode(3)
Yes
Start new
conversion
START/SYNC
Command?
No
No
0 = Single-Shot
conversion mode
Conversion
mode selection(2)
1 = Continuous
conversion mode
POWERDOWN
Command?
Yes
(1)
Any reset (power-on, command, or pin) immediately resets the device.
(2)
The conversion mode is selected with the CM bit in the configuration register.
(3)
The POWERDOWN command allows any ongoing conversion to complete before placing the device in power-down
mode.
Figure 33. Operating Flow Chart
8.4.1 Power-Up and Reset
The ADS1119 is reset in one of three ways: either by a power-on reset, by the RESET pin, or by a RESET
command.
When a reset occurs, the configuration register resets to the default values and the device enters a low-power
state. The device then waits for the START/SYNC command to enter conversion mode; see the I2C Timing
Requirements table for reset timing information.
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Device Functional Modes (continued)
8.4.1.1 Power-On Reset
During power up, the device is held in reset. The power-on reset releases approximately 500 µs after both
supplies have exceeded their respective power-up reset thresholds. After this time all internal circuitry (including
the voltage reference) are stable and communication with the device is possible. As part of the power-on reset
process, the device sets all bits in the configuration register to the respective default settings. After power-up, the
device enters a low-power state. This power-up behavior is intended to prevent systems with tight power-supply
requirements from encountering a current surge during power-up.
8.4.1.2 RESET Pin
Reset the ADC by taking the RESET pin low for a minimum of tw(RSL) and then returning the pin high. After the
rising edge of the RESET pin, a delay time of td(RSSTA) is required before communicating with the device; see the
I2C Timing Requirements table for reset timing information.
8.4.1.3 Reset by Command
Reset the ADC by using the RESET command (06h or 07h). No delay time is required after the RESET
command is latched before starting to communicate with the device as long as the timing requirements (see the
I2C Timing Requirements table) for the (repeated) START and STOP conditions are met. Alternatively, the device
also responds to the I2C general-call software reset.
8.4.2 Conversion Modes
The device operates in one of two conversion modes that are selected by the CM bit in the configuration register.
These conversion modes are single-shot conversion and continuous conversion mode. A START/SYNC
command must be issued each time the CM bit is changed.
8.4.2.1 Single-Shot Conversion Mode
In single-shot conversion mode, the device only performs a conversion when a START/SYNC command is
issued. The device consequently performs one single conversion and returns to a low-power state afterwards.
The internal oscillator and all analog circuitry are turned off while the device waits in this low-power state until the
next conversion is started. Writing to the configuration register when a conversion is ongoing functions as a new
START/SYNC command that stops the current conversion and restarts a single new conversion. Each
conversion is fully settled (assuming the analog input signal settles to the final value before the conversion starts)
because the device digital filter settles within a single cycle.
8.4.2.2 Continuous Conversion Mode
In continuous conversion mode, the device continuously performs conversions. When a conversion completes,
the device places the result in the output buffer and immediately begins another conversion.
In order to start continuous conversion mode, the CM bit must be set to 1 followed by a START/SYNC command.
The first conversion starts 28.5 · tCLK after the START/SYNC command is latched. Writing to the configuration
register during an ongoing conversion restarts the current conversion. Send a START/SYNC command
immediately after the CM bit is set to 1.
Stop continuous conversions by sending the POWERDOWN command.
8.4.3 Power-Down Mode
When the POWERDOWN command is issued, the device enters power-down mode after completing the current
conversion. In this mode, all analog circuitry (including the voltage reference) are powered down and the device
typically only uses 400 nA of current. When in power-down mode, the device holds the configuration register
settings and responds to commands, but does not perform any data conversions.
Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuous
conversion mode, depending on the conversion mode selected by the CM bit.
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8.5 Programming
8.5.1 I2C Interface
The ADS1119 uses an I2C-compatible (inter-integrated circuit) interface for serial communication. I2C is a 2-wire
communication interface that allows communication of a master device with multiple slave devices on the same
bus through the use of device addressing. Each slave device on an I2C bus must have a unique address.
Communication on the I2C bus always takes place between two devices: one acting as the master and the other
as the slave. Both the master and slave can receive and transmit data, but the slave can only read or write under
the direction of the master. The ADS1119 always acts as an I2C slave device.
An I2C bus consists of two lines: SDA and SCL. SDA carries data and SCL provides the clock. Devices on the
I2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high.
Instead, the bus wires are pulled high by pullup resistors; thus, the bus wires are always high when a device is
not driving the lines low. As a result of this configuration, two devices do not conflict. If two devices drive the bus
simultaneously, there is no driver contention.
See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.
8.5.1.1 I2C Address
The ADS1119 has two address pins: A0 and A1. Each address pin can be tied to either DGND, DVDD, SDA, or
SCL, providing 16 possible unique addresses. This configuration allows up to 16 different ADS1119 devices to
be present on the same I2C bus. Table 5 shows the truth table for the I2C addresses for the possible address pin
connections.
At the start of every transaction, that is between the START condition (first falling edge of SDA) and the first
falling SCL edge of the address byte, the ADS1119 decodes its address configuration again.
Table 5. I2C Address Truth Table
A1
A0
I2C ADDRESS
DGND
DGND
100 0000
DGND
DVDD
100 0001
DGND
SDA
100 0010
DGND
SCL
100 0011
DVDD
DGND
100 0100
DVDD
DVDD
100 0101
DVDD
SDA
100 0110
DVDD
SCL
100 0111
SDA
DGND
100 1000
SDA
DVDD
100 1001
SDA
SDA
100 1010
SDA
SCL
100 1011
SCL
DGND
100 1100
SCL
DVDD
100 1101
SCL
SDA
100 1110
SCL
SCL
100 1111
8.5.1.2 Serial Clock (SCL) and Serial Data (SDA)
The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line.
The ADS1119 cannot act as a master and as a result can never drive SCL.
The serial data (SDA) line allows for bidirectional communication between the host (the master) and the
ADS1119 (the slave). When the master reads from a ADS1119, the ADS1119 drives the data line; when the
master writes to a ADS1119, the master drives the data line.
Data on the SDA line must be stable during the high period of the clock. The high or low state of the data line
can only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When in
an idle state, the master should hold SCL high.
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8.5.1.3 Data Ready (DRDY)
DRDY is an open-drain output pin that indicates when a new conversion result is ready for retrieval. When DRDY
falls low, new conversion data are ready. DRDY transitions back high when the conversion result is latched for
output transmission. In case a conversion result in continuous conversion mode is not read, DRDY releases high
for tw(DRH) before the next conversion completes. See the I2C Timing Requirements table for more details.
8.5.1.4 Interface Speed
The ADS1119 supports I2C interface speeds up to 1 Mbps. Standard-mode (Sm) with bit rates up to 100 kbps,
fast-mode (Fm) with bit rates up to 400 kbps, and fast-mode plus (Fm+) with bit rates up to 1 Mbps are
supported. High-speed mode (Hs-mode) is not supported.
8.5.1.5 Data Transfer Protocol
Figure 34 shows the format of the data transfer. The master initiates all transactions with the ADS1119 by
generating a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a START
condition. The bus is considered to be busy after the START condition.
Following the START condition, the master sends the 7-bit slave address corresponding to the address of the
ADS1119 that the master wants to communicate with. The master then sends an eighth bit that is a data
direction bit (R/W). An R/W bit of 0 indicates a write operation, and an R/W bit of 1 indicates a read operation.
After the R/W bit, the master generates a ninth SCLK pulse and releases the SDA line to allow the ADS1119 to
acknowledge (ACK) the reception of the slave address by pulling SDA low. In case the device does not
recognize the slave address, the ADS1119 holds SDA high to indicate a not acknowledge (NACK) signal.
Next follows the data transmission. If the transaction is a read (R/W = 1), the ADS1119 outputs data on SDA. If
the transaction is a write (R/W = 0), the host outputs data on SDA. Data are transferred byte-wise, most
significant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte
must be acknowledged (via the ACK bit) by the receiver. If the transaction is a read, the master issues the ACK.
If the transaction is a write, the ADS1119 issues the ACK.
The master terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDA
line while SCL is high defines a STOP condition. The bus is considered free again tBUF (bus-free time) after the
STOP condition.
SDA
A6 ± A0
D7 ± D0
D7 ± D0
SCL
1-7
8
9
1-8
9
1-8
9
ADDRESS
R/W
ACK
from slave
DATA
ACK
from receiver
DATA
ACK
from receiver
S
START
Condition
P
STOP
Condition
Figure 34. I2C Data Transfer Format
8.5.1.6 I2C General Call (Software Reset)
The ADS1119 responds to the I2C general-call address (0000 000) if the R/W bit is 0. The device acknowledges
the general-call address and, if the next byte is 06h, performs a reset. The general-call software reset has the
same effect as the RESET command.
8.5.1.7 Timeout
The ADS1119 offers a I2C timeout feature that can be used to recover communication when a serial interface
transmission is interrupted. If the host initiates contact with the ADS1119 but subsequently remains idle for
14000 · tMOD before completing a command, the ADS1119 interface is reset. If the ADS1119 interface resets
because of a timeout condition, the host must abort the transaction and restart the communication again by
issuing a new START condition.
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8.5.2 Data Format
The device provides 16 bits of data in binary two's complement format. Use Equation 5 to calculate the size of
one code (LSB).
1 LSB = (2 · VREF / Gain) / 216 = +FS / 215
(5)
A positive full-scale input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a
negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these
codes for signals that exceed full-scale.
Table 6 summarizes the ideal output codes for different input signals.
Table 6. Ideal Output Code versus Input Signal
INPUT SIGNAL,
VIN = VAINP – VAINN
15
≥ FS (2
IDEAL OUTPUT CODE (1)
15
– 1) / 2
7FFFh
FS / 215
(1)
0001h
0
0000h
–FS / 215
FFFFh
≤ –FS
8000h
Excludes the effects of noise, INL, offset, and gain errors.
Figure 35 shows the mapping of the analog input signal to the output codes.
7FFFh
0001h
0000h
FFFFh
...
Output Code
...
7FFEh
8001h
8000h
...
-FS
2
15
-FS
2
0
...
+FS
Input Voltage VIN
2
-1
15
15
+FS
2
-1
15
Figure 35. Code Transition Diagram
NOTE
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use
the positive code range from 0000h to 7FFFh. However, because of device offset, the
ADS1119 can still output negative codes when VAINP is close to 0 V.
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8.5.3 Commands
As Table 7 shows, the device offers six different commands to control device operation. Four commands are
stand-alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG)
and write (WREG) register data from and to the device require additional information as part of the instruction.
Table 7. Command Definitions
COMMAND
DESCRIPTION
COMMAND BYTE (1)
RESET
Reset the device
0000 011x
START/SYNC
Start or restart conversions
0000 100x
POWERDOWN
Enter power-down mode
0000 001x
RDATA
Read data by command
0001 xxxx
RREG
Read register at address r
0010 0rxx
WREG
Write configuration register
0100 00xx
(1)
Operands: r = register address (0 or 1), x = don't care.
8.5.3.1 Command Latching
Commands are not processed until latched by the ADS1119. Commands are latched on the eighth falling edge of
SCL in the command byte.
NOTE
The legend for Figure 36 to Figure 40:
From master to slave
S = START condition
Sr = Repeated START condition
P = STOP condition
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
8.5.3.2 RESET (0000 011x)
This command resets the device to the default states. No delay time is required after the RESET command is
latched before starting to communicate with the device as long as the timing requirements (see the I2C Timing
Requirements table) for the (repeated) START and STOP conditions are met.
8.5.3.3 START/SYNC (0000 100x)
In single-shot conversion mode, the START/SYNC command is used to start a single conversion, or (when sent
during an ongoing conversion) to reset the digital filter and then restart a single new conversion. When the
device is set to continuous conversion mode, the START/SYNC command must be issued one time to start
converting continuously. Sending the START/SYNC command when converting in continuous conversion mode
resets the digital filter and restarts continuous conversions.
8.5.3.4 POWERDOWN (0000 001x)
The POWERDOWN command places the device into power-down mode. This command shuts down all internal
analog components, but holds all register values. In case the POWERDOWN command is issued when a
conversion is ongoing, the conversion completes before the ADS1119 enters power-down mode. As soon as a
START/SYNC command is issued, all analog components return to their previous states.
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8.5.3.5 RDATA (0001 xxxx)
The RDATA command loads the output shift register with the most recent conversion result. Reading conversion
data must be performed as shown in Figure 36 by using two I2C communication frames. The first frame is an I2C
write operation where the R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host
sends the RDATA command to the ADS1119. The second frame is an I2C read operation where the R/W bit at
the end of the address byte is 1 to indicate a read. The ADS1119 reports the latest ADC conversion data in this
second I2C frame. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY pin
at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded,
DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is
high.
S
SLAVE ADDRESS
‡‡‡
W
CONVERSION DATA (MSB)
A
RDATA
A
Sr
A
CONVERSION DATA (LSB)
A
P
SLAVE ADDRESS
R
A
‡‡‡
Figure 36. Read Conversion Data Sequence
8.5.3.6 RREG (0010 0rxx)
The RREG command reads the value of the register at address r. Reading a register must be performed as
shown in Figure 37 by using two I2C communication frames. The first frame is an I2C write operation where the
R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host sends the RREG command
including the register address to the ADS1119. The second frame is an I2C read operation where the R/W bit at
the end of the address byte is 1 to indicate a read. The ADS1119 reports the contents of the requested register
in this second I2C frame.
‡‡‡
S
SLAVE ADDRESS
W
A
RREG
A
‡‡‡
Sr
SLAVE ADDRESS
R
A
REGISTER DATA
A
P
Figure 37. Read Register Sequence
8.5.3.7 WREG (0100 00xx dddd dddd)
The WREG command writes dddd dddd to the configuration register. Figure 38 shows the sequence for writing
the configuration register. The R/W bit at the end of the address byte is 0 to indicate a write. The WREG
command forces the digital filter to reset and any ongoing ADC conversion to restart.
S
SLAVE ADDRESS
W
A
WREG
A
REGISTER DATA
A
P
Figure 38. Write Register Sequence
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8.5.4 Reading Data and Monitoring for New Conversion Results
Conversion data are read by issuing the RDATA command. The ADS1119 responds to the RDATA command
with the latest conversion result. There are two ways to monitor for new conversion data.
One way is to monitor for the falling edge of the DRDY signal. When DRDY falls low, a new conversion result is
available for retrieval using the RDATA command. Figure 39 shows the timing diagram for collecting data using
the DRDY signal to indicate new data.
DRDY
‡‡‡
S
SLAVE ADDRESS
W
CONVERSION DATA (MSB)
‡‡‡
A
RDATA
A
Sr
A
CONVERSION DATA (LSB)
A
P
SLAVE ADDRESS
R
A
‡‡‡
Figure 39. Using the DRDY Pin to Check for New Conversion Data
Another way to monitor for a new conversion result is to periodically read the DRDY bit in the status register. If
set, the DRDY bit indicates that a new conversion result is ready for retrieval. The host can subsequently issue
an RDATA command to retrieve the data. The rate at which the host polls the ADS1119 for new data must be at
least as fast as the data rate in continuous conversion mode to prevent the host from missing a conversion
result.
If a new conversion result becomes ready during an I2C transmission, the transmission is not corrupted. The new
data are loaded into the output shift register upon the following RDATA command.
Figure 40 shows the timing diagram for collecting data using the DRDY bit in the status register to indicate new
data.
S
SLAVE ADDRESS
‡‡‡
REGISTER DATA (01h)
A
Sr
SLAVE ADDRESS
R
A
‡‡‡
Sr
W
A
RREG (01h)
A
Sr
SLAVE ADDRESS
W
A
A
CONVERSION DATA (MSB)
SLAVE ADDRESS
R
A
‡‡‡
RDATA
A
‡‡‡
CONVERSION DATA (LSB)
A
P
Figure 40. Using the DRDY Bit to Check for New Conversion Data
8.6 Register Map
8.6.1 Configuration and Status Registers
The device has two 8-bit registers (configuration and status) that are accessible through the I2C interface using
the RREG and WREG commands. After power-up or reset, both registers are set to the default values (which are
all 0). All register values are retained during power-down mode. Table 8 shows the register map of the two
registers.
Table 8. Register Map
REGISTER
(Hex)
BIT 7
0h
1h
BIT 6
MUX[2:0]
DRDY
BIT 5
BIT 4
BIT 3
GAIN
BIT 2
DR[1:0]
BIT 1
BIT 0
CM
VREF
ID[6:0]
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8.6.2 Register Descriptions
Table 9 lists the access codes for the ADS1119 registers.
Table 9. Register Access Type Codes
Access Type
Code
Description
R
R
Read
R/W
R/W
Read-Write
-n
Value after reset or the default value
8.6.2.1 Configuration Register (address = 0h) [reset = 00h]
Figure 41. Configuration Register
7
6
MUX[2:0]
R/W-0h
5
4
GAIN
R/W-0h
3
2
DR[1:0]
R/W-0h
1
CM
R/W-0h
0
VREF
R/W-0h
Table 10. Configuration Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
MUX[2:0]
R/W
0h
Input multiplexer configuration
These bits configure the input multiplexer.
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
4
GAIN
R/W
0h
AINP
AINP
AINP
AINP
AINP
AINP
AINP
AINP
= AIN0, AINN = AIN1 (default)
= AIN2, AINN = AIN3
= AIN1, AINN = AIN2
= AIN0, AINN = AGND
= AIN1, AINN = AGND
= AIN2, AINN = AGND
= AIN3, AINN = AGND
and AINN shorted to AVDD / 2
Gain configuration
This bit configures the device gain.
0 : Gain = 1 (default)
1 : Gain = 4
3:2
DR[1:0]
R/W
0h
Data rate
These bits control the data rate setting.
00
01
10
11
1
CM
R/W
0h
:
:
:
:
20 SPS (default)
90 SPS
330 SPS
1000 SPS
Conversion mode
This bit sets the conversion mode for the device.
0 : Single-shot conversion mode (default)
1 : Continuous conversion mode
0
VREF
R/W
0h
Voltage reference selection
This bit selects the voltage reference source that is used for the conversion.
0 : Internal 2.048-V reference selected (default)
1 : External reference selected using the REFP and REFN inputs
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8.6.2.2 Status Register (address = 1h) [reset = 00h]
Figure 42. Status Register
7
DRDY
R-0h
6
5
4
3
RESERVED
R-xxh
2
1
0
Table 11. Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DRDY
R
0h
Conversion result ready flag
This bit flags if a new conversion result is ready. This bit is reset when conversion
data are read.
0 : No new conversion result available (default)
1 : New conversion result ready
6:0
RESERVED
R
xxh
Reserved
Values are subject to change without notice.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1119 is a precision, 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) that integrates all
features required to implement the most common system monitoring functions, such as supply voltage, current,
and temperature monitoring. Primary considerations when designing an application with the ADS1119 include
analog input filtering, and establishing an appropriate external reference for ratiometric measurements.
Connecting and configuring the interface appropriately is another concern. These considerations are discussed in
the following sections.
9.1.1 Interface Connections
Figure 43 shows the principle interface connections for the ADS1119.
GPIO/IRQ
DVSS
DVDD
SDA
SCL
Microcontroller with I2C Interface
0.1 PF
3.3 V
Rp
3.3 V
3.3 V
3.3 V
2 A1
SDA 15
3 RESET
Rp
SCL 16
Rp
3.3 V
1 A0
DRDY 14
4 DGND
DVDD 13
3.3 V
Device
5 AGND
AVDD 12
6 AIN3
AIN0 11
7 AIN2
AIN1 10
8 REFN
3.3 V
0.1 PF
0.1 PF
REFP 9
Figure 43. Interface Connections
The ADS1119 interfaces directly to standard-mode, fast-mode, or fast-mode plus I2C controllers. Any
microcontroller I2C peripheral, including master-only and single-master I2C peripherals, operates with the
ADS1119. Details of the I2C communication protocol of the device can be found in the Programming section. The
ADS1119 does not perform clock-stretching (that is, the device never pulls the clock line low), so this function
does not need to be provided for unless other clock-stretching devices are present on the same I2C bus.
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Application Information (continued)
Pullup resistors are required on both the SDA and SCL lines, as well as on the open-drain DRDY output. The
size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value
resistors yield lower power consumption when the bus lines are pulled low, but increase the transition times on
the bus, which limits the bus speed. Lower-value resistors allow higher interface speeds, but at the expense of
higher power consumption when the bus lines are pulled low. Long bus lines have higher capacitance and
require smaller pullup resistors to compensate. Do not use resistors that are too small because the bus drivers
may be unable to pull the bus lines low. See the I2C-Bus Specification and User Manual for details on pullup
resistor sizing.
9.1.2 Connecting Multiple Devices on the Same I2C Bus
Up to 16 ADS1119 devices can be connected to a single I2C bus by using different address pin configurations for
each device. Use the address pins, A0 and A1, to set the ADS1119 to one of 16 different I2C addresses.
Figure 44 shows an example with three ADS1119 devices on the same I2C bus. One set of pullup resistors is
required per bus line. If needed, decrease the pullup resistor values to compensate for the additional bus
capacitance presented by multiple devices and increased line length.
GPIO/IRQ
Rp
DVDD
1 A0
SCL 16
2 A1
SDA 15
3 RESET
4 DGND
DVDD
1 A0
SCL 16
2 A1
SDA 15
DRDY 14
3 RESET
DVDD 13
4 DGND
AVDD 12
5 AGND
Device 1
5 AGND
DVDD
DVDD
Rp
DVSS
DVDD
SDA
SCL
Microcontroller with I2C Interface
1 A0
SCL 16
2 A1
SDA 15
DRDY 14
3 RESET
DVDD 13
4 DGND
AVDD 12
5 AGND
Device 2
DRDY 14
DVDD 13
Device 3
AVDD 12
6 AIN3
AIN0 11
6 AIN3
AIN0 11
6 AIN3
AIN0 11
7 AIN2
AIN1 10
7 AIN2
AIN1 10
7 AIN2
AIN1 10
8 REFN
REFP 9
8 REFN
REFP 9
8 REFN
REFP 9
Figure 44. Connecting Multiple ADS1119 Devices on the Same I2C Bus
9.1.3 Unused Inputs and Outputs
To minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or
connect the inputs to mid-supply or to AVDD. Connecting unused analog or reference inputs to AGND is possible
as well, but can yield higher leakage currents on other analog inputs than the previously mentioned options.
Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digital
inputs to the appropriate levels, DVDD or DGND, even when in power-down mode. Connections for unused
digital pins are:
• Tie the RESET pin to DVDD if the RESET pin is not used
• If the DRDY output is not used, leave the DRDY pin unconnected or tie the DRDY pin to DVDD using a weak
pullup resistor
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Application Information (continued)
9.1.4 Analog Input Filtering
Analog input filtering serves two purposes:
• Limits the effect of aliasing during the ADC sampling process
• Attenuates unwanted noise components outside the bandwidth of interest
In most cases, a first-order resistor capacitor (RC) filter is sufficient to completely eliminate aliasing or to reduce
the effect of aliasing to a level within the noise floor of the sensor. A good starting point for a system design with
the ADS1119 is to use a differential RC filter with a cutoff frequency set somewhere between the selected output
data rate and 25 kHz. Make the series resistor values as small as possible to reduce voltage drops across the
resistors caused by the device input currents to a minimum. However, the resistors should be large enough to
limit the current into the analog inputs to less than 10 mA in the event of an overvoltage. Then choose the
differential capacitor value to achieve the target filter cutoff frequency. Common-mode filter capacitors to GND
can be added as well, but should always be at least ten times smaller than the differential filter capacitor.
Internal to the device, prior to the buffer inputs, is an EMI filter. The cutoff frequency of this filter is approximately
31.8 MHz, which helps reject high-frequency interferences.
9.1.5 External Reference and Ratiometric Measurements
The full-scale range (FSR) of the ADS1119 is defined by the reference voltage and the gain setting (FSR =
±VREF / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to
the specific system needs. An external reference must be used if VIN is greater than 2.048 V. For example, an
external 5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing
between 0 V and 5 V.
The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric
measurement the same excitation source that is used to excite the sensor is also used to establish the reference
for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite
both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with
the element being measured. The voltage that develops across the reference element is used as the reference
source for the ADC. These components cancel out in the ADC transfer function because current noise and drift
are common to both the sensor measurement and the reference. The output code is only a ratio of the sensor
element and the value of the reference resistor. The value of the excitation current source itself is not part of the
ADC transfer function.
9.1.6 Establishing Proper Limits on the Absolute Input Voltage
The ADS1119 can be used to measure various types of input signal configurations: single-ended, pseudodifferential, and fully differential signals. However, configuring the device properly for the respective signal type is
important.
Signals where the negative analog input is fixed and referenced to analog ground (VAINN = 0 V) are commonly
called single-ended signals. The absolute input voltages of the ADS1119 can be as low as 100 mV below AGND
and as large as 100 mV above AVDD. Using the gain of 4 is still possible in this configuration. Measuring a 0-mA
to 20-mA or 4-mA to 20-mA signal across a load resistor of 100 Ω referenced to GND is a typical example. The
ADS1119 can directly measure the signal across the load resistor using the internal 2.048-V reference and gain
= 1.
Signals where the negative analog input (AINN) is fixed at a voltage other the 0 V are referred to as pseudodifferential signals.
Fully differential signals in contrast are defined as signals having a constant common-mode voltage where the
positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.
The ADS1119 can measure pseudo-differential and fully differential signals.
Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals
can in general be measured with the ADS1119. A signal is called bipolar when either the positive or negative
input can swing below 0 V. Bipolar signals cannot be measured with the ADS1119.
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Application Information (continued)
9.1.7 Pseudo Code Example
The following list shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS1119 in continuous
conversion mode. The DRDY pin is used to indicate availability of new conversion data. The default configuration
register settings are changed to gain = 4 and continuous conversion mode.
Power-up;
Delay to allow power supplies to settle and power-on reset to complete; minimum of 500 µs;
Configure the I2C interface of the microcontroller;
Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt
input;
Send the RESET command (06h) to make sure the device is properly reset after power-up;
Write the respective register configuration with the WREG command (40h, 12h);
As an optional sanity check, read back the configuration register with the RREG command (20h);
Send the START/SYNC command (08h) to start converting in continuous conversion mode;
Loop
{
Wait for DRDY to transition low;
Send the RDATA command (10h) to read 2 bytes of conversion data;
}
Send the POWERDOWN command (02h) to stop conversions and put the device in power-down mode;
TI recommends running an offset calibration before performing any measurements or when changing the gain or
MUX settings. The internal offset of the device can, for example, be measured by shorting the inputs to midsupply (MUX[2:0] = 111). The microcontroller then takes multiple readings from the device with the inputs shorted
and stores the average value in the microcontroller memory. When measuring the sensor signal, the
microcontroller then subtracts the stored offset value from each device reading to obtain an offset compensated
result; the offset can be either positive or negative in value.
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9.2 Typical Application
This application example describes how to use the ADS1119 for the most common system monitoring functions
(such as voltage measurement, high-side current measurement using a current sense amplifier, and temperature
measurement using a thermistor or 2-wire RTD). Figure 45 shows a typical circuit implementation.
3.3 V
3.3 V
3.3 V
0.1 PF
0.1 PF
0.1 PF
3.3 V
REFP
REFN
AVDD
RREF
DVDD
2.048-V
Reference
RF0
Reference
MUX
ADS1119
AIN0
3.3 V
Thermistor
CF0
SCL
3.3 V
SDA
0.1 PF
AIN1
Gain
1 or 4
MUX
+
16-bit
û ADC
RF2
RShunt
Digital Filter
and
I2C Interface
INA180
A0
A1
DRDY
AIN2
CF2
-
RESET
Buffers
RF3
Low Drift
Oscillator
AIN3
0 V to 2 V
Load
CF3
DGND
AGND
Figure 45. Typical System Monitoring Example Using the ADS1119
9.2.1 Design Requirements
Table 12 lists the design requirements for this application.
Table 12. Design Requirements
DESIGN PARAMETER
VALUE
Supply voltage
3.3 V
Voltage measurement range
0 V to 2 V
Voltage measurement accuracy (1)
±0.5 mV
Current measurement range (unidirectonal)
0.5 A to 10 A
Maximum voltage drop across shunt resistor
20 mV
Current measurement accuracy
(1)
±5 mA
Thermistor type
NTC
Thermistor nominal resistance
10 kΩ
Thermistor temperature range
–40°C to +125°C
Thermistor temperature measurement accuracy (1)
±0.1°C
Update rate
100 ms
(1)
After offset and gain calibration at TA = 25°C.
9.2.2 Detailed Design Procedure
In order to take one reading from each of the three input signals within 100 ms, the ADS1119 must use a data
rate of 90 SPS or faster. When using a data rate setting of 90 SPS, every conversion takes approximately
11.3 ms according to Table 4. Consequently, all three signals can be measured within approximately 34 ms
when also accounting for the time to read conversion results and to write new configuration register settings
between conversions.
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All three signal measurements use a single-ended measurement implementation. The voltage and current
measurements use the GND connection within the MUX, whereas the thermistor measurement uses an external
GND connection through AIN1 to showcase the two different options for implementing a single-ended
measurement.
RC filters are provided on all three analog inputs of the device, which act as antialiasing filters and to limit the
current into the analog inputs in case of overvoltage events. The filter component values are chosen according to
the guidelines in the Analog Input Filtering section as RF = 1 kΩ and CF = 100 nF to create a filter corner
frequency of fC = 1 / (2π · RF · CF) = 1.6 kHz.
9.2.2.1 Voltage Monitoring
The ADS1119 can measure single-ended signals ranging from AGND to VREF / Gain. In order to monitor voltages
up to 2 V, the device is configured to use the internal 2.048-V reference and gain = 1.
Equation 6 details the relationship between output codes of the ADS1119 and the input voltage on AIN3.
VAIN3 = (VREF / Gain) · (Code / 215) = 2.048 V · Code / 215
(6)
An external voltage reference must be provided on the external reference inputs of the device in case larger
voltages than 2.048 V are to be monitored. The device can measure input signals up to the positive analog
supply voltage in case AVDD is used as the positive reference input (REFP) and AGND as the negative
reference input (REFN). However the ADS1119 cannot monitor its own supply voltage in that case. As described
in Equation 6, when using VAIN3 = AVDD and VREF = AVDD, the device will always output a positive full-scale
code irrespective of the value of AVDD. To monitor the supply of the ADC, use a resistor divider instead to divide
the supply voltage down to below 2.048 V and measure the voltage using the internal reference.
The input-referred peak-to-peak noise of the ADC is ideally a factor smaller than the required measurement
accuracy of ±0.5 mV. At 90 SPS using gain = 1 the ADS1119 offers an input-referred noise of 62.5 µVPP, which
meets this requirement.
9.2.2.2 High-Side Current Measurement
The unidirectional, high-side load current measurement is implemented using a shunt resistor, RShunt, and a
current-sense amplifier, INA180, with a gain of 100. To meet the requirement of a maximum voltage drop across
RShunt of 20 mV at the maximum current of 10 A, the shunt resistor must be RShunt ≤ 20 mV / 10 A = 2 mΩ. The
output signal of the INA180 is fed single-endedly to input AIN2 of the ADS1119. Consequently, the voltage at
AIN2 ranges from 0 V to (2 mΩ · 10 A · 100) = 2 V, which can be measured using the internal 2.048-V reference
and gain = 1 of the ADC.
Equation 7 through Equation 9 describe the relationship between output codes of the ADS1119 and the current
across the shunt resistor.
VAIN2 = (VREF / GainADC) · (Code / 215) = 2.048 V · Code / 215
VShunt = VAIN2 / GainINA = VAIN2 / 100
IShunt = VShunt / RShunt = (VREF · Code) / (GainADC· GainINA · RShunt · 215) = (2.048 V · Code) / (100 · 2 mΩ · 215)
(7)
(8)
(9)
9.2.2.3 Thermistor Measurement
The temperature measurement using a 10-kΩ thermistor is implemented using a ratiometric measurement
approach to achieve best accuracy. The analog supply voltage, AVDD, is used as the excitation voltage for the
thermistor in a resistor divider configuration, as well as the external reference voltage, VREF, for the ADS1119.
The relationship between output codes of the ADS1119 and the thermistor resistance, RThermistor, is derived using
the following equations. Equation 10 expresses the input voltage at input AIN0 as the voltage across RThermistor,
whereas Equation 11 shows how the ADC converts the voltage at AIN0 into corresponding digital codes.
VAIN0 = RThermistor / (RThermistor + RREF) · VREF
VAIN0 = (VREF / Gain) · (Code / 215)
(10)
(11)
Setting Equation 10 equal to Equation 11 and solving for RThermistor yields the relationship between thermistor
resistance and ADC code.
RThermistor / (RThermistor + RREF) = Gain · (Code / 215)
RThermistor = RREF · Gain · (Code / 215) / [1 – Gain · (Code / 215)]
(12)
(13)
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Equation 13 proves that the output code and thus the accuracy of the thermistor measurement is independent of
the excitation voltage. The accuracy of the reference resistor, RREF, is typically dominating the measurement
accuracy in such a ratiometric circuit implementation. A high-precision, low-drift resistor is therefore required for
RREF. For best performance, the value of RREF is chosen such that the ratio between RREF and RThermistor_Max
equals the ratio between RThermistor_Min and RREF. Equation 14 is therefore used to calculate RREF.
RREF² = RThermistor_Min · RThermistor_Max
(14)
At the two temperature measurement extremes, –40°C and +125°C, a typical 10-kΩ NTC exhibits a resistance of
RThermistor_Max = 239.8 kΩ and RThermistor_Min = 425.3 Ω, respectively. Using Equation 14, RREF calculates to
10.1 kΩ. A 10-kΩ resistor is chosen for this example. Consequently, when using Equation 10, the voltage at the
ADC input ranges from 0.13 V to 3.17 V. Thus, an ADC gain = 1 must be used for the measurement.
The microcontroller interfacing to the ADS1119 converts RThermistor into a corresponding thermistor temperature
by either solving the Steinhart-Hart equation or leveraging a look-up table.
9.2.2.4 Register Settings
Table 13 summarizes the configuration register bit settings used for the different measurements in this example.
Table 13. Configuration Register Settings
MEASUREMENT
BIT SETTINGS
Voltage
1100 0100
AIN3:AGND, gain = 1, DR = 90 SPS, single-shot conversion mode, internal VREF
DESCRIPTION
Current
1010 0100
AIN2:AGND, gain = 1, DR = 90 SPS, single-shot conversion mode, internal VREF
Thermistor
0000 0101
AIN0:AIN1, gain = 1, DR = 90 SPS, single-shot conversion mode, external VREF
9.2.3 Application Curve
Figure 46 shows the measurement results for the voltage measurement on AIN3. The measurements are taken
at TA = 25°C. The black curve shows the measurement error in mV without any offset and gain calibration. The
red curve shows the measurement error after offset and gain calibration. The gain calibration removes both the
gain error and the error introduced by the initial inaccuracy of the internal voltage reference.
0.2
Measurement Error (mV)
0
-0.2
-0.4
-0.6
-0.8
Before Calibration
After Calibration
-1
0
0.2
0.4
0.6
0.8
1
1.2
VAIN3 (V)
1.4
1.6
1.8
2
Figure 46. Measurement Error of Voltage Measurement
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10 Power Supply Recommendations
The device requires two power supplies: analog (AVDD, AGND) and digital (DVDD, DGND). The analog power
supply is independent of the digital power supply. The digital supply sets the digital I/O levels.
10.1 Power-Supply Sequencing
The power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed the
respective analog or digital power-supply voltage and current limits. Wait approximately 500 µs after all power
supplies are stabilized before communicating with the device to allow the power-on reset process to complete.
10.2 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. As shown in Figure 47, AVDD and
DVDD must be decoupled with at least a 0.1-µF capacitor. Place the bypass capacitors as close to the powersupply pins of the device as possible using low-impedance connections. TI recommends using multi-layer
ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL)
characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise
environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise
immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to
ground planes. Connect analog and digital grounds together as close to the device as possible.
1 A0
SCL 16
2 A1
SDA 15
3 RESET
3.3 V
DRDY 14
DVDD 13
4 DGND
Device
5 AGND
AVDD 12
6 AIN3
AIN0 11
7 AIN2
AIN1 10
8 REFN
3.3 V
0.1 PF
0.1 PF
REFP 9
Figure 47. Power-Supply Decoupling
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11 Layout
11.1 Layout Guidelines
Employing best design practices is recommended when laying out a printed-circuit board (PCB) for both analog
and digital components. This recommendation generally means that the layout separates analog components
[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital
components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate
arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching
regulators].
The following basic recommendations for layout of the ADS1119 help achieve the best possible performance of
the ADC. A good design can be ruined with a bad circuit layout.
• Separate analog and digital signals. To start, partition the board into analog and digital sections where the
layout permits. Routing digital lines away from analog lines prevents digital noise from coupling back into
analog signals.
• The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but is not necessary.
Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in the
layout, the split between the analog and digital grounds must be connected together at the ADC.
• Fill void areas on signal layers with ground fill.
• Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground
plane is cut or has other traces that block the current from flowing right next to the signal trace, another path
must be found to return to the source and complete the circuit. If forced into a larger path, the chance that the
signal radiates increases. Sensitive signals are more susceptible to EMI interference.
• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass
capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active
device yields the best results.
• Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react
with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source
signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI
pickup and reduces the high-frequency impedance at the input of the device.
• Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor
can create a parasitic thermocouple that can add an offset to the measurement. Differential inputs must be
matched for both the inputs going to the measurement source.
• Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best
input combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 and
AIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G
(NPO) that have stable properties and low noise characteristics.
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REFP
REFN
11.2 Layout Example
Vias connect to either the bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
(GND = AGND = DGND).
AIN1
AIN2
AIN0
10: AIN1
7: AIN2
11: AIN0
6: AIN3
12: AVDD
5: AGND
13: DVDD
4: DGND
14: DRDY
3: RESET
15: SDA
2: A1
16: SCL
1: A0
DRDY
SCL
SDA
A0
DVDD
AIN3
RESET
8: REFN
A1
AVDD
9: REFP
Figure 48. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, INAx180 Low- and High-Side Voltage Output, Current-Sense Amplifiers data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
NXP Semiconductors is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS1119IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS1119
ADS1119IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS1119
ADS1119IPWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS1119
ADS1119IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1119
ADS1119IRTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1119
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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