ADS1130IPWR

ADS1130 AD S11 30 www.ti.com SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 18-Bit Analog-to-Digital Converter For Bridge Sensors Check for Samples: ADS1130 FEATURES DESCRIPTION • • • • • • The ADS1130 is a precision, 18-bit analog-to-digital converter (ADC). With an onboard low-noise gain amplifier, onboard oscillator, and precision 18-bit delta-sigma ADC, the ADS1130 provides a complete front-end solution for bridge sensor applications including weigh scales and strain gauges. 1 2 • • • • • 18-Bit Noise-Free Resolution Complete Front-End for Bridge Sensor Onboard Gain of 64 Onboard Oscillator Selectable 10SPS or 80SPS Data Rates Simultaneous 50Hz and 60Hz Rejection at 10SPS External Voltage Reference up to 5V for Ratiometric Measurements Simple, Pin-Driven Control Two-Wire Serial Digital Interface Tiny TSSOP-16 Package Supply Range: 2.7V to 5.3V APPLICATIONS • • Weigh Scales Strain Gauges The low-noise amplifier has a gain of 64, supporting a full-scale differential input of ±39mV. The delta-sigma ADC has 18-bit effective resolution and is comprised of a third-order modulator and fourth-order digital filter. Two data rates are supported: 10SPS (with both 50Hz and 60Hz rejection) and 80SPS. The ADS1130 can be put into a low-power standby mode or shut off completely in power-down mode. All of the features of the ADS1130 are controlled by dedicated pins; there are no digital registers to program. Data are output over an easily-isolated serial interface that connects directly to the MSP430 and other microcontrollers. The ADS1130 is available in a TSSOP-16 package and is specified for operation from –40°C to +85°C. AVDD CAP REFP REFN DVDD PDWN AINP DRDY/DOUT DS ADC Gain = 64 SCLK AINN SPEED Internal Oscillator AGND CAP DGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2012, Texas Instruments Incorporated ADS1130 SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS1130 UNIT AVDD to AGND –0.3 to +6 V DVDD to DGND –0.3 to +6 V AGND to DGND –0.3 to +0.3 V 100, momentary mA 10, continuous mA Analog input voltage to AGND –0.3 to AVDD + 0.3 V Digital input voltage to DGND –0.3 to DVDD + 0.3 V +150 °C Operating temperature range –40 to +85 °C Storage temperature range –60 to +150 °C Input current Maximum junction temperature (1) 2 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 ADS1130 www.ti.com SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS All specifications at TA = +25°C, AVDD = DVDD = REFP = +5V, and REFN = AGND, unless otherwise noted. ADS1130 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage (AINP – AINN) ±0.5VREF/64 Common-mode input range AGND + 1.5V Differential input current V AVDD – 1.5V V ±2 nA SPEED = high 80 SPS SPEED = low 10 SPS 4 Conversions SYSTEM PERFORMANCE Resolution No missing codes Data rate Digital filter settling time Full settling Integral nonlinearity (INL) Differential input, end-point fit 18 Bits ±20 ppm of FSR Input offset error ±120 ppm of FSR Input offset drift ±10 nV/°C Gain error ±1 % Gain drift ±5 ppm/°C 90 dB Normal-mode rejection fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS Common-mode rejection at dc 100 dB fDATA = 10SPS 300 nVPP (1) fDATA = 80SPS 500 nVPP (1) at dc 100 dB Input-referred noise Power-supply rejection VOLTAGE REFERENCE INPUT Voltage reference input (VREF) AVDD + 0.1V V Negative reference input (REFN) VREF = REFP – REFN AGND – 0.1 1.5 REFP – 1.5 V Positive reference input (REFP) REFN + 1.5 AVDD + 0.1 Voltage reference input current AVDD V 10 nA DIGITAL Logic levels VIH 0.7 DVDD DVDD + 0.1 V VIL DGND 0.2 DVDD V VOH IOH = 1mA VOL IOL = 1mA Input leakage DVDD – 0.4 V 0 < VIN < DVDD Serial clock input frequency (fSCLK) 0.2 DVDD V ±10 μA 5 MHz POWER SUPPLY Power-supply voltage (AVDD, DVDD) Analog supply current Digital supply current Power dissipation, total 5.3 V Normal mode, AVDD = 3V 2.7 900 1500 μA Normal mode, AVDD = 5V 900 1500 μA Standby mode 0.1 1 μA Power-down 0.1 1 μA Normal mode, DVDD = 3V 60 100 μA Normal mode, DVDD = 5V 95 150 μA Standby mode, SCLK = high, DVDD = 3V 45 70 μA Standby mode, SCLK = high, DVDD = 5V 65 80 μA Power-down 0.2 μA Normal mode, AVDD = DVDD = 3V 2.9 mW Normal mode, AVDD = DVDD = 5V 5.0 mW Standby mode, AVDD = DVDD = 5V 0.3 mW TEMPERATURE Operating temperature range –40 +85 °C Specified temperature range –40 +85 °C (1) PP signifies peak-to-peak noise. Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 3 ADS1130 SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 www.ti.com PIN CONFIGURATION PW PACKAGE TSSOP-16 (TOP VIEW) DVDD 1 16 DRDY/DOUT DGND 2 15 SCLK DGND 3 14 PDWN DGND 4 13 SPEED ADS1130 CAP 5 12 AVDD CAP 6 11 AGND AINP 7 10 REFP AINN 8 9 REFN PIN DESCRIPTIONS NAME TERMINAL ANALOG/DIGITAL INPUT/OUTPUT DVDD 1 Digital Digital power supply: 2.7V to 5.3V DGND 2-4 Digital Digital ground CAP 5, 6 Analog Gain amplifier bypass capacitor connection AINP 7 Analog input Positive analog input AINN 8 Analog input Negative analog input REFN 9 Analog input Negative reference input REFP 10 Analog input Positive reference input AGND 11 Analog Analog ground AVDD 12 Analog Analog power supply, 2.7V to 5.3V DESCRIPTION Data rate select: SPEED 13 Digital input SPEED DATA RATE 0 10SPS 1 80SPS PDWN 14 Digital input Power-down: Holding this pin low powers down the entire converter and resets the ADC. SCLK 15 Digital input Serial clock: Clock out data on the rising edge. Also used to initiate Sleep mode. See the Standby Mode section for more details. DRDY/DOUT 16 Digital output Dual-purpose output: Data ready: Indicates valid data by going low. Data output: Outputs data, MSB first, on the first rising edge of SCLK. 4 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 ADS1130 www.ti.com SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 OVERVIEW CAP The ADS1130 is a precision, 18-bit ADC that includes a low-noise amplifier, internal oscillator, third-order delta-sigma (ΔΣ) modulator, and fourth-order digital filter. The ADS1130 provides a complete front-end solution for bridge sensor applications such as weigh scales, strain gauges, and pressure sensors. Data can be output at 10SPS for excellent 50Hz and 60Hz rejection, or at 80SPS when higher speeds are needed. The ADS1130 is easy to configure, and all digital control is accomplished through dedicated pins; there are no registers to program. A simple twowire serial interface retrieves the data. 450W RINT AINP 18pF A1 R Gain = 1 F1 R1 A3 RF2 ADC RINT A2 450W AINN 18pF ANALOG INPUTS (AINP, AINN) CAP The input signal to be measured is applied to the input pins AINP and AINN. The ADS1130 accepts differential input signals, but can also measure unipolar signals. LOW-NOISE AMPLIFIER The ADS1130 features a low-drift, low-noise amplifier that provides a complete front-end solution for bridge sensors. A simplified diagram is shown in Figure 1. It consists of two chopper-stabilized amplifiers (A1 and A2) and three accurately-matched resistors (R1, RF1, and RF2), which construct a differential front-end stage with a gain of 64, followed by gain stage A3 (Gain = 1). The inputs are equipped with an electromagnetic interference (EMI) filter, as shown in Figure 1. The cutoff frequency of the EMI filter is 19.6MHz. With a 5V reference, the bipolar input range is –39mV to +39mV. The inputs of the ADS1130 are protected with internal ESD diodes connected to the power-supply rails. Figure 1. Simplified Diagram of the Amplifier Bypass Capacitor Place a 0.1μF external capacitor between the two capacitor pins (CAP). A high-quality capacitor is recommended for best performance. VOLTAGE REFERENCE INPUTS (REFP, REFN) The voltage reference used by the modulator is generated from the voltage difference between REFP and REFN: VREF = REFP – REFN. The reference inputs use a structure similar to that of the analog inputs. In order to increase the reference input impedance, a switching buffer circuitry is used to reduce the input equivalent capacitance. The reference drift and noise impact ADC performance. In order to achieve best results, pay close attention to the reference noise and drift specifications. A simplified diagram of the circuitry on the reference inputs is illustrated in Figure 2. The switches and capacitors can be modeled approximately using an effective impedance of: 1 Z EFF + 2f MODC BUF Where: fMOD = modulator sampling frequency (76.8kHz) CBUF = input capacitance of the buffer Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 5 ADS1130 SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 www.ti.com For the ADS1130: 1 Z EFF + + 500MW (2)(76.8kHz)(13fF) 0 -20 -40 -60 REFN Gain (dB) REFP -80 -100 -120 -140 AVDD AVDD -160 ESD Protection -180 -200 CBUF 0 (1) ZEFF = 500MW 38.4 76.8 Frequency (kHz) Figure 3. Frequency Response (1) fMOD = 76.8kHz. 0 Data Rate = 10SPS Figure 2. Simplified Reference Input Circuitry -50 Gain (dB) ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise, do not exceed AVDD by 100mV: -100 GND – 100mV < (REFP or REFN) < AVDD + 100mV FREQUENCY RESPONSE -150 0 The ADS1130 uses a sinc4 digital filter with the frequency response shown in Figure 3. The frequency response repeats at multiples of the modulator sampling frequency of 76.8kHz. The overall response is that of a low-pass filter with a –3dB cutoff frequency of 3.32Hz with the SPEED pin tied low (10SPS data rate) and 11.64Hz with the SPEED pin tied high (80SPS data rate). The benefit of using a sinc4 filter is that every frequency notch has four zeros on the same location. This response, combined with the low-drift internal oscillator, provides an excellent normal-mode rejection of line-cycle interference. Figure 4(b) shows the same plot, but enlarges the view at the 50Hz and 60Hz notches with the SPEED pin tied low (10SPS data rate). 6 20 30 40 50 60 70 80 90 100 Frequency (Hz) (a) -50 Data Rate = 10SPS Gain (dB) To help see the response at lower frequencies, Figure 4(a) illustrates the response out to 100Hz, when the data rate = 10SPS. Notice that signals at multiples of 10Hz are rejected, and therefore simultaneous rejection of 50Hz and 60Hz is achieved. 10 -100 -150 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Frequency (Hz) (b) Figure 4. Frequency Response Out To 100Hz Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 ADS1130 www.ti.com SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 Table 2. Ideal Output Code vs Input Signal(1) SETTLING TIME Large changes in the input signal require settling time. For example, an external multiplexer in front of the ADS1130 can cause large changes in the input voltage when switching the multiplexer input channels. Abrupt changes in the input require four data conversion cycles to settle. When continuously converting, five readings may be necessary in order to settle the data. If the change in input occurs in the middle of the first conversion, four more full conversions of the fully-settled input are required to get fully-settled data. Discard the first four readings because they contain only partially-settled data. Figure 5 illustrates the settling time for the ADS1130 in Continuous Conversion mode. DATA RATE The ADS1130 data rate is set by the SPEED pin, as shown in Table 1. When SPEED is low, the data rate is nominally 10SPS. This data rate provides the lowest noise, and also has excellent rejection of both 50Hz and 60Hz line-cycle interference. For applications requiring fast data rates, setting SPEED high selects a data rate of nominally 80SPS. INPUT SIGNAL VIN (AINP – AINN) IDEAL OUTPUT ≥ +0.5VREF/64 1FFFFh (+0.5VREF/64)/(217 – 1) 00001h 0 00000h 17 (–0.5VREF/64)/(2 3FFFFh – 1) ≤ –0.5VREF/64 40000h (1) Excludes effects of noise, INL, offset, and gain errors. DATA READY/DATA OUTPUT (DRDY/DOUT) This digital output pin serves two purposes. First, it indicates when new data are ready by going low. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, most significant bit (MSB) first. Data are shifted out on each subsequent SCLK rising edge. After all 18 bits have been retrieved, the pin can be forced high with additional SCLKs. It then stays high until new data are ready. This configuration is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. SERIAL CLOCK INPUT (SCLK) Table 1. Data Rate Settings SPEED PIN DATA RATE 0 10SPS 1 80SPS This digital input shifts serial data out with each rising edge. This input has built-in hysteresis, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise and fall times of SCLK are both less than 50ns. DATA FORMAT The ADS1130 outputs 18 bits of data in binary two’s complement format. The least significant bit (LSB) has a weight of (0.5VREF/64)(217 – 1). The positive full-scale input produces an output code of 1FFFFh and the negative full-scale input produces an output code of 40000h. The output clips at these codes for signals exceeding full-scale. Table 2 summarizes the ideal output codes for different input signals. Abrupt Change in External VIN VIN Start of Conversion DRDY/DOUT First Conversion; includes unsettled VIN. Second Conversion; VIN settled, but digital filter unsettled. Third Conversion; VIN settled, but digital filter unsettled. Fourth Conversion; VIN settled, but digital filter unsettled. Fifth Conversion; VIN and digital filter both settled. Conversion Time Figure 5. Settling Time in Continuous Conversion Mode Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 7 ADS1130 SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 www.ti.com DATA RETRIEVAL or else the data are overwritten. Avoid data retrieval during the update period (tUPDATE). To avoid having DRDY/DOUT remain in the state of the last bit, the 24 SCLKs may be applied to force DRDY/DOUT high. This technique is useful when a host controlling the device is polling DRDY/DOUT to determine when data are ready. Do not apply more than 24 SCLKs during data retrieval. The ADS1130 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as shown in Figure 6. After DRDY/DOUT goes low, begin shifting out the data by applying SCLKs. Data are shifted out MSB first. It is not required to shift out all 18 bits of data, but the data must be retrieved before new data are updated (within tCONV) Data New Data Ready Data Ready MSB DRDY/DOUT 17 LSB 16 15 0 tPD tHT tDS SCLK tSCLK tUPDATE 1 18 tSCLK tCONV Figure 6. Data Retrieval Timing SYMBOL tDS tSCLK MIN DRDY/DOUT low to first SCLK rising edge SCLK positive or negative pulse width tHT SCLK rising edge to old data bit valid: hold time 0 Data updating: no readback allowed 39 Conversion time (1/data rate) MAX UNITS ns 100 SCLK rising edge to new data bit valid: propagation delay tCONV TYP 0 tPD tUPDATE 8 DESCRIPTION ns 50 ns ns μs SPEED = 1 12.5 ms SPEED = 0 100 ms Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 ADS1130 www.ti.com SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 STANDBY MODE When tSTANDBY has passed with SCLK held high, Standby mode activates. DRDY/DOUT stays high when Standby mode begins. SCLK must remain high to stay in Standby mode. To exit Standby mode (wakeup), set SCLK low. The first data after exiting Standby mode is valid. Standby mode dramatically reduces power consumption by shutting down most of the circuitry. In Standby mode, the entire analog circuitry is powered down and only the clock source circuitry is awake to reduce the wake-up time from the Standby mode. To enter Standby mode, simply hold SCLK high after DRDY/DOUT goes low; see Figure 7. Standby mode can be initiated at any time during readback. Data Ready Standby Mode DRDY/DOUT SCLK 17 16 15 0 1 Start Conversion 17 18 tDSS tSTANDBY tS_RDY Figure 7. Standby Mode Timing (can be used for single conversions) SYMBOL tDSS tSTANDBY tS_RDY DESCRIPTION MIN MAX UNITS SCLK high after DRDY/DOUT goes low SPEED = 1 to activate Standby mode SPEED = 0 0 12.44 ms 0 99.94 ms SPEED = 1 20 SPEED = 0 20 SPEED = 1 52.51 52.51 ms SPEED = 0 401.8 401.8 ms Standby mode activation time Data ready after exiting Standby mode μs μs Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 9 ADS1130 SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 www.ti.com POWER-UP SEQUENCE blank When powering up the ADS1130, AVDD and DVDD must be powered up before the PDWN pin goes high, as shown in Figure 8. If PDWN is not controlled by a microprocessor, a simple RC delay circuit must be implemented, as shown in Figure 9. POWER-DOWN MODE Power-Down mode shuts down the entire ADC circuitry and reduces the total power consumption close to zero. To enter Power-Down mode, simply hold the PDWN pin low. Power-Down mode also resets the entire circuitry to free the ADC circuitry from locking up to an unknown state. Power-Down mode can be initiated at any time during readback; it is not necessary to retrieve all 18 bits of data beforehand. Figure 10 shows the wake-up timing from Power-Down mode. AVDD DVDD PDWN ³ 10ms Figure 8. Power-Up Timing Sequence DVDD(1) 1.2kW Connect to ADS1130 PDWN pin 2.2nF blank blank (1) AVDD must be powered up at least 10μs before PDWN goes high. blank Figure 9. RC Delay Circuit Start Conversion Power-Down Mode tPDWN Data Ready CLK Source Wakeup PDWN DRDY/DOUT tWAKEUP tTS_RDY SCLK Figure 10. Wake-Up Timing from Power-Down Mode SYMBOL tWAKEUP tPDWN 10 DESCRIPTION MIN Wake-up time after Power-Down mode PDWN pulse width 30 Submit Documentation Feedback TYP UNITS 8 μs μs Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 ADS1130 www.ti.com SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2009) to Revision A • Page Deleted NRND watermark .................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1130IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1130 ADS1130IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1130 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of