ADS1131ID

ADS1131 www.ti.com SBAS449C – JULY 2009 – REVISED OCTOBER 2013 18-Bit Analog-to-Digital Converter for Bridge Sensors Check for Samples: ADS1131 FEATURES DESCRIPTION • • • • • • • • The ADS1131 is a precision, 18-bit analog-to-digital converter (ADC). With an onboard, low-noise amplifier, onboard oscillator, precision 18-bit deltasigma (ΔΣ) ADC, and bridge power switch, the ADS1131 provides a complete front-end solution for bridge sensor applications including weigh scales, strain gauges, and load cells. 1 2 • • • • • Complete Front-End for Bridge Sensors Available in an SO Package Internal Amplifier, Gain of 64 Internal Oscillator Low-Side Power Switch for Bridge Sensor 18-Bit Noise-Free Resolution Selectable 10SPS or 80SPS Data Rates Simultaneous 50Hz and 60Hz Rejection at 10SPS External Voltage Reference up to 5V for Ratiometric Measurements Simple, Pin-Driven Control Two-Wire Serial Digital Interface Supply Range: 3V to 5.3V –40°C to +85°C Temperature Range The low-noise amplifier has a gain of 64, supporting a full-scale differential input of ±39mV. The ΔΣ ADC has 18-bit effective resolution and is comprised of a third-order modulator and fourth-order digital filter. Two data rates are supported: 10SPS (with both 50Hz and 60Hz rejection) and 80SPS. The ADS1131 can be put into a low-power standby mode or shut off completely in power-down mode. The ADS1131 is controlled by dedicated pins; there are no digital registers to program. Data are output over an easily-isolated serial interface that connects directly to the MSP430 and other microcontrollers. APPLICATIONS • • • • The ADS1131 is available in an SO-16 package and is specified from –40°C to +85°C. Weigh Scales Strain Gauges Load Cells Industrial Process Control AVDD CAP CAP VREFP VREFN DVDD PDWN AINP DRDY/DOUT G = 64 DS ADC AINN Internal Oscillator SCLK SPEED SW GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated ADS1131 SBAS449C – JULY 2009 – REVISED OCTOBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE AND ORDERING INFORMATION (1) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS1131 UNIT AVDD to GND –0.3 to +6 V DVDD to GND –0.3 to +6 V 100, momentary mA 10, continuous mA Analog input voltage to GND –0.3 to AVDD + 0.3 V Digital input voltage to GND –0.3 to DVDD + 0.3 V Input current Maximum junction temperature +150 °C Operating temperature range –40 to +85 °C Storage temperature range –60 to +150 °C (1) 2 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 ADS1131 www.ti.com SBAS449C – JULY 2009 – REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C. All specifications at AVDD = DVDD = VREFP = +5V, and VREFN = GND, unless otherwise noted. ADS1131 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage (AINP – AINN) ±0.5VREF/64 V VREF = AVDD = 5V ±39.0 mV VREF = AVDD = 3V ±23.4 mV Common-mode input range GND + 1.5V Differential input current AVDD – 1.5V V ±2 nA LOW-SIDE POWER SWITCH On-resistance (RON) Ω AVDD = 5V, ISW = 30mA 3.5 5 AVDD = 3V, ISW = 30mA 4 7 Ω 30 mA Current through switch SYSTEM PERFORMANCE Resolution No missing codes Data rate 18 Bits SPEED = high 80 SPS SPEED = low 10 SPS Digital filter settling time Full settling 4 Conversions Integral nonlinearity (INL) Differential input, end-point fit ±8 ppm Input offset error 10 μV Input offset drift ±15 nV/°C Gain error 1 % Gain drift ±4 ppm/°C dB Normal-mode rejection fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS 90 Common-mode rejection At dc 110 dB fDATA = 10SPS, AVDD = VREF = 5V 1 LSB fDATA = 80SPS, AVDD = VREF = 5V 1.7 LSB fDATA = 10SPS, AVDD = VREF = 5V 300 nV fDATA = 80SPS, AVDD = VREF = 5V 500 nV At dc 100 dB Noise (peak-to-peak) Power-supply rejection VOLTAGE REFERENCE INPUT Voltage reference input (VREF) AVDD + 0.1V V Negative reference input (VREFN) VREF = VREFP – VREFN AGND – 0.1 1.5 VREFP – 1.5 V Positive reference input (VREFP) VREFN + 1.5 AVDD + 0.1 Voltage reference input current AVDD V 10 nA DIGITAL INPUT/OUTPUT (DVDD = 2.7V to 5.3V) Logic levels VIH 0.8 DVDD DVDD + 0.1 V VIL GND 0.2 DVDD V VOH IOH = 500μA VOL IOL = 500μA Input leakage DVDD – 0.4 0 < VDIGITAL INPUT < DVDD Serial clock input frequency (fSCLK) V 0.2 DVDD V ±10 μA 5 MHz Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 3 ADS1131 SBAS449C – JULY 2009 – REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C. All specifications at AVDD = DVDD = VREFP = +5V, and VREFN = GND, unless otherwise noted. ADS1131 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY Power-supply voltage (AVDD, DVDD) Analog supply current Digital supply current Power dissipation, total 3 5.3 V Normal mode, AVDD = 3V 900 μA Normal mode, AVDD = 5V 900 μA Standby mode 0.1 μA Power-down 0.1 μA Normal mode, DVDD = 3V 60 μA Normal mode, DVDD = 5V 95 μA Standby mode, SCLK = high, DVDD = 3V 45 μA Standby mode, SCLK = high, DVDD = 5V 65 μA Power-down 0.2 μA Normal mode, AVDD = DVDD = 3V 2.9 mW Normal mode, AVDD = DVDD = 5V 5.0 mW TEMPERATURE Operating temperature range –40 +85 °C Specified temperature range –40 +85 °C THERMAL INFORMATION ADS1131D THERMAL METRIC (1) D UNITS 16 PINS θJA Junction-to-ambient thermal resistance 133.8 θJC(top) Junction-to-case(top) thermal resistance 71.4 θJB Junction-to-board thermal resistance 60.0 ψJT Junction-to-top characterization parameter 17.4 ψJB Junction-to-board characterization parameter 53.3 θJC(bottom) Junction-to-case(bottom) thermal resistance n/a (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 ADS1131 www.ti.com SBAS449C – JULY 2009 – REVISED OCTOBER 2013 PIN CONFIGURATION D PACKAGE SO-16 (TOP VIEW) DVDD 1 16 DRDY/DOUT GND 2 15 SCLK GND 3 14 PDWN SPEED 4 13 AVDD CAP 5 12 SW CAP 6 11 GND AINP 7 10 VREFP AINN 8 9 VREFN PIN DESCRIPTIONS NAME TERMINAL ANALOG/DIGITAL INPUT/OUTPUT DVDD 1 Digital Digital power supply GND 2 Supply Ground for digital and analog supplies GND 3 Supply Ground for digital and analog supplies DESCRIPTION Data rate select: SPEED 4 CAP 5 CAP AINP Digital input SPEED DATA RATE 0 10SPS 1 80SPS Analog Gain amplifier bypass capacitor connection 6 Analog Gain amplifier bypass capacitor connection 7 Analog input Positive analog input AINN 8 Analog input Negative analog input VREFN 9 Analog input Negative reference input VREFP 10 Analog input Positive reference input GND 11 Supply Ground for digital and analog supplies SW 12 Analog Low-side power switch AVDD 13 Supply Analog power supply PDWN 14 Digital input Power-down: holding this pin low powers down the entire converter and resets the ADC. SCLK 15 Digital input Serial clock: clock out data on the rising edge. Also used to initiate Standby mode. See the Standby Mode section for more details. DRDY/DOUT 16 Digital output Dual-purpose output: Data ready: indicates valid data by going low. Data output: outputs data, MSB first, on the first rising edge of SCLK. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 5 ADS1131 SBAS449C – JULY 2009 – REVISED OCTOBER 2013 www.ti.com OVERVIEW The ADS1131 is a precision, 18-bit ADC that includes a low-noise PGA, internal oscillator, third-order deltasigma (ΔΣ) modulator, and fourth-order digital filter. The ADS1131 provides a complete front-end solution for bridge sensor applications such as weigh scales, strain gauges, and pressure sensors. Data can be output at 10SPS for excellent 50Hz and 60Hz rejection, or at 80SPS when higher speeds are needed. The ADS1131 is easy to configure, and all digital control is accomplished through dedicated pins; there are no registers to program. A simple twowire serial interface retrieves the data. –39mV to +39mV, and the unipolar input ranges from 0mV to +39mV. The inputs of the ADS1131 are protected with internal diodes connected to the power-supply rails. These diodes clamp the applied signal to prevent it from damaging the input circuitry. CAP 450W RINT AINP 18pF A1 R Gain = 1 F1 R1 ANALOG INPUTS (AINP, AINN) A3 RF2 The input signal to be measured is applied to the input pins AINP and AINN. The ADS1131 accepts differential input signals, but can also measure unipolar signals. When measuring unipolar (or singleended signals) with respect to ground, connect the negative input (AINN) to ground and connect the input signal to the positive input (AINP). Note that when the ADS1131 is configured this way, only half of the converter full-scale range is used, because only positive digital output codes are produced. ADC RINT A2 450W AINN 18pF CAP Figure 1. Simplified Diagram of the Amplifier LOW-NOISE AMPLIFIER External Capacitor The ADS1131 features a low-drift, low-noise amplifier that provides a complete front-end solution for bridge sensors. A simplified diagram of the amplifier is shown in Figure 1. It consists of two chopperstabilized amplifiers (A1 and A2) and three accurately matched resistors (R1, RF1, and RF2) that construct a differential front-end stage with a gain of 64, followed by gain stage A3 (Gain = 1). The inputs are equipped with an EMI filter, as shown in Figure 1. The cutoff frequency of the EMI filter is 20MHz. By using AVDD as the reference input, the bipolar input ranges from An external capacitor (CEXT) across the ADS1131 two CAP pins combines with the internal resistor RINT (onchip) to create a low-pass filter. The recommended value for CEXT is 0.1μF which provides a corner frequency of 720Hz. This low-pass filter serves two purposes. First, the input signal is bandlimited to prevent aliasing by the ADC and to filter out the highfrequency noise. Second, it attenuates the chopping residue from the amplifier to improve temperature drift performance. NPO or C0G capacitors are recommended. For optimal performance, place the external capacitor very close to the CAP pins. 6 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 ADS1131 www.ti.com SBAS449C – JULY 2009 – REVISED OCTOBER 2013 VOLTAGE REFERENCE INPUTS (VREFP, VREFN) LOW-SIDE POWER SWITCH (SW) The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs. In order to increase the reference input impedance, a switching buffer circuitry is used to reduce the input equivalent capacitance. The reference drift and noise impact ADC performance. In order to achieve best results, pay close attention to the reference noise and drift specifications. A simplified diagram of the circuitry on the reference inputs is shown in Figure 2. The switches and capacitors can be modeled approximately using an effective impedance of: ZEFF = 500MW VREFP The ADS1131 incorporates an internal switch for use with an external bridge sensor, as shown in Figure 3. The switch can be used in a return path for the bridge power. By opening the switch, power dissipation in the bridge is eliminated. The switch is controlled by the ADS1131 conversion status. During normal conversions, the switch is closed (the SW pin is connected to GND). During standby or power-down modes, the switch is opened (the SW pin is high impedance). When using the switch, it is recommended that the negative reference input (VREFN) be connected directly to the bridge ground terminal, as shown in Figure 3 for best performance. +VDD VREFN ADS1131 VREFP AVDD AVDD Bridge Sensor AINP ESD Protection CBUF AINN ZEFF = 500MW VREFN SW Figure 2. Simplified Reference Input Circuitry GND ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise, do not exceed AVDD by 100mV: CLOCK SOURCE GND – 100mV < (VREFP or VREFN) < AVDD + 100mV The ADS1131 uses an internal oscillator. No external clock circuitry is required. Figure 3. Low-Side Power Switch Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 7 ADS1131 SBAS449C – JULY 2009 – REVISED OCTOBER 2013 www.ti.com FREQUENCY RESPONSE 0 Data Rate = 10SPS 4 -50 Gain (dB) The ADS1131 uses a sinc digital filter with the frequency response. The frequency response repeats at multiples of the modulator sampling frequency of 76.8kHz. The overall response is that of a low-pass filter with a –3dB cutoff frequency of 3.32Hz with the SPEED pin tied low (10SPS data rate) and 11.64Hz with the SPEED pin tied high (80SPS data rate). -100 To help see the response at lower frequencies, Figure 4(a) illustrates the nominal response out to 100Hz, when the data rate = 10SPS. Notice that signals at multiples of 10Hz are rejected, and therefore simultaneous rejection of 50Hz and 60Hz is achieved. -150 0 20 30 40 50 60 70 80 90 100 Frequency (Hz) (a) The benefit of using a sinc4 filter is that every frequency notch has four zeros on the same location. This response, combined with the low drift internal oscillator, provides an excellent normal-mode rejection of line-cycle interference. -50 Data Rate = 10SPS Gain (dB) Figure 4(b) zooms in on the 50Hz and 60Hz notches with the SPEED pin tied low (10SPS data rate). 10 -100 -150 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Frequency (Hz) (b) Figure 4. Nominal Frequency Response Out To 100Hz 8 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 ADS1131 www.ti.com SBAS449C – JULY 2009 – REVISED OCTOBER 2013 Table 1. Data Rate Settings SETTLING TIME Fast changes in the input signal require time to settle. For example, an external multiplexer in front of the ADS1131 can generate abrupt changes in input voltage by simply switching the multiplexer input channels. These sorts of changes in the input require four data conversion cycles to settle. When continuously converting, five readings may be necessary in order to settle the data. If the change in input occurs in the middle of the first conversion, four more full conversions of the fully-settled input are required to obtain fully-settled data. Discard the first four readings because they contain only partiallysettled data. Figure 5 illustrates the settling time for the ADS1131. SPEED PIN DATA RATE 0 10SPS 1 80SPS DATA FORMAT The ADS1131 outputs 18 bits of data in binary twos complement format. The least significant bit (LSB) has a weight of (0.5VREF/64)(217 – 1). The positive full-scale input produces an output code of 1FFFFh and the negative full-scale input produces an output code of 20000h. The output clips at these codes for signals exceeding full-scale. Table 2 summarizes the ideal output codes for different input signals. Table 2. Ideal Output Code vs Input Signal DATA RATE The ADS1131 data rate is set by the SPEED pin, as shown in Table 1. When SPEED is low, the data rate is nominally 10SPS. This data rate provides the lowest noise, and also has excellent rejection of both 50Hz and 60Hz line-cycle interference. For applications requiring fast data rates, setting SPEED high selects a data rate of nominally 80SPS. INPUT SIGNAL VIN (AINP – AINN) IDEAL OUTPUT ≥ +0.5VREF/64 1FFFFh (+0.5VREF/64)/(217 – 1) 00001h 0 00000h (–0.5VREF/64)/(217 – 1) 3FFFFh ≤ –0.5VREF/64 20000h 1. Excludes effects of noise, INL, offset, and gain errors. Abrupt Change in VIN VIN Start of Conversion DRDY/DOUT 1st Conversion; includes unsettled VIN. 2nd Conversion; VIN settled, but digital filter unsettled. 3rd Conversion; VIN settled, but digital filter unsettled. 4th Conversion; VIN settled, but digital filter unsettled. 5th Conversion; VIN and digital filter both settled. Conversion Time Figure 5. Settling Time in Continuous Conversion Mode Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 9 ADS1131 SBAS449C – JULY 2009 – REVISED OCTOBER 2013 www.ti.com DATA READY/DATA OUTPUT (DRDY/DOUT) DATA RETRIEVAL This digital output pin serves two purposes. First, it indicates when new data are ready by going low. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, most significant bit (MSB) first. Data are shifted out on each subsequent SCLK rising edge. After all 18 bits have been retrieved, the pin can be forced high with an additional SCLK. It then stays high until new data are ready. This configuration is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. The ADS1131 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as shown in Figure 6. After DRDY/DOUT goes low, begin shifting out the data by applying SCLKs. Data are shifted out MSB first. It is not required to shift out all 18 bits of data, but the data must be retrieved before new data are updated (within tCONV) or else the data will be overwritten. Avoid data retrieval during the update period (tUPDATE). If only 18 SCLKs have been applied, DRDY/DOUT remains at the state of the last bit shifted out until it is taken high (see tUPDATE), indicating that new data are being updated. To avoid having DRDY/DOUT remain in the state of the last bit, the 19th SCLK can be applied to force DRDY/DOUT high, as shown in Figure 7. This technique is useful when a host controlling the device is polling DRDY/DOUT to determine when data are ready. SERIAL CLOCK INPUT (SCLK) This digital input shifts serial data out with each rising edge. This input has built-in hysteresis, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise and fall times of SCLK are both less than 50ns. Data New Data Ready Data Ready MSB DRDY/DOUT 17 LSB 16 15 0 tPD tHT tDS tSCLK tUPDATE 1 SCLK 18 tSCLK tCONV Figure 6. 18-Bit Data Retrieval Timing SYMBOL tDS tSCLK tPD (1) tHT (1) tUPDATE tCONV DESCRIPTION MIN DRDY/DOUT low to first SCLK rising edge SCLK positive or negative pulse width TYP ns ns 50 20 ns ns 90 μs SPEED = 1 12.5 ms SPEED = 0 100 ms Data updating: no readback allowed Conversion time (1/data rate) UNITS 100 SCLK rising edge to new data bit valid: propagation delay SCLK rising edge to old data bit valid: hold time MAX 0 (1) Minimum required from simulation. 10 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 ADS1131 www.ti.com SBAS449C – JULY 2009 – REVISED OCTOBER 2013 STANDBY MODE When tSTANDBY has passed with SCLK held high, Standby mode activates. DRDY/DOUT stays high when Standby mode begins. SCLK must remain high to stay in Standby mode. To exit Standby mode (wakeup), set SCLK low. The first data after exiting Standby mode are valid. Standby mode dramatically reduces power consumption by shutting down most of the circuitry. In Standby mode, the entire analog circuitry is powered down and only the clock source circuitry is awake to reduce the wake-up time from the Standby mode. To enter Standby mode, simply hold SCLK high after DRDY/DOUT goes low; see Figure 8. Standby mode can be initiated at any time during readback; it is not necessary to retrieve all 18 bits of data beforehand. Data Data Ready New Data Ready DRDY/DOUT 17 16 15 0 1 SCLK 18 19 19th SCLK to Force DRDY/DOUT High Figure 7. Data Retrieval with DRDY/DOUT Forced High Afterwards Data Ready Standby Mode DRDY/DOUT SCLK 17 16 15 1 0 Start Conversion 17 18 tDSS tSTANDBY tS_RDY Figure 8. Standby Mode Timing (Can be used for single conversions) SYMBOL DESCRIPTION tDSS (1) SCLK high after DRDY/DOUT goes low to activate Standby mode tSTANDBY Standby mode activation time tS_RDY (1) MAX UNITS SPEED = 1 MIN 12.44 ms SPEED = 0 99.94 ms SPEED = 1 0.0125 SPEED = 0 0.1 Data ready after exiting Standby SPEED = 1 mode SPEED = 0 TYP s s No change (typical time required) ms 401.8 ms (1) Based on an ideal internal oscillator. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 11 ADS1131 SBAS449C – JULY 2009 – REVISED OCTOBER 2013 www.ti.com POWER-DOWN MODE Power-Down mode shuts down the entire ADC circuitry and reduces the total power consumption close to zero. To enter Power-Down mode, simply hold the PDWN pin low. Power-Down mode also resets the entire circuitry. Power-Down mode can be initiated at any time during readback; it is not necessary to retrieve all 18 bits of data beforehand. Figure 9 shows the wake-up timing from Power-Down mode. Start Conversion Power-Down Mode tPDWN Data Ready CLK Source Wakeup PDWN DRDY/DOUT tTS_RDY tWAKEUP SCLK Figure 9. Wake-Up Timing from Power-Down Mode SYMBOL tWAKEUP (1) tPDWN (1) DESCRIPTION MIN Wake-up time after Power-Down mode PDWN pulse width (1) Based on an ideal internal oscillator. 12 Submit Documentation Feedback 26 TYP UNITS 7.95 μs μs Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 ADS1131 www.ti.com SBAS449C – JULY 2009 – REVISED OCTOBER 2013 APPLICATION EXAMPLE Weigh Scale System Figure 10 shows a typical ADS1131 application as part of a weigh scale system. 2.7V to 5.3V 3V (1) 1 mF 13 AVDD 10 5 - VREFP CAP DRDY/DOUT 0.1mF 6 SCLK CAP + ADS1131 7 8 VDD DVDD (2) Load Cell (1) 1mF 1 PDWN SPEED AINP 16 15 14 4 MSP430x4xx or Other Microprocessor AINN 9 VREFN 12 SW GND GND 2, 3, 11 (1) Place a 0.1μF or higher capacitor as close as possible on both AVDD and DVDD. (2) Place capacitor very close to the ADS1131 CAP pins for optimal performance. Figure 10. Weigh Scale Example Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 13 ADS1131 SBAS449C – JULY 2009 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2011) to Revision C Page • Changed pin 12 name from PSW to SW in pinout drawing ................................................................................................. 5 • Changed pin 12 name from PSW to SW in Pin Descriptions table ...................................................................................... 5 • Changed pin numbers in Figure 10 to match the device pinout ......................................................................................... 13 Changes from Revision A (May 2010) to Revision B Page • Changed Supply Range Features bullet ............................................................................................................................... 1 • Deleted ESD Ratings row and footnote 2 from Absolute Maximum Ratings table ............................................................... 2 • Changed Digital Input/Output, VIH Logic level parameter minimum specification in Electrical Characteristics table ........... 3 • Changed Power Supply, Power-supply voltage parameter minimum specification in Electrical Characteristics table ........ 4 • Deleted Power Supply, Analog supply current parameter maximum specifications in Electrical Characteristics table ....... 4 • Deleted Power Supply, Digital supply current parameter maximum specifications in Electrical Characteristics table ........ 4 • Deleted Power Supply, Power dissipation parameter maximum specifications in Electrical Characteristics table .............. 4 • Deleted minimum specification and added typical specification to tUPDATE row of table corresponding to Figure 6 ........... 10 • Deleted Power-Up Sequence section ................................................................................................................................. 12 14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADS1131 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1131ID ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1131 ADS1131IDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1131 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of