ADS1148IRHBR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 ADS114x 16-Bit, 2-kSPS, Analog-to-Digital Converters With Programmable Gain Amplifier (PGA) for Sensor Measurement 1 Features 3 Description • • • The ADS1146, ADS1147, and ADS1148 devices are precision, 16-bit analog-to-digital converters (ADCs) that include many integrated features to reduce system cost and component count for sensor measurement applications. The devices feature a low-noise, programmable gain amplifier (PGA), a precision delta-sigma (ΔΣ) ADC with a single-cycle settling digital filter, and an internal oscillator. The ADS1147 and ADS1148 devices also provide a builtin, low-drift voltage reference, and two matched programmable excitation current sources (IDACs). 1 • • • • • • • • • • • • Programmable Data Rates Up to 2 kSPS Single-Cycle Settling for All Data Rates Simultaneous 50-Hz and 60-Hz Rejection at 20 SPS Analog Multiplexer With 8 (ADS1148) and 4 (ADS1147) Independently Selectable Inputs Programmable Gain: 1 V/V to 128 V/V Dual-Matched Programmable Excitation Current Sources Low-Drift Internal 2.048-V Reference Sensor Burnout Detection 4 or 8 General-Purpose I/Os (ADS1147 and ADS1148) Internal Temperature Sensor Power Supply and VREF Monitoring (ADS1147 and ADS1148) Self and System Calibration SPI™-Compatible Serial Interface Analog Supply: Unipolar (2.7 V to 5.25 V) or Bipolar (±2.5 V) Digital Supply: 2.7 V to 5.25 V 2 Applications • • • • Temperature Measurement – RTDs, Thermocouples, and Thermistors Pressure Measurement Flow Meters Factory Automation and Process Control An input multiplexer supports four differential inputs for the ADS1148, two for the ADS1147, and one for the ADS1146. In addition, the multiplexer integrates sensor burn-out detection, voltage bias for thermocouples, system monitoring, and general purpose digital I/Os (ADS1147 and ADS1148). The PGA provides selectable gains up to 128 V/V. These features provide a complete front-end solution for temperature sensor measurement applications including thermocouples, thermistors, and resistance temperature detectors (RTDs) and other small signal measurements including resistive bridge sensors. The digital filter settles in a single cycle to support fast channel cycling when using the input multiplexer and provides data rates up to 2 kSPS. For data rates of 20 SPS or less, both 50-Hz and 60-Hz interference are rejected by the filter. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADS1146 TSSOP (16) 5.00 mm × 4.40 mm ADS1147 TSSOP (20) 6.50 mm × 4.40 mm TSSOP (28) 9.70 mm × 4.40 mm VQFN (32) 5.00 mm × 5.00 mm ADS1148 (1) For all available packages, see the orderable addendum at the end of the datasheet. Functional Block Diagrams AVDD REFP REFN REFP0/ REFN0/ AVDD GPIO0 GPIO1 DVDD Burnout Detect Burnout Detect ADS1146 ADS1148 Only REFP1 REFN1 VREFOUT VREFCOM VREF Mux VBIAS VBIAS DVDD Voltage Reference ADS1147 ADS1148 Adjustable Digital Filter Serial Interface And Control GPIO AINP Input Mux AINN PGA 3rd Order û Modulator Adjustable Digital Filter Serial Interface And Control Internal Oscillator SCLK AIN0/IEXC DIN AIN1/IEXC DRDY DOUT/ DRDY AIN3/IEXC/GPIO3 CS START AIN4/IEXC/GPIO4 RESET AIN6/IEXC/GPIO6 SCLK System Monitor AIN2/IEXC/GPIO2 Input Mux PGA DIN 3rd Order û Modulator AIN5/IEXC/GPIO5 Dual IDACs AIN7/IEXC/GPIO7 DRDY DOUT/ DRDY CS START RESET Internal Oscillator ADS1148 Only Burnout Detect Burnout Detect AVSS CLK DGND AVSS IEXC1 IEXC2 ADS1148 Only CLK DGND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 1 1 1 2 4 5 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 8 Electrical Characteristics........................................... 9 Timing Requirements .............................................. 11 Switching Characteristics ........................................ 11 Typical Characteristics ............................................ 13 8 Parameter Measurement Information ................ 15 9 Detailed Description ............................................ 16 8.1 Noise Performance ................................................. 15 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ 16 16 17 28 9.5 Programming........................................................... 33 9.6 Register Maps ......................................................... 42 10 Application and Implementation........................ 62 10.1 Application Information.......................................... 62 10.2 Typical Applications .............................................. 68 10.3 Do's and Don'ts ..................................................... 78 11 Power Supply Recommendations ..................... 80 11.1 Power Supply Sequencing .................................... 80 11.2 Power Supply Decoupling ..................................... 80 12 Layout................................................................... 81 12.1 Layout Guidelines ................................................. 81 12.2 Layout Example .................................................... 82 13 Device and Documentation Support ................. 83 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 83 83 83 83 83 83 83 14 Mechanical, Packaging, and Orderable Information ........................................................... 84 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (April 2012) to Revision G Page • Added ESD Ratings table and Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections..................................................................................................................... 1 • Updated Features and Description sections to include use in applications other than temperature measurement .............. 1 • Merged all Pin Functions into one table ................................................................................................................................. 6 • Changed values in the Thermal Information table to align with JEDEC standards................................................................ 8 • Added Absolute input current specification to Electrical Characteristics................................................................................ 9 • Changed compliance voltage for excitation current sources in Electrical Characteristics, now refers to Figure 9 and Figure 10; changed initial error and initial mismatch to absolute error and absolute mismatch ............................................ 9 • Changed IDAC mismatch specification in Electrical Characteristics table to reflect proper distribution ................................ 9 • Re-ordered elements in Timing Requirements tables, changed timing references to tCLK ................................................... 11 • Changed Low-Noise PGA section ........................................................................................................................................ 18 • Modified Figure 20 to show variable resistor position ......................................................................................................... 18 • Added fCLK/fMOD column to Table 5 ....................................................................................................................................... 22 • Changed Chip Select (CS) section....................................................................................................................................... 33 • Changed Data Output and Data Ready (DOUT/DRDY) section .......................................................................................... 34 • Changed Figure 42, 43, and 44............................................................................................................................................ 35 • Added more infomation to Data Format section; added Figure 45 ...................................................................................... 36 • Modified Figure 46 to include CS status through SLEEP and WAKEUP command ............................................................ 38 • Updated Figure 47 and Figure 48 to show start of command execution ............................................................................. 38 • Removed figure for SDATAC (0001 011x) (Stop Read Data Continuous) command.......................................................... 40 • Updated Figure 53 to show MUX1 as the start of the data byte for the given command and register location................... 40 2 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Revision History (continued) • Updated Figure 54 to show start of calibration timing .......................................................................................................... 41 • Updated Figure 79 and Figure 80 to better show timing information ................................................................................... 66 Changes from Revision E (April 2012) to Revision F • Page Added ADS1148, QFN-32 row to Package/Ordering Information table ................................................................................. 4 Changes from Revision D (October 2011) to Revision E • Page Added RHB pin configuration ................................................................................................................................................. 5 Changes from Revision C (April 2010) to Revision D Page • Added footnote to Analog Inputs, Full-scale input voltage parameter typical specification in Electrical Characteristics table ........................................................................................................................................................................................ 9 • Deleted Analog Inputs, Mux leakage current parameter from Electrical Characteristics table .............................................. 9 • Added tCSPW to minimum specification in Timing Characteristics for Figure 1...................................................................... 11 • Changed tDTS minimum specification in Timing Requirements............................................................................................. 11 • Updated Figure 1 to show tCSPW timing ................................................................................................................................ 12 • Added Figure 6, Figure 5, Figure 9, and Figure 10 .............................................................................................................. 13 • Added Figure 15, Figure 16, Figure 11, and Figure 12 ........................................................................................................ 14 • Corrected Figure 19 to remove constant short..................................................................................................................... 17 • Added Table 4 to Analog Input Impedance section ............................................................................................................. 21 • Corrected Figure 29 and Figure 30 ...................................................................................................................................... 23 • Added details to Bias Voltage Generation section ............................................................................................................... 26 • Added Channel Cycling and Overload Recovery section..................................................................................................... 30 • Corrected Table 10............................................................................................................................................................... 31 • Added Equation 18 to Calibration section ............................................................................................................................ 31 • Added details to Calibration Commands section.................................................................................................................. 32 • Added details to Digital Interface section ............................................................................................................................. 33 • Added Restricted command to Table 15 .............................................................................................................................. 37 Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 3 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 5 Device Comparison Table PRODUCT RESOLUTION (BITS) NUMBER OF INPUTS VOLTAGE REFERENCE EXCITATION CURRENT SOURCES PACKAGE (PINS) ADS1246 24 1 Differential External No TSSOP (16) ADS1247 24 4-Input Multiplexer Internal or External Yes TSSOP (20) ADS1248 24 8-Input Multiplexer Internal or External Yes TSSOP (28) ADS1146 16 1 Differential External No TSSOP (16) ADS1147 16 4-Input Multiplexer Internal or External Yes TSSOP (20) 16 8-Input Multiplexer Internal or External Yes TSSOP (28) 16 8-Input Multiplexer Internal or External Yes VQFN (32) ADS1148 4 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 6 Pin Configuration and Functions PW Package 16-Pin TSSOP Top View DVDD 1 DGND 16 2 CLK 15 3 RESET 14 4 REFP 13 5 REFN 12 6 AINP 11 7 AINN PW Package 28-Pin TSSOP Top View 10 8 9 DVDD 1 28 SCLK DGND 2 27 DIN CLK 3 26 DOUT/DRDY RESET 4 25 DRDY REFP0/GPIO0 5 24 CS REFN0/GPIO1 6 23 START REFP1 7 22 AVDD REFN1 8 21 AVSS VREFOUT 9 20 IEXC1 VREFCOM 10 19 IEXC2 AIN0/IEXC 11 18 AIN3/IEXC/GPIO3 AIN1/IEXC 12 17 AIN2/IEXC/GPIO2 AIN4/IEXC/GPIO4 13 16 AIN7/IEXC/GPIO7 AIN5/IEXC/GPIO5 14 15 AIN6/IEXC/GPIO6 SCLK DIN DOUT/DRDY DRDY CS START AVDD AVSS Not to scale Not to scale PW Package 20-Pin TSSOP Top View 13 AVSS AIN0/IEXC 9 12 AIN3/IEXC/GPIO3 AIN1/IEXC 10 11 AVDD AVSS IEXC1 IEXC2 28 27 26 25 3 22 AIN7/IEXC/GPIO7 NC 4 21 AIN6/IEXC/GPIO6 NC 5 20 AIN5/IEXC/GPIO5 Thermal Pad NC 6 19 AIN4/IEXC/GPIO4 DVDD 7 18 AIN1/IEXC DGND 8 17 AIN0/IEXC CLK 9 Not to scale AIN2/IEXC/GPIO2 NC 16 8 15 VREFCOM AIN2/IEXC/GPIO2 VREFOUT AVDD AIN3/IEXC/GPIO3 23 VREFCOM 14 24 2 14 7 1 13 VREFOUT DIN SCLK REFP1 START REFN1 CS 15 START 16 6 29 5 12 REFP0/GPIO0 REFN0/GPIO1 REFN0/GPIO1 DRDY CS DOUT/DRDY 17 DRDY 18 4 30 3 31 CLK RESET 11 DIN 10 SCLK 19 RESET 20 2 REFP0/GPIO0 1 DOUT/DRDY DVDD DGND 32 RHB Package 32-Pin VQFN Top View Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Not to scale Submit Documentation Feedback 5 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Pin Functions PIN NAME ADS1146 ADS1147 TYPE (1) ADS1148 DESCRIPTION (2) TSSOP (16) TSSOP (20) TSSOP (28) VQFN (32) AIN0/IEXC — 9 11 17 I Analog input 0, optional excitation current output AIN1/IEXC — 10 12 18 I Analog input 1, optional excitation current output AIN2/IEXC/GPIO2 — 11 17 23 I/O Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2 AIN3/IEXC/GPIO3 — 12 18 24 I/O Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3 AIN4/IEXC/GPIO4 — — 13 19 I/O Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4 AIN5/IEXC/GPIO5 — — 14 20 I/O Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5 AIN6/IEXC/GPIO6 — — 15 21 I/O Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6 AIN7/IEXC/GPIO7 — — 16 22 I/O Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7 AINN 8 — — — I Negative analog input AINP 7 — — — I Positive analog input AVDD 10 14 22 28 P Positive analog power supply, connect a 0.1-µF capacitor to AVSS AVSS 9 13 21 27 P Negative analog power supply CLK 3 3 3 9 I External clock input, tie to DGND to activate the internal oscillator. CS 12 16 24 30 I Chip select (active low) DGND 2 2 2 8 G Digital ground DIN 15 19 27 1 I Serial data input DOUT/DRDY 14 18 26 32 O Serial data output, or data out combined with data ready DRDY 13 17 25 31 O Data ready (active low) DVDD 1 1 1 7 P Digital power supply, connect a 0.1-µF capacitor to DGND IEXC1 — — 20 26 O Excitation current output 1 IEXC2 — — 19 25 O Excitation current output 2 NC — — — 3, 4, 5, 6 — Connect pin to AVSS or leave floating REFN 6 — — — I REFN0/GPIO1 — 6 6 12 I/O REFN1 — — 8 14 I Negative external reference input 1 REFP 5 — — — I Positive external reference input REFP0/GPIO0 — 5 5 11 I/O REFP1 — — 7 13 I Positive external reference input 1 RESET 4 4 4 10 I Reset (active low) SCLK 16 20 28 2 I Serial clock input START 11 15 23 29 I Conversion start Thermal Pad — — — 33 — Connect pin to AVSS or leave floating VREFCOM — 8 10 16 O Negative internal reference voltage output, connect to AVSS when using a unipolar supply or to the mid-voltage ground when using a bipolar supply VREFOUT — 7 9 15 O Positive internal reference voltage output, connect a capacitor in the range of 1 µF to 47 µF to VREFCOM (1) (2) 6 Negative external reference input Negative external reference input 0, or general-purpose digital input/output pin 1 Positive external reference input 0, or general-purpose digital input/output pin 1 G = Ground, I = Input, O = Output, P = Power See Unused Inputs and Outputs for unused pin connections. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 7 Specifications 7.1 Absolute Maximum Ratings See (1) Power-supply voltage MIN MAX AVDD to AVSS –0.3 5.5 AVSS to DGND –2.8 0.3 DVDD to DGND –0.3 5.5 UNIT V Analog input voltage AINx, REFPx, REFNx, VREFOUT, VREFCOM, IEXC1, IEXC2 AVSS – 0.3 AVDD + 0.3 V Digital input voltage SCLK, DIN, DOUT/DRDY, DRDY, CS, START, RESET, CLK DGND – 0.3 DVDD + 0.3 V Continuous, any pin except power supply pins –10 10 Momentary, any pin except power supply pins –100 100 Input current Temperature (1) Junction, TJ mA 150 Storage, Tstg –60 °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 7 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 7.3 Recommended Operating Conditions Over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY Analog power supply Digital power supply AVDD to AVSS 2.7 AVSS to DGND –2.65 5.25 0.1 AVDD to DGND 2.25 5.25 DVDD to DGND 2.7 5.25 V VREF / Gain V 0.5 (AVDD – AVSS) – 1 V AVSS – 0.1 V(REFPx) – 0.5 V V(REFNx) + 0.5 AVDD + 0.1 V V ANALOG INPUTS (1) VIN Differential input voltage V(AINP) – V(AINN) (2) VCM Common-mode input voltage (V(AINP) + V(AINN)) / 2 –VREF / Gain See Equation 3 VOLTAGE REFERENCE INPUTS (3) VREF Differential reference input voltage V(REFNx) Absolute negative reference voltage V(REFPx) Absolute positive reference voltage V(REFPx) – V(REFNx) EXTERNAL CLOCK INPUT (4) fCLK External clock frequency 1 4.5 External clock duty cycle 25% 75% MHz AVSS AVDD V DGND DVDD V Operating ambient temperature –40 125 °C Specified ambient temperature –40 105 °C GENERAL-PURPOSE INPUTS AND OUTPUTS (GPIO) GPIO input voltage DIGITAL INPUTS Digital input voltage TEMPERATURE RANGE TA (1) (2) (3) (4) AINP and AINN denote the positive and negative inputs of the PGA. For VREF > 2.7 V, the differential input voltage must not exceed 2.7 V / Gain. REFPx and REFNx denote the differential reference input pair (ADS1146, ADS1147), or one of the two available differential reference input pairs (ADS1148). External clock only required if the internal oscillator is not used. 7.4 Thermal Information THERMAL METRIC (1) ADS1146 ADS1147 ADS1148 PW (TSSOP) PW (TSSOP) PW (TSSOP) RHB (VQFN) 16 PINS 20 PINS 28 PINS 32 PINS UNIT RθJA Junction-to-ambient thermal resistance 95.2 87.4 74.2 32.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.9 21.7 20.2 23.9 °C/W RθJB Junction-to-board thermal resistance 41 39.6 31.8 6.6 °C/W ψJT Junction-to-top characterization parameter 1.5 0.8 0.8 0.3 °C/W ψJB Junction-to-board characterization parameter 40.4 38.9 31.3 6.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — — 1.6 °C/W (1) 8 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 7.5 Electrical Characteristics Minimum and maximum specifications apply from TA = –40°C to +105°C. Typical specifications are at TA = 25°C. All specifications are at AVDD = 5 V, DVDD = 3.3 V, AVSS = 0 V, VREF = 2.048 V, and fCLK = 4.096 MHz (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Differential input current 100 Absolute input current pA See Table 4 PGA PGA gain settings 1, 2, 4, 8, 16, 32, 64, 128 V/V SYSTEM PERFORMANCE Resolution DR No missing codes Data rate INL ADC conversion time Single-cycle settling Integral nonlinearity Differential input, end point fit, Gain = 1, VCM = 2.5 V –1 Offset error After calibration –1 Offset drift Gain error Gain drift Common-mode rejection PSRR Power supply rejection 0.5 1 1 100 Gain = 128 Excluding VREF errors SPS See Table 10 LSB nV/°C 0.5% Gain = 1, excludes VREF drift Gain = 128, excludes VREF drift LSB nV/°C 15 –0.5% 1 ppm°C –3.5 ppm/°C See Table 1 and Table 2 Normal mode rejection CMRR Bits Gain = 1 Noise NMRR 16 5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000 See Table 6 At DC, Gain = 1 90 At DC, Gain = 32 100 AVDD, DVDD at DC 100 dB 30 nA dB VOLTAGE REFERENCE INPUTS Reference input current INTERNAL VOLTAGE REFERENCE VREF Internal reference voltage Reference drift (1) 2.038 2.048 2.058 20 50 TA = –40°C to +105°C Output current (2) –10 10 Load regulation 50 Start-up time V ppm/°C mA µV/mA See Table 7 INTERNAL OSCILLATOR Internal oscillator frequency 3.89 4.096 4.3 MHz EXCITATION CURRENT SOURCES (IDACs) Output current settings 50, 100, 250, 500, 750, 1000, 1500 Compliance voltage All currents Absolute error All currents, each IDAC Absolute mismatch All currents, between IDACs Temperature drift Each IDAC Temperature drift matching Between IDACs µA See Figure 9 and Figure 10 –6% ±1% 6% ±0.2% 200 ppm/°C 10 ppm/°C BURN-OUT CURRENT SOURCES Burn-out current source settings (1) (2) 0.5, 2, 10 µA Specified by the combination of design and final production test. Do not exceed this loading on the internal voltage reference. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 9 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Electrical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +105°C. Typical specifications are at TA = 25°C. All specifications are at AVDD = 5 V, DVDD = 3.3 V, AVSS = 0 V, VREF = 2.048 V, and fCLK = 4.096 MHz (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS VOLTAGE Bias voltage Bias voltage output impedance (AVDD + AVSS) / 2 V 400 Ω TEMPERATURE SENSOR Output voltage TA = 25°C Temperature coefficient 118 mV 405 µV/°C GENERAL-PURPOSE INPUTS AND OUTPUTS (GPIO) VIL Low-level input voltage AVSS 0.3 × AVDD V VIH High-level input voltage 0.7 × AVDD AVDD V VOL Low-level output voltage IOL = 1 mA AVSS 0.2 × AVDD V VOH High-level output voltage IOH = 1 mA 0.8 × AVDD V DIGITAL INPUTS AND OUTPUTS (OTHER THAN GPIO) VIL Low-level input voltage DGND 0.3 × DVDD V VIH High-level input voltage 0.7 × DVDD DVDD V VOL Low-level output voltage IOL = 1 mA DGND 0.2 × DVDD V VOH High-level output voltage IOH = 1 mA 0.8 × DVDD Input leakage DGND < VIN < DVDD 10 µA V –10 POWER SUPPLY IAVDD IDVDD PD 10 Analog supply current Digital supply current Power dissipation Submit Documentation Feedback Power-down mode 0.1 Converting, AVDD = 3.3 V, DR = 20 SPS, external reference 212 Converting, AVDD = 5 V, DR = 20 SPS, external reference 225 Additional current with internal reference enabled 180 Power-down mode 0.2 Normal operation, DVDD = 3.3 V, DR = 20 SPS, internal oscillator 210 Normal operation, DVDD = 5 V, DR = 20 SPS, internal oscillator 230 AVDD = DVDD = 3.3 V, DR = 20 SPS, internal oscillator, external reference 1.4 AVDD = DVDD = 5 V, DR = 20 SPS, internal oscillator, external reference 2.3 µA µA mW Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 7.6 Timing Requirements At TA = –40°C to +105°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted) PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE (SEE Figure 1 AND Figure 2) tCSSC Delay time, first SCLK rising edge after CS falling edge 10 ns tSCCS Delay time, CS rising edge after final SCLK falling edge 7 tCLK (1) tCSPW Pulse duration, CS high 5 tCLK tSCLK SCLK period tSPWH Pulse duration, SCLK high 0.25 0.75 tSCLK tSPWL Pulse duration, SCLK low 0.25 0.75 tSCLK tDIST Setup time, DIN valid before SCLK falling edge 5 ns tDIHD Hold time, DIN valid after SCLK falling edge 5 ns tSTD Setup time, SCLK low before DRDY rising edge 5 tCLK tDTS Delay time, SCLK rising edge after DRDY falling edge 1 tCLK 3 tCLK 488 ns 64 Conversions MINIMUM START TIME PULSE DURATION (SEE Figure 3) tSTART Pulse duration, START high RESET PULSE DURATION, SERIAL INTERFACE COMMUNICATION AFTER RESET (SEE Figure 4) tRESET Pulse duration, RESET low tRHSC Delay time, SCLK rising edge (start of serial interface communication) after RESET rising edge (1) (2) 4 tCLK 0.6 (2) ms tCLK = 1 / fCLK. The default clock frequency fCLK = 4.096 MHz. Applicable only when fCLK = 4.096 MHz, scales proportionally with fCLK frequency. 7.7 Switching Characteristics At TA = –40°C to +105°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted; see Figure 1 and Figure 2) PARAMETER TEST CONDITIONS tDOPD Propagation delay time, SCLK rising edge to valid new DOUT tDOHD DOUT hold time tCSDO Propagation delay time, CS rising edge to DOUT high impedance tPWH Pulse duration, DRDY high MIN TYP MAX DVDD ≤ 3.6 V 50 DVDD > 3.6 V 180 UNIT 0 ns 10 3 Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ns Submit Documentation Feedback ns tCLK 11 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com tCSPW CS tSCLK tCSSC tSPWH tSCCS SCLK tDIST tDIHD DIN DIN[0] DIN[7] tSPWL DIN[6] DIN[5] DIN[4] DIN[1] tDOPD DOUT[7] DOUT/DRDY DOUT[6] DIN[0] tDOHD DOUT[5] DOUT[4] DOUT[1] DOUT[0] tCSDO Figure 1. Serial Interface Timing, DRDY MODE Bit = 0 tDTS tPWH DRDY tSTD(1) 1 2 3 4 5 6 7 8 SCLK(2) (1) This timing diagram is applicable only when the CS pin is low. SCLK does not need to be low during tSTD when CS is high. (2) SCLK must only be sent in multiples of eight during partial retrieval of output data. Figure 2. Serial Interface Timing to Allow Conversion Result Loading tSTART START Figure 3. Minimum Start Pulse Duration tRESET RESET CS SCLK tRHSC Figure 4. Reset Pulse Duration and Serial Interface Communication After Reset 12 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 7.8 Typical Characteristics TA = 25°C, AVDD = 5 V, AVSS = 0 V, and VREF = 2.5 V (unless otherwise noted) 0 3.0 32 Units 2.5 2.0 Data Rate Error (%) Reference Drift (ppm) −20 −40 −60 −80 1.5 1.0 DVDD = 5V 0.5 0 DVDD = 3.3V -0.5 -1.0 -1.5 -2.0 −100 -2.5 −120 -3.0 0 200 400 600 Time (hours) 800 1000 -40 20 40 60 80 100 120 Temperature (°C) Figure 5. Internal Reference Long-Term Drift Figure 6. Data Rate Error vs Temperature 1.002 0.004 1.5mA Setting, 10 Units 1.001 0.003 1.000 0.999 IEXC1 - IEXC2 (mA) Normalized Output Current 0 -20 G000 50mA 100mA 0.998 0.997 500mA 0.996 250mA 0.995 750mA 0.994 0.993 1mA 0.992 IDAC Current Settings 0.002 0.001 0 -0.001 -0.002 -0.003 1.5mA 0.991 -0.004 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -40 0 -20 20 40 60 80 100 120 Temperature (°C) AVDD (V) Figure 7. IDAC Line Regulation Figure 8. IDAC Drift 1.01 1.1 1.005 Normalized IDAC Current Normalized IDAC Current 1 0.9 0.8 0.7 0.6 0.5 50µA 100µA 250µA 500µA 750µA 1mA 1.5mA 0.4 0.3 0.2 0.1 0 0 1 1 0.995 0.99 0.985 2 3 Voltage (V) 4 Figure 9. IDAC Voltage Compliance 5 0.98 0 1 2 3 Voltage (V) 4 5 Figure 10. IDAC Voltage Compliance Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 13 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Typical Characteristics (continued) TA = 25°C, AVDD = 5 V, AVSS = 0 V, and VREF = 2.5 V (unless otherwise noted) 600 290 550 270 Digital Current (mA) Analog Current (mA) 500 450 AVDD = 5V 400 350 AVDD = 3.3V 300 250 200 250 DVDD = 5V 230 DVDD = 3.3V 210 190 150 170 100 5 10 20 40 80 160 320 640 1000 2000 5 10 20 40 80 160 320 640 1000 2000 Data Rate (SPS) Data Rate (SPS) Figure 11. Analog Supply Current vs Data Rate Figure 12. Digital Supply Current vs Data Rate 330 800 AVDD = 5V DVDD = 5V 2kSPS 700 310 320/640/1kSPS 500 40/80/160SPS 400 5/10/20SPS 300 200 Digital Current (mA) Analog Current (mA) 2kSPS 600 290 320/640/1kSPS 270 250 230 40/80/160SPS 100 210 0 190 5/10/20SPS -40 -20 0 20 40 60 80 100 120 -40 -20 0 40 60 80 100 120 Figure 14. Digital Supply Current vs Temperature Figure 13. Analog Supply Current vs Temperature 700 310 AVDD = 3.3V 2kSPS DVDD = 3.3V 600 290 500 320/640/1kSPS 400 40/80/160SPS 300 5/10/20SPS 200 Digital Current (mA) 2kSPS Analog Current (mA) 20 Temperature (°C) Temperature (°C) 270 320/640/1kSPS 250 230 40/80/160SPS 100 210 0 190 5/10/20SPS -40 14 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure 15. Analog Supply Current vs Temperature Figure 16. Digital Supply Current vs Temperature Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 8 Parameter Measurement Information 8.1 Noise Performance The ADC noise performance is optimized by adjusting the data rate and PGA setting. Generally, the lowest inputreferred noise is achieved using the highest gain possible, consistent with the input signal range. Do not set the gain too high or the result is ADC overrange. Noise also depends on the output data rate. As the data rate reduces, the ADC bandwidth correspondingly reduces. This reduction in total bandwidth results in lower overall noise. Table 1 and Table 2 summarize the noise performance of the device. The data are representative of typical noise performance at TA = 25°C. The data shown are the result of averaging the readings from multiple devices and were measured with the inputs shorted together. Table 1 lists the input-referred noise in units of µVPP for the conditions shown. Table 2 lists the corresponding data in units of ENOB (effective number of bits) where ENOB for the peak-to-peak noise is defined in Equation 1. ENOB = ln((2 × VREF/Gain) / VNPP) / ln(2) where • VNPP is the input referred peak-to-peak noise voltage (1) Table 1. Noise in µVPP At VREF = 2.048 V, AVDD = 5 V, AVSS = 0 V PGA SETTING DATA RATE (SPS) 1 2 4 8 16 32 64 128 5 62.5 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 0.98 (1) 0.49 (1) 10 62.5 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 0.98 (1) 0.49 (1) 20 62.5 (1) (1) (1) (1) (1) (1) (1) 0.55 40 62.5 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 0.98 (1) 0.75 80 62.5 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 1.09 0.98 (1) (1) (1) (1) (1) (1) (1) 31.25 31.25 15.63 15.63 7.81 7.81 3.91 3.91 1.95 1.95 0.98 160 62.5 1.88 1.57 320 62.5 (1) 35.3 17.52 8.86 4.35 3.03 2.44 2.34 640 93.06 45.2 18.73 12.97 6.51 4.2 3.69 3.5 1000 284.59 129.77 61.3 33.04 16.82 9.08 5.42 4.65 2000 273.39 130.68 67.13 36.16 19.22 9.87 6.93 6.48 Peak-to-peak noise rounded up to 1 LSB. Table 2. Effective Number of Bits From Peak-to-Peak Noise At VREF = 2.048 V, AVDD = 5 V, AVSS = 0 V PGA SETTING DATA RATE (SPS) 1 2 4 8 16 32 64 128 5 16 16 16 16 16 16 16 16 10 16 16 16 16 16 16 16 16 20 16 16 16 16 16 16 16 15.8 40 16 16 16 16 16 16 16 15.4 80 16 16 16 16 16 16 15.8 15 160 16 16 16 16 16 16 15.1 14.3 320 16 15.8 15.8 15.8 15.8 15.4 14.7 13.7 640 15.4 15.5 15.7 15.3 15.3 14.9 14.1 13.2 1000 13.8 13.9 14 13.9 13.9 13.8 13.5 12.7 2000 13.9 13.9 13.9 13.8 13.7 13.7 13.2 12.3 Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 15 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9 Detailed Description 9.1 Overview The ADS1146, ADS1147 and ADS1148 devices are highly integrated 16-bit data converters. The devices include a low-noise, high-input impedance programmable gain amplifier (PGA), a delta-sigma (ΔΣ) ADC with an adjustable single-cycle settling digital filter, internal oscillator, and an SPI-compatible serial interface. The ADS1147 and ADS1148 also include a flexible input multiplexer with system monitoring capability and general-purpose I/O settings, a low-drift voltage reference, and two matched current sources for sensor excitation. Figure 17 and Figure 18 show the various functions incorporated into each device. 9.2 Functional Block Diagrams AVDD REFP REFN DVDD Burnout Detect ADS1146 VBIAS SCLK DIN AINP Input Mux AINN 3rd Order û Modulator PGA Serial Interface And Control Adjustable Digital Filter DRDY DOUT/DRDY CS START RESET Internal Oscillator Burnout Detect AVSS CLK DGND Copyright © 2016, Texas Instruments Incorporated Figure 17. ADS1146 Diagram REFP0/ REFN0/ AVDD GPIO0 GPIO1 Burnout Detect ADS1148 Only REFP1 REFN1 VREFOUT VREFCOM Voltage Reference VREF Mux VBIAS DVDD ADS1147 ADS1148 GPIO AIN0/IEXC SCLK System Monitor AIN1/IEXC AIN2/IEXC/GPIO2 Input Mux AIN3/IEXC/GPIO3 AIN4/IEXC/GPIO4 PGA DIN 3rd Order û Modulator Adjustable Digital Filter Serial Interface And Control DRDY DOUT/DRDY CS START AIN5/IEXC/GPIO5 Dual IDACs AIN6/IEXC/GPIO6 AIN7/IEXC/GPIO7 RESET Internal Oscillator ADS1148 Only Burnout Detect AVSS IEXC1 IEXC2 ADS1148 Only CLK DGND Copyright © 2016, Texas Instruments Incorporated Figure 18. ADS1147 and ADS1148 Diagram 16 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.3 Feature Description 9.3.1 ADC Input and Multiplexer The ADC measures the input signal through the onboard PGA. All analog inputs are connected to the internal AINP or AINN analog inputs through the analog multiplexer. Figure 19 shows a block diagram of the analog input multiplexer. The input multiplexer connects to eight (ADS1148) or four (ADS1147) analog inputs. Any analog input pin can be selected as the positive input or negative input through the MUX0 register, while the ADS1146 has AINP and AINN connections for a single differential channel. The multiplexer also allows the on-chip excitation current and bias voltage to be selected to a specific channel. Through the input multiplexer, the ambient temperature (internal temperature sensor), AVDD, DVDD, and external reference can all be selected for measurement. See the System Monitor section for more details. On the ADS1147 and ADS1148, the analog inputs can also be configured as general-purpose inputs and outputs (GPIOs). See the General-Purpose Digital I/O section for more details. AVDD AVDD IDAC2 IDAC1 System Monitors AVSS AVDD VBIAS AVDD AVDD AIN0 AVSS AVDD VBIAS AIN1 ADS1147/8 Only AVSS AVDD Temperature Diode VREFP VREFN VREFP1/4 VBIAS VREFN1/4 VREFP0/4 AIN2 AVSS AVDD VREFN0/4 VBIAS AVDD/4 AIN3 AVSS/4 DVDD/4 ADS1148 Only AVSS AVDD DGND/4 VBIAS AIN4 AVDD AVSS AVDD VBIAS Burnout Current Source (0.5 µA, 2 µA, 10 µA) AIN5 AINP AVSS AVDD VBIAS AVSS AVDD VBIAS AINN PGA To ADC AIN6 AIN7 Burnout Current Source (0.5 µA, 2 µA, 10 µA) AVSS Copyright © 2016, Texas Instruments Incorporated Figure 19. Analog Input Multiplexer Circuit Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 17 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Feature Description (continued) ESD diodes protect the ADC inputs. To prevent these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100 mV, and do not exceed AVDD by more than 100 mV, as shown in Equation 2. Note that the same caution is true if the inputs are configured to be GPIOs. AVSS – 100 mV < V(AINX) < AVDD + 100 mV (2) 9.3.2 Low-Noise PGA The ADS1146, ADS1147, and ADS1148 feature a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 by register SYS0. Figure 20 shows a simplified diagram of the PGA. The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped with an electromagnetic interference (EMI) filter, as shown in Figure 20. As with any PGA, ensure that the input voltage stays within the specified common-mode input range. The common-mode input (VCM) must be within the range shown in Equation 3. § ¨ AVSS ¨ © 0.1 V VIN (MAX) ˜ Gain · § ¸ d VCM d ¨ AVDD ¸ ¨ 2 ¹ © 0.1 V VIN (MAX)˜ Gain · ¸ ¸ 2 ¹ (3) 454 + AINP A1 7.5 pF RF 7.5 pF R C RG ADC R RF 7.5 pF A2 454 + AINN 7.5 pF Figure 20. Simplified Diagram of the PGA Gain is changed inside the device using a variable resistor, RG. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 4. FSR = ±VREF / Gain (4) Table 3 shows the corresponding full-scale input ranges when using the internal 2.048-V reference. Table 3. PGA Full-Scale Range 18 PGA GAIN SETTING FSR 1 ±2.048 V 2 ±1.024 V 4 ±0.512 V 8 ±0.256 V 16 ±0.128 V 32 ±0.064 V 64 ±0.032 V 128 ±0.016 V Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.3.2.1 PGA Common-Mode Voltage Requirements To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section. The outputs of both amplifiers (A1 and A2) in Figure 20 can not swing closer to the supplies (AVSS and AVDD) than 100 mV. If the outputs OUTP and OUTN are driven to within 100 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition, the output voltages must meet Equation 5. AVSS + 0.1 V ≤ V(OUTN), V(OUTP) ≤ AVDD – 0.1 V (5) Translating the requirements of Equation 5 into requirements referred to the PGA inputs (AINP and AINN) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design; therefore, the common-mode voltage at the output of the PGA can be assumed to be the same as the commonmode voltage of the input signal, as shown in Figure 21. AINP + A1 ½ V IN RF OUTP ½ Gain·V IN RG VCM = ½ (V (AINP) + V(AINN)) ½ Gain·V IN RF OUTN ½ V IN A2 AINN + Figure 21. PGA Common-Mode Voltage The common-mode voltage is calculated using Equation 6. VCM = ½ (V(AINP) + V(AINN)) = ½ (V(OUTP) + V(OUTN)) (6) The voltages at the PGA inputs (AINP and AINN) can be expressed as Equation 7 and Equation 8. V(AINP) = VCM + ½ VIN V(AINN) = VCM – ½ VIN (7) (8) The output voltages (V(OUTP) and V(OUTN)) can then be calculated as Equation 9 and Equation 10. V(OUTP) = VCM + ½ Gain × VIN V(OUTN) = VCM – ½ Gain × VIN (9) (10) The requirements for the output voltages of amplifiers A1 and A2 (Equation 5) can now be translated into requirements for the input common-mode voltage range using Equation 9 and Equation 10, which are given in Equation 11 and Equation 12. VCM (MIN) ≥ AVSS + 0.1 V + ½ Gain × VIN (MAX) VCM (MAX) ≤ AVDD – 0.1 V – ½ Gain × VIN (MAX) (11) (12) To calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (VIN (MAX)) that occurs in the application must be used. VIN (MAX) can be less than the maximum possible full-scale value. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 19 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.3.2.2 PGA Common-Mode Voltage Calculation Example The following paragraphs explain how to apply Equation 11 and Equation 12 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference, VREF = 2.5 V. The maximum possible differential input voltage VIN = (V(AINP) – V(AINN)) that can be applied is then limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 11 and Equation 12 yield an allowed VCM range of 1.35 V ≤ VCM ≤ 1.95 V. If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire fullscale range but is limited to VIN (MAX) = ±0.1 V, for example, then this reduced input signal amplitude relaxes the VCM restriction to 0.9 V ≤ VCM ≤ 2.4 V. In the case of a fully-differential sensor signal, each input (AINP, AINN) can swing up to ±50 mV around the common-mode voltage (V(AINP) + V(AINN)) / 2, which must remain between the limits of 0.9 V and 2.4 V. The output of a symmetrical wheatstone bridge is an example of a fully-differential signal. Figure 22 shows a situation where the common-mode voltage of the input signal is at the lowest limit. V(OUTN) is exactly at 0.1 V in this case. Any further decrease in common-mode voltage (VCM) or increase in differential input voltage (VIN) drives V(OUTN) below 0.1 V and saturates amplifier A2. V(AINP) = 0.95 V + A1 50 mV RF V(OUTP) = 1.7 V 800 mV VCM = 0.9 V RF / 7.5 RF 800 mV V(OUTN) = 0.1 V 50 mV A2 V(AINN) = 0.85 V + Figure 22. Example Where VCM is at the Lowest Limit In contrast, the signal of an RTD is of a pseudo-differential nature (if implemented as shown in the 3-Wire RTD Measurement System section), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage from 0.85 V to 2.35 V. The positive input can then swing up to VIN (MAX) = 100 mV above the negative input. In this case, the common-mode voltage changes at the same time the voltage on the positive input changes. That is, while the input signal swings between 0 V ≤ VIN ≤ VIN (MAX), the common-mode voltage swings between V(AINN) ≤ VCM ≤ V(AINN) + ½ VIN (MAX). Satisfying the common-mode voltage requirements for the maximum input voltage VIN (MAX) ensures the requirements are met throughout the entire signal range. 20 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Figure 23 and Figure 24 show examples of both fully-differential and pseudo-differential signals, respectively. AINP AINP VCM VCM 1.0 V 100 mV 1.0 V 100 mV AINN AINN 0V 0V Figure 23. Fully-Differential Input Signal Figure 24. Pseudo-Differential Input Signal NOTE With a unipolar power supply, the input range does not extend to the ground. Equation 11 and Equation 12 show the common-mode voltage requirements. • VCM (MIN) ≥ AVSS + 0.1 V + ½ Gain × VIN (MAX) • VCM (MAX) ≤ AVDD – 0.1 V – ½ Gain × VIN (MAX) 9.3.2.3 Analog Input Impedance The device inputs are buffered through a high-input impedance PGA before they reach the ΔΣ modulator. For the majority of applications, the input current is minimal and can be neglected. However, because the PGA is chopper-stabilized for noise and offset performance, the input impedance is best described as a small absolute input current. The absolute input current for selected channels is approximately proportional to the selected modulator clock. Table 4 shows the typical values for these currents with a differential voltage coefficient and the corresponding input impedances over data rate. Table 4. Typical Values for Analog Input Current Over Data Rate (1) (1) CONDITION ABSOLUTE INPUT CURRENT EFFECTIVE INPUT IMPEDANCE DR = 5 SPS, 10 SPS, 20 SPS ± (0.5 nA + 0.1 nA/V) 5000 MΩ DR = 40 SPS, 80 SPS, 160 SPS ± (2 nA + 0.5 nA/V) 1200 MΩ DR = 320 SPS, 640 SPS, 1 kSPS ± (4 nA + 1 nA/V) 600 MΩ DR = 2 kSPS ± (8 nA + 2 nA/V) 300 MΩ Input current with VCM = 2.5 V, TA = 25°C, AVDD = 5 V, and AVSS = 0 V. 9.3.3 Clock Source The device can use either the internal oscillator or an external clock. Connect the CLK pin to DGND before power-on or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator, with the device then operating on the external clock. After the device switches to the external clock, it cannot be switched back to the internal oscillator without cycling the power supplies or resetting the device. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 21 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.3.4 Modulator A third-order delta-sigma modulator is used in the ADS1146, ADS1147, and ADS1148 devices. The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream. To save power, the modulator clock runs from 32 kHz up to 512 kHz for different data rates, as shown in Table 5. Table 5. Modulator Clock Frequency for Different Data Rates DATA RATE (SPS) (1) MODULATOR RATE (fMOD) (1) (kHz) fCLK/fMOD 5, 10, 20 32 128 40, 80, 160 128 32 320, 640, 1000 256 16 2000 512 8 Using the internal oscillator or an external 4.096-MHz clock. 9.3.5 Digital Filter The ADC uses linear-phase finite impulse response (FIR) digital filters that can be adjusted for different output data rates. The digital filter always settles in a single cycle. Table 6 shows the exact data rates when an external clock equal to 4.096 MHz is used. Also shown is the signal –3-dB bandwidth, and the 50-Hz and 60-Hz attenuation. For good 50-Hz or 60-Hz rejection, use a data rate of 20 SPS or slower. The frequency responses of the digital filter are shown in Figure 25 to Figure 35. Figure 28 shows a detailed view of the filter frequency response from 48 Hz to 62 Hz for a 20-SPS data rate. All filter plots are generated with a 4.096-MHz external clock. Data rates and digital filter frequency responses scale proportionally with changes in the system clock frequency. The internal oscillator frequency has a variation, as specified in the Electrical Characteristics section, that also affects data rates and the digital filter frequency response. Table 6. Digital Filter Specifications (1) ATTENUATION NOMINAL DATA RATE ACTUAL DATA RATE –3-dB BANDWIDTH fIN = 50 Hz ±0.3 Hz fIN = 60 Hz ±0.3 Hz fIN = 50 Hz ±1 Hz fIN = 60 Hz ±1 Hz 5 SPS 5.018 SPS 2.26 Hz –106 dB –74 dB –81 dB –69 dB 10 SPS 10.037 SPS 4.76 Hz –106 dB –74 dB –80 dB –69 dB 20 SPS 20.075 SPS 14.8 Hz –71 dB –74 dB –66 dB –68 dB 40 SPS 40.15 SPS 9.03 Hz — — — — 80 SPS 80.301 SPS 19.8 Hz — — — — 160 SPS 160.6 SPS 118 Hz — — — — 320 SPS 321.608 SPS 154 Hz — — — — 640 SPS 643.21 SPS 495 Hz — — — — 1000 SPS 1000 SPS 732 Hz — — — — 2000 SPS 2000 SPS 1465 Hz — — — — (1) Values shown for fCLK = 4.096 MHz. 22 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 0 0 -20 -20 Magnitude (dB) Magnitude (dB) www.ti.com -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 20 40 60 80 100 120 140 160 180 200 20 0 40 60 Frequency (Hz) 0 -60 -20 -70 -60 -80 -80 -90 -100 -110 -100 -120 -120 0 20 40 60 80 48 100 120 140 160 180 200 50 Figure 27. Filter Profile With Data Rate = 20 SPS -20 -20 -40 -40 Gain (dB) 0 56 58 60 62 -60 -80 -80 -100 -100 -120 54 Figure 28. Detailed View of Filter Profile With Data Rate = 20 SPS Between 48 Hz and 62 Hz 0 -60 52 Frequency (Hz) Frequency (Hz) Magnitude (dB) 100 120 140 160 180 200 Figure 26. Filter Profile With Data Rate = 10 SPS Magnitude (dB) Magnitude (dB) Figure 25. Filter Profile With Data Rate = 5 SPS -40 80 Frequency (Hz) -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) Frequency (Hz) Figure 29. Filter Profile With Data Rate = 40 SPS Figure 30. Filter Profile With Data Rate = 80 SPS Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 23 ADS1146, ADS1147, ADS1148 www.ti.com 0 0 -20 -20 Magnitude (dB) Magnitude (dB) SBAS453G – JULY 2009 – REVISED AUGUST 2016 -40 -60 -80 -100 -60 -80 -100 -120 -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Frequency (Hz) Frequency (Hz) Figure 31. Filter Profile With Data Rate = 160 SPS Figure 32. Filter Profile With Data Rate = 320 SPS 0 0 -20 -20 Magnitude (dB) Magnitude (dB) -40 -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 1 2 3 4 5 6 7 8 9 10 Frequency (kHz) Frequency (Hz) Figure 33. Filter Profile With Data Rate = 640 SPS Figure 34. Filter Profile With Data Rate = 1 kSPS 0 Magnitude (dB) -20 -40 -60 -80 -100 -120 0 2 4 6 8 10 12 14 16 18 20 Frequency (kHz) Figure 35. Filter Profile With Data Rate = 2 kSPS 24 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.3.6 Voltage Reference Input The voltage reference for the device is the differential voltage between REFP and REFN, given by Equation 13. VREF = V(REFP) – V(REFN) (13) In the case of the ADS1146, these pins are dedicated inputs. For the ADS1147 and ADS1148, there is a multiplexer that selects the reference inputs, as shown in Figure 36. The reference inputs use buffers to increase the input impedance. As with the analog inputs, REFP0 and REFN0 can be configured as digital I/Os on the ADS1147 and ADS1148. ADS1148 Only REFP1 REFN1 REFP0 REFN0 Reference Multiplexer VREFP VREFOUT VREFCOM Internal Voltage Reference VREFN ADC Figure 36. Reference Input Multiplexer The reference input circuit has ESD diodes to protect the inputs. To prevent the diodes from turning on, make sure the voltage on the reference input pin is not less than AVSS – 100 mV, and does not exceed AVDD + 100 mV, as shown in Equation 14. AVSS – 100 mV < (V(REFP) or V(REFN)) < AVDD + 100 mV (14) 9.3.7 Internal Voltage Reference The ADS1147 and ADS1148 have an internal voltage reference with a low temperature coefficient. The output of the voltage reference is 2.048 V (nominal) with the capability of both sourcing and sinking up to 10 mA of current. The voltage reference must have a capacitor connected between VREFOUT and VREFCOM. The value of the capacitance must be in the range of 1 µF to 47 µF. Large values provide more filtering of the reference; however, the turnon time increases with capacitance, as shown in Table 7. For stability reasons, VREFCOM must have a low-impedance path to AC ground nodes, such as GND. VREFCOM may be connected to AVSS (for a ±2.5-V analog power supply) as long as AVSS has a low-impedance path less than 10 Ω to AC ground. In case this impedance is higher than 10 Ω, connect a capacitor of at least 0.1 µF between VREFCOM and an AC ground node (for example, GND). NOTE Because time is required for the voltage reference to settle to the final voltage, take care when the device is turned off between conversions. Allow adequate time for the internal reference to fully settle before starting a new conversion. Table 7. Internal Reference Settling Time VREFOUT CAPACITOR SETTLING ERROR 1 µF 4.7 µF 47 µF TIME TO REACH THE SETTLING ERROR ±0.5% 70 µs ±0.1% 110 µs ±0.5% 290 µs ±0.1% 375 µs ±0.5% 2.2 ms ±0.1% 2.4 ms Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 25 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com The internal reference is controlled by the MUX1 register; by default, the internal reference is off after power up (see the ADS1147 and ADS1148 Detailed Register Definitions section for more details). Therefore, the internal reference must first be turned on and then connected through the internal reference multiplexer. Because the internal reference is used to generate the current reference for the excitation current sources, it must be turned on before the excitation currents become available. 9.3.8 Excitation Current Sources The ADS1147 and ADS1148 provide two matched excitation current sources (IDACs) for RTD applications. For three-wire RTD applications, the matched current sources can be used to cancel the errors caused by sensor lead resistance. The output current of the IDACs can be programmed to 50 µA, 100 µA, 250 µA, 500 µA, 750 µA, 1000 µA, or 1500 µA. The two matched current sources can be connected to dedicated current output pins IEXC1 and IEXC2 (ADS1148 only), or to any analog input pin (ADS1147 and ADS1148); see the ADS1147 and ADS1148 Detailed Register Definitions section for more information. Both current sources can be connected to the same pin. The internal reference must be turned on and the proper amount of capacitance applied to VREFOUT when using the excitation current sources. 9.3.9 Sensor Detection To help detect a possible sensor malfunction, the device provides selectable current sources (0.5 µA, 2 µA, or 10 µA) to act as burn-out current sources. When enabled, one current source sources current to the selected positive analog input (AINP) while the other current source sinks current from the selected negative analog input (AINN). In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading may also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading may indicate a shorted sensor. The absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero. The ADC readings of a functional sensor may be corrupted when the burn-out current sources are enabled. TI recommends disabling the burn-out current sources when performing the precision measurement, and only enabling them to test for sensor fault conditions. 9.3.10 Bias Voltage Generation A selectable bias voltage is provided for use with unbiased thermocouples. The bias voltage is (AVDD + AVSS) / 2 and can be applied to any analog input channel through the internal input multiplexer. Table 8 lists the bias voltage turnon times for different sensor capacitances. The internal bias voltage generator, when selected on multiple channels, causes them to be internally shorted. Because of this, take care to limit the amount of current that may flow through the device. TI recommends that under no circumstances must more than 5 mA be allowed to flow through this path. This applies when the device is in operation and when it is powered down. Table 8. Bias Voltage Settling Time 26 SENSOR CAPACITANCE SETTLING TIME 0.1 µF 220 µs 1 µF 2.2 ms 10 µF 22 ms 200 µF 450 ms Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.3.11 General-Purpose Digital I/O The ADS1148 has eight pins and the ADS1147 has four pins that serve a dual purpose as either analog inputs or GPIOs. Three registers control the function of the GPIO pins. Use the GPIO configuration register (IOCFG) to enable a pin as a GPIO pin. The GPIO direction register (IODIR) configures the GPIO pin as either an input or an output. Finally, the GPIO data register (IODAT) contains the GPIO data. If a GPIO pin is configured as an input, the respective IODAT[x] bit reads the status of the pin; if a GPIO pin is configured as an output, write the output status to the respective IODAT[x] bit. For more information about the use of GPIO pins, see the ADS1147 and ADS1148 Detailed Register Definitions section. Figure 37 shows a diagram of how these functions are combined onto a single pin. Note that when the pin is configured as a GPIO, the corresponding logic is powered from AVDD and AVSS. When the ADS1147 and ADS1148 are operated with bipolar analog supplies, the GPIO outputs bipolar voltages. Care must be taken loading the GPIO pins when used as outputs because large currents can cause droop or noise on the analog supplies. IOCFG IODIR REFx0/GPIOx AINx/GPIOx DIO WRITE To Analog Mux DIO READ Figure 37. Analog and Data Interface Pin 9.3.12 System Monitor The ADS1147 and ADS1148 provide a system monitor function. This function can measure the analog power supply, digital power supply, external voltage reference, or ambient temperature. Note that the system monitor function provides a coarse result. When the system monitor is enabled, the analog inputs are disconnected. 9.3.12.1 Power-Supply Monitor The system monitor can measure the analog or digital power supply. When measuring the power supply (VSP), the resulting conversion is approximately 1/4 of the actual power supply voltage, as shown in Equation 15. Conversion Result = (VSP / 4) / VREF (15) 9.3.12.2 External Voltage Reference Monitor The ADC can measure the external voltage reference. In this configuration, the monitored external voltage reference (VREX) is connected to the analog input. The result (conversion code) is approximately 1/4 of the actual reference voltage, as shown in Equation 16. Conversion Result = (VREX / 4) / VREF (16) NOTE The internal reference voltage must be enabled when measuring an external voltage reference using the system monitor. 9.3.12.3 Ambient Temperature Monitor On-chip diodes provide temperature-sensing capability. When selecting the temperature monitor function, the anodes of two diodes are connected to the ADC. Typically, the difference in diode voltage is 118 mV at TA = 25°C with a temperature coefficient of 405 µV/°C. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 27 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.4 Device Functional Modes 9.4.1 Power Up When DVDD is powered up, the internal power-on reset module generates a pulse that resets all digital circuitry. All the digital circuits are held in a reset state for 216 system clocks to allow the analog circuits and the internal digital power supply to settle. SPI communication cannot occur until the internal reset is released. 9.4.2 Reset When the RESET pin goes low, the device is immediately reset. All registers are restored to default values. The device stays in reset mode as long as the RESET pin stays low. When the RESET pin goes high, the ADC comes out of reset mode and is able to convert data. After the RESET pin goes high, the digital filter and the registers are held in a reset state for 0.6 ms when fCLK = 4.096 MHz. Therefore, valid SPI communication can only be resumed 0.6 ms after the RESET pin goes high; see Figure 4. When the RESET pin goes low, the clock selection is reset to the internal oscillator. A reset can also be performed by the RESET command through the serial interface and is functionally the same as using the RESET pin. For information about using the RESET command, see the RESET section. 9.4.3 Power-Down Mode Power consumption is reduced to a minimum by placing the device into power-down mode. There are two ways to put the device into power-down mode: using the SLEEP command and taking the START pin low. During power-down mode, the internal reference status depends on the setting of the VREFCON bits in the MUX1 register; see the Register Maps section for details. 9.4.4 Conversion Control The START pin provides precise control of conversions. Pulse the START pin high to begin a conversion, as shown in Figure 38 and Table 9. The conversion completion is indicated by the DRDY pin going low and with the DOUT/DRDY pin when the DRDY MODE bit is 1 in the IDAC0 register. When the conversion completes, the device automatically powers down. During power down, the conversion result can be retrieved; however, START must be taken high before communicating with the configuration registers. The device stays powered down until the START pin is returned high to begin a new conversion. When the START pin returned high, the decimation filter is held in a reset state for 32 modulator clock cycles internally to allow the analog circuits to settle. Holding the START pin high configures the device to continuously convert as shown in Figure 39. tSTART START tCONV DOUT/DRDY 1 2 3 16 SCLK DRDY ADS1146/47/48 Status Converting Power-down Figure 38. Timing for Single Conversion Using START Pin 28 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Table 9. START Pin Conversion Times for Figure 38 SYMBOL tCONV (1) DESCRIPTION (1) DATA RATE (SPS) VALUE UNIT 5 200.295 ms 10 100.644 ms 20 50.825 ms 40 25.169 ms 80 12.716 ms 160 6.489 ms 320 3.247 ms 640 1.692 ms 1000 1.138 ms 2000 0.575 ms Time from START pulse to DRDY and DOUT/DRDY going low For fCLK = 4.096MHz START Data Ready Data Ready Data Ready DOUT/DRDY ADS1146/7/8 Status Converting Converting Converting Converting NOTE: SCLK held low in this example. Figure 39. Timing for Conversion with START Pin High With the START pin held high, the ADC converts the selected input channels continuously. This configuration continues until the START pin is taken low. The START pin can also be used to perform synchronized measurements for multi-channel applications by pulsing the START pin. With multiple devices, if each device receives the START pin pulse at the same time, all devices start a conversion on the rise of the start pin. If all devices are operating with the same data rate, all of the devices complete the conversion at the same time. Conversions can also be initiated through SPI commands. Similar to using the START pin, the device can be put into a power-down mode using the SLEEP command. Functionally, this is similar to taking the START pin low. To initiate a conversion, the WAKEUP command powers up the ADC and starts a conversion, similar to returning the START pin high. Note that the START pin must be held high to use commands to control conversions. Do not combine using the START pin and using commands to control conversions. Also, sending a SYNC command immediately starts a new ADC conversion. For the SYNC command, the digital filter is reset, starting a new conversion without completing the previous conversion. This is useful in synchronizing conversions from multiple devices or maintaining periodic timing from multiple channels. Similarly, writing to any of the first four registers (MUX0, VBIAS, MUX1, or SYS0; addresses 00h to 04h) automatically resets the digital filter. A change in any of these registers makes the appropriate setup change in the device, but also restarts the conversion similar to a SYNC command. 9.4.4.1 Settling Time for Channel Multiplexing The device is a true single-cycle settling ΔΣ converter. The first data available after the start of a conversion are fully settled and valid for use, provided that the input signal has settled to its final result. The time required to settle is roughly equal to the inverse of the data rate. The exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see Table 10 for specific values. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 29 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.4.4.2 Channel Cycling and Overload Recovery When cycling through channels, take care when configuring the device to ensure that settling occurs within one cycle. For setups that cycle through MUX channels, but do not change PGA and data rate settings, changing the MUX0 register is sufficient. However, when changing PGA and data rate settings, ensure that an overload condition cannot occur during the data transmission. When configuration register data are transferred to the device, new settings become active at the end of each byte sent. Therefore, a brief overload condition can occur during the transmission of configuration data after the completion of the MUX0 byte and before the completion of the SYS0 byte. This temporary overload can result in intermittent incorrect readings. To ensure that an overload does not occur, it may be necessary to split the communication into two separate communications allowing the change of the SYS0 register before the change of the MUX0 register. In the event of an overloaded state, take care to ensure single-cycle settling into the next cycle. Because the device implements a chopper-stabilized PGA, changing data rates during an overload state can cause the chopper to become unstable. This instability results in slow settling time. To prevent this slow settling, always change the PGA setting or MUX setting to a non-overloaded state before changing the data rate. 9.4.4.3 Single-Cycle Settling The ADS1146, ADS1147, and ADS1148 are capable of single-cycle settling across all gains and data rates. However, to achieve single-cycle settling at 2 kSPS, special care must be taken with respect to the interface using WREG to change a configuration register. When operating at 2 kSPS, the SCLK period must not exceed 520 ns, and the time between the beginning of writing a register byte data and the beginning of a subsequent register byte data must not exceed 4.2 µs. Additionally, when performing multiple individual write commands to the first four registers, wait at least 64 oscillator clocks before initiating another write command. 9.4.4.4 Digital Filter Reset Operation Apart from the RESET command and the RESET pin, the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0 registers is performed, when a SYNC command is issued, or the START pin is taken high. The filter is reset four system clocks (tCLK) after the falling edge of the seventh SCLK of the SYNC command. Similarly, if any write operation takes place in the MUX0 register, regardless of whether the register value changed or not, the filter is reset after the completion of the MUX0 write. If any write activity takes place in the VBIAS, MUX1, or SYS0 registers, regardless of whether the register value changed or not, the filter is reset. The reset pulse lasts for 32 modulator clocks after the completion of the write operation. If there are multiple write operations, the resulting reset pulse may be viewed as the ANDed result of the different active low pulses created individually by each action. Table 10 shows the conversion time after a filter reset. Note that this time depends on the operation initiating the reset. Also, the first conversion after a filter reset has a slightly different time than the second and subsequent conversions. 30 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Table 10. Data Conversion Time FIRST DATA CONVERSION TIME AFTER FILTER RESET NOMINAL DATA RATE (SPS) (1) EXACT DATA RATE (SPS) HARDWARE RESET, RESET COMMAND, START PIN HIGH, WAKEUP COMMAND, VBIAS, MUX1, or SYS0 REGISTER WRITE SYNC COMMAND, MUX0 REGISTER WRITE (ms) (1) NO. OF SYSTEM CLOCK CYCLES SECOND AND SUBSEQUENT CONVERSION TIME AFTER FILTER RESET (ms) (1) NO. OF SYSTEM CLOCK CYCLES (ms) (1) NO. OF SYSTEM CLOCK CYCLES 5 5.019 199.258 816160 200.26 820265 199.250 816128 10 10.038 99.633 408096 100.635 412201 99.625 408064 20 20.075 49.820 204064 50.822 208169 49.812 204032 40 40.151 24.920 102072 25.172 103106 24.906 102016 80 80.301 12.467 51064 12.719 52098 12.453 51008 160 160.602 6.241 25560 6.492 26594 6.226 25504 320 321.608 3.124 12796 3.250 13314 3.109 12736 640 643.216 1.569 6428 1.695 6946 1.554 6368 1000 1000.000 1.014 4156 1.141 4674 1.000 4096 2000 2000.000 0.514 2108 0.578 2370 0.500 2048 For fCLK = 4.096 MHz. 9.4.5 Calibration The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 40, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC) to digitally scale the gain. A digital clipping circuit ensures that the output code does not exceed 16 bits. Equation 17 shows the scaling. + S ´ OFC Register FSC Register 400000h ADC - Output Data Clipped to 16 Bits Final Output Figure 40. Calibration Block Diagram Final Output Data = (Input - OFC[2:1]) ´ FSC[2:0] 400000h (17) The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically by calibration commands. The offset and gain calibration features are intended for correction of minor system level offset and gain errors. When entering manual values into the calibration registers, take care to avoid scaling down the gain register to values far below a scaling factor of 1.0. Under extreme situations it is possible to over-range the ADC. Avoid encountering situations where analog inputs are connected to voltages greater than VREF / Gain. Take care when increasing digital gain with the FSC register. When implementing custom digital gains less than 20% higher than nominal and offsets less than 40% of full scale, no special care is required. When operating at digital gains greater than 20% higher than nominal and offsets greater than 40% of full scale, make sure that the offset and gain registers follow the conditions of Equation 18. 2V 1.251 V ! Offset Scaling Gain Scaling (18) Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 31 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.4.5.1 Offset Calibration Register: OFC[2:0] The offset calibration is a 24-bit word, composed of three 8-bit registers. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. The upper 16 bits, OFC[2:1], are the most important bits of the offset calibration register for calibration and can correct offsets ranging from –FS to +FS, as shown in Table 11. The lower eight bits, OFC[0], provide sub-LSB correction and are used by the calibration commands. If a calibration command is issued and the offset register is then read for storage and re-use later, it is recommended that all 24 bits of the OFC be used. When the calibration commands are not used and the offset is corrected by writing a user-calculated value to the OFC register, it is recommended that only OFC[2:1] be used and that OFC[0] be left as all zeros. A register value of 000000h provides no offset correction. Note that while the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 11), avoid overloading the analog inputs. Table 11. Final Output Code vs Offset Calibration Register Setting (1) OFFSET REGISTER FINAL OUTPUT CODE WITH VIN = 0 (1) 7FFFFFh 8000h 000100h FFFFh 000000h 0000h FFFF00h 0001h 800000h 7FFFh Excludes effects of noise and inherent offset errors. 9.4.5.2 Full-Scale Calibration Register: FSC[2:0] The full-scale or gain calibration is a 24-bit word composed of three 8-bit registers. The full-scale calibration value is 24-bit, straight binary, normalized to 1.0 at code 400000h. Table 12 summarizes the scaling of the fullscale register. Note that while the full-scale calibration register can correct gain errors > 1 (with gain scaling < 1), make sure to avoid overloading the analog inputs. Table 12. Gain Correction Factor vs Full-Scale Calibration Register Setting FULL-SCALE REGISTER GAIN SCALING 800000h 2 400000h 1 200000h 0.5 000000h 0 9.4.5.3 Calibration Commands The device provide commands for three types of calibration: system gain calibration, system offset calibration and self offset calibration. Where absolute accuracy is required, TI recommends performing a calibration after power up, a change in temperature, a change of gain and in some cases a change in channel. At the completion of calibration, the DRDY signal goes low indicating the calibration has completed. The first data after calibration are always valid. If the START pin is taken low or a SLEEP command is issued after any calibration command, the devices powers down after completing calibration. After a calibration has started, allow the calibration to complete before issuing any other commands (other than the SLEEP command). Issuing commands during a calibration can result in corrupted data. If this occurs, either resend the calibration command that was aborted or issue a device reset. 9.4.5.3.1 System Offset and Self Offset Calibration System offset calibration corrects both internal and external offset errors. The system offset calibration is initiated by sending the SYSOCAL command while applying a zero differential input voltage (VIN = 0 V) to the selected analog inputs with the inputs set within the specified input common-mode range, ideally at mid-supply. 32 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 The self offset calibration is initiated by sending the SELFOCAL command. During self offset calibration, the selected inputs are disconnected from the internal circuitry and a zero differential signal is applied internally, connecting the inputs to mid-supply. With both offset calibrations the offset calibration register (OFC) is updated afterwards. When either offset calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately. An offset calibration must be performed before a gain calibration. 9.4.5.3.2 System Gain Calibration System gain calibration corrects for gain error in the signal path. The system gain calibration is initiated by sending the SYSGCAL command while applying a full-scale input to the selected analog inputs. Afterwards the full-scale calibration register (FSC) is updated. When a system gain calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately. 9.4.5.4 Calibration Timing When calibration is initiated, the device performs 16 consecutive data conversions and averages the results to calculate the calibration value. This provides a more accurate calibration value. The time required for calibration is shown in Table 13 and can be calculated using Equation 19. Calibration Time t CAL 50 fCLK 32 fMOD 16 fDATA (19) Table 13. Calibration Time vs Data Rate (1) DATA RATE (SPS) CALIBRATION TIME (tCAL) (ms) (1) 5 3201.01 10 1601.01 20 801.012 40 400.26 80 200.26 160 100.14 320 50.14 640 25.14 1000 16.14 2000 8.07 For fCLK = 4.096 MHz. 9.5 Programming 9.5.1 Digital Interface The device provides an SPI-compatible serial communication interface plus a data ready signal (DRDY). Communication is full-duplex with the exception of a few limitations in regards to the RREG command and the RDATA command. These limitations are explained in detail in the Commands section. For the basic serial interface timing characteristics, see Figure 1 and Figure 2 of this document. 9.5.1.1 Chip Select (CS) The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT/DRDY pin enters a high-impedance state. Therefore, reading and writing to the serial interface are ignored and the serial interface is reset. DRDY pin operation is independent of CS. DRDY still indicates that a new conversion has completed and is forced high as a response to SCLK, even if CS is high. Taking CS high deactivates only the SPI communication with the device. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 33 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Programming (continued) 9.5.1.2 Serial Clock (SCLK) SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but TI recommends keeping SCLK as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and shifted out of DOUT on the rising edge of SCLK. 9.5.1.3 Data Input (DIN) DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the falling edge of SCLK. The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is to be sent to the device when reading out data, send the NOP command on DIN. 9.5.1.4 Data Ready (DRDY) The DRDY pin goes low to indicate a new conversion is complete, and the conversion result is stored in the conversion result buffer. SCLK must be held low for tDTS after the DRDY low transition (see Figure 2) so that the conversion result is loaded into both the result buffer and the output shift register. Therefore, issue no commands during this time frame if the conversion result is to be read out later. This constraint applies only when CS is asserted and the device is in RDATAC mode. When CS is not asserted, SPI communication with other devices on the SPI bus does not affect loading of the conversion result. After the DRDY pin goes low, it is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for 0 instead of waiting for a falling edge). If the DRDY pin is not taken high by clocking in SCLKs after it falls low, a short high pulse for a duration of tPWH indicates new data are ready. 9.5.1.5 Data Output and Data Ready (DOUT/DRDY) The DOUT/DRDY pin has two modes: data out (DOUT) only, or DOUT combined with data ready (DRDY). The DRDY MODE bit determines the function of this pin and can be found in the ID register in the ADS1146 and the IDAC0 register in the ADS1147 and ADS1148. In either mode, the DOUT/DRDY pin goes to a high-impedance state when CS is taken high. When the DRDY MODE bit is set to 0, this pin functions as DOUT only. Data are clocked out on the rising edge of SCLK, MSB first (as shown in Figure 41). When the DRDY MODE bit is set to 1, this pin functions as both DOUT and DRDY. Data are shifted out as with DOUT, but the pin adds the DRDY function. Note that this mode is not operational when the device is in stop read data continuous mode when the SDATAC command is given. The DRDY MODE bit modifies only the DOUT/DRDY pin functionality. The DRDY pin functionality remains unaffected. SCLK DOUT/DRDY(1) 1 2 D[15] D[14] 3 D[13] 14 D[2] 15 D[1] 16 1 2 8 D[0] DRDY CS tied low. Figure 41. Data Retrieval With the DRDY MODE Bit = 0 (Disabled) When the DRDY MODE bit is enabled and a new conversion is complete, DOUT/DRDY goes low if it is high. If it is already low, then DOUT/DRDY goes high and then goes low (as shown in Figure 42). Similar to the DRDY pin, a falling edge on the DOUT/DRDY pin signals that a new conversion result is ready. After DOUT/DRDY goes low, the data can be clocked out by providing 16 SCLKs if the device is in read data continuous mode. To force DOUT/DRDY high (so that DOUT/DRDY can be polled for a 0 instead of waiting for a falling edge), a no 34 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Programming (continued) operation command (NOP) or any other command that does not load the data output register can be sent after reading out the data. Because SCLKs can only be sent in multiples of eight, a NOP can be sent to force DOUT/DRDY high if no other command is pending. The DOUT/DRDY pin goes high after the first rising edge of SCLK after reading the conversion result completely (as shown in Figure 43). The same condition also applies after an RREG command. After all the register bits have been read out, the first rising edge of SCLK forces DOUT/DRDY high. Figure 44 shows an example where sending an extra NOP command after reading out a register with an RREG command forces the DOUT/DRDY pin high. SCLK DOUT/DRDY(1) 1 2 3 14 D[2] D[15] D[14] D[13] DIN NOP 15 16 D[1] 1 2 D[15] D[14] D[0] 16 D[0] NOP NOP DRDY CS tied low. Figure 42. Data Retrieval With the DRDY MODE Bit = 1 (Enabled) SCLK DOUT/DRDY(1) 1 2 3 14 D[2] D[15] D[14] D[13] DIN 15 16 D[1] 1 2 8 1 2 D[15] D[14] D[0] NOP NOP 16 D[0] NOP DRDY DRDY MODE bit enabled, CS tied low. Figure 43. DOUT/DRDY Forced High After Retrieving the Conversion Result SCLK 1 2 8 1 2 DOUT/DRDY(1) DIN 8 1 2 8 1 2 8 XXh RREG 00h NOP NOP DRDY MODE bit enabled, CS tied low. Figure 44. DOUT/DRDY Forced High After Reading Register Data 9.5.1.6 SPI Reset SPI communication is reset in several ways. To reset the serial interface (without resetting the registers or the digital filter), the CS pin can be pulled high. Taking the RESET pin low resets the serial interface along with all the other digital functions. This also returns all registers to their default values and start a new conversion. In systems where CS is tied low permanently, register writes must always be fully completed in 8-bit increments. If a glitch on SCLK disrupts SPI communications, commands are not recognized by the device. The device implements a timeout function for all listed commands in the event that data are corrupted and the CS pin is permanently tied low. The SPI timeout resets the interface if idle for 64 conversion cycles. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 35 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Programming (continued) 9.5.1.7 SPI Communication During Power-Down Mode When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. The RDATA command can be used to repeatedly read the last conversion result during power-down mode. Other commands do not function because the internal clock is shut down to save power during power-down mode. 9.5.2 Data Format The device provides 16 bits of data in binary twos complement format. The size of one code (LSB) is calculated using Equation 20. 1 LSB = (2 × VREF / Gain) / 216 = +FS / 215 (20) A positive full-scale (FS) input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 14 summarizes the ideal output codes for different input signals. Table 14. Ideal Output Code vs Input Signal INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE (1) ≥ FS (215 – 1) / 215 7FFFh 15 FS / 2 (1) 0001h 0 0000h –FS / 215 FFFFh ≤ –FS 8000h Excludes effects of noise, linearity, offset, and gain errors. Figure 45 shows the mapping of the analog input signal to the output codes. 7FFFh 0001h 0000h FFFFh ‡‡‡ Output Code ‡‡‡ 7FFEh 8001h 8000h ±FS ±FS ‡‡‡ 215 ± 1 215 0 FS ‡‡‡ Input Voltage VIN ±FS 215 ± 1 215 Figure 45. Code Transition Diagram 36 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.5.3 Commands The device offers 13 commands to control device operation as shown in Table 15. Some of the commands are stand-alone commands (WAKEUP, SLEEP, SYNC, RESET, SYSOCAL, SYSGCAL, and SELFOCAL). There are three additional commands used to control the read of data from the device (RDATA, RDATAC, and SDATAC). The commands to read (RREG) and write (WREG) configuration register data from and to the device require additional information as part of the instruction. A no-operation command (NOP) can be used to clock out data from the device without clocking in a command. Operands: • n = number of registers to be read or written (number of bytes – 1) • r = register (0 to 15) • x = don't care Table 15. SPI Commands COMMAND (1) (1) DESCRIPTION 1st COMMAND BYTE 2nd COMMAND BYTE WAKEUP Exit power down mode 0000 000x (00h, 01h) SLEEP Enter power down mode 0000 001x (02h, 03h) SYNC Synchronize ADC conversions 0000 010x (04h, 05h) RESET Reset to default values 0000 011x (06h, 07h) NOP No operation 1111 1111 (FFh) RDATA Read data once 0001 001x (12h, 13h) RDATAC Read data continuous mode 0001 010x (14h, 15h) SDATAC Stop read data continuous mode 0001 011x (16h, 17h) RREG Read from register rrrr 0010 rrrr (2xh) 0000 nnnn WREG Write to register rrrr 0100 rrrr (4xh) 0000 nnnn SYSOCAL System offset calibration 0110 0000 (60h) SYSGCAL System gain calibration 0110 0001 (61h) SELFOCAL Self offset calibration 0110 0010 (62h) Restricted Restricted command. Never send to the device. 1111 0001 (F1h) 0000 010x (04,05h) When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. 9.5.3.1 WAKEUP (0000 000x) Use the WAKEUP command to power up the device after a SLEEP command. After execution of the WAKEUP command, the device powers up on the falling edge of the eighth SCLK. 9.5.3.2 SLEEP (0000 001x) The SLEEP command places the device into power-down mode. When the SLEEP command is issued, the device completes the current conversion and then goes into power-down mode. Note that this command does not automatically power down the internal voltage reference; see the VREFCON bits in the MUX1 section for each device for further details. To exit power-down mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command. Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device, as shown in Figure 46. NOTE If the START pin is held low, a WAKEUP command does not power up the device. When using the SLEEP command, CS must be held low for the duration of the power-down mode. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 37 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com CS DIN SLEEP WAKEUP 0000 001X 0000 000X 1 8 SCLK DRDY Normal Mode Status Normal Mode Power-down Mode Finish Current Conversion Start New Conversion Figure 46. SLEEP and WAKEUP Commands Operation 9.5.3.3 SYNC (0000 010x) The SYNC command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices simultaneously. SYNC DIN 0000 010X 0000 010X 1 7 8 SCLK Synchronization Occurs Here 4 tCLK Figure 47. SYNC Command Operation 9.5.3.4 RESET (0000 011x) The RESET command restores the registers to the respective default values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the serial interface. If the RESET command is issued when the serial interface is out of synchonization due to a glitch on SCLK, the device does not reset. The CS pin can be used to reset the serial interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6 ms when the system clock frequency is 4.096 MHz, similar to the hardware reset. Therefore, SPI communication can only be started 0.6 ms after the RESET command is issued, as shown in Figure 48. DIN ANY SPI COMMAND RESET 1 7 8 1 8 SCLK 4 tCLK 0.6 ms Figure 48. SPI Communication after an SPI Reset 38 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.5.3.5 RDATA (0001 001x) The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result is read out by sending 16 SCLKs, as shown in Figure 49. This command also works in RDATAC mode. DRDY RDATA 0001 001X DIN DOUT NOP NOP MSB LSB SCLK 1 8 1 16 Figure 49. Figure Read Data Once When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are being shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the serial interface, as shown in Figure 50. 1 2 7 8 9 10 15 16 1 2 15 16 SCLK DOUT DIN D[15] D[14] NOP D[9] D[8] NOP D[7] D[6] NOP D[1] D[0] RDATA D[15] D[14] NOP D[1] D[0] NOP DRDY Figure 50. Using RDATA in Full-Duplex Mode 9.5.3.6 RDATAC (0001 010x) The RDATAC command enables read data continuous mode. This is the default mode after a power up or reset. In read data continuous mode, new conversion results are automatically loaded onto DOUT. The conversion result can be received from the device after the DRDY signal goes low by sending 16 SCLKs. It is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the command takes effect on the next DRDY as shown in Figure 51. Be sure to complete data retrieval (conversion result or register read-back) before DRDY returns low, or the resulting data is corrupted. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge occurs. DRDY RDATAC DIN NOP 0001 010X 16 Bits DOUT SCLK 1 8 1 16 Figure 51. Read Data Continuously Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 39 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.5.3.7 SDATAC (0001 011x) The SDATAC command terminates read data continuous mode. In stop read data continuous mode, the conversion result is not automatically loaded onto DOUT when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY. If DRDY is not actively monitored for data conversions, the stop read data continuous mode is the preferred method of reading data. In this mode, a read of ADC data is not interrupted by the completion of a new ADC conversion. 9.5.3.8 RREG (0010 rrrr, 0000 nnnn) The RREG command outputs the data from up to 15 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the value of the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. The two byte command structure for RREG is listed below. • First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read. • Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1. • Byte(s): data read from the registers are clocked out with NOPs. It is not possible to use the full-duplex nature of the serial interface when reading out the register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in Figure 52. Any command sent during the readout of the register data is ignored. Thus, TI recommends sending NOPs through DIN when reading out the register data. 1st 2nd Command Command Byte Byte 0010 0001 0000 0001 DIN DOUT VBIAS MUX1 Data Byte Data Byte Figure 52. Read from Register 9.5.3.9 WREG (0100 rrrr, 0000 nnnn) The WREG command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte. The command structure for WREG is listed below. • First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written. • Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1. • Byte(s): data to be written to the registers. DIN 0100 0010 0000 0001 MUX1 SYS0 1st Command 2nd Command Data Byte Data Byte Figure 53. Write to Register 40 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.5.3.10 SYSOCAL (0110 0000) The SYSOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be externally shorted to a voltage within the input common-mode range. The inputs must be near the mid-supply voltage of (AVDD + AVSS) / 2. The OFC register is updated when the command completes. Timing for the calibration commands can be found in Figure 54. Calibration Starts Calibration Complete tCAL DRDY CALIBRATION COMMAND DIN 1 8 SCLK 4 tCLK Figure 54. Calibration Command 9.5.3.11 SYSGCAL (0110 0001) The SYSGCAL command initiates the system gain calibration. For a system gain calibration, the input must be set to full-scale. The FSC register is updated after this operation. Timing for the calibration commands can be found in Figure 54. 9.5.3.12 SELFOCAL (0110 0010) The SELFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply and performs the calibration. The OFC register is updated after this operation. Timing for the calibration commands can be found in Figure 54. 9.5.3.13 NOP (1111 1111) This is a no-operation command. This is used to clock out data without clocking in a command. 9.5.3.14 Restricted Command (1111 0001) This is a restricted command. This command must never be issued to the device. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 41 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6 Register Maps 9.6.1 ADS1146 Register Map Table 16. ADS1146 Register Map ADDRESS REGISTER 00h BCS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 1 01h VBIAS 0 02h MUX1 CLKSTAT 0 0 0 0 0 0 0 0 0 03h SYS0 0 04h OFC0 OFC[7:0] 05h OFC1 OFC[15:8] 06h OFC2 OFC[23:16] 07h FSC0 FSC[7:0] 08h FSC1 FSC[15:8] 09h FSC2 FSC[23:16] 0Ah ID BCS[1:0] VBIAS[1:0] MUXCAL[2:0] PGA[2:0] DR[3:0] DRDY MODE ID[3:0] 0 0 0 9.6.2 ADS1146 Detailed Register Definitions 9.6.2.1 BCS—Burn-out Current Source Register (offset = 00h) [reset = 01h] These bits control the sensor burn-out detect current source. Figure 55. Burn-out Current Source Register 7 6 5 0 R-0h BCS[1:0] R/W-0h 4 0 R-0h 3 0 R-0h 2 0 R-0h 1 0 R-0h 0 1 R-1h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17. Burn-out Current Source Register Field Descriptions 42 BIT FIELD TYPE RESET DESCRIPTION 7:6 BCS[1:0] R/W 0h Burn-out Detect Current Source These bits control the setting of the sensor burn-out detect current source 00: Burn-out current source off (default) 01: Burn-out current source on, 0.5 µA 10: Burn-out current source on, 2 µA 11: Burn-out current source on, 10 µA 5:0 RESERVED R 01h Reserved Always write 000001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.6.2.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h] This register enables a bias voltage on the analog inputs. Figure 56. Bias Voltage Register 7 0 R-0h 6 0 R-0h 5 0 R-0h 4 0 R-0h 3 0 R-0h 2 0 R-0h 1 0 VBIAS[1:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. Bias Voltage Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 7:2 RESERVED R 00h Reserved Always write 000000 1 VBIAS[1] R/W 0h VBIAS[1] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AINN 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AINN 0 VBIAS[0] R/W 0h VBIAS[0] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AINP 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AINP Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 43 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6.2.3 MUX—Multiplexer Control Register (offset = 02h) [reset = x0h] Figure 57. Multiplexer Control Register 7 CLKSTAT R-xh 6 0 R-0h 5 0 R-0h 4 0 R-0h 3 0 R-0h 2 1 MUXCAL[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19. Multiplexer Control Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION CLKSTAT R xh Clock status This bit is read-only and indicates whether the internal oscillator or external clock is being used. 0: Internal oscillator in use 1: External clock in use 6:3 RESERVED R 0h Reserved Always write 0000 2:0 MUXCAL[2:0] R/W 0h System Monitor Control These bits are used to select a system monitor. The MUXCAL selection supercedes the selections from the VBIAS register. 000: Normal operation (default) 001: Offset calibration. The analog inputs are disconnected and AINP and AINN are internally connected to mid-supply (AVDD + AVSS) / 2. 010: Gain calibration. The analog inputs are connected to the voltage reference. 011: Temperature measurement. The inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device. 7 Table 20 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement. Table 20. MUXCAL Settings 44 MUXCAL[2:0] PGA GAIN SETTING ADC INPUT 000 Set by SYS0 register Normal operation 001 Set by SYS0 register Offset calibration: inputs shorted to mid-supply (AVDD + AVSS) / 2 010 Forced to 1 Gain calibration: V(REFP) – V(REFN) (full-scale) 011 Forced to 1 Temperature measurement diode Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.6.2.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h] Figure 58. System Control Register 0 7 0 R-0h 6 5 PGA[2:0] R/W-0h 4 3 2 1 0 DR[3:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21. System Control Register 0 Field Descriptions BIT FIELD TYPE RESET DESCRIPTION RESERVED R 0h Reserved Always write 0 6:4 PGA[2:0] R/W 0h Gain Setting for PGA These bits determine the gain of the PGA 000: PGA = 1 (default) 001: PGA = 2 010: PGA = 4 011: PGA = 8 100: PGA = 16 101: PGA = 32 110: PGA = 64 111: PGA = 128 3:0 DR[3:0] R/W 0h Data Output Rate Setting These bits determine the data output rate of the ADC 0000: DR = 5 SPS (default) 0001: DR = 10 SPS 0010: DR = 20 SPS 0011: DR = 40 SPS 0100: DR = 80 SPS 0101: DR = 160 SPS 0110: DR = 320 SPS 0111: DR = 640 SPS 1000: DR = 1000 SPS 1001 to 1111: DR = 2000 SPS 7 Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 45 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6.2.5 OFC—Offset Calibration Coefficient Registers (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h] These bits make up the offset calibration coefficient register of the ADS1146. Figure 59. Offset Calibration Coefficient Registers 7 6 5 4 3 2 1 0 11 10 9 8 19 18 17 16 OFC[7:0] R/W-00h 15 14 13 12 OFC[15:8] R/W-00h 23 22 21 20 OFC[23:16] R/W-00h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22. Offset Calibration Coefficient Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 23:0 OFC[23:0] R/W 000000h Offset Calibration Register Three registers compose the ADC 24-bit offset calibration word and is in twos complement format. The upper 16 bits (OFC[23:8]) can correct offsets ranging from -FS to +FS, while the lower eight bits (OFC[7:0]) provide sub-LSB correction. The ADC subtracts the register value from the conversion result before full scale operation. 9.6.2.6 FSC—Full-Scale Calibration Coefficient Registers (offset = 07h, 08h, 09h) [reset = 00h, 00h, 40h] These bits make up the full-scale calibration coefficient register. Figure 60. Full-Scale Calibration Coefficient Registers 7 6 5 4 3 2 4 0 11 10 9 8 19 18 17 16 FSC[7:0] R/W-00h 15 14 13 12 FSC[15:8] R/W-00h 23 22 21 20 FSC[23:16] R/W-40h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23. Full-Scale Calibration Coefficient Register Field Descriptions 46 BIT FIELD TYPE RESET DESCRIPTION 23:0 FSC[23:0] R/W 400000h Full-Scale Calibration Register Three registers compose the ADC 24-bit full-scale calibration word. The 24-bit word is straight binary. The ADC divides the register value of the FSC register by 400000h to derive the scale factor for calibration. After the offset calibration, the ADC multiplies the scale factor by the conversion result. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.6.2.7 ID—ID Register (offset = 0Ah) [reset = x0h] Figure 61. ID Register 7 6 5 4 3 DRDY MODE R/W-0h ID[3:0] R-xh 2 0 R-0h 1 0 R-0h 0 0 R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24. ID Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 7:4 ID[3:0] R xh Revision Identification Read-only, factory-programmed bits used for revision identification. Note: The revision ID may change without notification DRDY MODE R/W 0h Data Ready Mode Setting This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the dedicated DRDY pin continues to indicate data ready, active low. 0: DOUT/DRDY pin functions only as Data Out (default) 1: DOUT/DRDY pin functions both as Data Out and Data Ready, active low (1) RESERVED R 0h RESERVED These bits must always be set to 000 3 2:0 (1) Cannot be used in SDATAC mode 9.6.3 ADS1147 and ADS1148 Register Map Table 25. ADS1147 and ADS1148 Register Map ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BCS[1:0] BIT 4 BIT 3 00h MUX0 01h VBIAS MUX_SP[2:0] 02h MUX1 CLKSTAT 03h SYS0 0 04h OFC0 05h OFC1 OFC[15:8] 06h OFC2 OFC[23:16] 07h FSC0 FSC[7:0] 08h FSC1 FSC[15:8] 09h FSC2 FSC[23:16] 0Ah IDAC0 ID[3:0] 0Bh IDAC1 I1DIR[3:0] 0Ch GPIOCFG 0Dh GPIODIR IODIR[7:0] 0Eh GPIODAT IODAT[7:0] BIT 2 BIT 1 BIT 0 MUX_SN[2:0] VBIAS[7:0] VREFCON[1:0] REFSELT[1:0] PGA[2:0] MUXCAL[2:0] DR[3:0] OFC[7:0] DRDY MODE IMAG[2:0] I2DIR[3:0] IOCFG[7:0] Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 47 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6.4 ADS1147 and ADS1148 Detailed Register Definitions 9.6.4.1 MUX0—Multiplexer Control Register 0 (offset = 00h) [reset = 01h] This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits. Figure 62. Multiplexer Control Register 0 7 6 BCS[1:0] R/W-0h 5 4 MUX_SP[2:0] R/W-0h 3 2 1 MUX_SN[2:0] R/W-1h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26. Multiplexer Control Register 0 Register Field Descriptions 48 BIT FIELD TYPE RESET DESCRIPTION 7:6 BCS[1:0] R/W 0h Burn-out Detect Current Source Register These bits control the setting of the sensor burnout detect current source 00: Burn-out current source off (default) 01: Burn-out current source on, 0.5 µA 10: Burn-out current source on, 2 µA 11: Burn-out current source on, 10 µA 5:3 MUX_SP[2:0] R/W 0h Multiplexer Selection - ADC Positive Input Positive input channel selection bits 000: AIN0 (default) 001: AIN1 010: AIN2 011: AIN3 100: AIN4 (ADS1148 only) 101: AIN5 (ADS1148 only) 110: AIN6 (ADS1148 only) 111: AIN7 (ADS1148 only) 2:0 MUX_SN[2:0] R/W 1h Multiplexer Selection - ADC Negative Input Negative input channel selection bits 000: AIN0 001: AIN1 (default) 010: AIN2 011: AIN3 100: AIN4 (ADS1148 only) 101: AIN5 (ADS1148 only) 110: AIN6 (ADS1148 only) 111: AIN7 (ADS1148 only) Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.6.4.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h] Figure 63. Bias Voltage Register (ADS1147) 7 0 R-0h 6 0 R-0h 5 0 R-0h 4 0 R-0h 3 2 1 0 VBIAS[3:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27. Bias Voltage Register Field Descriptions (ADS1147) BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0h Reserved Always write 0000 3 VBIAS[3] R/W 0h VBIAS[3] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN3 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN3 2 VBIAS[2] R/W 0h VBIAS[2] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN2 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN2 1 VBIAS[1] R/W 0h VBIAS[1] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN1 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN1 0 VBIAS[0] R/W 0h VBIAS[0] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN0 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN0 Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 49 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Figure 64. Bias Voltage Register (ADS1148) 7 6 5 4 3 2 1 0 VBIAS[7:0] R/W-00h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28. Bias Voltage Register Field Descriptions (ADS1148) BIT 50 FIELD TYPE RESET DESCRIPTION 7 VBIAS[7] R/W 0h VBIAS[7] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN7 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN7 6 VBIAS[6] R/W 0h VBIAS[6] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN6 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN6 5 VBIAS[5] R/W 0h VBIAS[5] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN5 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN5 4 VBIAS[4] R/W 0h VBIAS[4] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN4 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN4 3 VBIAS[3] R/W 0h VBIAS[3] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN3 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN3 2 VBIAS[2] R/W 0h VBIAS[2] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN2 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN2 1 VBIAS[1] R/W 0h VBIAS[1] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN1 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN1 0 VBIAS[0] R/W 0h VBIAS[0] Voltage Enable A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN0 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN0 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.6.4.3 MUX1—Multiplexer Control Register 1 (offset = 02h) [reset = x0h] Figure 65. Multiplexer Control Register 1 7 CLKSTAT R-xh 6 5 4 VREFCON[1:0] R/W-0h 3 2 REFSELT[1:0] R/W-0h 1 MUXCAL[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29. Multiplexer Control Register 0 Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION CLKSTAT R xh Clock Status This bit is read-only and indicates whether the internal oscillator or external clock is being used 0: Internal oscillator in use 1: External clock in use 6:5 VREFCON[1:0] R/W 0h Internal Reference Control These bits control the internal voltage reference. These bits allow the reference to be turned on or off completely, or allow the reference state to follow the state of the device. Note that the internal reference is required for operation of the IDAC functions. 00: Internal reference is always off (default) 01: Internal reference is always on 10 or 11: Internal reference is on when a conversion is in progress and powers down when the device receives a SLEEP command or the START pin is taken low 4:3 REFSELT[1:0] R/W 0h Reference Select Control These bits select the reference input for the ADC. 00: REFP0 and REFN0 reference inputs selected (default) 01: REFP1 and REFN1 reference inputs selected (ADS1148 only) 10: Internal reference selected 11: Internal reference selected and internally connected to REFP0 and REFN0 input pins 2:0 MUXCAL[2:0] (1) R/W 0h System Monitor Control These bits are used to select a system monitor. The MUXCAL selection supercedes selections from the MUX0, MUX1, and VBIAS registers (includes MUX_SP, MUX_SN, VBIAS, and reference input selections). 000: Normal operation (default) 001: Offset calibration. The analog inputs are disconnected and AINP and AINN are internally connected to mid-supply (AVDD + AVSS) / 2. 010: Gain calibration. The analog inputs are connected to the voltage reference. 011: Temperature measurement. The inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device. 100: REF1 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP1) – V(REFN1)) / 4 (ADS1148 only) 101: REF0 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP0) – V(REFN0)) / 4 110: Analog supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (AVDD – AVSS) / 4 111: Digital supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (DVDD – DGND) / 4 7 (1) When using either reference monitor, the internal reference must be enabled. Table 30 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 51 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Table 30. MUXCAL Settings MUXCAL[2:0] PGA GAIN SETTING ADC INPUT 000 Set by SYS0 register Normal operation 001 Set by SYS0 register Inputs shorted to mid-supply (AVDD + AVSS) / 2 010 Forced to 1 V(REFP) – V(REFN) (full-scale) 011 Forced to 1 Temperature measurement diode 100 Forced to 1 (V(REFP1) – V(REFN1)) / 4 101 Forced to 1 (V(REFP0) – V(REFN0)) / 4 110 Forced to 1 (AVDD – AVSS) / 4 111 Forced to 1 (DVDD – DGND) / 4 9.6.4.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h] Figure 66. System Control Register 0 7 0 6 R-0h 5 PGA[2:0] 4 3 2 1 0 DR[3:0] R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31. System Control Register 0 Field Descriptions BIT FIELD TYPE RESET DESCRIPTION RESERVED R 0h Reserved Always write 0 6:4 PGA[2:0] R/W 0h Gain Setting for PGA These bits determine the gain of the PGA 000: PGA = 1 (default) 001: PGA = 2 010: PGA = 4 011: PGA = 8 100: PGA = 16 101: PGA = 32 110: PGA = 64 111: PGA = 128 3:0 DR[3:0] R/W 0h Data Output Rate Setting These bits determine the data output rate of the ADC 0000: DR = 5 SPS (default) 0001: DR = 10 SPS 0010: DR = 20 SPS 0011: DR = 40 SPS 0100: DR = 80 SPS 0101: DR = 160 SPS 0110: DR = 320 SPS 0111: DR = 640 SPS 1000: DR = 1000 SPS 1001 to 1111: DR = 2000 SPS 7 52 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.6.4.5 OFC—Offset Calibration Coefficient Register (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h] These bits make up the offset calibration coefficient register of the ADS1147 and ADS1148. Figure 67. Offset Calibration Coefficient Register 7 6 5 4 3 2 1 0 11 10 9 8 19 18 17 16 OFC[7:0] R/W-00h 15 14 13 12 OFC[15:8] R/W-00h 23 22 21 20 OFC[23:16] R/W-00h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32. Offset Calibration Coefficient Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 23:0 OFC[23:0] R/W 000000h Offset Calibration Register Three registers compose the ADC 24-bit offset calibration word and is in twos complement format. The upper 16 bits (OFC[23:8]) can correct offsets ranging from -FS to +FS, while the lower eight bits (OFC[7:0]) provide sub-LSB correction. The ADC subtracts the register value from the conversion result before full scale operation. 9.6.4.6 FSC—Full-Scale Calibration Coefficient Register (offset = 07h, 08h, 09h) [reset = 00h, 00h, 40h] These bits make up the full-scale calibration coefficient register. Figure 68. Full-Scale Calibration Coefficient Register 7 6 5 4 3 2 4 0 11 10 9 8 19 18 17 16 FSC[7:0] R/W-00h 15 14 13 12 FSC[15:8] R/W-00h 23 22 21 20 FSC[23:16] R/W-40h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33. Full-Scale Calibration Coefficient Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 23:0 FSC[23:0] R/W 400000h Full-Scale Calibration Register Three registers compose the ADC 24-bit full-scale calibration word. The 24-bit word is straight binary. The ADC divides the register value of the FSC register by 400000h to derive the scale factor for calibration. After the offset calibration, the ADC multiplies the scale factor by the conversion result. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 53 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6.4.7 IDAC0—IDAC Control Register 0 (offset = 0Ah) [reset = x0h] Figure 69. IDAC Control Register 0 7 6 5 4 3 DRDY MODE R/W-0h ID[3:0] R-xh 2 1 IMAG[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34. IDAC Control Register 0 Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 7:4 ID[3:0] R xh Revision Identification Read-only, factory-programmed bits used for revision identification. Note: The revision ID may change without notification DRDY MODE R/W 0h Data Ready Mode Setting This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the dedicated DRDY pin continues to indicate data ready, active low. 0: DOUT/DRDY pin functions only as Data Out (default) 1: DOUT/DRDY pin functions both as Data Out and Data Ready, active low (1) IMAG[2:0] R/W 0h IDAC Excitation Current Magnitude The ADS1147 and ADS1148 have two excitation current sources (IDACs) that can be used for sensor excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the internal reference to be on. 000: off (default) 001: 50 µA 010: 100 µA 011: 250 µA 100: 500 µA 101: 750 µA 110: 1000 µA 111: 1500 µA 3 2:0 (1) 54 Cannot be used in SDATAC mode Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 9.6.4.8 IDAC1—IDAC Control Register 1 (offset = 0Bh) [reset = FFh] Figure 70. IDAC Control Register 1 7 6 5 4 3 2 I1DIR[3:0] R/W-Fh 1 0 I2DIR[3:0] R/W-Fh LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The two IDACs on the ADS1148 can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs. Table 35. IDAC Control Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 7:4 I1DIR[3:0] R/W Fh IDAC Excitation Current Output 1 These bits select the output pin for the first excitation current source 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 (ADS1148 only) 0101: AIN5 (ADS1148 only) 0110: AIN6 (ADS1148 only) 0111: AIN7 (ADS1148 only) 10x0: IEXC1 (ADS1148 only) 10x1: IEXC2 (ADS1148 only) 11xx: Disconnected (default) 3:0 I2DIR[3:0] R/W Fh IDAC Excitation Current Output 2 These bits select the output pin for the second excitation current source 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 (ADS1148 only) 0101: AIN5 (ADS1148 only) 0110: AIN6 (ADS1148 only) 0111: AIN7 (ADS1148 only) 10x0: IEXC1 (ADS1148 only) 10x1: IEXC2 (ADS1148 only) 11xx: Disconnected (default) Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 55 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6.4.9 GPIOCFG—GPIO Configuration Register (offset = 0Ch) [reset = 00h] Figure 71. GPIO Configuration Register (ADS1147) 7 0 R-0h 6 0 R-0h 5 0 R-0h 4 0 R-0h 3 2 1 0 IOCFG[3:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 36. GPIO Configuration Register Field Descriptions (ADS1147) 56 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0h Reserved Always write 0000 3 IOCFG[3] R/W 0h GPIO[3] (AIN3) Pin Configuration 0: GPIO[3] is not enabled (default) 1: GPIO[3] is applied to AIN3 2 IOCFG[2] R/W 0h GPIO[2] (AIN2) Pin Configuration 0: GPIO[2] is not enabled (default) 1: GPIO[2] is applied to AIN2 1 IOCFG[1] R/W 0h GPIO[1] (REFN0) Pin Configuration 0: GPIO[1] is not enabled (default) 1: GPIO[1] is applied to REFN0 0 IOCFG[0] R/W 0h GPIO[0] (REFP0) Pin Configuration 0: GPIO[0] is not enabled (default) 1: GPIO[0] is applied to REFP0 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Figure 72. GPIO Configuration Register (ADS1148) 7 6 5 4 3 2 1 0 IOCFG[7:0] R/W-00h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 37. GPIO Configuration Register Field Descriptions (ADS1148) BIT FIELD TYPE RESET DESCRIPTION 7 IOCFG[7] R/W 0h GPIO[7] (AIN7) Pin Configuration 0: GPIO[7] is not enabled (default) 1: GPIO[7] is applied to AIN7 6 IOCFG[6] R/W 0h GPIO[6] (AIN6) Pin Configuration 0: GPIO[6] is not enabled (default) 1: GPIO[6] is applied to AIN6 5 IOCFG[5] R/W 0h GPIO[5] (AIN5) Pin Configuration 0: GPIO[5] is not enabled (default) 1: GPIO[5] is applied to AIN5 4 IOCFG[4] R/W 0h GPIO[4] (AIN4) Pin Configuration 0: GPIO[4] is not enabled (default) 1: GPIO[4] is applied to AIN4 3 IOCFG[3] R/W 0h GPIO[3] (AIN3) Pin Configuration 0: GPIO[3] is not enabled (default) 1: GPIO[3] is applied to AIN3 2 IOCFG[2] R/W 0h GPIO[2] (AIN2) Pin Configuration 0: GPIO[2] is not enabled (default) 1: GPIO[2] is applied to AIN2 1 IOCFG[1] R/W 0h GPIO[1] (REFN0) Pin Configuration 0: GPIO[1] is not enabled (default) 1: GPIO[1] is applied to REFN0 0 IOCFG[0] R/W 0h GPIO[0] (REFP0) Pin Configuration 0: GPIO[0] is not enabled (default) 1: GPIO[0] is applied to REFP0 Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 57 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6.4.10 GPIODIR—GPIO Direction Register (offset = 0Dh) [reset = 00h] Figure 73. GPIO Direction Register (ADS1147) 7 0 R-0h 6 0 R-0h 5 0 R-0h 4 0 R-0h 3 2 1 0 IODIR[3:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 38. GPIO Direction Register Field Descriptions (ADS1147) 58 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0h Reserved Always write 0000 3 IODIR[3] R/W 0h GPIO[3] (AIN3) Pin Direction Configures GPIO[3] as a GPIO input or GPIO output 0: GPIO[3] is an output (default) 1: GPIO[3] is an input 2 IODIR[2] R/W 0h GPIO[2] (AIN2) Pin Direction Configures GPIO[2] as a GPIO input or GPIO output 0: GPIO[2] is an output (default) 1: GPIO[2] is an input 1 IODIR[1] R/W 0h GPIO[1] (REFN0) Pin Direction Configures GPIO[1] as a GPIO input or GPIO output 0: GPIO[1] is an output (default) 1: GPIO[1] is an input 0 IODIR[0] R/W 0h GPIO[0] (REFP0) Pin Direction Configures GPIO[0] as a GPIO input or GPIO output 0: GPIO[0] is an output (default) 1: GPIO[0] is an input Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Figure 74. GPIO Direction Register (ADS1148) 7 6 5 4 3 2 1 0 IODIR[7:0] R/W-00h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 39. GPIO Direction Register Field Descriptions (ADS1148) BIT FIELD TYPE RESET DESCRIPTION 7 IODIR[7] R/W 0h GPIO[7] (AIN7) Pin Direction Configures GPIO[7] as a GPIO input or GPIO output 0: GPIO[7] is an output (default) 1: GPIO[7] is an input 6 IODIR[6] R/W 0h GPIO[6] (AIN6) Pin Direction Configures GPIO[6] as a GPIO input or GPIO output 0: GPIO[6] is an output (default) 1: GPIO[6] is an input 5 IODIR[5] R/W 0h GPIO[5] (AIN5) Pin Direction Configures GPIO[5] as a GPIO input or GPIO output 0: GPIO[5] is an output (default) 1: GPIO[5] is an input 4 IODIR[4] R/W 0h GPIO[4] (AIN4) Pin Direction Configures GPIO[4] as a GPIO input or GPIO output 0: GPIO[4] is an output (default) 1: GPIO[4] is an input 3 IODIR[3] R/W 0h GPIO[3] (AIN3) Pin Direction Configures GPIO[3] as a GPIO input or GPIO output 0: GPIO[3] is an output (default) 1: GPIO[3] is an input 2 IODIR[2] R/W 0h GPIO[2] (AIN2) Pin Direction Configures GPIO[2] as a GPIO input or GPIO output 0: GPIO[2] is an output (default) 1: GPIO[2] is an input 1 IODIR[1] R/W 0h GPIO[1] (REFN0) Pin Direction Configures GPIO[1] as a GPIO input or GPIO output 0: GPIO[1] is an output (default) 1: GPIO[1] is an input 0 IODIR[0] R/W 0h GPIO[0] (REFP0) Pin Direction Configures GPIO[0] as a GPIO input or GPIO output 0: GPIO[0] is an output (default) 1: GPIO[0] is an input Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 59 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 9.6.4.11 GPIODAT—GPIO Data Register (offset = 0Eh) [reset = 00h] Figure 75. GPIO Data Register (ADS1147) 7 0 R-0h 6 0 R-0h 5 0 R-0h 4 0 R-0h 3 2 1 0 IODAT[3:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 40. GPIO Data Register Field Descriptions (ADS1147) 60 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0h Reserved Always write 0000 3 IODAT[3] R/W 0h GPIO[3] (AIN3) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[3] is low (default) 1: GPIO[3] is high 2 IODAT[2] R/W 0h GPIO[2] (AIN2) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[2] is low (default) 1: GPIO[2] is high 1 IODAT[1] R/W 0h GPIO[1] (REFN0) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[1] is low (default) 1: GPIO[1] is high 0 IODAT[0] R/W 0h GPIO[0] (REFP0) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[0] is low (default) 1: GPIO[0] is high Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Figure 76. GPIO Data Register (ADS1148) 7 6 5 4 3 2 1 0 IODAT[7:0] R/W-00h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 41. GPIO Data Register Field Descriptions (ADS1148) BIT FIELD TYPE RESET DESCRIPTION 7 IODAT[7] R/W 0h GPIO[7] (AIN7) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[7] is low (default) 1: GPIO[7] is high 6 IODAT[6] R/W 0h GPIO[6] (AIN6) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[6] is low (default) 1: GPIO[6] is high 5 IODAT[5] R/W 0h GPIO[5] (AIN5) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[5] is low (default) 1: GPIO[5] is high 4 IODAT[4] R/W 0h GPIO[4] (AIN4) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[4] is low (default) 1: GPIO[4] is high 3 IODAT[3] R/W 0h GPIO[3] (AIN3) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[3] is low (default) 1: GPIO[3] is high 2 IODAT[2] R/W 0h GPIO[2] (AIN2) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[2] is low (default) 1: GPIO[2] is high 1 IODAT[1] R/W 0h GPIO[1] (REFN0) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[1] is low (default) 1: GPIO[1] is high 0 IODAT[0] R/W 0h GPIO[0] (REFP0) Pin Data Configured as an output, read returns the register value Configured as an input, write sets the register value only 0: GPIO[0] is low (default) 1: GPIO[0] is high Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 61 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The ADS1146, ADS1147, and ADS1148 make up a family of precision, 16-bit, ΔΣ ADCs that offers many integrated features to ease the measurement of the most common sensor types including various types of temperature and bridge sensors. Primary considerations when designing an application with these devices include connecting and configuring the serial interface, designing the analog input filtering, establishing an appropriate external reference for ratiometric measurements, and setting the common-mode input voltage for the internal PGA. These considerations are discussed in the following sections. 10.1.1 Serial Interface Connections Figure 77 shows the principle serial interface connections for the ADS1148. 47 GPIO 3.3 V 47 1 0.1 PF DVDD SCLK 28 SCLK 47 2 DGND DIN 27 MOSI 47 3 CLK DOUT/DRDY 26 MISO Microcontroller with SPI 47 4 RESET DRDY 25 GPIO/IRQ 47 5 REFP0 CS 24 GPIO 47 6 REFN0 START 23 GPIO 5V 7 REFP1 AVDD 3.3 V 22 DVDD Device 1 PF 8 REFN1 AVSS 21 9 VREFOUT IEXC1 20 10 VREFCOM IEXC2 19 11 AIN0 AIN0 18 12 AIN1 AIN1 17 13 AIN4 AIN7 16 14 AIN5 AIN6 15 0.1 PF 0.1 PF DVSS Copyright © 2016, Texas Instruments Incorporated Figure 77. Serial Interface Connections Most microcontroller SPI peripherals can operate with the ADS1148. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol employed by the device can be found in the Serial Interface Timing Requirements section. TI recommends placing 47-Ω resistors in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, DRDY, RESET and START). This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care must be taken to meet all SPI timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines. 62 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Application Information (continued) 10.1.2 Analog Input Filtering Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and second, to reduce external noise from being a part of the measurement. As with any sampled system, aliasing can occur if proper anti-alias filtering is not in place. Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the actual frequency band of interest below half the sampling frequency. Note that inside a ΔΣ ADC, the input signal is sampled at the modulator frequency, fMOD and not at the output data rate. The filter response of the digital filter repeats at multiples of the fMOD, as shown in Figure 78. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any frequency components present in the input signal around the modulator frequency or multiples thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter. Magnitude Sensor Signal Unwanted Signals Unwanted Signals Output Data Rate fMOD / 2 fMOD Frequency fMOD Frequency fMOD Frequency Magnitude Digital Filter Aliasing of Unwanted Signals Output Data Rate fMOD / 2 Magnitude External Antialiasing Filter Roll-Off Output Data Rate fMOD / 2 Figure 78. Effect of Aliasing Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 63 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Application Information (continued) Many sensor signals are inherently bandlimited; for example, the output of a thermocouple has a limited rate of change. In this case, the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However, any noise pickup along the sensor wiring or the application circuitry can potentially alias into the pass-band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and cellular phones. Another noise source typically exists on the printed-circuit board (PCB) itself in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result. A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond fMOD/2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS1148 attenuates signals to a certain degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise components are usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a cutoff frequency set at the output data rate or 10× higher is generally a good starting point for a system design. Internal to the device, prior to the PGA inputs, is an EMI filter; see Figure 20. The cutoff frequency of this filter is approximately 47 MHz, which helps reject high-frequency interferences. 10.1.3 External Reference and Ratiometric Measurements The full-scale range of the ADS1148 is defined by the reference voltage and the PGA gain (FSR = ±VREF / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to the specific system requirements. An external reference must be used if VIN > 2.048 V. For example, an external 2.5-V reference is required to measure signals as large as 2.5 V. Note that the input signal must be within the common-mode input range to be valid, and that the reference input voltage must be between 0.5 V and (AVDD – AVSS – 1 V). The buffered reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric measurement, the same excitation source that is used to excite the sensor is also used to establish the reference for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with the element being measured. The voltage that develops across the reference element is used as the reference source for the ADC. In this configuration, current noise and drift are common to both the sensor measurement and the reference; therefore, these components cancel out in the ADC transfer function. The output code is only a ratio of the sensor element value and the reference resistor value, and is not affected by the absolute value of the excitation current. 10.1.4 Establishing a Proper Common-Mode Input Voltage The ADS1148 is used to measure various types of signal configurations. However, configuring the input of the device properly for the respective signal type is important. The ADS1148 features an 8-input multiplexer (while the ADS1147 has a 4-input multiplexer). Each input can be independently selected as the positive input or the negative input to be measured by the ADC. With an 8-input multiplexer, the user can measure four independent differential-input channels. The user can also choose to measure 7 channels, using one input as a fixed common input. Regardless of the analog input configuration, make sure that all inputs, including the common input are within the common-mode input voltage range. If the supply is unipolar (for example, AVSS = 0 V and AVDD = 5 V), then V(AINN) = 0 V is not within the commonmode input range as shown by Equation 3. Therefore, a single-ended measurement with the common input connected to ground is not possible. TI recommends connecting the common-input to mid-supply or alternatively to VREFOUT. Note that the common-mode range becomes further restricted with increasing PGA gain. If the supply is bipolar (AVSS = –2.5 V and AVDD = 2.5 V), then ground is within the common-mode input range. Single-ended measurements with the common input connected to 0 V are possible in this case. For a detailed explanation of the common-mode input range as it relates to the PGA see the PGA CommonMode Voltage Requirements section. 64 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Application Information (continued) 10.1.5 Isolated (or Floating) Sensor Inputs Isolated sensors (sensors that are not referenced to the ADC ground) must have a common-mode voltage established within the specified ADC input range. Level shift the common-mode voltage by external resistor biasing, by connecting the negative lead to ground (bipolar analog supply), or by connecting to a DC voltage (unipolar analog supply). The 2.048-V reference output voltage may also be used to provide level shifting to floating sensor inputs. 10.1.6 Unused Inputs and Outputs To minimize leakage currents on the analog inputs, leave unused analog inputs floating, connect them to midsupply, or connect them to AVDD. Connecting unused analog inputs to AVSS is possible as well, but can yield higher leakage currents than the options mentioned before. Do not float unused digital inputs or excessive power-supply leakage current may result. Tie all unused digital inputs to the appropriate levels, DVDD or DGND, including when in power-down mode. If the DRDY output is not used, leave the pin unconnected or tie it to DVDD using a weak pullup resistor. 10.1.7 Pseudo Code Example The following list shows a pseudo code sequence with the required steps to set up the device and the microcontroller that interfaces to the ADC to take subsequent readings from the ADS1148 in stop read data continuous (SDATAC) mode. In SDATAC mode, it is sufficient to wait for a time period longer than the data rate to retrieve the conversion result. New conversion data does not interrupt the reading of registers or data on DOUT. However in this example, the dedicated DRDY pin is used to indicate availability of new conversion data instead of waiting a set time period for a readout. The default configuration register settings are changed to PGA gain = 16, using the internal reference, and a data rate of 20 SPS. Power up; Delay for a minimum of 16 ms to allow power supplies to settle and power-on reset to complete; Enable the device by setting the START pin high; Configure the serial interface of the microcontroller to SPI mode 1 (CPOL = 0, CPHA =1); If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an output; Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt input; Set CS to the device low; Delay for a minimum of tCSSC; Send the RESET command (06h) to make sure the device is properly reset after power up; Delay for a minimum of 0.6 ms; Send SDATAC command (16h) to prevent the new data from interrupting data or register transactions; Write the respective register configuration with the WREG command (40h, 03h, 01h, 00h, 03h and 42h); As an optional sanity check, read back all configuration registers with the RREG command (four bytes from 20h, 03h); Send the SYNC command (04h) to start the ADC conversion; Delay for a minimum of tSCCS; Clear CS to high (resets the serial interface); Loop { Wait for DRDY to transition low; Take CS low; Delay for a minimum of tCSSC; Send the RDATA command (12h); Send 16 SCLKs to read out conversion data on DOUT/DRDY; Delay for a minimum of tSCCS; Clear CS to high; } Take CS low; Delay for a minimum of tCSSC; Send the SLEEP command (02h) to stop conversions and put the device in power-down mode; Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 65 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Application Information (continued) 10.1.8 Channel Multiplexing Example This example applies only to the ADS1147 and ADS1148. It explains a method to use the device with two sensors connected to two different analog channels. Figure 79 shows the sequence of SPI operations performed on the device. After power up, 216 tCLK cycles are required before communication can be started. During the first 216 tCLK cycles, the device is internally held in a reset state. In this example, one of the sensors is connected to channels AIN0 and AIN1 and the other sensor is connected to channels AIN2 and AIN3. The ADC is operated at a data rate of 2 kSPS. The PGA gain is set to 32 for both sensors. VBIAS is connected to the negative terminal of both sensors (that is, channels AIN1 and AIN3). All these settings can be changed by performing a block write operation on the first four registers of the device. After the DRDY pin goes low, the conversion result can be immediately retrieved by sending in 16 SCLK pulses because the device defaults to RDATAC mode. As the conversion result is being retrieved, the active input channels can be switched to AIN2 and AIN3 by writing into the MUX0 register in a full-duplex manner, as shown in Figure 79. The write operation is completed with an additional eight SCLK pulses. The time from the write operation into the MUX0 register to the next DRDY low transition is shown in Figure 79 and is 0.513 ms in this case. After DRDY goes low, the conversion result can be retrieved and the active channel can be switched as before. Power-up sequence ADC initial setup Multiplexer change to channel 2 Data retrieval for channel 2 conversion (1) 16 ms DVDD START RESET CS WREG WREG NOP DIN SCLK Conversion result for channel 1 Conversion result for channel 2 DOUT Initial setting: AIN0 is the positive channel, AIN1 is the negative channel, Internal reference selected, PGA gain = 32, DR = 2 kSPS, VBIAS is connected to pins AIN1 and AIN3 DRDY (1) 0.513 ms for MUX0 write tDRDY AIN2 is the positive channel, AIN3 is the negative channel. For fCLK = 4.096 MHz. Figure 79. SPI Communication Sequence for Channel Multiplexing 66 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Application Information (continued) 10.1.9 Power-Down Mode Example This second example deals with performing one conversion after power up and then entering power-down mode. In this example, a sensor is connected to input channels AIN0 and AIN1. Commands to set up the device must occur at least 216 system clock cycles after powering up the device. The ADC operates at a data rate of 2 kSPS. The PGA gain is set to 32. VBIAS is connected to the negative terminal of the sensor (that is, channel AIN1). All these settings can be changed by performing a block write operation on the first four registers of the device. After performing the block write operation, the START pin can be taken low. The device enters the power-down mode as soon as DRDY goes low 0.575 ms after writing into the SYS0 register. The conversion result can be retrieved even after the device enters power-down mode by sending 16 SCLK pulses. Power-up sequence ADC is put in power-down mode after a single conversion. Data are retrieved when the ADC is powered down ADC initial setup 16 ms(1) DVDD START RESET CS WREG NOP DIN SCLK Conversion result for channel 1 DOUT DRDY Initial setting: AIN0 is the positive channel, AIN1 is the negative channel, Internal reference selected, PGA gain = 32, DR = 2 kSPS, VBIAS is connected to AIN1 (1) tDRDY (0.575 ms) ADC enters power-down mode For fCLK = 4.096 MHz. Figure 80. SPI Communication Sequence for Entering Power-Down Mode After a Conversion Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 67 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 10.2 Typical Applications 10.2.1 Ratiometric 3-Wire RTD Measurement System Figure 81 shows a 3-wire RTD application circuit with lead-wire compensation using the ADS1147. The two IDAC current sources integrated in the ADS1147 are used to implement the lead-wire compensation. One IDAC current source (IDAC1) provides excitation to the RTD element. The other current source (IDAC2) has the same current setting, providing cancellation of lead-wire resistance by generating a voltage drop across lead-wire resistance RLEAD2 equal to the voltage drop across RLEAD1. Because the voltage across the RTD is measured differentially at ADC pins AIN1 and AIN2, the voltages across the lead-wire resistances cancel. The ADC reference voltage (pins REFP0 and REFN0) is derived from the voltage across RREF with the currents from IDAC1 and IDAC2, providing ratiometric cancellation of current-source drift. RREF also level shifts the RTD signal to within the ADC specified common-mode input range. IDAC1 CI_CM1 RI1 ADS1147 IDAC2 AIN0/IEXC1 AIN1 RLEAD1 CI_DIFF RRTD AIN2 RLEAD2 RI2 CI_CM2 MUX û ADC PGA AIN3/IEXC2 RLEAD3 Reference Buffer/MUX REFN0 REFP0 CR_CM1 CR_CM2 CR_DIFF RR1 RR2 IIDAC1 + IIDAC2 RREF Copyright © 2016, Texas Instruments Incorporated Figure 81. Ratiometric 3-Wire RTD Measurement System Featuring the ADS1147 10.2.1.1 Design Requirements Table 42 shows the design requirements of the 3-wire RTD application. Table 42. 3-Wire RTD Application Requirements PARAMETER (1) 68 VALUE Supply voltage 3.3 V Data rate 20 SPS RTD type 3-wire PT100 RTD excitation current 1 mA Temperature –200°C to 850°C Calibrated temperature measurement accuracy at TA = 25ºC (1) ±0.2°C Not accounting for error of RTD; a two-point gain and offset calibration are performed, as well as chopping of the excitation currents to remove IDAC mismatch errors. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 10.2.1.2 Detailed Design Procedure 10.2.1.2.1 Topology Figure 82 shows the basic topology of a ratiometric measurement using an RTD. Shown are the ADC with the RTD and a reference resistor RREF. There is a single current source, labeled IDAC1 which is used to excite the RTD as well as to establish a reference voltage for the ADC across RREF. IDAC1 û ADC RRTD REFP REFN RREF Figure 82. Example of a Ratiometric RTD Measurement With IDAC1, the ADC measures the RTD voltage using the voltage across RREF as the reference. This gives a measurement such that the output code is proportional to the ratio of the RTD voltage and the reference voltage as shown in Equation 21 and Equation 22. Code ∝ VRTD / VREF Code ∝ (RRTD × IIDAC1) / (RREF × IIDAC1) (21) (22) The currents cancel so that the equation reduces to Equation 23: Code ∝ RRTD / RREF (23) As shown in Equation 23, the measurement depends on the resistive value of the RTD and the reference resistor RREF, but not on the IDAC1 current value. Therefore, the absolute accuracy and temperature drift of the excitation current does not matter. This is a ratiometric measurement. As long as there is no current leakage from IDAC1 outside of this circuit, the measurement depends only on RRTD and RREF. In Figure 83, the lead resistances of a 3-wire RTD are shown and another excitation current source is added, labeled IDAC2. IDAC1 RLEAD1 RRTD û ADC RLEAD2 REFP RLEAD3 REFN IDAC2 RREF Figure 83. Example of Lead Wire Compensation Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 69 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com With a single excitation current source, RLEAD1 adds an error to the measurement. By adding IDAC2, the second excitation current source is used to cancel out the error in the lead wire resistance. When adding the lead resistances and the second current source, the equation becomes: Code ∝ (VRTD + (RLEAD1 × IIDAC1) – (RLEAD2 × IIDAC2)) / (VREF × (IIDAC1 + IIDAC2)) (24) If the lead resistances match and the excitation currents match, then RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2. The lead wire resistances cancel out so that Equation 24 reduces to the result in Equation 25 maintaining a ratiometric measurement. Code ∝ RRTD / (2 × RREF) (25) RLEAD3 is not part of the measurement, because it is not in the input measurement path or in the reference input path. As Equation 24 shows, the two current sources must be matched to cancel the lead resistances of the RTD wires. Any mismatch in the two current sources is minimized by using the multiplexer to swap or chop the two current sources between the two inputs. Taking measurements in both configurations and averaging the readings reduces the effects of mismatched current sources. The design uses the multiplexer in the ADS1147 to implement this chopping technique to remove the mismatch error between IDAC1 and IDAC2. 10.2.1.2.2 RTD Selection The RTD is first chosen to be a PT100 element. The RTD resistance is defined by the Callendar-Van Dusen (CVD) equations and the resistance of the RTD is known depending on the temperature. The PT100 RTD has an impedance of 100 Ω at 0˚C and roughly 0.385 Ω of resistance change per 1˚C in temperature change. With a desired temperature measurement accuracy of 0.2˚C, this translates to a resistive measurement accuracy of approximately 0.077 Ω. The RTD resistance at the low end of the temperature range of –200˚C is 18.59 Ω and the resistance at the high end of the temperature range of 850˚C is 390.48 Ω. 10.2.1.2.3 Excitation Current For the best possible resolution, the voltage across the RTD must be made as large as possible compared to the noise floor in the measurement. In general, measurement resolution improves with increasing excitation current. However, a larger excitation current creates self-heating in the RTD, which causes drift and error in the measurement. The selection of excitation currents trades off resolution against sensor self-heating. The excitation current sources in this design are selected to be 1 mA. This maximizes the value of the RTD voltage while keeping the self-heating low. The typical range of RTD self-heating coefficients is 2.5 mW/°C for small, thin-film elements and 65 mW/°C for larger, wire-wound elements. With 1-mA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less than 0.4 mW and keeps the measurement errors due to self-heating to less than 0.01˚C. As mentioned in the Topology section, chopping of the excitation current sources cancels mismatches between the IDACs. This technique is necessary for getting the best possible accuracy from the system. Mismatch between the excitation current sources is a large source of error if chopping is not implemented. The internal reference voltage must be enabled while using the IDACs, even if an external ratiometric measurement is used for ADC conversions. Table 43 shows the ADS1147 register settings for setting up the internal reference and the excitation current sources. Table 43. Register Bit Settings for Excitation Current Sources REGISTER (ADDRESS) MUX1 (02h) (1) (2) 70 (1) BIT NAME BIT VALUES COMMENT VREFCON[1:0] 01 Internal reference enabled MUX1 (02h) REFSELT[1:0] 00 REFP0 and REFN0 reference inputs selected IDAC0 (0Ah) IMAG[2:0] 110 IDAC magnitude = 1 mA IDAC1 (0Bh) I1DIR[3:0] (2) 0000 IDAC1 = AIN0 IDAC1 (0Bh) I2DIR[3:0] (2) 0011 IDAC2 = AIN3 The internal reference is required to be enabled to use the IDAC current sources. To implement chopping, swap IDAC1 direction for IDAC2 direction. Set I1DIR[3:0] = 0011 and I2DIR[3:0] = 0000 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 10.2.1.2.4 Reference Resistor, RREF TI recommends setting the common-mode voltage of the measurement near mid-supply, this helps keep the input within the common-mode input range of the PGA. The reference resistor is selected to be 820 Ω. The voltage across RREF is calculated from Equation 26. VREF = RREF × (IIDAC1 + IIDAC2) = 820 Ω × 2 mA = 1.64 V (26) With AVDD = 3.3 V, Equation 26 shows that the input voltage is just below mid-supply. The excitation current sources operate properly to a maximum IDAC compliance voltage. Above this compliance voltage, the current sources lose current regulation. In this example, the output voltage of the excitation current source is calculated from the sum of the voltages across the RTD and RREF as shown in Equation 27. VIDAC1 MAX = RRTD MAX × IIDAC1 + (RREF × (IIDAC1 + IIDAC2)) = 0.4 V + 1.64 V = 2.04 V (27) A compliance voltage of 3.3 V – 2.04 V = 1.26 V is sufficient for proper IDAC operation. See Figure 9 and Figure 10 in the Typical Characteristics section for details. Because the voltage across RREF sets the reference voltage for the ADC, the tolerance and temperature drift of RREF directly affect the measurement gain. A resistor with 0.01% maximum tolerance is selected for this measurement. 10.2.1.2.5 PGA Setting Because the excitation current is small to reduce self-heating, the PGA in the ADS1147 is used to amplify the signal across the RTD to use the full-scale range of the ADC. Starting with the reference voltage, the ADC is able to measure a differential input signal range of ±1.64 V. The maximum allowable PGA gain setting is based on the reference voltage, the maximum RTD resistance, and the excitation current. As mentioned previously, the maximum resistance of the RTD is seen at the top range of the temperature measurement at 850°C. This gives the largest voltage measurement of the ADC. RRTD@850°C is 390.48 Ω. VRTD MAX = RRTD@850°C × IIDAC1 = 390.48 Ω × 1 mA = 390.48 mV (28) With a reference voltage of 1.64 V, the maximum gain for the PGA, without over-ranging the ADC, is shown in Equation 29. GainMAX = VREF / VRTD MAX = 1.64 V / 390.48 mV = 4.2 V/V (29) Selecting a PGA gain of 4 gives a maximum measurement of 95% of the positive full-scale range. Table 44 shows the register settings to set the PGA gain as well as the inputs for the ADC. Table 44. Register Bit Settings for the Input Multiplexer and PGA REGISTER (ADDRESS) BIT NAME BIT VALUES COMMENT MUX0 (01h) MUX_SP[2:0] 001 AINP = AIN1 MUX0 (01h) MUX_SN[2:0] 010 AINN = AIN2 SYS0 (03h) PGA[2:0] 010 PGA Gain = 4 10.2.1.2.6 Common-Mode Input Range Now that the component values are selected, the common-mode input range must be verified to ensure that the ADC and PGA are not limited in operation. Start with the maximum input voltage, which gives the most restriction in the common-mode input range. At the maximum input voltage, the common-mode input voltage seen by the ADC is shown in Equation 30. VCM = VREF + (VRTD_MAX / 2) = 1.64 V + (390.48 mV / 2) = 1.835 V (30) As mentioned in the Low-Noise PGA section, the common-mode input range is shown in Equation 3 and is applied to Equation 31. AVSS + 0.1 V + (VRTD_MAX × Gain) / 2 ≤ VCM ≤ AVDD – 0.1 V – (VRTD_MAX × Gain) / 2 (31) After substituting in the appropriate values, the common-mode input range can be found in Equation 32 and Equation 33. 0 V + 0.1 V + (390.48 mV × 4) / 2 ≤ VCM ≤ 3.3 V – 0.1 V – (390.48 mV × 4) / 2 881 mV ≤ VCM ≤ 2.42 V Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 (32) (33) Submit Documentation Feedback 71 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Because VCM = 1.835 V is within the limits of Equation 33, the RTD measurement is within the input commonmode range of the ADC and PGA. At the RTD voltage minimum (VRTD MIN = 18.59 mV), a similar calculation can be made to show that the input common-mode voltage is within the range as well. 10.2.1.2.7 Input and Reference Low-Pass Filters The differential filters chosen for this application are designed to have a –3-dB corner frequency at least 10 times larger than the bandwidth of the ADC. The selected ADS1147 sampling rate of 20 SPS results in a –3-dB bandwidth of 14.8 Hz. The –3-dB filter corner frequency is set to be roughly 250 Hz at mid-scale measurement resistance. For proper operation, the differential cutoff frequencies of the reference and input low-pass filters must be well matched. This can be difficult because as the resistance of the RTD changes over the span of the measurement, the filter cutoff frequency changes as well. To mitigate this effect, the two resistors used in the input filter (RI1 and RI2) are chosen to be two orders of magnitude larger than the RTD. Input bias currents of the ADC causes a voltage drop across the filter resistors that shows up as a differential offset error if the bias currents and/or filter resistors are not equal. TI recommends limiting the resistors to at most 10 kΩ to reduce DC offset errors due to input bias current. RI1 and RI2 are chosen to be 4.7 kΩ. The input filter differential capacitor (CI_DIFF) is calculated starting from the cutoff frequency as shown in Equation 34. f–3dB_DIFF = 1 / (2 π × CI_DIFF × (RI1 + RRTD + RI2)) f–3dB_DIFF = 1 / (2 π × CI_DIFF × (4.7 kΩ + 150 Ω + 4.7 kΩ)) (34) (35) After solving for CI_DIFF, the capacitor is chosen to be a standard value of 68 nF. To ensure that mismatch of the common-mode filter capacitors does not translate to a differential voltage, the common-mode capacitors (CI_CM1 and CI_CM2) are chosen to be 10 times smaller than the differential capacitor, making them 6.8 nF each. This results in a common-mode cutoff frequency that is roughly 20 times larger than the differential filter, making the matching of the common-mode cutoff frequencies less critical. f–3dB_CM+ = 1 / (2 π × CI_CM1 × (RI1 + RRTD + RREF)) f–3dB_CM– = 1 / (2 π × CI_CM1 × (RI2 + RREF)) (36) (37) After substituting values into Equation 36 and Equation 37, the common-mode cutoff frequencies are found to be f–3dB_CM+ = 4.13 kHz and f–3dB_CM– = 4.24 kHz. Often, filtering the reference input is not necessary and adding bulk capacitance at the reference input is sufficient. However, equations showing a design procedure calculating filter values for the reference inputs are shown below. The differential reference filter is designed to have a –3-dB corner frequency of 250 Hz to match the differential input filter. The two reference filter resistors are selected to be 9.09 kΩ, several times larger than the value of RREF. The reference filter resistors must not be sized larger than 10 kΩ or DC bias errors become significant. The differential capacitor for the reference filter is calculated as shown in Equation 38. f–3dB_DIFF = 1 / (2 π × CR_DIFF × (RR1 + RRTD + RR2)) CR_DIFF ≈ 33 nF (38) (39) After solving for CR_DIFF, the capacitor is chosen to be a standard value of 33 nF. To ensure that mismatch of the common-mode filter capacitors does not translate to a differential voltage, the reference common-mode capacitors (CR_CM1 and CR_CM2) are chosen to be 10 times smaller than the reference differential capacitor, making them 3.3 nF each. Again, the resulting cutoff frequency for the common-mode filters is roughly 20 times larger than the differential filter, making the matching of the cutoff frequencies less critical. f–3dB_CM+ = 1 / (2 π × CR_CM1 × (RR1 + RREF)) f–3dB_CM– = 1 / (2 π × CR_CM2 × RR2) (40) (41) After substituting values into Equation 40 and Equation 41, common-mode cutoff frequencies for the reference filter are found to be f–3dB_CM+ = 4.87 kHz and f–3dB_CM+ = 5.31 kHz. 72 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 10.2.1.2.8 Register Settings The register settings for this design are shown in Table 45. Table 45. Register Settings REGISTER (1) (2) NAME SETTING DESCRIPTION 00h MUX0 0Ah Select AINP = AIN1 and AINN = AIN2 01h VBIAS 00h 02h MUX1 20h Internal reference enabled, REFP0 and REFN0 reference inputs selected 03h SYS0 22h PGA Gain = 4, DR = 20 SPS 04h OFC0 (1) xxh 05h OFC1 xxh 06h OFC2 xxh 07h FSC0 (1) xxh 08h FSC1 xxh 09h FSC2 xxh 0Ah IDAC0 x6h ID bits may be version dependent, IDAC magnitude set to 1 mA 0Bh IDAC1 03h (2) IDAC1 set to AIN0; IDAC2 set to AIN3 0Ch GPIOCFG 00h 0Dh GPIOCDIR 00h 0Eh GPIODAT 00h A two-point gain calibration and offset calibration remove errors from the RREF tolerance, offset voltage and gain error. The results are used for the OFC and FSC registers To chop the excitation current sources, swap output pins with IDAC1 register and set to 30h 10.2.1.3 Application Curves To test the accuracy of the acquisition circuit, a series of calibrated, high-precision discrete resistors are used as the input to the system. Measurements are taken at TA = 25°C. Figure 84 displays the uncalibrated resistance measurement accuracy of the system over an input span from 20 Ω to 400 Ω. For each resistor value, 512 measurements are taken. With each measurement, IDAC1 and IDAC2 are chopped to remove the excitation current mismatch. The uncalibrated measurement error is displayed in Figure 85. The offset and gain error can be primarily attributed to the offset and gain error of the ADC. However, the accuracy of RREF contributes directly to the accuracy of the measurement. To keep the gain error low, RREF must be a low-drift precision resistor. Precision temperature measurement applications are typically calibrated to remove the effects of gain and offset errors, which generally dominate the total system error. The simplest calibration method is a linear, or two-point, calibration which applies an equal and opposite gain and offset term to cancel the measured system gain and offset errors. Using the results of Figure 85, the uncalibrated gain and offset error are then used to modify the Offset Calibration and the Full-Scale Calibration registers in the device. The results of this calibrated system measurement are shown in Figure 86. The results in Figure 86 are converted to temperature accuracy by dividing the results by the RTD sensitivity (α) at the measured resistance. Over the full resistance input range, the maximum total measured error is ±0.011 Ω. Equation 42 uses the measured resistance error and the nominal RTD sensitivity to calculate the measured temperature accuracy. Error (W) 0.011 W Error ( oC) = = = ± 0.0286 oC W a@ 0o C 0.385 o C (42) Figure 87 displays the calculated temperature measurement accuracy of the circuit assuming a linear RTD resistance to temperature response. It does not include any linearity compensation of the RTD. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 73 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 0.0 35000 Resistance Measurement Error ( ADC Measurement (Code) 30000 y = 79.880x - 0.603 25000 20000 15000 10000 5000 Uncalibrated Results Best Fit Line 0 0 100 200 300 400 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 0 500 RRTD ( 100 200 300 400 RRTD ( C001 Figure 84. Resistance Measurement Results With Precision Resistors Before Calibration C002 Figure 85. Resistance Measurement Error With Precision Resistors Before Calibration 0.04 Temperature Measurement Error (ƒC) 0.015 Resistance Measurement Error ( -0.1 0.010 0.005 0.000 -0.005 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.010 0 100 200 RRTD ( 300 0 400 100 Figure 86. Resistance Measurement Error With Precision Resistors After Calibration 200 300 400 RRTD ( C003 C004 Figure 87. Calculated Temperature Measurement Error from Resistance Measurement Error Table 46 compares the measurement accuracy with the design goal from Table 42. Table 46. Comparison of Design Goals and Measured Performance GOAL 74 MEASURED Calibrated resistance measurement accuracy at TA = 25ºC ±0.077 Ω ±0.011 Ω Calibrated temperature measurement accuracy at TA = 25ºC ±0.2°C ±0.029°C Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 10.2.2 K-Type Thermocouple Measurement (–200°C to 1250°C) With Cold-Junction Compensation Figure 88 shows the basic connections of a thermocouple measurement system based on the ADS1148. This circuit uses a cold-junction compensation measurement based on the Ratiometric 3-Wire RTD Measurement System topology shown in the previous application example. Using the IEXC1 and IEXC2 pins allow for routing of the IDAC currents without using any other analog pins. Along with the thermocouple and cold-junction measurements, four other analog inputs (AIN4 to AIN7 not shown in the schematic) are available for alternate measurements or use as GPIO pins. 3.3 V 3.3 V 3.3 V 0.1 µF Isothermal Block RB1 CI_CM1 RI1 AIN0 CI_DIFF RI2 Thermocouple 0.1 µF DVDD AVDD ADS1148 AIN1 û ADC PGA CI_CM2 MUX RB2 AIN2 Reference Mux AIN3 RRTD RRTD_I1 CRTD_I_CM1 IEXC1 IDAC1 CRTD_I_DIFF 3-Wire RTD IEXC2 IDAC2 Internal Reference RRTD_I2 CRTD_I_CM2 AVSS DGND REFN0 REFP0 CR_CM1 CR_DIFF RR1 CR_CM2 RR2 RREF Copyright © 2016, Texas Instruments Incorporated Figure 88. Thermocouple Measurement System Using the ADS1148 10.2.2.1 Design Requirements Table 47 shows the design requirements of the thermocouple application for the ADS1148. Table 47. Example Thermocouple Application Requirements (1) PARAMETER VALUE Supply voltage 3.3 V Reference voltage Internal 2.048-V reference Update rate ≥ 10 readings per second Thermocouple type K Temperature measurement –200ºC to 1250ºC Measurement accuracy at TA = 25ºC (1) ±0.5ºC Not accounting for error of thermocouple and the cold-junction measurement; offset calibration is performed at T(TC) = T(CJ) = 25°C; no gain calibration. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 75 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 10.2.2.2 Detailed Design Procedure 10.2.2.2.1 Biasing Resistors The biasing resistors RB1 and RB2 are used to set the common-mode voltage of the thermocouple to within the specified common-mode voltage range of the PGA (in this example, to mid-supply AVDD / 2). If the application requires the thermocouple to be biased to GND, a bipolar supply (for example, AVDD = 2.5 V and AVSS = –2.5 V) must be used for the device to meet the common-mode voltage requirement of the PGA. When choosing the values of the biasing resistors, care must be taken so that the biasing current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing resistors range from 1 MΩ to 50 MΩ. In addition to biasing the thermocouple, RB1 and RB2 are also useful for detecting an open thermocouple lead. When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AIN0 and AIN1) to AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this failure condition. 10.2.2.2.2 Input Filtering Although the digital filter attenuates high-frequency components of noise, TI recommends providing a first-order, passive RC filter at the inputs to further improve performance. The differential RC filter formed by RI1, RI2, and the differential capacitor CI_DIFF offers a cutoff frequency that is calculated using Equation 43. fC = 1 / (2 π × (RI1 + RI2) × CI_DIFF) (43) Two common-mode filter capacitors (CI_CM1 and CI_CM2) are also added to offer attenuation of high-frequency, common-mode noise components. TI recommends that the differential capacitor CI_DIFF be at least an order of magnitude (10×) larger than the common-mode capacitors (CI_CM1 and CI_CM2) because mismatches in the common-mode capacitors can convert common-mode noise into differential noise. The filter resistors RF1 and RF2 also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occurs. Care must be taken when choosing the filter resistor values because the input currents flowing into and out of the device cause a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs. For thermocouple measurements, TI recommends limiting the filter resistor values to below 10 kΩ. The filter component values used in this design are: RI1 = RI2 = 1 kΩ, CI_DIFF = 100 nF, and CI_CM1 = CI_CM2 = 10 nF. 10.2.2.2.3 PGA Setting The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple voltage occurs at TTC = 1250°C and is VTC = 50.644 mV as defined in the tables published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature of TCJ = 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device. Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at TTC = 1250°C produces an output voltage of VTC = 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction temperature of TCJ = –40°C. The maximum gain that can be applied when using the internal 2.048-V reference is then calculated as 39.3 from Equation 44. The next smaller PGA gain setting the device offers is 32. GainMAX = VREF / VTC MAX = 2.048 V / 52.171 mV = 39.3 (44) 10.2.2.2.4 Cold-Junction Measurement AIN2 and AIN3 are attached to a 3-wire RTD that is used to measure the cold-junction temperature. Similar to the example in the Ratiometric 3-Wire RTD Measurement System section, the 3-wire RTD design is the same except the inputs and excitation current sources have been changed. Note that RREF and PGA Gain can be optimized for a reduced temperature range. 76 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 The device does not perform an automatic cold-junction compensation of the thermocouple. This compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one or multiple readings of the thermocouple voltage from the device and then sets the device to measure the cold junction with the RTD to compensate for the cold-junction temperature. An algorithm similar to the following must be implemented on the microcontroller to compensate for the coldjunction temperature: 1. Measure the thermocouple voltage, V(TC), between AIN0 and AIN1. 2. Measure the temperature of the cold junction, T(CJ), using a ratiometric measurement with the 3-wire RTD across AIN2 and AIN3. 3. Convert the cold-junction temperature into an equivalent thermoelectric voltage, V(CJ), using the tables or equations provided by NIST. 4. Add V(TC) and V(CJ) and translate the summation back into a thermocouple temperature using the NIST tables or equations again. There are alternate methods of measuring the cold-junction temperature. The additional analog input channels of the device can be used in this case to measure the cold-junction temperature with a thermistor or an alternate analog temperature sensor. 10.2.2.2.5 Calculated Resolution To get an approximation of the achievable temperature resolution, the peak-to-peak noise of the ADS1148 at Gain = 32 and DR = 20 SPS (1.95 µVPP) is taken from Table 1. The noise is divided by the average sensitivity of a K-type thermocouple (41 µV/°C), as shown in Equation 45. Temperature Resolution = 1.95 µV / 41 µV/°C = 0.048°C (45) 10.2.2.2.6 Register Settings The register settings for this design are shown in Table 48. The inputs are selected to measure the thermocouple and the internal reference is enabled and selected. The excitation current sources are also enabled and selected. While this does consume some power, it allows for a quick transition for the cold-junction measurement. Table 48. Register Settings for the Thermocouple Measurement REGISTER NAME SETTING DESCRIPTION 00h MUX0 01h Select AINP = AIN0, AINN = AIN1 01h VBIAS 00h 02h MUX1 30h Internal reference enabled, internal reference selected 03h SYS0 52h PGA Gain = 32, DR = 20 SPS 04h OFC0 xxh 05h OFC1 xxh 06h OFC2 xxh 07h FSC0 xxh 08h FSC1 xxh 09h FSC2 xxh 0Ah IDAC0 x6h IDAC magnitude set to 1 mA IDAC1 set to IEXC1, IDAC2 set to IEXC2 0Bh IDAC1 89h 0Ch GPIOCFG 00h 0Dh GPIOCDIR 00h 0Eh GPIODAT 00h Changing to the cold-junction measurement, the registers are set to measure the RTD. This requires changing the input, the reference input, the gain, and any calibration settings required for the measurement accuracy. Table 49 shows the register settings for the RTD measurement used for cold-junction compensation. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 77 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com Table 49. Register Settings for the Cold-Junction Measurement REGISTER NAME SETTING DESCRIPTION 00h MUX0 13h Select AINP = AIN2, AINN = AIN3 01h VBIAS 00h 02h MUX1 20h Internal reference enabled, REFP0 and REFN0 selected 03h SYS0 22h PGA Gain = 4, DR = 20 SPS 04h OFC0 xxh Calibration values are different between measurement settings 05h OFC1 xxh 06h OFC2 xxh 07h FSC0 xxh 08h FSC1 xxh 09h FSC2 xxh 0Ah IDAC0 x6h IDAC magnitude set to 1 mA 0Bh IDAC1 89h IDAC1 set to IEXC1, IDAC2 set to IEXC2 0Ch GPIOCFG 00h 0Dh GPIOCDIR 00h 0Eh GPIODAT 00h 10.3 Do's and Don'ts • • • • • • • • • • Do partition the analog, digital, and power supply circuitry into separate sections on the PCB. Do use a single ground plane for analog and digital grounds. Do place the analog components close to the ADC pins using short, direct connections. Do keep the SCLK pin free of glitches and noise. Do verify that the analog input voltages are within the specified PGA input voltage range under all input conditions. Do float unused analog input pins to minimize input leakage current. Connecting unused pins to AVDD is the next best option. Do provide current limiting to the analog inputs in case overvoltage faults occur. Do use a low-dropout linear regulator (LDO) to reduce ripple voltage generated by switch-mode power supplies. This is especially true for AVDD where the supply noise may affect the performance. Don't cross analog and digital signals. Don't allow the analog and digital power supply voltages to exceed 5.5 V under all conditions, including during power up and power down. Figure 89 shows Do's and Don'ts of ADC circuit connections. 78 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 Do's and Don'ts (continued) INCORRECT 5V AVDD Device AINP 16-bit û ADC PGA AINN AVSS 0V 0V Input grounded, unipolar supply CORRECT CORRECT 2.5 V 5V AVDD AVDD Device Device AINP AINP 16-bit û ADC PGA 2.5 V AINN AVSS AVSS 0V -2.5 V 0V Input referenced to mid-supply, unipolar supply INCORRECT 5V AVDD 16-bit û ADC PGA AINN Input grounded, bipolar supply 3.3 V 5V 3.3 V INCORRECT DVDD AVDD PGA 16-bit û ADC PGA 16-bit û ADC AVSS DGND AVSS DGND Device Inductive supply or ground connections 5V CORRECT AVDD 3.3 V Device DVDD AGND/DGND isolation 2.5 V CORRECT 3.3 V DVDD AVDD PGA 16-bit û ADC PGA 16-bit û ADC AVSS DGND AVSS DGND Device Device DVDD -2.5 V Low impedance AGND/DGND connection Low impedance AGND/DGND connection Figure 89. Do's and Don'ts Circuit Connections Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 79 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 11 Power Supply Recommendations The device requires two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or unipolar (for example, AVDD = 3.3 V, AVSS = 0 V) and is independent of the digital power supply. The digital supply sets the digital I/O levels (with the exception of the GPIO levels which are set by the analog supply of AVDD to AVSS). 11.1 Power Supply Sequencing The power supplies can be sequenced in any order but in no case must any analog or digital inputs exceed the respective analog or digital power-supply voltage limits. Wait at least 216 tCLK cycles after all power supplies are stabilized before communicating with the device to allow the power-on reset process to complete. 11.2 Power Supply Decoupling Good power-supply decoupling is important to achieve optimum performance. AVDD, AVSS (when using a bipolar supply) and DVDD must be decoupled with at least a 0.1-µF capacitor, as shown in Figure 90. Place the bypass capacitors as close to the power-supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. TI recommends connecting analog and digital ground together as close to the device as possible. 3.3 V 3.3 V 0.1 µF 1 DVDD SCLK 28 1 DVDD SCLK 28 2 DGND DIN 27 2 DGND DIN 27 3 CLK DOUT/DRDY 26 3 CLK DOUT/DRDY 26 4 RESET DRDY 25 4 RESET DRDY 25 5 REFP0 CS 24 5 REFP0 CS 24 6 REFN0 START 23 6 REFN0 START 23 7 REFP1 AVDD 22 0.1 µF +2.5 V 5V 7 REFP1 AVDD 22 Device 0.1 µF Device 8 REFN1 AVSS 21 9 VREFOUT IEXC1 20 10 VREFCOM IEXC2 19 11 AIN0 AIN0 12 AIN1 13 14 0.1 µF 8 REFN1 AVSS 21 9 VREFOUT IEXC1 20 10 VREFCOM IEXC2 19 18 11 AIN0 AIN0 18 AIN1 17 12 AIN1 AIN1 17 AIN4 AIN7 16 13 AIN4 AIN7 16 AIN5 AIN6 15 14 AIN5 AIN6 15 0.1 µF -2.5 V 1 µF 1 µF Figure 90. Power Supply Decoupling for Unipolar and Bipolar Supply Operation 80 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 12 Layout 12.1 Layout Guidelines TI recommends employing best design practices when laying out a printed-circuit board (PCB) for both analog and digital components. This recommendation generally means that the layout separates analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 91. Although Figure 91 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component. Ground Fill or Ground Plane Supply Generation Microcontroller Device Optional: Split Ground Cut Signal Conditioning (RC Filters and Amplifiers) Ground Fill or Ground Plane Optional: Split Ground Cut Ground Fill or Ground Plane Interface Transceiver Connector or Antenna Ground Fill or Ground Plane Figure 91. System Component Placement The following outlines some basic recommendations for the layout of the ADS1148 to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout. • • • • • • • • Separate analog and digital signals. To start, partition the board into analog and digital sections where the layout permits. Route digital lines away from analog lines. This prevents digital noise from coupling back into analog signals. The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but this is not necessary. Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in the layout, the split between the analog and digital grounds must be connected to together at the ADC. Fill void areas on signal layers with ground fill. Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing right next to the signal trace, it has to find another path to return to the source and complete the circuit. If it is forced into a larger path, it increases the chance that the signal radiates. Sensitive signals are more susceptible to EMI interference. Use bypass capacitors on supplies to reduce high frequency noise. Do not place vias between bypass capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active device yields the best results. Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI pickup and reduce the high frequency impedance seen by the device. Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor may create a parasitic themocouple which can add an offset to the measurement. Differential inputs must be matched for both the inputs going to the measurement source. Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best input combinations for differential measurements use adjacent analog input lines such as AIN0, AIN1 and AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have stable properties and low noise characteristics. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 81 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 12.2 Layout Example Digital supply DVDD SCLK DGND DIN CLK DOUT/ DRDY RESET DRDY REFP0 CS Other digital Route digital lines away from analog and reference inputs Controller SPI REFN0 START REFP1 AVDD REFN1 AVSS VREFOUT IEXC1 +2.5 V Positive analog supply Reference inputs Internal reference bypass VREFCOM Place ground plane under device Negative analog ±2.5 V supply Excitation currents may be routed to elements measured by the analog inputs and then routed to the reference inputs IEXC2 AIN0 AIN3 AIN1 AIN2 Analog inputs Use differential and commonmode capacitors for analog inputs as shown for AIN0 and AIN1 AIN4 AIN7 AIN5 AIN6 Figure 92. ADS114x Layout Example 82 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 ADS1146, ADS1147, ADS1148 www.ti.com SBAS453G – JULY 2009 – REVISED AUGUST 2016 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation see the following: • Example Temperature Measurement Applications Using the ADS1247 and ADS1248 (SBAA180) • RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices (SBAA201) • 3-Wire RTD Measurement System Reference Design, –200°C to 850°C (SLAU520) • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (SBAA147) 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 50. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS1146 Click here Click here Click here Click here Click here ADS1147 Click here Click here Click here Click here Click here ADS1148 Click here Click here Click here Click here Click here 13.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.5 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. 13.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 Submit Documentation Feedback 83 ADS1146, ADS1147, ADS1148 SBAS453G – JULY 2009 – REVISED AUGUST 2016 www.ti.com 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 84 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS1146 ADS1147 ADS1148 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1146IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 ADS1146 ADS1146IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 ADS1146 ADS1147IPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1147 ADS1147IPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1147 ADS1148IPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1148 ADS1148IPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1148 ADS1148IRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS 1148 ADS1148IRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS 1148 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of