ADS1198CZXGT

ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Low-Power, 8-Channel, 16-Bit Analog Front-End for Biopotential Measurements Check for Samples: ADS1194, ADS1196, ADS1198 FEATURES 1 • 23 • • • • • • • • • • • • • • Eight Low-Noise PGAs and Eight High-Resolution ADCs (ADS1198) Low Power: 0.55mW/channel Input-Referred Noise: 12μVPP (150Hz BW, G = 6) Input Bias Current: 200pA Data Rate: 125SPS to 8kSPS CMRR: –105dB Programmable Gain: 1, 2, 3, 4, 6, 8, or 12 Supports AAMI EC11, EC13, IEC60601-1, IEC60601-2-27, and IEC60601-2-51 Standards Supplies: Unipolar or Bipolar – Analog: 2.7V to 5.25V – Digital: 1.65V to 3.6V Built-In Right Leg Drive Amplifier, Lead-Off Detection, WCT, Test Signals Pace Detection Channel Select Built-In Oscillator and Reference Flexible Power-Down, Standby Mode SPI™-Compatible Serial Interface Operating Temperature Range: 0°C to +70°C With its high levels of integration and exceptional performance, the ADS1194/6/8 family enables the creation of scalable medical instrumentation systems at significantly reduced size, power, and overall cost. The ADS1194/6/8 have a flexible input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the right leg drive (RLD) output signal. The ADS1194/6/8 operate at data rates as high as 8kSPS, thereby allowing the implementation of software pace detection. Lead-off detection can be implemented internal to the device, either with a pull-up/pull-down resistor or an excitation current sink/source. Three integrated amplifiers generate the Wilson Center Terminal (WCT) and the Goldberger terminals (GCT) required for a standard 12-lead medical electrocardiogram (ECG). Multiple ADS1194/6/8 devices can be cascaded in high channel count systems in a daisy-chain configuration. Package options include a tiny 8mm × 8mm, 64-ball BGA and a TQFP-64. Both packages are specified over the temperature range of 0°C to +70°C. REF Test Signals and Monitors Reference ADC1 • A2 ADC2 A3 ADC3 A4 ADC4 INPUTS Control A5 ADC5 A6 ADC6 A7 ADC7 ADC8 A8 DESCRIPTION The ADS1194/6/8 are a family of multichannel, simultaneous sampling, 16-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with a built-in programmable gain amplifier (PGA), internal reference, and an onboard oscillator. Oscillator MUX GPIO AND CONTROL • Medical Instrumentation (ECG) including: – Patient monitoring; Holter, event, stress, and vital signs Including ECG, AED, Telemedicine – Evoked audio potential (EAP), Sleep study monitor High-Precision, Simultaneous, Multichannel Signal Acquisition SPI CLK A1 SPI APPLICATIONS To Channel WCT Wilson Terminal ¼ ¼ ¼ RLD PACE 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FAMILY AND ORDERING INFORMATION (1) PRODUCT PACKAGE OPTION NUMBER OF CHANNELS ADC RESOLUTION MAXIMUM SAMPLE RATE (kSPS) OPERATING TEMPERATURE RANGE RESPIRATION CIRCUITRY BGA 4 16 8 0°C to +70°C No TQFP 4 16 8 0°C to +70°C No BGA 6 16 8 0°C to +70°C No TQFP 6 16 8 0°C to +70°C No BGA 8 16 8 0°C to +70°C No TQFP 8 16 8 0°C to +70°C No BGA 4 24 32 0°C to +70°C External ADS1294R BGA 4 24 32 –40°C to +85°C Yes ADS1294 TQFP 4 24 32 –40°C to +85°C External ADS1296 BGA 6 24 32 0°C to +70°C External ADS1296R BGA 6 24 32 –40°C to +85°C Yes ADS1296 TQFP 6 24 32 –40°C to +85°C External ADS1298 BGA 8 24 32 0°C to +70°C External ADS1298R BGA 8 24 32 –40°C to +85°C Yes ADS1298 TQFP 8 24 32 –40°C to +85°C External ADS1194 ADS1196 ADS1198 ADS1294 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS1194, ADS1196, ADS1198 UNIT AVDD to AVSS –0.3 to +5.5 V DVDD to DGND –0.3 to +3.9 V AVSS to DGND –3 to +0.2 V VREF input to AVSS AVSS – 0.3 to AVDD + 0.3 V Analog input to AVSS AVSS – 0.3 to AVDD + 0.3 V Digital input voltage to DGND –0.3 to DVDD + 0.3 V Digital output voltage to DGND –0.3 to DVDD + 0.3 V Input current (momentary) 100 mA Input current (continuous) 10 mA 0 to +70 °C Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins ±2000 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins ±500 V –60 to +150 °C +150 °C Operating temperature range ESD ratings ADS1194, ADS1196, ADS1198 Storage temperature range Maximum junction temperature (TJ) (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted. ADS1194, ADS1196, ADS1198 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale differential input voltage (AINP – AINN) ±VREF/GAIN See the Input Common-Mode Range subsection of the PGA Settings and Input Range section Input common-mode range Input capacitance Input bias current 20 pF ±200 Input = 1.5V, TA = +25°C pA ±1 Input = 1.5V TA = 0°C to +70°C No lead-off DC input impedance V nA 1000 MΩ Current source lead-off detection 500 MΩ Pull-up resistor lead-off detection 10 MΩ PGA PERFORMANCE Gain settings 1, 2, 3, 4, 6, 8, 12 Bandwidth See Table 4 ADC PERFORMANCE Resolution No missing codes Data rate 16 Bits 125 8000 SPS CHANNEL PERFORMANCE DC Performance Gain = 6 (1), 10 seconds of data Input-referred noise Gain settings other than 6 Integral nonlinearity µVPP 12.2 Gain = 6, 256 points, 0.5 seconds of data 12.6 µVPP See Noise Measurements section LSB (2) ±1 Full-scale with gain = 6, best fit ±500 Offset error Offset error drift μV μV/°C 2 Gain error Excluding voltage reference error Gain drift Excluding voltage reference drift ±0.2 Gain match between channels ±0.5 % of FS 5 ppm/°C 0.3 % of FS AC Performance Common-mode rejection ratio (CMRR) fCM = 50Hz, 60Hz (3) –105 dB Power-supply rejection ratio (PSRR) fPS = 50Hz, 60Hz 85 dB Crosstalk fIN = 50Hz, 60Hz –100 dB Signal-to-noise ratio (SNR) fIN = 10Hz input, gain = 6 97 dB Total harmonic distortion (THD) 10Hz, –0.5dBFs –95 dB –100 DIGITAL FILTER –3dB bandwidth Digital filter settling (1) (2) (3) 0.262fDR Full setting 4 Hz Conversions Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted (without electrode resistance) over a 10-second interval. Input referred LSB in volts = (2 × VREF/(Gain*216)). CMRR is measured with a common-mode signal of AVSS + 0.3V to AVDD – 0.3V. The values indicated are the minimum of the eight channels. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 3 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted. ADS1194, ADS1196, ADS1198 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RIGHT LEG DRIVE (RLD) AMPLIFIER AND PACE AMPLIFIERS µVrms RLD integrated noise BW = 150Hz RLD Gain bandwidth product 50kΩ || 10pF load, gain = 1 8 Pace noise BW = 8kHz Pace Gain bandwidth product 50kΩ || 10pF load, PGA gain = 1 80 kHz RLD Slew rate 50kΩ || 10pF load, gain = 1 0.2 V/µs Pace Slew rate 50kΩ || 10pF load, PGA gain = 1 0.04 V/µs Pace amplifier crosstalk Crosstalk between Pace amplifiers 100 kHz 20 µVrms 60 Pace amplifier output resistance Ω 50 µA AVDD = 3V Maximum Pace and RLD current 75 µA Short-circuit to GND (AVDD = 3V) 270 µA Short-circuit to supply (AVDD = 3V) 550 µA Short-circuit to GND (AVDD = 5V) 490 µA Short-circuit to supply (AVDD = 5V) 810 µA 60Hz, –0.5dBFS –70 AVDD = 5V Pace and RLD amplifier drive strength Total harmonic distortion Common-mode range Internal 200kΩ resistor matching 0.1 Short-circuit current Quiescent power consumption dB AVDD – 0.3 AVSS + 0.7 Common-mode resistor matching dB 100 V % ±0.25 mA 20 μA Either RLD or Pace amplifier WILSON CENTER TERMINAL (WCT) AMPLIFIER Input voltage noise density See Table 3 µVRMS Gain bandwidth product See Table 3 kHz Slew rate See Table 3 V/s Total harmonic distortion fIN = 100Hz Common-mode range 90 Quiescent power consumption dB AVDD – 0.3 AVSS + 0.3 See Table 3 V μA LEAD-OFF DETECT Frequency See Register Map section for settings 0, fDR/4 kHz Current See Register Map section for settings 4, 8, 12, 16 nA Current accuracy ±20 % Comparator threshold accuracy ±30 mV 3V supply VREF = (VREFP – VREFN) 2.5 V 5V supply VREF = (VREFP – VREFN) 4.1 V AVSS V EXTERNAL REFERENCE Reference input voltage Negative input (VREFN) Positive input (VREFP) AVSS + 2.5 Input impedance V 10 kΩ Register bit CONFIG3.VREF_4V = 0, AVDD ≥ 2.7V 2.4 V Register bit CONFIG3.VREF_4V = 1, AVDD ≥ 4.4V 4.0 V INTERNAL REFERENCE Output voltage ±0.2 VREF accuracy Drift Start-up time 4 Submit Documentation Feedback % 35 ppm/°C 150 ms Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted. ADS1194, ADS1196, ADS1198 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM MONITORS Analog supply reading error 2 Digital supply reading error 2 % 150 ms From power-up Device wake up STANDBY mode % 9 ms Temperature sensor reading, voltage 145 mV Temperature sensor reading, coefficient 490 μV/°C Test Signal Signal frequency See Register Map section for settings fCLK/221, fCLK/220 Hz Signal voltage See Register Map section for settings ±1, ±2 mV ±2 Accuracy % CLOCK Nominal frequency Internal oscillator clock frequency 2.048 MHz TA = +25°C 0.5 0°C ≤ TA ≤ +70°C ±2 % 20 μs Internal oscillator start-up time Internal oscillator power consumption % μW 120 External clock input frequency CLKSEL pin = 0 0.5 2.048 2.25 MHz DIGITAL INPUT/OUTPUT (DVDD = 1.65V to 3.6V) Logic level VIH 0.8DVDD DVDD + 0.1 V VIL –0.1 0.2DVDD V VOH IOH = –500μA VOL IOL = +500μA Input current (IIN) 0V < VDigitalInput < DVDD DVDD – 0.4 V –10 0.4 V +10 μA POWER-SUPPLY REQUIREMENTS Analog supply (AVDD – AVSS) 2.7 3 5.25 V Digital supply (DVDD) 1.65 1.8 3.6 V AVDD – DVDD –2.1 3.6 V SUPPLY CURRENT (RLD, WCT, and Pace Amplifiers Turned Off) IAVDD Normal mode (ADS1198) IDVDD AVDD – AVSS = 3V 1.3 mA AVDD – AVSS = 5V 1.6 mA DVDD = 3.0V 0.5 mA DVDD = 1.8V 0.3 mA Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 5 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted. ADS1194, ADS1196, ADS1198 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER DISSIPATION (Analog Supply = 3V, RLD, WCT, and Pace Amplifiers Turned Off) Quiescent power dissipation ADS1194 Normal mode 3 3.3 mW ADS1196 Normal mode 3.6 4 mW ADS1198 Normal mode 4.3 4.8 mW Power-down Standby mode Quiescent channel power PGA + ADC 10 μW 2 mW 350 µW POWER DISSIPATION (Analog Supply = 5V, RLD, WCT, and Pace Amplifiers Turned Off) Quiescent power dissipation ADS1194 Normal mode 5.7 mW ADS1196 Normal mode 6.9 mW ADS1198 Normal mode 8.2 mW Power-down Standby mode, internal reference Quiescent channel power PGA + ADC 20 μW 4 mW 620 µW TEMPERATURE Specified temperature range 0 +70 °C Operating temperature range 0 +70 °C –60 +150 °C Storage temperature range THERMAL INFORMATION THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance θJCtop ADS1194/6/8 ADS1194/6/8 PAG ZXG 64 PINS 64 PINS 29 29 Junction-to-case (top) thermal resistance 10.4 10.4 θJB Junction-to-board thermal resistance 14.8 14.8 ψJT Junction-to-top characterization parameter 0.2 0.2 ψJB Junction-to-board characterization parameter 8.2 8.2 θJCbot Junction-to-case (bottom) thermal resistance n/a n/a (1) 6 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com NOISE MEASUREMENTS The ADS1194/6/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals. Table 1 summarizes the noise performance of the ADS1194/6/8, with a 3V analog power supply. Table 2 summarizes the noise performance of the ADS1194/6/8 with a 5V analog power supply. The data are representative of typical noise performance at TA = +25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the peak-to-peak noise for each reading. For the two highest data rates, the noise is limited by quantization noise of the ADC and does not have a gaussian distribution. The ratio between rms noise and peak-to-peak noise for these two data rates are approximately 10. For the lower data rates, the ratio is approximately 6.6. Table 1 and Table 2 show measurements taken with an internal reference. In many of the settlings, espeically at the lower data rates, the inherent device noise is less than 1LSB. For these cases, the noise is rounded up to 1LSB. The data are also representative of the ADS1194/6/8 noise performance when using a low-noise external reference such as the REF5025. Table 1. Input-Referred Noise (μVPP) 3V Analog Supply and 2.4V Reference (1) (2) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2 PGA GAIN = 3 PGA GAIN = 4 PGA GAIN = 6 PGA GAIN = 8 PGA GAIN = 12 000 8000 2096 2930 1470 937 681 436 319 205 001 4000 1048 563 265 173 124 77 56 36 010 2000 524 104 51 33 24 17 13 9.5 011 1000 262 73.3 36.6 24.4 18.3 12.2 9.2 6.1 100 500 131 73.3 36.6 24.4 18.3 12.2 9.2 6.1 101 250 65 73.3 36.6 24.4 18.3 12.2 9.2 6.1 110 125 32.5 73.3 36.6 24.4 18.3 12.2 9.2 6.1 (1) (2) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. For data rates less than 2kSPS, the noise is rounded up to 1LSB. Input-referred LSB in volts = (2 × VREF/(Gain × 216)). Table 2. Input-Referred Noise (μVPP) 5V Analog Supply and 4V Reference (1) (2) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2 PGA GAIN = 3 PGA GAIN = 4 PGA GAIN = 6 PGA GAIN = 8 PGA GAIN = 12 000 8000 2096 4923 2450 1598 1196 765 560 362 001 4000 1048 959 481 307 222 142 100 63 010 2000 524 166 81 52 40 26 19 12.3 011 1000 262 122.1 61.1 40.7 30.5 20.4 15.3 10.2 100 500 131 122.1 61.1 40.7 30.5 20.4 15.3 10.2 101 250 65 122.1 61.1 40.7 30.5 20.4 15.3 10.2 110 125 32.5 122.1 61.1 40.7 30.5 20.4 15.3 10.2 (1) (2) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. For data rates less than 2kSPS, the noise is rounded up to 1LSB. Input-referred LSB in volts = (2 × VREF/(Gain × 216)). Table 3. Typical WCT Performance PARAMETER ANY ONE (A, B, or C) ANY TWO (A+B, A+C, or B+C) ALL THREE (A+B+C) UNIT Noise 563 404 330 nVRMS Power 36 40 44 μA –3dB BW 30 59 89 kHz Slew rate BW limited BW limited BW limited — Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 7 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com PIN CONFIGURATIONS ZXG PACKAGE BGA-64 (TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE) H G F E D C B A IN1P IN2P IN3P IN4P IN5P IN6P IN7P IN8P 1 IN1N IN2N IN3N IN4N IN5N IN6N IN7N IN8N 2 VREFP VCAP4 TESTN_ PACE_OUT2 TESTP_ PACE_OUT1 WCT RLDINV RLDOUT RLDIN 3 VREFN RESV3 RESV2 RESV1 AVSS RLDREF AVDD AVDD 4 VCAP1 PWDN GPIO1 GPIO4 AVSS AVSS AVSS AVSS 5 VCAP2 RESET DAISY_IN GPIO3 DRDY AVDD AVDD AVDD 6 DGND START CS GPIO2 DGND DGND VCAP3 AVDD1 7 CLK DIN SCLK DOUT DVDD DVDD CLKSEL AVSS1 8 BGA PIN ASSIGNMENTS NAME TERMINAL FUNCTION DESCRIPTION IN8P (1) 1A Analog input Differential analog positive input 8 (ADS1198 only) IN7P (1) 1B Analog input Differential analog positive input 7 (ADS1198 only) IN6P (1) 1C Analog input Differential analog positive input 6 (ADS1196/8 only) IN5P (1) 1D Analog input Differential analog positive input 5 (ADS1196/8 only) IN4P (1) 1E Analog input Differential analog positive input 4 IN3P (1) 1F Analog input Differential analog positive input 3 IN2P (1) 1G Analog input Differential analog positive input 2 IN1P (1) 1H Analog input Differential analog positive input 1 IN8N (1) 2A Analog input Differential analog negative input 8 (ADS1198 only) IN7N (1) 2B Analog input Differential analog negative input 7 (ADS1198 only) IN6N (1) 2C Analog input Differential analog negative input 6 (ADS1196/8 only) IN5N (1) 2D Analog input Differential analog negative input 5 (ADS1196/8 only) IN4N (1) 2E Analog input Differential analog negative input 4 (1) 2F Analog input Differential analog negative input 3 IN2N (1) 2G Analog input Differential analog negative input 2 IN1N (1) 2H Analog input Differential analog negative input 1 IN3N (1) 8 Connect unused analog inputs IN1x to IN8x to AVDD. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com BGA PIN ASSIGNMENTS (continued) (2) NAME TERMINAL FUNCTION DESCRIPTION RLDIN 3A Analog input Right leg drive input to MUX. If unused, short to AVDD. RLDOUT 3B Analog output RLDINV 3C Analog input/output Right leg drive inverting input WCT 3D Analog output Wilson Center Terminal output TESTP_PACE_OUT1 3E Analog input/buffer output Internal test signal/single-ended buffer output based on register settings. If unused, short to AVDD. TESTN_PACE_OUT2 3F Analog input/output Internal test signal/single-ended buffer output based on register settings. If unused, short to AVDD. Right leg drive output VCAP4 3G Analog output VREFP 3H Analog input/output Analog bypass capacitor AVDD 4A Supply Analog supply AVDD 4B Supply Analog supply RLDREF 4C Analog input Positive reference voltage Right leg drive noninverting input AVSS 4D Supply RESV1 4E Digital input Analog ground RESV2 4F Analog output Reserved for future use; leave floating RESV3 4G Analog output Reserved for future use; leave floating VREFN 4H Analog input AVSS 5A Supply Analog ground AVSS 5B Supply Analog ground AVSS 5C Supply Analog ground AVSS 5D Supply Analog ground GPIO4 5E Digital input/output General-purpose input/output pin GPIO1 5F Digital input/output General-purpose input/output pin PWDN 5G Digital input Power-down; active low VCAP1 5H Analog input/output Analog bypass capacitor AVDD 6A Supply Analog supply AVDD 6B Supply Analog supply AVDD 6C Supply Analog supply DRDY 6D Digital output GPIO3 6E Digital input/output DAISY_IN (2) 6F Digital input Daisy-chain input RESET 6G Digital input System reset; active low Analog bypass capacitor Reserved for future use; must tie to logic low (DGND) Negative reference voltage Data ready; active low General-purpose input/output pin VCAP2 6H — AVDD1 7A Supply VCAP3 7B — DGND 7C Supply Digital ground DGND 7D Supply Digital ground GPIO2 7E Digital input/output CS 7F Digital input SPI chip select; active low START 7G Digital input Start conversion DGND 7H Supply Digital ground AVSS1 8A Supply Analog ground for charge pump CLKSEL 8B Digital input Master clock select DVDD 8C Supply Digital power supply DVDD 8D Supply Digital power supply DOUT 8E Digital output SPI data out SCLK 8F Digital input SPI clock CLK 8G Digital input/output DIN 8H Digital input Analog supply for charge pump Analog bypass capacitor, internally-generated AVDD + 1.9V General-purpose input/output pin External master clock input or internal clock output SPI data in When DAISY_IN is not used, tie to logic '0'. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 9 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com 49 DGND 50 DVDD 52 CLKSEL 51 DGND 54 AVDD1 53 AVSS1 55 VCAP3 57 AVSS 56 AVDD 59 AVDD 58 AVSS 60 RLDREF 62 RLDIN 61 RLDINV 64 WCT 63 RLDOUT PAG PACKAGE TQFP-64 (TOP VIEW) IN8N 1 48 DVDD IN8P 2 47 DRDY IN7N 3 46 GPIO4 IN7P 4 45 GPIO3 IN6N 5 44 GPIO2 IN6P 6 43 DOUT IN5N 7 42 GPIO1 IN5P 8 41 DAISY_IN IN4N 9 40 SCLK IN4P 10 39 CS IN3N 11 38 START IN3P 12 37 CLK IN2N 13 36 RESET AVSS 32 RESV1 31 VCAP2 30 NC 29 NC 27 VCAP1 28 VCAP4 26 VREFN 25 VREFP 24 AVSS 23 DGND AVDD 22 33 AVDD 21 IN1P 16 AVSS 20 DIN AVDD 19 PWDN 34 TESTP_PACE_OUT1 17 35 TESTN_PACE_OUT2 18 IN2P 14 IN1N 15 PAG PIN ASSIGNMENTS NAME TERMINAL FUNCTION DESCRIPTION IN8N (1) 1 Analog input Differential analog negative input 8 (ADS1198 only) IN8P (1) 2 Analog input Differential analog positive input 8 (ADS1198 only) IN7N (1) 3 Analog input Differential analog negative input 7 (ADS1198 only) (1) 4 Analog input Differential analog positive input 7 (ADS1198 only) IN6N (1) 5 Analog input Differential analog negative input 6 (ADS1196/8 only) IN6P (1) 6 Analog input Differential analog positive input 6 (ADS1196/8 only) IN5N (1) 7 Analog input Differential analog negative input 5 (ADS1196/8 only) IN5P (1) 8 Analog input Differential analog positive input 5 (ADS1196/8 only) IN4N (1) 9 Analog input Differential analog negative input 4 IN4P (1) 10 Analog input Differential analog positive input 4 IN3N (1) 11 Analog input Differential analog negative input 3 IN3P (1) 12 Analog input Differential analog positive input 3 IN2N (1) 13 Analog input Differential analog negative input 2 IN2P (1) 14 Analog input Differential analog positive input 2 IN1N (1) 15 Analog input Differential analog negative input 1 IN1P (1) 16 Analog input Differential analog positive input 1 IN7P (1) 10 Connect unused analog inputs IN1x to IN8x to AVDD. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com PAG PIN ASSIGNMENTS (continued) NAME TERMINAL FUNCTION TESTP_PACE_OUT1 17 Analog input/buffer output DESCRIPTION Internal test signal/single-ended buffer output based on register settings TESTN_PACE_OUT2 18 Analog input/output Internal test signal/single-ended buffer output based on register settings AVDD 19 Supply Analog supply AVSS 20 Supply Analog ground AVDD 21 Supply Analog supply AVDD 22 Supply Analog supply AVSS 23 Supply Analog ground VREFP 24 Analog input/output Positive reference voltage VREFN 25 Analog input Negative reference voltage VCAP4 26 Analog output NC 27 — No connection; leave floating VCAP1 28 — Analog bypass capacitor NC 29 — No connection; leave floating VCAP2 30 — Analog bypass capacitor RESV1 31 Digital input AVSS 32 Supply Analog ground DGND 33 Supply Digital ground DIN 34 Digital input SPI data in PWDN 35 Digital input Power-down; active low RESET 36 Digital input System reset; active low CLK 37 Digital input/output START 38 Digital input Start conversion CS 39 Digital input SPI chip select; active low SCLK 40 Digital input SPI clock DAISY_IN 41 Digital input Daisy-chain input. If not used, short to logic zero (DGND). GPIO1 42 Digital input/output DOUT 43 Digital output GPIO2 44 Digital input/output General-purpose input/output pin GPIO3 45 Digital input/output General-purpose input/output pin GPIO4 46 Digital input/output General-purpose input/output pin DRDY 47 Digital output Analog bypass capacitor Reserved for future use; must tie to logic low (DGND) External master clock input or internal clock output General-purpose input/output pin SPI data out Data ready; active low DVDD 48 Supply Digital power supply DGND 49 Supply Digital ground DVDD 50 Supply Digital power supply DGND 51 Supply Digital ground CLKSEL 52 Digital input AVSS1 53 Supply Analog ground AVDD1 54 Supply Analog supply VCAP3 55 Analog Analog bypass capacitor, internally generated AVDD + 1.9V AVDD 56 Supply Analog supply AVSS 57 Supply Analog ground AVSS 58 Supply Analog ground for charge pump AVDD 59 Supply Analog supply for charge pump RLDREF 60 Analog input RLDINV 61 Analog input/output Right leg drive inverting input RLDIN 62 Analog input Right leg drive input to MUX RLDOUT 63 Analog output Right leg drive output WCT 64 Analog output Wilson Center Terminal output Master clock select Right leg drive noninverting input Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 11 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com TIMING CHARACTERISTICS tCLK CLK tCSSC tSCLK SCLK tCSH tSDECODE CS 1 tSPWL tSPWH 3 2 8 1 tDIHD tDIST tSCCS 3 2 8 tDOHD tDOPD DIN tCSDOZ tCSDOD Hi-Z Hi-Z DOUT NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing tDISCK2ST MSBD1 DAISY_IN SCLK 1 2 tDISCK2HT LSBD1 3 152 154 153 155 tDOPD DOUT LSB MSB Don’t Care MSBD1 NOTE: Daisy-chain timing is shown for the 8-channel ADS1198. Figure 2. Daisy-Chain Interface Timing Timing Requirements For Figure 1 and Figure 2 Specifications apply from 0°C to +70°C. Load on DOUT = 20pF || 100kΩ. 2.7V ≤ DVDD ≤ 3.6V PARAMETER DESCRIPTION tCLK Master clock period tCSSC CS low to first SCLK; setup time MIN TYP 414 1.65V ≤ DVDD ≤ 2.0V MAX MIN 514 414 TYP MAX UNIT 514 ns 6 17 ns SCLK period 50 66.6 ns SCLK pulse width, high and low 15 25 ns tDIST DIN valid to SCLK falling edge; setup time 10 10 ns tDIHD Valid DIN after SCLK falling edge; hold time 10 11 ns tDOHD SCLK falling edge to invalid DOUT; hold time 10 10 tDOPD SCLK rising edge to DOUT valid; setup time tCSH CS high pulse 2 2 tCSDOD CS low to DOUT driven 8 20 ns tSCCS Eighth SCLK falling edge to CS high 4 4 tCLKs tSDECODE Command decode time 4 4 tCLKs tCSDOZ CS high to DOUT Hi-Z tDISCK2ST DAISY_IN valid to SCLK rising edge; setup time 10 10 ns tDISCK2HT DAISY_IN valid after SCLK rising edge; hold time 10 10 ns tSCLK tSPWH, 12 L Submit Documentation Feedback 17 ns 32 10 ns tCLKs 20 ns Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted. INL vs TEMPERATURE INL vs PGA GAIN 1 1 +70°C +50°C +25°C 0°C 0.6 0.4 0.8 Integral Nonlinearity (LSB) Integral Nonlinearity (LSB) 0.8 0.2 0 -0.2 -0.4 -0.6 -0.8 0.6 0.4 0.2 0 -0.2 PGA 1 PGA 2 PGA 3 PGA 4 -0.4 -0.6 -0.8 -1 -1 -1 0 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 1 0.8 -1 0.2 0.4 0.6 1 0.8 Input (Normalized to Full-Scale) Figure 3. Figure 4. FFT PLOT FFT PLOT 0 0 PGA Gain = 6 THD = -92dB SNR = 74dB fDR = 8kSPS -40 -60 PGA Gain = 6 THD = -96dB SNR = 96.7dB fDR = 500SPS -20 -40 Amplitude (dBFS) -20 Amplitude (dBFS) 0 -0.8 -0.6 -0.4 -0.2 Input (Normalized to Full-Scale Range) -80 -100 -120 -140 -60 -80 -100 -120 -160 -140 -180 -160 -180 -200 0 500 1000 1500 2000 2500 3000 3500 0 4000 50 100 150 Frequency (Hz) Frequency (Hz) Figure 5. Figure 6. CMRR vs FREQUENCY 200 250 THD vs FREQUENCY -125 -110 -120 Total Harmonic Distortion (dBc) Common-Mode Rejection Ratio (dB) PGA 6 PGA 8 PGA 12 -115 -110 -105 -100 -95 PGA = 1 PGA = 2 PGA = 3 PGA = 4 -90 -85 PGA = 6 PGA = 8 PGA = 12 -105 -100 -95 -90 PGA = 1 PGA = 2 PGA = 3 PGA = 4 -85 -80 PGA = 6 PGA = 8 PGA = 12 fDR = 4kSPS -75 -80 10 1k 100 10 Frequency (Hz) Figure 7. 100 1k Frequency (Hz) Figure 8. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 13 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted. PSRR vs FREQUENCY ADS1198 CHANNEL POWER 9 fDR = 4kSPS 8 100 AVDD = 5V 7 95 Power (mW) Power-Supply Rejection Ratio (dB) 105 90 85 Gain = 1 80 Gain = 6 Gain = 2 75 70 10 4 AVDD = 3V 3 1 Gain = 12 Gain = 4 5 2 Gain = 8 Gain = 3 6 0 1k 100 0 1 2 Frequency (Hz) 3 Figure 9. 6 7 8 INPUT LEAKAGE vs INPUT VOLTAGE 120 140 Mean = 0.78 s = 0.92 Input Leakage Current (pA) Number of Occurrences 5 Figure 10. 16nA LEADOFF CURRENT ACCURACY DISTRIBUTION 120 4 Number of Channels Enabled 100 80 60 40 20 100 80 60 40 20 0 0 -2 -1.3 -0.6 0.12 0.82 1.51 2.21 0.1 2.91 3.61 0.6 1.1 1.6 2.1 2.6 3.1 Input Common-Mode Voltage (V) Error Current (nA) Figure 11. Figure 12. INPUT LEAKAGE CURRENT vs TEMPERATURE 1000 Leakage Current (pA) 900 800 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 Temperature (°C) Figure 13. 14 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com OVERVIEW The ADS1194/6/8 are low-power, multichannel, simultaneously-sampling, 16-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG), electroencephalography (EEG), and electromyography (EMG) applications. The devices can also be used in high-performance, multichannel data acquisition systems by powering down the ECG-specific circuitry. The ADS1194/6/8 have a highly programmable multiplexer that allows for temperature, supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The ADCs in the device offer data rates from 125SPS to 8kSPS. Communication to the device is accomplished using an SPI-compatible interface. The device provides four GPIO pins for general use. Multiple devices can be synchronized using the START pin. The internal reference can be programmed to either 2.4V or 4V. The internal oscillator generates a 2.048MHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using a pull-up/pull-down resistor or a current source/sink. An internal ac lead-off detection feature is also available. The device supports both hardware pace detection and software pace detection. The Wilson center terminal (WCT) block can be used to generate the WCT point of the standard 12-lead ECG. THEORY OF OPERATION This section contains details of the ADS1194/6/8 internal functional elements; see Figure 14. The analog blocks are discussed first, followed by the digital interface. Blocks implementing ECG-specific functions are covered at the end. Throughout this document, fCLK denotes the frequency of the signal at the CLK pin, tCLK denotes the period of the signal at the CLK pin, fDR denotes the output data rate, tDR denotes the time period of the output data, and fMOD denotes the frequency at which the modulator samples the input. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 15 16 Submit Documentation Feedback ADS1196 and ADS1198 Only Product Folder Link(s): ADS1194 ADS1196 ADS1198 EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter AVSS AVSS1 MUX WCT From Wmuxb From Wmuxa B A RLD Amplifier PGA8 PGA7 PGA6 PGA5 PGA4 PGA3 PGA2 RLD RLD RLD IN REF OUT From Wmuxc C Power-Supply Signal PGA1 Temperature Sensor Input Test Signal Lead-Off Excitation Source RLD INV G = 0.4 PACE OUT2 PACE Amplifier 2 DS ADC8 DS ADC7 DS ADC6 DS ADC5 DS ADC4 DS ADC3 DS ADC2 DS ADC1 Reference VREFP VREFN G = 0.4 PACE OUT1 DGND Oscillator PACE Amplifier 1 Control SPI DVDD START RESET PWDN GPIO2 GPIO4 GPIO3 GPIO1 CLK CLKSEL CS SCLK DIN DOUT DRDY SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 WCT IN8N IN8P IN7N IN7P IN6N IN6P IN5N IN5P IN4N IN4P IN3N IN3P IN2N IN2P IN1N IN1P AVDD AVDD1 ADS1194, ADS1196 ADS1198 www.ti.com ADS1198 Only Figure 14. Functional Block Diagram Copyright © 2010–2011, Texas Instruments Incorporated ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com EMI FILTER An RC filter at the input acts as an electromagnetic interference (EMI) filter on all of the channels. The –3dB filter bandwidth is approximately 3MHz. INPUT MULTIPLEXER The ADS1194/6/8 input multiplexers are very flexible and provide many configurable signal switching options. Figure 15 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks, one for each channel. TEST_PACE_OUT1, TEST_PACE_OUT2, and RLD_IN are common to all eight blocks. VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration and configuration. Selection of switch settings for each channel is made by writing the appropriate values to the CHnSET[2:0] register (see the CHnSET: Individual Channel Settings section for details) and by writing the RLD_MEAS bit in the CONFIG3 register (see the CONFIG3: Configuration Register 3 subsection of the Register Map section for details). More details of the ECG-specific features of the multiplexer are discussed in the Input Multiplexer subsection of the ECG-Specifc Functions section. ADS119x MUX INT_TEST TESTP_PACE_OUT1 INT_TEST MUX[2:0] = 101 TestP TempP MvddP (1) MUX[2:0] = 100 MUX[2:0] = 011 From LoffP MUX[2:0] = 000 VINP MUX[2:0] = 110 EMI Filter To PgaP MUX[2:0] = 010 AND RLD_MEAS MUX[2:0] = 001 (AVDD + AVSS) 2 MUX[2:0] = 111 MUX[2:0] = 000 VINN RLDIN From LoffN MUX[2:0] = 001 To PgaN MUX[2:0] = 010 AND RLD_MEAS RLD_REF MvddN (1) TempN MUX[2:0] = 011 MUX[2:0] = 100 MUX[2:0] = 101 TestN INT_TEST TESTN_PACE_OUT2 INT_TEST (1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section. Figure 15. Input Multiplexer Block for One Channel Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 17 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD – AVSS)/2 to both inputs of the channel. This setting can be used to test the inherent noise of the device in the user system. Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in subsystem verification at power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance testing. Control of the test signals is accomplished through register settings (see the CONFIG2: Configuration Register 2 subsection in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls switching at the required frequency. The test signals are multiplexed and transmitted out of the device at the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins. A bit register, INT_TEST = 0, deactivates the internal test signals so that the test signal can be driven externally. This feature allows the calibration of multiple devices with the same signal. The test signal feature cannot be used in conjunction with the external hardware pace feature (see the External Hardware Approach subsection of the ECG-Specific Functions section for details). Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2) When hardware pace detect is not used, the TESTP_PACE_OUT1 and TESPN_PACE_OUT2 signals can be used as a multiplexed differential input channel. These inputs can be multiplexed to any of the eight channels. The performance of the differential input signal fed through these pins is identical to the normal channel performance. Temperature Sensor (TempP, TempN) The ADS1194/6/8 contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in Figure 16. The difference in current densities of the diodes yields a difference in voltage that is proportional to absolute temperature. As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note that self-heating of the ADS1194/6/8 causes a higher reading than the temperature of the surrounding PCB. The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, the temperature reading code must first be scaled to μV. Temperature (°C) = Temperature Reading (mV) - 145,300mV 490mV/°C + 25°C (1) Temperature Sensor Monitor AVDD 1x 2x To MUX TempP To MUX TempN 8x 1x AVSS Figure 16. Measurement of the Temperature Sensor in the Input 18 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Supply Measurements (MVDDP, MVDDN) Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channel 3 and 4, (MVDDP – MVDDN) is DVDD/2. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'. Lead-Off Excitation Signals (LoffP, LoffN) The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section. Auxiliary Single-Ended Input The RLD_IN pin is primarily used for routing the right leg drive signal to any of the electrodes in case the right leg drive electrode falls off. However, the RLD_IN pin can be used as a multiple single-ended input channel. The signal at the RLD_IN pin can be measured with respect to the voltage at the RLD_REF pin using any of the eight channels. This measurement is done by setting the channel multiplexer setting to '010' and the RLD_MEAS bit of the CONFIG3 register to '1'. ANALOG INPUT The analog input to the ADS1198 is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span between –VREF to +VREF. Note that the absolute range for INP and INN must be between AVSS – 0.3 V and AVDD + 0.3 V. Refer to Table 6 for an explanation of the correlation between the analog input and the digital codes. There are two general methods of driving the analog input of the ADS1198: single-ended or differential, as shown in Figure 17 and Figure 18. When the input is single-ended, the INN input is held at the common-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + 1/2VREF) and the (common-mode – 1/2VREF). When the input is differential, the common-mode is given by (INP + INN)/2. Both the INP and INN inputs swing from (common-mode + 1/2VREF to common-mode – 1/2VREF). For optimal performance, it is recommended that the ADS1198 be used in a differential configuration. -1/2VREF to +1/2VREF VREF peak-to-peak ADS1198 ADS1198 Common Voltage Common Voltage Single-Ended Input VREF peak-to-peak Differential Input Figure 17. Methods of Driving the ADS1198: Single-Ended or Differential CM + 1/2VREF +1/2VREF INP CM Voltage -1/2VREF INN = CM Voltage CM - 1/2VREF t Single-Ended Inputs INP CM + 1/2VREF +VREF CM Voltage CM - 1/2VREF INN -VREF t Differential Inputs (INP) + (INN) , Common-Mode Voltage (Single-Ended Mode) = INN. 2 Input Range (Differential Mode) = (AINP - AINN) = VREF - (-VREF) = 2VREF. Common-Mode Voltage (Differential Mode) = Figure 18. Using the ADS1198 in the Single-Ended and Differential Input Modes Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 19 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com PGA SETTINGS AND INPUT RANGE The PGA is a differential input/differential output amplifier, as shown in Figure 19. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel Settings subsection of the Register Map section for details). The ADS1194/6/8 have CMOS inputs and hence have negligible current noise. Table 4 shows the typical values of bandwidths for various gain settings. Note that Table 4 shows the small-signal bandwidth. For large signals, the performance is limited by the slew rate of the PGA. From MuxP PgaP R2 50kW R1 20kW (for Gain = 6) To ADC R2 50kW PgaN From MuxN Figure 19. PGA Implementation Table 4. PGA Gain versus Bandwidth GAIN NOMINAL BANDWIDTH AT ROOM TEMPERATURE (kHz) 1 158 2 97 3 85 4 64 6 43 8 32 12 21 The resistor string of the PGA that implements the gain has 120kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of differential signal at input. Input Common-Mode Range The usable input common-mode range of the front end depends on various parameters, including the maximum differential input signal, supply voltage, PGA gain, etc. This range is described in Equation 2: AVDD - 0.2 - Gain VMAX_DIFF 2 > CM > AVSS + 0.2 + Gain VMAX_DIFF 2 where: VMAX_DIFF = maximum differential signal at the input of the PGA CM = common-mode range (2) For example: If VDD = 3V, gain = 6, and VMAX_DIFF = 350mV Then 1.25V < CM < 1.75V 20 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Input Differential Dynamic Range The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This range is shown in Equation 3. VREF ±VREF Max (INP - INN) < ; Full-Scale Range = Gain Gain (3) The 3V supply, with a reference of 2.4V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300mV. For higher dynamic range, a 5V supply with a reference of 4V (set by the VREF_4V bit of the CONFIG3 register) can be used to increase the differential dynamic range. ADC ΔΣ Modulator Power Spectral Density (dB) Each channel of the ADS1194/6/8 has a 16-bit ΔΣ ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK/8. As in the case of any ΔΣ modulator, the noise of the ADS1194/6/8 is shaped until fMOD/2, as shown in Figure 20. The on-chip digital decimation filters explained in the next section can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of the analog antialiasing filters that are typically needed with nyquist ADCs. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 0.001 0.01 0.1 Normalized Frequency (fIN/fMOD) 1 G001 Figure 20. Modulator Noise Spectrum Up To 0.5 × fMOD Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 21 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com DIGITAL DECIMATION FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection and ac lead-off detection. The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a global setting that affects all channels and, therefore, in a device all channels operate at the same data rate. Sinc Filter Stage (sinx/x) The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter. Equation 4 shows the scaled Z-domain transfer function of the sinc filter. H(z) = 1 - Z- N 3 1 - Z- 1 (4) The frequency domain transfer function of the sinc filter is shown in Equation 5. 3 sin H(f) = N ´ sin Npf fMOD pf fMOD where: N = decimation ratio 22 Submit Documentation Feedback (5) Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 21 shows the frequency response of the sinc filter and Figure 22 shows the roll-off of the sinc filter. With a step change at input, the filter takes 3 × tDR to settle. The fourth DRDY pulse is settled data. After a rising edge of the START signal, the filter takes tSETTLE time to give the first data output. The settling time of the filters at various data rates are discussed in the START subsection of the SPI Interface section. Figure 23 and Figure 24 show the filter transfer function until fMOD/2 and fMOD/16, respectively, at different data rates. Figure 25 shows the transfer function extended until 4 × fMOD. It can be seen that the passband of the ADS1194/6/8 repeats itself at every fMOD. The input R-C anti-aliasing filters in the system should be chosen such that any interference in frequencies around multiples of fMOD are attenuated sufficiently. 0 0 -20 -0.5 -40 Gain (dB) Gain (dB) -1.0 -60 -80 -1.5 -2.0 -100 -2.5 -120 -3.0 -140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.05 0.10 Normalized Frequency (fIN/fDR) 0.15 0.30 0.35 Figure 22. Sinc Filter Roll-Off 0 0 DR[2:0] = 110 DR[2:0] = 110 -20 DR[2:0] = 000 DR[2:0] = 000 -40 Gain (dB) -40 Gain (dB) 0.25 Normalized Frequency (fIN/fDR) Figure 21. Sinc Filter Frequency Response -20 0.20 -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 0.01 0.02 Normalized Frequency (fIN/fMOD) 0.04 0.05 0.06 0.07 Normalized Frequency (fIN/fMOD) Figure 23. Transfer Function of On-Chip Decimation Filters Until fMOD/2 10 0.03 Figure 24. Transfer Function of On-Chip Decimation Filters Until fMOD/16 DR[2:0] = 000 DR[2:0] = 110 -10 Gain (dB) -30 -50 -70 -90 -110 -130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (fIN/fMOD) Figure 25. Transfer Function of On-Chip Decimation Filters Until 4fMOD for DR[2:0] = 000 and DR[2:0] = 110 Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 23 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com REFERENCE Figure 26 shows a simplified block diagram of the internal reference of the ADS1194/6/8. The reference voltage is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS. 22mF VCAP1 R1 (1) Bandgap 2.4V or 4V R3 VREFP (1) 10mF R2 (1) VREFN AVSS To ADC Reference Inputs (1) For VREF = 2.4: R1 = 12.5kΩ, R2 = 25kΩ, and R3 = 25kΩ. For VREF = 4V: R1 = 10.5kΩ, R2 = 15kΩ, and R3 = 35kΩ. Figure 26. Internal Reference The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10Hz, so that the reference noise does not dominate the system noise. When using a 3V analog supply, the internal reference must be set to 2.4V. In case of a 5V analog supply, the internal reference can be set to 4V by setting the VREF_4V bit in the CONFIG2 register. Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 27 shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the CONFIG3 register. This power-down is also used to share internal references when two devices are cascaded. By default the device wakes up in external reference mode. 100kW 10pF +5V 0.1mF 100W +5V VIN To VREFP Pin OPA211 100W 10mF OUT 22mF REF5025 TRIM 0.1mF 100mF 22mF Figure 27. External Reference Driver 24 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CLOCK The ADS1194/6/8 provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit. The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 5. The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that during power-down the external clock be shut down to save power. Table 5. CLKSEL Pin and CLK_EN Bit CLKSEL PIN CONFIG1.CLK_EN BIT CLOCK SOURCE CLK PIN STATUS 0 X External clock Input: external clock 1 0 Internal clock oscillator 3-state 1 1 Internal clock oscillator Output: internal clock oscillator DATA FORMAT The ADS1194/6/8 outputs 16 bits of data per channel in binary twos complement format, MSB first. The LSB has a weight of VREF/(215 – 1). A positive full-scale input produces an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at these codes for signals exceeding full-scale. Table 6 summarizes the ideal output codes for different input signals. Table 6. Ideal Input Code versus Input Signal (1) (1) (2) INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE (2) ≥ VREF 7FFFh +VREF/(215 – 1) 0001h 0 0000h –VREF/(215 – 1) FFFFh ≤ –VREF (215/215 – 1) 8000h Assumes gain = 1. Excludes effects of noise, linearity, offset, and gain error. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 25 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com SPI INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls the ADS1194/6/8 operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available. Chip Select (CS) Chip select (CS) selects the ADS1194/6/8 for SPI communication. CS must remain low for the entire duration of the serial communication. After the serial communication is finished, always wait eight or more tCLK cycles before taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low. Serial Clock (SCLK) SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT pins into and out of the ADS1194/6/8. Even though the input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. The absolute maximum limit for SCLK is specified in the Serial Interface Timing table. When shifting in commands with SCLK, make sure that the entire set of SCLKs is issued to the device. Failure to do so results in the device being placed into an unknown state, requiring CS to be taken high to recover. For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of bits of resolution, and output data rate. (For multiple cascaded devices, see the Standard Mode subsection of the Multiple Device Configuration section.) tSCLK < (tDR – 4tCLK)/(NBITS × NCHANNELS + 24) For example, if the ADS1198 is used in a 500SPS mode (8 channels, 16-bit resolution), the minimum SCLK speed is 80kHz. Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. The above calculation assumes that there are no other commands issued in between data captures. Data Input (DIN) The data input pin (DIN) is used along with SCLK to send data to the ADS1194/6/8 (opcode commands and register data). The device latches data on DIN on the falling edge of SCLK. 26 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1194/6/8. Data on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available. This feature can be used to minimize the number of connections between the device and the system controller. The START signal must be high or the START command must be issued before retrieving data from the device. Figure 28 shows the data output protocol for ADS1198. DRDY CS SCLK 152 SCLKs DOUT STAT CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 24-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit DIN Figure 28. SPI Bus Data Output for the ADS1198 (8-Channels) Data Retrieval Data retrieval can be accomplished in one of two methods. The read data continuous command can be used to set the device in a mode to read the data continuously without sending opcodes. The read data command can be used to read just one data output from the device (see the SPI Command Definitions section for more details). The conversion data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read operation. The number of bits in the data output depends on the number of channels and the number of bits per channel. For the ADS1198, the number of data outputs is (24 status bits + 16 bits × 8 channels = 152 bits) for all data rates. The format of the 24 status bits is: (1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO register). The data format for each channel data are twos complement and MSB first. When channels are powered down using the user register setting, the corresponding channel output is set to '0'. However, the sequence of channel outputs remains the same. For the ADS1194 and the ADS1196, the last four and two channel outputs shown in Figure 28 are zeros. Status and GPIO register bits are loaded into the 24-bit status word 2tCLKs before DRDY goes low. The ADS1194/6/8 also provide a multiple readback feature. The data can be read out multiple times by simply giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_EN bit in CONFIG1 register must be set to '1' for multiple readbacks. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 27 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Data Ready (DRDY) DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. The behavior of DRDY is determined by whetehr the device is in RDATAC mode or the RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read Data subsections of the SPI Command Definitions section for further detials). Regardless of the status of the CS signal, a rising edge on SCLK pulls DRDY high. Hence, when using multiple devices in the SPI bus, it is recommended that SCLK be gated with CS. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. The START pin or the START command is used to place the device either in normal data capture mode or pulse data capture mode. Figure 29 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1198). DOUT is latched at the rising edge of SCLK. DRDY is pulled high at the falling edge of SCLK. Note that DRDY goes high on the first falling edge SCLK regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. DRDY Bit 151 DOUT Bit 149 Bit 150 SCLK Figure 29. DRDY with Data Retrieval (CS = 0 in RDATA Mode) GPIO The ADS1194/6/8 have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the data returned are the level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the GPIOD bit sets the output value. If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on or after a reset. Figure 30 shows the GPIO port structure. GPIO1 can be used as the PACEIN signal; GPIO2 is multiplexed with RESP_BLK signal; GPIO3 is multiplexed with the RESP signal; and GPIO4 is multiplexed with the RESP_PH signal. GPIO Data (read) GPIO Pin GPIO Data (write) GPIO Control Figure 30. GPIO Port Pin Power-Down (PWDN) When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin high. Upon exiting from power-down mode, the internal oscillator and the reference require a wake-up time. It is recommended that during power-down the external clock is shut down to save power. 28 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Reset (RESET) There are two methods to reset the ADS1194/6/8: pull the RESET pin low, or send the RESET opcode command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 CLK cycles to complete initialization of the configuration registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to a new value with a WREG command. START The START pin must be set high for at least two tCLKs, or the START command sent, to begin conversions. When START is low, or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversion, hold the START pin low. The ADS1194/6/8 feature two modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT (bit 3 of the CONFIG4 register). In multiple device configurations the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for more details). Settling Time The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when START signal is pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates that data are ready. Figure 31 shows the timing diagram and Table 7 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Table 6 describes the settling time as a function of tCLK. Note that when START is held high and there is a step change in the input signal, it takes 3 × tDR for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse. This time must be considered when trying to measure narrow pace pulses for pacer detection. tSETTLE START Pin or START Opcode DIN tDR 4/fCLK DRDY Figure 31. Settling Time Table 7. Settling Time for Different Data Rates DR[2:0] SETTLING TIME UNIT 000 1160 tCLK 001 2312 tCLK 010 4616 tCLK 011 9224 tCLK 100 18440 tCLK 101 36872 tCLK 110 73736 tCLK Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 29 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Continuous Mode Conversions begin when the START pin is taken high for at least two tCLKs or when the START opcode command is sent. As seen in Figure 32, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete. Figure 33 and Table 8 show the required timing of DRDY to the START pin and the START/STOP opcode commands when controlling conversions in this mode. To keep the converter running continuously, the START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the START signal is pulsed or a STOP command must be issued followed by a START command. This conversion mode is ideal for applications that require a fixed continuous stream of conversion results. START Pin or or (1) DIN (1) START Opcode STOP Opcode tDR DRDY (1) tSETTLE START and STOP opcode commands take effect on the seventh SCLK falling edge. Figure 32. Continuous Conversion Mode tSDSU DRDY and DOUT tDSHD START Pin or STOP Opcode (1) STOP(1) STOP(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission. Figure 33. START to DRDY Timing Table 8. Timing Characteristics for Figure 33 (1) SYMBOL (1) 30 MIN UNIT tSDSU START pin low or STOP opcode to DRDY setup time to halt further conversions DESCRIPTION 16 1/fCLK tDSHD START pin low or STOP opcode to complete current conversion 16 1/fCLK START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Single-Shot Mode The single-shot mode is enabled by setting the SINGLE_SHOT bit in CONFIG4 register to '1'. In single-shot mode, the ADS1194/6/8 perform a single conversion when the START pin is taken high for at least two tCLKs, or when the START opcode command is sent. As seen in Figure 34, when a conversion is complete, DRDY goes low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To begin a new conversion, take the START pin low and then back high, or transmit the START opcode again. Note that when switching from continuous mode to pulse mode, make sure the START signal is pulsed or issue a STOP command followed by a START command. START tSETTLE 4/fCLK 4/fCLK Data Updating DRDY Figure 34. DRDY with No Data Retrieval in Single-Shot Mode This conversion mode is provided for applications that require a non-standard or non-continuous data rate. Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data rate by a factor of four. This mode leaves the system more susceptible to aliasing effects, requiring more complex analog or digital filtering. Loading on the host processor increases because it must toggle the START pin or send a START command to initiate a new conversion cycle. MULTIPLE DEVICE CONFIGURATION The ADS1194/6/8 are designed to provide configuration flexibility when multiple devices are used in a system. The SPI interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal per device, multiple devices can be connected together. The number of signals needed to interface n devices is 3 + n. The right-leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration, one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit. This master device clock is used as the external clock source for the other devices. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 31 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 35 shows the behavior of two devices when synchronized with the START signal. There are two ways to connect multiple devices with a optimal number of interface pins: cascade mode and daisy-chain mode. ADS11981 START CLK START1 DRDY DRDY1 CLK ADS11982 START2 DRDY DRDY2 CLK CLK tSETTLE START DRDY1 DRDY2 Figure 35. Synchronizing Multiple Converters 32 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Standard Mode Figure 36a shows a configuration with two devices cascaded together. One of the devices is an ADS1198 (eight-channel) and the other is an ADS1194 (four-channel). Together, they create a system with 12 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the majority of applications. DAISY-CHAIN MODE Daisy-chain mode is enabled by setting the DAISY_EN bit in the CONFIG1 register. Figure 36b shows the daisy-chain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT of one device is hooked up to the DAISY_IN of the other device, thereby creating a chain. One extra SCLK must be issued in between each data set. Also, when using daisy-chain mode the multiple readback feature is not available. Short the DAISY_IN pin to digital ground if not used. Figure 2 (Daisy-Chain Interface Timing) describes the required timing for the ADS1198 shown in Figure 36. Data from the ADS1198 appear first on DOUT, followed by a don’t care bit, and finally by the status and data words from the ADS1194. START (1) CLK START CLK DRDY INT CS GPO0 START (1) CLK START DRDY CLK INT CS GPO GPO1 ADS1198 (Device 0) SCLK SCLK MOSI ADS1198 (Device 0) SCLK DIN DIN SCLK MOSI DOUT MISO DAISY_IN0 DOUT0 MISO Host Processor START CLK DOUT1 DRDY CS DRDY CS START SCLK ADS1194 (Device 1) Host Processor SCLK CLK DIN DIN ADS1194 (Device 1) DOUT DAISY_IN1 0 b) Daisy-Chain Configuration a) Standard Configuration (1) To reduce pin count, set the START pin low and use the START serial command to synchronize and start conversions. Figure 36. Multiple Device Configurations In a case where all devices in the chain operate in the same register setting, DIN can be shared as well and thereby reduce the SPI communication signals to four, regardless of the number of devices. However, because the individual devices cannot be programmed, the RLD driver cannot be shared among the multiple devices. Furthermore, an external clock must be used. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 33 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Note that from Figure 2, the SCLK rising edge shifts data out of the ADS1194/6/8 on DOUT. The SCLK rising edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK rate speed, but it also makes the interface sensitive to board level signal delays. The more devices in the chain, the more challenging it could become to adhere to setup and hold times. A star pattern connection of SCLK to all devices, minimizing length of DOUT, and other PCB layout techniques help. Placing delay circuits such as buffers between DOUT and DAISY_IN are ways to mitigate this challenge. One other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Note also that daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries. Figure 37 shows a timing diagram for the daisy-chain mode. DOUT1 DAISY_IN0 MSB1 1 SCLK DOUT 0 LSB1 2 3 152 MSB0 154 153 LSB0 XX 155 MSB1 Data from first device (ADS1198) 241 LSB1 Data from second device (ADS1194) Figure 37. Daisy-Chain Timing The maximum number of devices that can be daisy-chained depends on the data rate at which the device is being operated. The maximum number of devices can be approximately calculated with Equation 6. fSCLK NDEVICES = fDR (NBITS)(NCHANNELS) + 24 where: NBITS = device resolution (depends on data rate), and NCHANNELS = number of channels in the device (4, 6, or 8). (6) For example, when the ADS1198 (eight-channel, 16-bit version) is operated at a 2kSPS data rate with a 4MHz fSCLK, 15 devices can be daisy-chained. 34 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com SPI COMMAND DEFINITIONS The ADS1194/6/8 provide flexible configuration control. The opcode commands, summarized in Table 9, control and configure the operation of the ADS1194/6/8. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data. CS can be taken high or held low between opcode commands but must stay low for the entire command operation (especially for multi-byte commands). System opcode commands and the RDATA command are decoded by the ADS1194/6/8 on the seventh falling edge of SCLK. The register read/write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing requirements when pulling CS high after issuing a command. Table 9. Command Definitions COMMAND DESCRIPTION FIRST BYTE SECOND BYTE System Commands WAKEUP Wake-up from standby mode. NOP command in normal mode. 0000 0010 (02h) STANDBY Enter standby mode 0000 0100 (04h) RESET Reset the device 0000 0110 (06h) START Start/restart (synchronize) conversions 0000 1000 (08h) STOP Stop conversion 0000 1010 (0Ah) Data Read Commands RDATAC Enable Read Data Continuous mode. This mode is the default mode at power-up. (1) 0001 0000 (10h) SDATAC Stop Read Data Continuously mode 0001 0001 (11h) RDATA Read data by command; supports multiple read back. 0001 0010 (12h) Register Read Commands RREG Read n nnnn registers starting at address rrrr 001r rrrr (2xh) (2) 000n nnnn (2) WREG Write n nnnn registers starting at address rrrr 010r rrrr (4xh) (2) 000n nnnn (2) (1) (2) When in RDATAC mode, the RREG command is ignored. n nnnn = number of registers to be read/written – 1. For example, to read/write three registers, set nnnn = 0 (0010). rrrr = starting register address for read/write opcodes. WAKEUP: Exit STANDBY Mode This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical Characteristics for details). There are no restrictions on the SCLK rate for this command and it can be issued any time. Any following command must be sent after 4 CLK cycles. STANDBY: Enter STANDBY Mode This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are no restrictions on the SCLK rate for this command and it can be issued any time. RESET: Reset Registers to Default Values This command resets the digital filter cycle and returns all register settings to the default values. See the Reset (RESET) subsection of the SPI Interface section for more details. There are no restrictions on the SCLK rate for this command and it can be issued any time. It takes 18 CLK cycles to execute the RESET command. Avoid sending any commands during this time. START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command then have a gap of 4 CLK cycles between them. When the START opcode is sent to the device, keep the START pin low until the STOP command is issued. (See the START subsection of the SPI Interface section for more details.) There are no restrictions on the SCLK rate for this command and it can be issued any time. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 35 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com STOP: Stop Conversions This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it can be issued any time. RDATAC: Read Data Continuous This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The read data continuous mode is the default mode of the device and the device defaults in this mode on power-up. RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a SDATAC command must be issued before any other commands can be sent to the device. There is no restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC opcode command should wait at least 4 CLK cycles. The timing for RDATAC is shown in Figure 38. As Figure 38 shows, there is a keep out zone of 4 CLK cycles around the DRDY pulse where this command cannot be issued in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from the device after RDATAC command is issued, make sure either the START pin is high or the START command is issued. Figure 38 shows the recommended way to use the RDATAC command. RDATAC is ideally suited for applications such as data loggers or recorders where registers are set once and do not need to be re-configured. START DRDY CS SCLK tUPDATE RDATAC Opcode DIN Hi-Z DOUT Status Register + 8-Channel Data (152 Bits) (1) Next Data tUPDATE = 4/fCLK. Do not read data during this time. Figure 38. RDATAC Usage SDATAC: Stop Read Data Continuous This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this command, but the following command must wait for 4 CLK cycles. 36 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make sure either the START pin is high or the START command is issued. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 39 shows the recommended ways to use the RDATA command. RDATA is best suited for ECG and EEG type systems, where register setting must be read or changed often between conversion cycles. START DRDY CS SCLK RDATA Opcode DIN RDATA Opcode Hi-Z DOUT Status Register+ 8-Channel Data (152 Bits) Figure 39. RDATA Usage Sending Multi-Byte Commands The ADS1194/6/8 serial interface decodes commands in bytes and requires four CLK cycles to decode and execute. Therefore, when sending multi-byte commands, a period of four CLKs must separate the end of one byte (or opcode) and the next. Assume CLK is 2.048MHz, then tSDECODE (4 tCLK) is 1.96µs. When SCLK is 16MHz, one byte can be transferred in 500ns. This byte transfer time does not meet the tSDECODE specification; therefore, a delay must be inserted so the end of the second byte arrives 1.46µs later. If SCLK is 4MHz, one byte is transferred in 2µs. Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without delay. In this later scenario, the serial port can be programmed to cease single-byte transfer per cycle to multiple bytes. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 37 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1. First opcode byte: 0010 rrrr, where rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1. The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 40. When the device is in read data continuous mode it is necessary to issue a SDATAC command before RREG command can be issued. RREG command can be issued any time. However, because this command is a multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire command. (1) CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA DOUT REG DATA + 1 Figure 40. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register) (OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001) WREG: Write to Register This opcode writes register data. The Register Write command is a two-byte opcode followed by the input of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to write – 1. First opcode byte: 0100 rrrr, where rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1. After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 41. WREG command can be issued any time. However, because this command is a multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire command. CS (1) 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2 DOUT Figure 41. WREG Command Example: Write Two Registers Starting from 00h (ID Register) (OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001) 38 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com REGISTER MAP Table 10 describes the various ADS1194/6/8 registers. Table 10. Register Assignments ADDRESS RESET VALUE (Hex) REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 XX DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0 Device Settings (Read-Only Registers) 00h ID Global Settings Across Channels 01h CONFIG1 04 0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0 02h CONFIG2 20 0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 03h CONFIG3 40 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_ SENS RLD_STAT 04h LOFF 00 COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_ EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 Channel-Specific Settings 05h CH1SET 00 PD1 GAIN12 GAIN11 GAIN10 0 MUXn2 MUXn1 MUXn0 06h CH2SET 00 PD2 GAIN22 GAIN21 GAIN20 0 MUX22 MUX21 MUX20 07h CH3SET 00 PD3 GAIN32 GAIN31 GAIN30 0 MUX32 MUX31 MUX30 08h CH4SET 00 PD4 GAIN42 GAIN41 GAIN40 0 MUX42 MUX41 MUX40 09h CH5SET (1) 00 PD5 GAIN52 GAIN51 GAIN50 0 MUX52 MUX51 MUX50 0Ah CH6SET (1) 00 PD6 GAIN62 GAIN61 GAIN60 0 MUX62 MUX61 MUX60 0Bh CH7SET (1) 00 PD7 GAIN72 GAIN71 GAIN70 0 MUX72 MUX71 MUX70 0Ch CH8SET (1) 00 PD8 GAIN82 GAIN81 GAIN80 0 MUX82 MUX81 MUX80 0Dh RLD_SENSP (2) 00 RLD8P (1) RLD7P (1) RLD6P (1) RLD5P (1) RLD4P RLD3P RLD2P RLD1P 0Eh RLD_SENSN (2) 00 RLD8N (1) RLD7N (1) RLD6N (1) RLD5N (1) RLD4N RLD3N RLD2N RLD1N 0Fh LOFF_SENSP (2) 00 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P 10h LOFF_SENSN (2) 00 LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N 11h LOFF_FLIP 00 LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1 Lead-Off Status Registers (Read-Only Registers) 12h LOFF_STATP 00 IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF 13h LOFF_STATN 00 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF GPIO and OTHER Registers (1) (2) 14h GPIO 0F GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 15h PACE 00 0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE 16h RESERVED 00 0 0 0 0 0 0 0 0 WCT_TO_ RLD PD_LOFF_ COMP 0 17h CONFIG4 00 0 0 0 0 SINGLE_ SHOT 18h WCT1 00 aVF_CH6 aVL_CH5 aVR_CH7 avR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0 19h WCT2 00 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0 CH5SET and CH6SET are not available for the ADS1194. CH7SET and CH8SET registers are not available for the ADS1194 and ADS1196. The RLD_SENSP, PACE_SENSP, LOFF_SENSP, LOFF_SENSN, and LOFF_FLIP registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194/6. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 39 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com User Register Description ID: ID Control Register (Factory-Programmed, Read-Only) Address = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0 The ID Control Register is programmed during device manufacture to indicate device characteristics. Bits[7:5] DEV_ID[5:3]: Device family identification These bits indicate the device family. 000 = Reserved 011 = Reserved 100 = Reserved 101 = ADS119x device family 110 = Reserved 111 = Reserved Bit 4 This bit reads high. Bit 3 This bit reads low. Bit 2 DEV_ID2: Channel number identification This bit reads high. Bits[1:0] DEV_ID[1:0]: Channel number identification These bits indicates number of channels. 00 = 4-channel ADS1194 01 = 6-channel ADS1196 10 = 8-channel ADS1198 11 = Reserved 40 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CONFIG1: Configuration Register 1 Address = 01h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0 Bit 7 Must always be set to '0' Bit 6 DAISY_EN: Daisy-chain/multiple readback mode This bit determines which mode is enabled. 0 = Daisy-chain mode (default) 1 = Multiple readback mode Bit 5 CLK_EN: CLK connection (1) This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1. 0 = Oscillator clock output disabled (default) 1 = Oscillator clock output enabled Bits[4:3] Must always be set to '0' Bits[2:0] DR[2:0]: Output data rate. fMOD = fCLK/16. These bits determine the output data rate of the device. (1) (1) Additional power will be consumed when driving external devices. BIT DATA RATE SAMPLE RATE (1) 000 fMOD/16 8kSPS 001 fMOD/32 4kSPS 010 fMOD/64 2kSPS 011 fMOD/128 1kSPS 100 (default) fMOD/256 500SPS 101 fMOD/512 250SPS 110 fMOD/1024 125SPS 111 DO NOT USE N/A fCLK = 2.048MHz. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 41 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CONFIG2: Configuration Register 2 Address = 02h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 Configuration Register 2 configures the test signal generation. See the Input Multiplexer section for more details. Bits[7:6] Must always be set to '0' Bits 5 Must always be set to '1' Bit 4 INT_TEST: TEST source This bit determines the source for the Test signal. 0 = Test signals are driven externally (default) 1 = Test signals are generated internally Bit 3 Must always be set to '0' Bit 2 TEST_AMP: Test signal amplitude These bits determine the Calibration signal amplitude. 0 = –1 × (VREFP – VREFN)/2.4mV (default) 1 = –2 × (VREFP – VREFN)/2.4mV Bits[1:0] TEST_FREQ[1:0]: Test signal frequency These bits determine the calibration signal frequency. 00 = Pulsed at fCLK/221 (default) 01 = Pulsed at fCLK/220 10 = Not used 11 = At dc 42 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CONFIG3: Configuration Register 3 Address = 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_SENS RLD_STAT Configuration Register 3 configures multi-reference and RLD operation. Bit 7 PD_REFBUF: Power-down reference buffer This bit determines the power-down reference buffer state. 0 = Power-down internal reference buffer (default) 1 = Enable internal reference buffer Bit 6 Must always be set to '1'. Default is '1' at power-up. Bit 5 VREF_4V: Reference voltage This bit determines the reference voltage, VREFP. 0 = VREFP is set to 2.4V (default) 1 = VREFP is set to 4V (use only with a 5V analog supply) Bit 4 RLD_MEAS: RLD measurement This bit enables RLD measurement. The RLD signal may be measured with any channel. 0 = Open (default) 1 = RLD_IN signal is routed to the channel that has the MUX_Setting 010 (VREF) Bit 3 RLDREF_INT: RLDREF signal This bit determines the RLDREF signal source. 0 = RLDREF signal fed externally (default) 1 = RLDREF signal (AVDD – AVSS)/2 generated internally Bit 2 PD_RLD: RLD buffer power This bit determines the RLD buffer power state. 0 = RLD buffer is powered down (default) 1 = RLD buffer is enabled Bit 1 RLD_LOFF_SENS: RLD sense selection This bit enables the RLD sense function. 0 = RLD sense is disabled (default) 1 = RLD sense is enabled Bit 0 RLD_STAT: RLD lead off status This bit determines the RLD status. 0 = RLD is connected (default) 1 = RLD is not connected Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 43 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com LOFF: Lead-Off Control Register Address = 04h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 The Lead-Off Control Register configures the Lead-Off detection operation. Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold These bits determine the lead-off comparator threshold level setting. See the Lead-Off Detection subsection of the ECG-Specific Functions section for a detailed description. Comparator positive side 000 = 95% (default) 001 = 92.5% 010 = 90% 011 = 87.5% 100 = 85% 101 = 80% 110 = 75% 111 = 70% Comparator negative side 000 = 5% (default) 001 = 7.5% 010 = 10% 011 = 12.5% 100 = 15% 101 = 20% 110 = 25% 111 = 30% Bit 4 VLEAD_OFF_EN: Lead-off detection mode This bit determines the lead-off detection mode. 0 = Current source mode lead-off (default) 1 = Pull-up/pull-down resistor mode lead-off Bits[3:2] ILEAD_OFF[1:0]: Lead-off current magnitude These bits determine the magnitude of current for the current lead-off mode. 00 = 4nA (default) 01 = 8nA 10 = 12nA 11 = 16nA Bits[1:0] FLEAD_OFF[1:0]: Lead-off frequency These bits determine the frequency of lead-off detect for each channel. 00 = When any bits of the LOFF_SENSP and LOFF_SENSN registers are turned on, make sure FLEAD_OFF[1:0] is either set to '01' or '11' (default) 01 = AC lead-off detection at fDR/4 10 = Do not use 11 = DC lead-off detection turned on 44 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CHnSET: Individual Channel Settings (n = 1:8) Address = 05h to 0Ch BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD GAIN2 GAIN1 GAIN0 0 MUXn2 MUXn1 MUXn0 The CH[1:8]SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels. Bit 7 PD: Power-down This bit determines the channel power mode for the corresponding channel. 0 = Normal operation (default) 1 = Channel power-down. When powering down a channel, it is recommended that the channel be set to input short by setting the appropriate MUXn[2:0] = 001 of the CHnSET register. Bits[6:4] GAIN[2:0]: PGA gain These bits determine the PGA gain setting. 000 = 6 (default) 001 = 1 010 = 2 011 = 3 100 = 4 101 = 8 110 = 12 Bit 3 Always write '0' Bits[2:0] MUXn[2:0]: Channel input These bits determine the channel input selection. 000 = Normal electrode input (default) 001 = Input shorted (for offset or noise measurements) 010 = Used in conjunction with RLD_MEAS bit for RLD measurements. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for more details. 011 = MVDD for supply measurement 100 = Temperature sensor 101 = Test signal 110 = RLD_DRP (positive electrode is the driver) 111 = RLD_DRN (negative electrode is the driver) RLD_SENSP Address = 0Dh BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RLD8P RLD7P RLD6P RLD5P RLD4P RLD3P RLD2P RLD1P This register controls the selection of the positive signals from each channel for right leg drive derivation. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details. Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194/6. RLD_SENSN Address = 0Eh BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RLD8N RLD7N RLD6N RLD5N RLD4N RLD3N RLD2N RLD1N This register controls the selection of the negative signals from each channel for right leg drive derivation. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details. Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and ADS1196. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 45 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com LOFF_SENSP Address = 0Fh BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STATP register bits are only valid if the corresponding LOFF_SENSP bits are set to '1'. Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and ADS1196. LOFF_SENSN Address = 10h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N This register selects the negative side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STATN register bits are only valid if the corresponding LOFF_SENSN bits are set to '1'. Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and ADS1196. LOFF_FLIP Address = 11h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1 This register controls the direction of the current used for lead-off derivation. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. LOFF_STATP (Read-Only Register) Address = 12h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF This register stores the status of whether the positive electrode on each channel is on or off. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. '0' is lead-on (default) and '1' is lead-off. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits are not set to '1'. When the LOFF_SENSEP bits are '0', the LOFF_STATP bits should be ignored. LOFF_STATN (Read-Only Register) Address = 13h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STATN values if the corresponding LOFF_SENSN bits are not set to '1'. '0' is lead-on (default) and '1' is lead-off. When the LOFF_SENSEN bits are '0', the LOFF_STATP bits should be ignored. 46 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com GPIO: General-Purpose I/O Register Address = 14h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 The General-Purpose I/O Register controls the action of the three GPIO pins. Bits [7:4] GPIOD[4:1]: GPIO data These bits are used to read and write data to the GPIO ports. When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. GPIO is not available in certain respiration modes. Bits [3:0] GPIOC[4:1]: GPIO control (corresponding GPIOD) These bits determine if the corresponding GPIOD pin is an input or output. 0 = Output 1 = Input (default) PACE: PACE Detect Register Address = 15h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE This register provides the PACE controls that configure the channel signal used to feed the external PACE detect circuitry. See the Pace Detect subsection of the ECG-Specific Functions section for details. Bits [7:5] Must always be set to '0' Bits [4:3] PACEE[1:0]: PACE even channels These bits control the selection of the even number channels available on TEST_PACE_OUT1. Note that only one channel may be selected at any time. 00 = Channel 2 (default) 01 = Channel 4 10 = Channel 6, ADS1196/8 only 11 = Channel 8, ADS1198 only Bits [2:1] PACEO[1:0]: PACE odd channels These bits control the selection of the odd number channels available on TEST_PACE_OUT2. Note that only one channel may be selected at any time. 00 = Channel 1 (default) 01 = Channel 3 10 = Channel 5, ADS1196/8 only (default) 11 = Channel 7, ADS1198 only Bit [0] PD_PACE: PACE detect buffer This bit is used to enable/disable the PACE detect buffer. 0 = PACE detect buffer turned off (default) 1 = PACE detect buffer turned on Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 47 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RESERVED Address = 16h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 0 0 Bits [7:0] Must always be set to '0' CONFIG4: Configuration Register 4 Address = 17h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 SINGLE_SHOT WCT_TO_RLD PD_LOFF_COMP 0 Bits [7:4] Must always be set to '0' Bit [3] SINGLE_SHOT: Single-shot conversion This bit sets the conversion mode. 0 = Continuous conversion mode (default) 1 = Single-shot mode Bit [2] WCT_TO_RLD: Connects the WCT to the RLD 0 = WCT to RLD connection off (default) 1 = WCT to RLD connection on Bit [1] PD_LOFF_COMP: Lead-off comparator power-down This bit powers down the lead-off comparators. 0 = Lead-off comparators disabled (default) 1 = Lead-off comparators enabled Bit [0] 48 Must always be set to '0' Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WCT1: Wilson Center Terminal and Augmented Lead Control Register Address = 18h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 aVF_CH6 aVL_CH5 aVR_CH7 aVR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0 The WCT1 control register configures the device WCT circuit channel selection and the augmented leads. Bit [7] aVF_CH6: Enable (WCTA + WCTB)/2 to the negative input of channel 6 (ADS1196/8 only) 0 = Disabled (default) 1 = Enabled Bit [6] aVL_CH5: Enable (WCTA + WCTC)/2 to the negative input of channel 5 (ADS1196/8 only) 0 = Disabled (default) 1 = Enabled Bit [5] aVR_CH7: Enable (WCTB + WCTC)/2 to the negative input of channel 7 (ADS1198 only) 0 = Disabled (default) 1 = Enabled Bit [4] aVR_CH4: Enable (WCTB + WCTC)/2 to the negative input of channel 4 0 = Disabled (default) 1 = Enabled Bit [3] PD_WCTA: Power-down WCTA 0 = Powered down (default) 1 = Powered on Bits [2:0] WCTA[2:0]: WCT amplifier A channel selection; typically connected to RA electrode. These bits select one of the eight electrode inputs of channels 1 to 4. 000 = Channel 1 001 = Channel 1 010 = Channel 2 011 = Channel 2 100 = Channel 3 101 = Channel 3 110 = Channel 4 111 = Channel 4 positive input connected to WCTA amplifier (default) negative input connected to WCTA amplifier positive input connected to WCTA amplifier negative input connected to WCTA amplifier Positive input connected to WCTA amplifier negative input connected to WCTA amplifier positive input connected to WCTA amplifier negative input connected to WCTA amplifier Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 49 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WCT2: Wilson Center Terminal Control Register Address = 19h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0 The WCT2 configuration register configures the device WCT circuit channel selection. Bit [7] PD_WCTC: Power-down WCTC 0 = Powered down (default) 1 = Powered on Bit [6] PD_WCTB: Power-down WCTB 0 = Powered down (default) 1 = Powered on Bits [5:3] WCTB[2:0]: WCT amplifier B channel selection; typically connected to LA electrode. These bits select one of the eight electrode inputs of channels 1 to 4. 000 = Channel 1 001 = Channel 1 010 = Channel 2 011 = Channel 2 100 = Channel 3 101 = Channel 3 110 = Channel 4 111 = Channel 4 Bits [2:0] positive input connected to WCTB amplifier negative input connected to WCTB amplifier positive input connected to WCTB amplifier (default) negative input connected to WCTB amplifier positive input connected to WCTB amplifier negative input connected to WCTB amplifier positive input connected to WCTB amplifier negative input connected to WCTB amplifier WCTC[2:0]: WCT amplifier C channel selection; typically connected to LL electrode. These bits select one of the eight electrode inputs of channels 1 to 4. 000 = Channel 1 001 = Channel 1 010 = Channel 2 011 = Channel 2 100 = Channel 3 101 = Channel 3 110 = Channel 4 111 = Channel 4 50 positive input connected to WCTC amplifier negative input connected to WCTC amplifier positive input connected to WCTC amplifier negative input connected to WCTC amplifier positive input connected to WCTC amplifier (default) negative input connected to WCTC amplifier positive input connected to WCTC amplifier negative input connected to WCTC amplifier Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ECG-SPECIFIC FUNCTIONS INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL) The input multiplexer has ECG-specific functions for the right-leg drive signal. The RLD signal is available at the RLDOUT pin once the appropriate channels are selected for the RLD derivation, feedback elements are installed external to the chip, and the loop is closed. This signal can be fed after filtering or fed directly into the RLDIN pin as shown in Figure 42. This RLDIN signal can be multiplexed into any one of the input electrodes by setting the MUX bits of the appropriate channel set registers to 110 for P-side or 111 for N-side. Figure 42 shows the RLD signal generated from channels 1, 2, and 3 and routed to the N-side of channel 8. This feature can be used to dynamically change the electrode that is used as the reference signal to drive the patient body. Note that the corresponding channel cannot be used and can be powered down. RLD_SENSP[0] = 1 IN1P EMI Filter PGA1 RLD_SENSN[0] = 1 MUX1[2:0] = 000 IN1N RLD_SENSP[1] = 1 IN2P EMI Filter PGA2 RLD_SENSN[1] = 1 MUX2[2:0] = 000 IN2N RLD_SENSP[2] = 1 IN3P EMI Filter PGA3 RLD_SENSN[2] = 1 MUX3[2:0] = 000 ¼ ¼ ¼ IN3N RLD_SENSP[7] = 0 IN8P EMI Filter PGA8 MUX8[2:0] = 111 RLD_SENSN[7] = 0 IN8N MUX Device RLDIN RLDREF_INT RLDREF_INT (AVDD + AVSS)/2 RLDREF RLD_AMP RLDOUT RLDINV (1) Filter or Feedthrough 1 MW (1) 1.5 nF (1) Typical values for example only. Figure 42. Example of RLDOUT Signal Configured to be Routed to IN8N Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 51 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com INPUT MULTIPLEXER (MEASURING THE RIGHT LEG DRIVE SIGNAL) Also, the RLDOUT signal can be routed to a channel (that is not used for the calculation of RLD) for measurement. Figure 43 shows the register settings to route the RLDIN signal to channel 8. The measurement is done with respect to the voltage on the RLDREF pin. If RLDREF is chosen to be internal, it would be at (AVDD + AVSS)/2. This feature is useful for debugging purposes during product development. RLD_SENSP[0] = 1 IN1P EMI Filter PGA1 RLD_SENSN[0] = 1 MUX1[2:0] = 000 IN1N RLD_SENSP[1] = 1 IN2P EMI Filter PGA2 RLD_SENSN[1] = 1 MUX2[2:0] = 000 IN2N RLD_SENSP[2] = 1 IN3P EMI Filter PGA3 RLD_SENSN[2] = 1 MUX3[2:0] = 000 ¼ ¼ ¼ IN3N RLD_SENSP[7] = 0 IN8P EMI Filter PGA8 MUX8[2:0] = 010 RLD_SENSN[7] = 0 IN8N MUX RLDREF_INT (AVDD + AVSS)/2 RLDREF_INT MUX8[2:0] = 010 AND RLD_MEAS = 1 RLD_AMP Device RLD_IN RLD_REF RLD_OUT RLD_INV (1) 1 MW Filter or Feedthrough (1) 1.5 nF (1) Typical values for example only. Figure 43. RLDOUT Signal Configured to be Read Back by Channel 8 52 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WILSON CENTER TERMINAL (WCT) AND CHEST LEADS In the standard 12-lead ECG, WCT voltage is defined as the average of Right Arm (RA), Left Arm (LA), and Left Leg (LL) electrodes. This voltage is used as the reference voltage for the measurement of the chest leads. The ADS1194/6/8 has three integrated low-noise amplifiers that generate the WCT voltage. Figure 44 shows the block diagram of the implementation. IN1P IN1N IN2P IN2N IN3P IN3N IN4P IN4N To Channel PGAs 8:1 MUX 8:1 MUX 30kW Wctb WCT2[2:0] WCT2[5:3] WCT1[2:0] Wcta 8:1 MUX Wctc 30kW 30kW ADS1194/6/8 WCT 80pF AVSS Figure 44. WCT Voltage The devices provide flexibility to choose any one of the eight signals (IN1P to IN4N) to be routed to each of the amplifiers to generate the average. Having this flexibility allows the RA, LA, and LL electrodes to be connected to any input of the first four channels depending on the lead configuration. Each of the three amplifiers in the WCT circuitry can be powered down individually with register settings. By powering up two amplifiers, the average of any two electrodes can be generated at the WCT pin. Powering up one amplifier provides the buffered electrode voltage at the WCT pin. Note that the WCT amplifiers have limited drive strength and thus should be buffered if used to drive a low-impedance load. See Table 3 for performance when using any 1, 2, or 3 of the WCT buffers. As can be seen in Table 3, the overall noise reduces when more than one WCT amplifier is powered up. This noise reduction is due to the fact that noise is averaged by the passive summing network at the output of the amplifiers. Powering down individual buffers gives negligible power savings because a significant portion of the circuitry is shared between the three amplifiers. The bandwidth of the WCT node is limited by the RC network. The internal summing network consists of three 30kΩ resistors and a 80pF capacitor. It is recommended that an external 100pF capacitor be added for optimal performance. The effective bandwidth depends on the number of amplifiers that are powered up, as shown in Table 3. The WCT node should be only be used to drive very high input impedances (typically greater than 500MΩ). Typical application would be to connect this WCT signal to the negative inputs of a ADS1194/6/8 to be used as a reference signal for the chest leads. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 53 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com As mentioned previously in this section, all three WCT amplifiers can be connected to one of the eight analog input pins. The inputs of the amplifiers are chopped and the chopping frequency is at 8kHz. The chop frequency shows itself at the output of the WCT amplifiers as a small square-wave riding on dc. The amplitude of the square-wave is the offset of the amplifier and is typically 5mVPP. This artifact as a result of the chopping function is out-of-band and thus does not interfere with ECG-related measurements. Note that if the output of a channel connected to the WCT (for example, VLEAD channels) is connected to one of the pace amplifiers for external pace detection, the artifact of chopping appears at the Pace amplifier output. Augmented Leads In the typical implementation of the 12-lead ECG with eight channels, the augmented leads are calculated digitally. In certain applications, it may be required that all leads be derived in analog rather than digital. The ADS1198 provides the option to generate the augmented leads by routing appropriate averages to channels 5 to 7. The same three amplifiers that are used to generate the WCT signal are used to generate the Goldberger terminal signals as well. Figure 45 shows an example of generating the augmented leads in analog domain. Note that in this implementation it takes more than eight channels to generate the standard 12 leads. Also, this feature is not available in the ADS1196 and ADS1194. IN1P IN1N IN2P IN2N IN3P IN3N IN4P IN4N To Channel PGAs 8:1 MUX Wctb 8:1 MUX WCT2[2:0] WCT2[5:3] WCT1[2:0] Wcta 8:1 MUX Wctc avF_ch4 ADS1198 avF_ch6 avF_ch5 avF_ch7 IN5P IN5N IN6P IN6N IN7P IN7N To Channel PGAs Figure 45. Analog Domain Augmented Leads Right Leg Drive with the WCT Point In certain applications, the out-of-phase version of the WCT is used as the right leg drive reference. The ADS1198 provides the option to have a buffered version of the WCT terminal at the RLD_OUT pin. This signal can be inverted in phase using an external amplifier and used as the right leg drive. Refer to the Right Leg Drive (RLD DC Bias Circuit) section for more details. 54 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com LEAD-OFF DETECTION Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these electrode connections to verify a suitable connection is present. The ADS1194/6/8 lead-off detection functional block provides significant flexibility to the user to choose from various lead-off detection strategies. Though called lead-off detection, this is in fact an electrode-off detection. The basic principle is to inject an excitation signal and measure the response to find out if the electrode is off. As shown in the lead-off detection functional block diagram in Figure 46, this circuit provides two different methods of determining the state of the patient electrode. The methods differ in the frequency content of the excitation signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENSP and LOFF_SENSN registers. Also, the internal excitation circuitry can be disabled and just the sensing circuitry can be enabled. AVDD AVSS FLEAD_OFF[0:1] Vx FLEAD_OFF[1:0] 10pF 10pF 7MW 7MW (AVDD + AVSS)/2 3.3MW Patient Skin, Electrode Contact Model Patient Protection Resistor 12pF 3.3MW 12pF 3.3MW 3.3MW 3.3MW Antialiasing Filter < 512kHz 3.3MW 47nF 51kW LOFF_STATP 100kW LOFF_SENSP AND VLEAD_OFF_EN LOFF_SENSN AND VLEAD_OFF_EN VINP 51kW 100kW EMI Filter VINN LOFF_SENSP AND VLEAD_OFF_EN 47nF 47nF 51kW AVDD PGA LOFF_SENSN AND VLEAD_OFF_EN AVSS To ADC LOFF_STATN 4-Bit DAC COMP_TH[2:0] 100kW RLD OUT Figure 46. Lead-Off Detection Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 55 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com DC Lead-Off In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either a pull-up/pull-down resistor or a current source/sink, shown in Figure 47. The selection is done by setting the VLEAD_OFF_EN bit in the LOFF register. One side of the channel is pulled to supply and the other side is pulled to ground. The pull-up resistor and pull-down resistor can be swapped (as shown in Figure 48) by setting the bits in the LOFF_FLIP register. In case of current source/sink, the magnitude of the current can be set by using the ILEAD_OFF[1:0] bits in the LOFF register. The current source/sink gives larger input impedance compared to the 10MΩ pull-up/pull-down resistor. AVDD AVDD AVDD ADS119x AVDD ADS119x ADS119x ADS119x 10MW 10MW INP INP INP PGA INN INP PGA PGA INN INN b) Current Source Figure 47. DC Lead-Off Excitation Options PGA INN 10MW 10MW a) Pull-Up/Pull-Down Resistors 10MW a) LOFF_FLIP = 0 10MW a) LOFF_FLIP = 1 Figure 48. LOFF_FLIP Usage Sensing of the response can be done either by looking at the digital output code from the device or by monitoring the input voltages with an on-chip comparator. If either of the electrodes is off, the pull-up resistors and/or the pull-down resistors saturate the channel. By looking at the output code it can be determined that either the P-side or the N-side is off. To pinpoint which one is off, the comparators must be used. The input voltage is also monitored using a comparator and a 4-bit DAC whose levels are set by the COMP_TH[2:0] bits in the LOFF register. The output of the comparators are stored in the LOFF_STATP and LOFF_STATN registers. These two registers are available as a part of the output data stream. (See the Data Output (DOUT) subsection of the SPI Interface section.) If dc lead-off is not used, the lead-off comparators can be powered down by setting the PD_LOFF_COMP bit in the CONFIG4 register. An example procedure to turn on dc lead-off is given in the Lead-Off subsection of the Quick-Start Guide section. 56 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com AC Lead-Off In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively providing pull-up resistors and pull-down resistors at the input with a fixed frequency. The ac signal is passed through an anti-aliasing filter to avoid aliasing. The frequency can be chosen by the FLEAD_OFF[1:0] bits in the LOFF register. The excitation frequency is a function of the output data rate and can be chosen to be either fDR/2 or fDR/4. This out-of-band excitation signal is passed through the channel and measured at the output. Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of the excitation signal at the output spectrum, the lead-off status can be calculated. Therefore, the ac lead-off detection can be accomplished simultaneously with the ECG signal acquisition. RLD LEAD-OFF The ADS1194/6/8 provide two modes for determining whether the RLD is correctly connected: • RLD lead-off detection during normal operation • RLD lead-off detection during power-up The following sections provide details of the two modes of operation. RLD Lead-Off Detection During Normal Operation During normal operation, the ADS1194/6/8 RLD lead-off at power-up function cannot be used because it is necessary to power off the RLD amplifier. RLD Lead Off Detection At Power-Up This feature is included in the ADS1194/6/8 for use in determining whether the right leg electrode is suitably connected. At power-up, the ADS1194/6/8 provide two measurement procedures to determine the RLD electrode connection status using either a current or a voltage pull-down resistor, as shown in Figure 49. The reference level of the comparator is set to determine the acceptable RLD impedance threshold. Patient Skin, Electrode Contact Model Patient Protection Resistor To ADC input (through VREF connection to any of the channels). 47nF 51kW RLD_STAT 100kW RLD_SENS AND RLD_SENS AND VLEAD_OFF_EN VLEAD_OFF_EN ILGND_OFF[1:0] AVSS AVSS Figure 49. RLD Lead-Off Detection at Power-Up When the RLD amplifier is powered on, the current source has no function. Only the comparator can be used to sense the voltage at the output of the RLD amplifier. The comparator thresholds are set by the same LOFF[7:5] bits used to set the thresholds for other negative inputs. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 57 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RIGHT LEG DRIVE (RLD DC BIAS CIRCUIT) The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow range, depending on the loop gain. Stabilizing the entire loop is specific to the individual user system based on the various poles in the loop. The ADS1194/6/8 integrates the muxes to select the channel and an operational amplifier. All the amplifier terminals are available at the pins, allowing the user to choose the components for the feedback loop. The circuit in Figure 50 shows the overall functional connectivity for the RLD bias circuit. The reference voltage for the right leg drive can be chosen to be internally generated (AVDD + AVSS)/2 or it can be provided externally with a resistive divider. The selection of an internal versus external reference voltage for the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the COFIG3 register. If the RLD function is not used, the amplifier can be powered down using the PD_RLD bit (see the CONFIG3: Configuration Register 3 subsection of the Register Map section for details). This bit is also used in daisy-chain mode to power-down all but one of the RLD amplifiers. The functionality of the RLDIN pin is explained in the Input Multiplexer section. An example procedure to use the RLD amplifier is shown in the Right Leg Drive subsection of the Quick-Start Guide section. 58 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com From MUX1P RLD1P 220kW PGA1P 50kW 220kW RLD2P PGA2P 20kW 50kW From MUX2P 50kW 20kW 220kW PGA1N From MUX1N RLD1N From MUX3P RLD3P 50kW 220kW PGA2N From MUX2N RLD2N 220kW PGA3P 50kW 220kW RLD4P PGA4P 20kW 50kW From MUX4P 50kW 20kW 220kW PGA3N From MUX3N RLD3N From MUX5P RLD5P 50kW 220kW PGA4N RLD4N From MUX4N RLD6P From MUX6P 220kW PGA5P 50kW 220kW PGA6P 20kW 50kW 50kW 20kW 220kW PGA5N From MUX5N RLD5N From MUX7P RLD7P 50kW 220kW PGA6N From MUX6N RLD6N 220kW PGA7P 50kW 220kW RLD8P PGA8P 20kW 50kW From MUX8P 50kW 20kW 220kW PGA7N From MUX7N RLD7N PGA8N RLDINV (1) CEXT 1.5nF 50kW 220kW From MUX8N RLD8N (1) REXT 1MW RLD Amp RLDOUT (AVDD + AVSS)/2 RLDREF_INT RLDREF RLDREF_INT (1) Typical values. (2) When CONFIG3.RLDREF_INT = 0, the RLDREF_INT switch is closed and the RLDREF_INT switch is open. When CONFIG3.RLDREF_INT = 1, the RLDREF_INT switch is open and the RLDREF_INT switch is closed. Figure 50. RLD Channel Selection(2) Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 59 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WCT as RLD In certain applications, the right leg drive is derived as the average of RA, LA, and LL. This level is the same as the WCT voltage. The WCT amplifier has limited drive strength and thus should be used only to drive very high impedances directly. As shown in Figure 51, the ADS1194/6/8 provide an option to internally buffer the WCT signal by setting the WCT_TO_RLD bit in the CONFIG4 register. The RLD_OUT and RLD_INV pins should be shorted external to the device. Note that before the RLD_OUT signal is connected to the RLD electrode, an external amplifier should be used to invert the phase of the signal for negative feedback. ADS119x RLD_INV RLD_OUT RLD Amp RLD (AVDD + AVSS)/2 RLDREF_INT RLD_REF From WCT Amplifiers WCT_TO_RLD RLD_REF RLDREF_INT WCT Figure 51. Using the WCT as the Right Leg Drive RLD Configuration with Multiple Devices Figure 52 shows multiple devices connected to an RLD. VA1-8 VA1-8 RLDIN RLD REF RLD OUT RLDINV Device 1 Power-Down RLDIN RLD REF VA1-8 VA1-8 RLD OUT RLDINV To Input MUX Device 2 To Input MUX To Input MUX Device N Power-Down RLDIN RLD REF VA1-8 VA1-8 RLD OUT RLDINV Figure 52. RLD Connection for Multiple Devices 60 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com PACE DETECT The ADS1194/6/8 provide flexibility for pace detection with external hardware by bringing out the output of the PGA at two pins: TESTP_PACE_OUT1 and TESTN_PACE_OUT2. External Hardware Approach The ADS1194/6/8 provide the option of bringing out the output of the PGA; see Figure 53. External hardware circuitry can be used to detect the presence of the pulse. The output of the pace detection logic can then be fed into the device through one of the GPIO pins. The GPIO data are transmitted through the SPI port. Two of the eight channels can be selected using register bits in the PACE register, one from the odd-numbered channels and the other from the even-numbered channels. During the differential to single-ended conversion, there is an attenuation of 0.4. Therefore, the total gain in the pace path is equal to (0.4 × PGA_GAIN). The pace out signals are multiplexed with the TESTP and TESTN signals through the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins respectively. The channel selection is done by setting bits[4:1] of the PACE register. If the pace circuitry is not used, the pace amplifiers can be turned off using the PD_PACE bit in the PACE register. Note that if the output of a channel connected to the WCT amplifier (for example, the VLEAD channels) is connected to one of the pace amplifiers for external pace detection, the artifact of chopping appears at the pace amplifier output. Refer to the Wilson Center Terminal (WCT) and Chest Leads section for more detials. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 61 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com PACE[2:1] PACE[4:3] From MUX1P 00 PGA1P 50kW 00 PGA2P 20kW From MUX2P 50kW 50kW 20kW PGA1N From MUX1N 00 From MUX3P 01 50kW PGA2N 00 From MUX2N 01 From MUX4P PGA3P 50kW PGA4P 20kW 50kW 50kW 20kW PGA3N From MUX3N 01 From MUX5P 10 50kW PGA4N From MUX4N 01 PGA5P 50kW 10 PGA6P 20kW From MUX6P 50kW 50kW 20kW PGA5N From MUX5N 10 From MUX7P 11 50kW PGA6N From MUX6N 10 PGA7P 50kW 11 PGA8P 20kW From MUX8P 50kW 50kW 20kW PGA7N From MUX7N 11 50kW (AVDD - AVSS) PGA8N 2 From MUX8N 11 200kW PDB_PACE TESTN_PACE_OUT2 PACE Amp 500kW GPIO1 (1) PACE_IN (GPIO1) 200kW (AVDD - AVSS) 2 200kW PDB_PACE TESTP_PACE_OUT1 PACE Amp 500kW 200kW (1) GPIO1 can be used as the PACE_IN signal. Figure 53. Hardware Pace Detection Option 62 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com QUICK-START GUIDE PCB LAYOUT Power Supplies and Grounding The ADS1194/6/8 have three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, it is recommended that AVDD1 and AVSS1 be star-connected to AVDD and AVSS. It is important to eliminate noise from AVDD and AVDD1 that is non-synchronous with the ADS1194/6/8 operation. Each supply of the ADS1194/6/8 should be bypassed with 1μF and a 0.1μF solid ceramic capacitors. It is recommended that placement of the digital circuits (DSP, microcontrollers, FPGAs, etc.) in the system is done such that the return currents on those devices do not cross the analog return path of the ADS1194/6/8. The ADS1194/6/8 can be powered from unipolar or bipolar supplies. The capacitors used for decoupling can be of the surface-mount, low-cost, low-profile, multi-layer ceramic type. In most cases, the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected to high or low frequency vibration, it is recommend to install a non-ferroelectric capacitor such as a tantalum or class 1 capacitor (for example, C0G or NPO). EIA class 2 and class 3 dielectrics (such as X7R, X5R, X8R, etc.) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming from the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation. Connecting the Device to Unipolar (+3V/+1.8V) Supplies Figure 54 illustrates the ADS1194/6/8 connected to a unipolar supply. In this example, analog supply (AVDD) is referenced to analog ground (AVSS) and digital supplies (DVDD) are referenced to digital ground (DGND). +3V +1.8V 0.1mF 1mF 1mF 0.1mF AVDD AVDD1 DVDD VREFP VREFN 0.1mF 10mF VCAP1 ADS1198 VCAP2 VCAP3 VCAP4 WCT AVSS1 AVSS DGND RESV1 100pF 1mF 1mF 0.1mF 1mF 22mF NOTE: Place the capacitors for supply, reference, WCT, and VCAP1 to VCAP4 as close to the package as possible. Figure 54. Single-Supply Operation Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 63 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Connecting the Device to Bipolar (±1.5V/1.8V) Supplies Figure 55 illustrates the ADS1194/6/8 connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supplies (DVDD and DVDD) are referenced to the device digital ground return (DVDD). +1.5V +1.8V 1mF 0.1mF 0.1mF 1mF AVDD AVDD1 DVDD VREFP 10mF 0.1mF VREFN -1.5V VCAP1 ADS1198 VCAP2 VCAP3 VCAP4 WCT AVSS1 AVSS DGND RESV1 100pF 1mF 1mF 1mF 0.1mF 1mF 22mF 0.1mF -1.5V NOTE: Place the capacitors for supply, reference, WCT, and VCAP1 to VCAP4 as close to the package as possible. Figure 55. Bipolar Supply Operation Shielding Analog Signal Paths As with any precision circuit, careful printed circuit board (PCB) layout ensures the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS. These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the input bias current of the ADS1194/6/8 if shielding is not implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB. Analog Input Structure The analog input of the ADS119x is shown in Figure 56. AVDD INxP, INxN 5kW 10pF AVSS Figure 56. Analog Input Protection Circuit 64 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 57. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse. After releasing RESET, the configuration register must be programmed, see the CONFIG1: Configuration Register 1 subsection of the Register Map section for details. The power-up sequence timing is shown in Table 11. tPOR Power Supplies tRST RESET 18 tCLK Start Using the Device Figure 57. Power-Up Timing Diagram Table 11. Power-Up Sequence Timing SYMBOL DESCRIPTION MIN tPOR Wait after power-up until reset 216 TYP MAX UNIT tCLK tRST Reset low width 2 tCLK SETTING THE DEVICE FOR BASIC DATA CAPTURE The following section outlines the procedure to configure the device in a basic state and capture data. This procedure is intended to put the device in a data sheet condition to check if the device is working properly in the user's system. It is recommended that this procedure be followed initially to get familiar with the device settings. Once this procedure has been verified, the device can be configured as needed. For details on the timings for commands refer to the appropriate sections in the data sheet. Also, some sample programming codes are added for the ECG-specific functions. Figure 58 illustrates a flowchart outlining the initial flow at power-up. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 65 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Analog/Digital Power-Up Set CLKSEL Pin = 0 and Provide External Clock fCLK = 2.048MHz Yes // Follow Power-Up Sequencing External Clock No Set CLKSEL Pin = 1 and Wait for Oscillator to Wake Up Set PWDN = 1 Set RESET = 1 Wait for 1s for Power-On Reset Issue Reset Pulse, Wait for 18 tCLKs Send SDATAC Command Set PDB_REFBUF = 1 and Wait for Internal Reference to Settle // If START is Tied High, After This Step // DRDY Toggles at fCLK/16384 // Delay for Power-On Reset and Oscillator Start-Up // Activate DUT // CS can be Either Tied Permanently Low // Or Selectively Pulled Low Before Sending // Commands or Reading/Sending Data from/to Device // Device Wakes Up in RDATAC Mode, so Send // SDATAC Command so Registers can be Written SDATAC No External Reference // If Using Internal Reference, Send This Command ¾WREG CONFIG3 0x80 Yes Write Certain Registers, Including Input Short // Set Device to DR = fMOD/1024 WREG CONFIG1 0x06 WREG CONFIG2 0x00 // Set All Channels to Input Short WREG CHnSET 0x01 Set START = 1 // Activate Conversion // After This Point DRDY Should Toggle at // fCLK/16384 RDATAC // Put the Device Back in RDATAC Mode RDATAC Capture Data and Check Noise // Look for DRDY and Issue 24 + n ´ 16 SCLKs Set Test Signals // Activate a (1mV ´ VREF/2.4) Square-Wave Test Signal // On All Channels SDATAC WREG CONFIG2 0x10 WREG CHnSET 0x05 RDATAC Capture Data and Test Signal // Look for DRDY and Issue 24 + n ´ 16 SCLKs Figure 58. Initial Flow at Power-Up 66 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Lead-Off Sample code to set dc lead-off with pull-up/pull-down resistors on all channels WREG LOFF 0x13 // Comparator threshold at 95% and 5%, pull-up/pull-down resistor // DC lead-off WREG CONFIG4 0x02 // Turn-on dc lead-off comparators WREG LOFF_SENSP 0xFF // Turn on the P-side of all channels for lead-off sensing WREG LOFF_SENSN 0xFF // Turn on the N-side of all channels for lead-off sensing Observe the status bits of the output data stream to monitor lead-off status. Right Leg Drive Sample code to choose RLD as an average of the first three channels. WREG RLD_SENSP 0x07 // Select channel 1—3 P-side for RLD sensing WREG RLD_SENSN 0x07 // Select channel 1—3 N-side for RLD sensing WREG CONFIG3 b’x1xx 1100 // Turn on RLD amplifier, set internal RLDREF voltage Sample code to route the RLD_OUT signal through channel 4 N-side and measure RLD with channel 5. Make sure the external side to the chip RLDOUT is connected to RLDIN. WREG CONFIG3 b’xxx1 1100 // Turn on RLD amplifier, set internal RLDREF voltage, set RLD measurement bit WREG CH4SET b’1xxx 0111 // Route RLDIN to channel 4 N-side WREG CH5SET b’1xxx 0010 // Route RLDIN to be measured at channel 5 w.r.t RLDREF Pace Detection Sample code to select channel 5 and 6 outputs for PACE WREG PACE b’0001 0101 // Power-up pace amplifier and select channel 5 and 6 for pace out Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 67 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2011) to Revision C Page • Added eighth Features bullet ................................................................................................................................................ 1 • Changed first paragraph of Description section ................................................................................................................... 1 • Deleted duplicate Digital input voltage and Digital output voltage rows from Absolute Maximum Ratings table ................. 2 • Changed AC Channel Performance, Common-mode rejection ratio and Power-supply rejection ratio parameter names in Electrical Characteristics table .............................................................................................................................. 3 • Changed description of Analog Input section ..................................................................................................................... 19 • Updated Figure 20 .............................................................................................................................................................. 21 • Changed description of Data Ready (DRDY) section ......................................................................................................... 28 • Changed description of START pin in START section ....................................................................................................... 29 • Changed conversion desacription in Continuous Mode section ......................................................................................... 30 • Changed START pin description in Single-Shot Mode section .......................................................................................... 31 • Changed default setting in bit description table for CONFIG1: Configuration Register 1 section ...................................... 41 • Changed setting description of bit 7 in CHnSET: Individual Channel Settings section ...................................................... 45 • Updated Figure 42 .............................................................................................................................................................. 51 • Updated Figure 43 .............................................................................................................................................................. 52 68 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Changes from Revision A (September 2010) to Revision B Page • Updated Family and Ordering Information table ................................................................................................................... 2 • Added Digital Filter section to Electrical Characteristics table .............................................................................................. 3 • Updated test conditions of Internal Reference, Output voltage parameter in Electrical Characteristics table ..................... 4 • Updated format of Power Dissipation (Analog Supply = 3V) section in the Electrical Characteristics table ........................ 6 • Changed 3V Power Dissipation, Quiescent channel power test conditions in the Electrical Characteristics table .............. 6 • Updated format of Power Dissipation (Analog Supply = 5V) section in the Electrical Characteristics table ........................ 6 • Changed 5V Power Dissipation, Quiescent channel power test conditions in the Electrical Characteristics table .............. 6 • Changed values of -3dB Bandwidth column of Table 1 ....................................................................................................... 7 • Changed values of -3dB Bandwidth column of Table 2 ....................................................................................................... 7 • Changed description of VCAP3 in BGA Pin Assignments table ........................................................................................... 9 • Changed CLK row in BGA Pin Assignments table ............................................................................................................... 9 • Changed CLK row of PAG Pin Assignments table ............................................................................................................. 11 • Changed description of VCAP3 in PAG Pin Assignments table ......................................................................................... 11 • Updated and moved Figure 14 ........................................................................................................................................... 16 • Changed description of CHnSET setting in Device Noise Measurements section ............................................................ 18 • Changed description of (MVDDP – MVDDN) for channels 1, 2, 5, 6, 7, and 8 in Supply Measurements (MVDDP, MVDDN) section ................................................................................................................................................................. 19 • Updated Equation 4 ............................................................................................................................................................ 22 • Updated Equation 5 ............................................................................................................................................................ 22 • Updated footnote 1 of Figure 26 ......................................................................................................................................... 24 • Added footnote 1 to Table 6 ............................................................................................................................................... 25 • Added status and GPIO register bit description to Data Retrieval section ......................................................................... 27 • Changed title of Figure 29 .................................................................................................................................................. 28 • Updated Figure 31 .............................................................................................................................................................. 29 • Updated Figure 32 .............................................................................................................................................................. 30 • Updated Figure 35 .............................................................................................................................................................. 32 • Changed STANDBY: Enter STANDBY Mode description .................................................................................................. 35 • Changed ID register row of Table 10 .................................................................................................................................. 39 • Changed ID: ID Control Register section ........................................................................................................................... 40 • Changed bit descriptions of ID: ID Control Register section .............................................................................................. 40 • Changed description for bits 4 to 1 of PACE: PACE Detect Register section .................................................................... 47 • Updated Figure 42 .............................................................................................................................................................. 51 • Updated Figure 43 .............................................................................................................................................................. 52 • Updated Figure 46 .............................................................................................................................................................. 55 • Updated Figure 49 .............................................................................................................................................................. 57 • Updated Figure 50 and added footnote 2 ........................................................................................................................... 59 • Updated Figure 51 .............................................................................................................................................................. 60 • Updated Figure 52 .............................................................................................................................................................. 60 • Updated Figure 53 .............................................................................................................................................................. 62 • Added Analog Input Structure section ................................................................................................................................ 64 Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 Submit Documentation Feedback 69 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1194CPAG ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 ADS1194 ADS1194CPAGR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 ADS1194 ADS1194CZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1194 ADS1194CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1194 ADS1196CPAG ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 ADS1196 ADS1196CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1196 ADS1198CPAG ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 ADS1198 ADS1198CPAGR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 ADS1198 ADS1198CZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1198 ADS1198CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1198 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of