ADS1201U

® ADS ADS1201 120 1 High Dynamic Range DELTA-SIGMA MODULATOR FEATURES DESCRIPTION ● ● ● ● ● The ADS1201 is a precision, 130dB dynamic range, delta-sigma (∆Σ) modulator operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers or low level signals. With the appropriate digital filter and modulator rate, the device can be used to achieve 24-bit analog-to-digital (A/D) conversion with no missing codes. Effective resolution of 20 bits can be maintained with a digital filter bandwidth of 1kHz at a modulator rate of 320kHz. 130dB DYNAMIC RANGE FULLY DIFFERENTIAL INPUT TWO-WIRE INTERFACE INTERNAL/EXTERNAL REFERENCE ON-CHIP SWITCHES FOR CALIBRATION APPLICATIONS ● ● ● ● ● ● INDUSTRIAL PROCESS CONTROL INSTRUMENTATION SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS AVDD AGND The ADS1201 is designed for use in high resolution measurement applications including smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. It is available in a 16-lead SOIC package. REF IN REF OUT VBIAS +2.5V Reference Bias Generator BIASEN REFEN AINP AINN Second-Order ∆Σ Modulator CAL GAIN/OFFSET MOUT MCLK DVDD DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © SBAS081 1997 Burr-Brown Corporation PDS-1417C Printed in U.S.A. October, 1999 SPECIFICATIONS At TA = +25°C, AVDD = DVDD = +5V, MCLK = 320kHz, REFEN LOW, BIASEN LOW, and external +2.5V reference, unless otherwise specified. ADS1201U PARAMETER CONDITIONS MIN ANALOG INPUT Absolute Input Voltage Range 0 –10 –5 –20 With VBIAS(1) Differential Input Voltage Range With VBIAS(1) Input Impedance Input Capacitance Input Leakage Current TYP See Note 2 250(4) 8 5 At TMIN to TMAX SYSTEM PERFORMANCE Dynamic Range Integral Linearity Error 10Hz 60Hz 1kHz 60Hz 1kHz Offset Error(2) Offset Drift(3) Gain Error(2) Gain Error Drift(3) Common-Mode Rejection Power Supply Rejection REFERENCE Internal Reference (REFOUT) Drift Noise Load Current Output Impedance External Reference (REFIN) Load Current VBIAS Output Drift Load Current DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH (MCLK) VIL (MCLK) VOH (MOUT) VOL (MOUT) MCLK Frequency POWER SUPPLY REQUIREMENTS Power Supply Voltage Supply Current Analog Current Digital Current Additional Analog Current REFOUT Enabled VBIAS Enabled Total Power Dissipation Bandwidth(5) Bandwidth(5) Bandwidth(5) Bandwidth(5) Bandwidth(5) 115(6) MAX UNITS +5 +10 +5 +20 V V V V kΩ pF pA nA 50 1 130(6) 120(6) 115(6) ±0.0015 ±0.0015 At DC 80 2.4 Source or Sink See Note 7 1 See Note 7 1 100 80 2.5 25 50 –1 2.6 1 2 2.0 Using Internal Reference 3.15 3.3 50 3.0 2.5 3.45 10 dB dB dB %FSR %FSR µV µV/°C ppm µV/°C dB dB V ppm/°C µVp-p mA Ω V µA V ppm/°C mA TTL Compatible CMOS IOH IOL IIH = +5µA IIL = +5µA = 2 TTL Loads = 2 TTL Loads 2.0 –0.3 2.4 Specified Performance 0.02 0.4 1 V V V V MHz 4.75 5.25 V No Load No Load REFOUT, V BIAS Disabled TEMPERATURE RANGE Specified Performance –40 DVDD +0.3 0.8 4.6 0.4 mA mA 1.6 1 25 40 mA mA mW +85 °C NOTES: (1) This range is set with external resistors and VBIAS (as described in the text). Other ranges are possible. (2) After the on-chip offset and gain calibration functions have been employed. (3) Re-calibration can reduce these errors. (4) Input impedance changes with MCLK. (5) Assume brick wall digital filter is used. (6) 20 Log (full scale/r ms noise). (7) After calibration, these errors will be of the order of the effective resolution. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS1201 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Analog Input: Current ................................................ ±100mA, Momentary ±10mA, Continuous Voltage ................................... AGND –0.3V to AVDD +0.3V AVDD to DVDD ........................................................................... –0.3V to 6V AVDD to AGND ......................................................................... –0.3V to 6V DVDD to DGND ......................................................................... –0.3V to 6V AGND to DGND ................................................................................ ±0.3V REFIN Voltage to AGND ............................................ –0.3V to AVDD +0.3V Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V Lead Temperature (soldering, 10s) .............................................. +300°C Internal Power Dissipation ............................................................. 500mW This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PIN DESCRIPTIONS PIN CONFIGURATION Top View SOIC AVDD 1 16 REFEN REFOUT 2 15 MOUT REFIN 3 14 MCLK NIC 4 ADS1201 PIN NO NAME DESCRIPTION 1 2 AVDD REFOUT 3 4 5 6 7 8 REFIN NIC AINP AINN AGND VBIAS 9 BIASEN 10 GAIN/OFFSET 11 CAL 12 13 14 DGND DVDD MCLK 15 16 MOUT REFEN Analog Input: Analog Supply, +5V nominal. Analog Output: Internal Reference Voltage Output: +2.5V nominal. Analog Input: Reference Voltage Input. Not Internally Connected. Analog Input: Noninverting Input. Analog Input: Inverting Input. Analog Input: Analog Ground. Analog Output: Bias Voltage Output, nominally +3.3V (with +2.5V reference). Digital Input: Bias Voltage Enable Input (HIGH = enabled, LOW = disabled). Digital Input: Gain/Offset Calibration Select Input (with CAL LOW; HIGH = gain configuration, LOW = offset configuration). Digital Input: Calibration Control Input (HIGH = normal operation, LOW = gain or offset calibration configuration). Digital Input: Digital Ground. Digital Input: Digital Supply, +5V nominal. Digital Input: Modulator Clock Input. CMOS compatible. Digital Output: Modulator Output. Digital Input: REFOUT Voltage Enable Input (HIGH = enabled, LOW = disabled). 13 DVDD AINP 5 12 DGND AINN 6 11 CAL AGND 7 10 GAIN/OFFSET VBIAS 8 9 BIASEN PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER ADS1201U SOL-16 211 –40°C to +85°C ADS1201U ADS1201U Rails " " " " ADS1201U/1K Tape and Reel " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS1201U/1K” will get a single 1000-piece Tape and Reel. ® 3 ADS1201 TYPICAL PERFORMANCE CURVES At TA = +25°C, AVDD = DVDD = +5V, MCLK = 320kHz, REFEN LOW, BIASEN LOW, and external +2.5V reference, unless otherwise specified. rms NOISE LINEARITY 1.2 1.5 1.0 1 0.5 0 (ppm) (ppm) 0.8 0.6 –0.5 –1.0 –1.5 0.4 –2.0 –2.5 0.2 –3.0 0 –3.5 –5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 VDIN (V) 0 1 2 3 4 5 VDIN (V) PSRR vs FREQUENCY CMRR vs FREQUENCY 70 110 105 PSRR (dB) CMRR (dB) 68 66 64 100 62 95 60 0.1 1 10 100 0.1 1000 1.0 10 TYPICAL SINK CURRENT 1k 10k 100k TYPICAL SOURCE CURRENT 30 30 25 25 20 20 IOUT (mA) IOUT (mA) 100 Frequency (Hz) Frequency (Hz) 15 15 10 10 5 5 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 VOL (V) 1.0 1.5 2.0 2.5 VOL (V) ® ADS1201 0.5 4 3.0 3.5 4.0 4.5 5.0 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, AVDD = DVDD = +5V, MCLK = 320kHz, REFEN LOW, BIASEN LOW, and external +2.5V reference, unless otherwise specified. CMRR vs VDIN 110 CMRR (dB) 105 100 95 90 85 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VDIN (V) GENERAL DESCRIPTION THEORY OF OPERATION The ADS1201 is a single channel, second-order, CMOS analog modulator designed for high resolution conversions from dc to 1000Hz. The output of the converter (MOUT) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage. The combination of an ADS1201 and a processor that is programmed to implement a digital filter results in a high resolution A/D converter system. This system allows flexibility with the digital filter design and is capable of A/D conversion results that have a dynamic range that exceeds 130dB (see Figure 1). The differential analog input of the ADS1201 is implemented with a switched capacitor circuit. This switched capacitor circuit implements a 2nd-order modulator stage which digitizes the input signal into a binary output stream. The input stage of the converter can be configured to sample an analog signal or to perform a calibration which quantifies offset and gain errors. The sample clock (MCLK) provides the switched capacitor network and modulator clock signal for the A/D conversion process, as well as the output data framing clock. Different frequencies for this clock allows for a variety of performance solutions in resolution and signal bandwidth. The analog input signal is continuously sampled by the A/D converter and compared to an internal or external voltage reference. A digital stream appears at the output of the converter. This digital stream accurately represents the analog input voltage over time. Analog Supply 1 AVDD REFEN 16 2 REFOUT MOUT 15 3 REFIN MCLK 14 4 NIC 5 AINP DGND 12 6 AINN CAL 11 7 AGND 8 VBIAS 10µF Digital Supply 0.1µF DVDD 13 ADS1201 200Ω 0.1µF Processor 200Ω 47pF GAIN/OFFSET 10 47pF BIASEN 9 FIGURE 1. Connection Diagram for the ADS1201 Delta-Sigma Modulator Including External Processor. ® 5 ADS1201 1-Bit Data Stream Switched Capacitor Analog Input Processor for Filtering 2nd-Order Charge-Balancing A/D Converter Analog Inputs Programmable Gain Amp 2nd-Order Modulator VIN+ VREF 1-Bit DAC VIN– FIGURE 2. Block Diagram of the ADS1201. ANALOG INPUT STAGE out of the analog inputs exceed 10mA. In addition, the linearity of the device is guaranteed only when the analog voltage applied to either input resides within the range defined by AGND = > –30mV and < = AVDD + 30mV. If either of the inputs exceed these limits, the input protection diodes on the front end of the converter will begin to turn on. This will induce leakage paths resulting in nonlinearities in the conversion process. Analog Input The input design topology of the ADS1201 is based on a fully differential switched capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (100dB) and excellent power supply rejection. The input impedance of the analog input is dependent on the input capacitor and modulator clock frequency (MCLK), which is also the sampling frequency of the converter. Figure 3 shows the basic input structure of the ADS1201. The relationship between the input impedance of the ADS1201 and the modulator clock frequency is: A IN Input Im pedance(Ω) = For this reason, the 0V to 5V input range must be used with caution. Should AVDD be 4.75V, the analog input signal would swing outside the guaranteed specifications of the device. Designs utilizing this mode of operation should consider limiting the span to a slightly smaller range. Common-mode voltages are also a significant concern and must be carefully analyzed. 1E12 12 • fMCLK The input impedance becomes a consideration in designs where the source impedance of the input signal is significant. In this case, it is possible for a portion of the signal to be lost across this external source impedance. The importance of this effect depends on the desired system performance. Modulator There are two restrictions on the analog input signal to the ADS1201. Under no conditions should the current into or The modulator topology is fundamentally a 2nd-order, chargebalancing A/D converter, as the one conceptualized in Figure 4. The analog input voltage and the output of the 1-bit DAC is differentiated, providing an analog voltage at X2 and X3. The voltage at X2 and X3 are presented to their individual integrators. The output of these integrators progress in a negative or positive direction. When the value of the signal at X4 equals the comparator reference voltage, the output of the comparator switches from negative to positive or positive to negative, depending on its original state. When the output value of the comparator switches from a HIGH to LOW or vise versa, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage at X6, causing the integrators to progress in the opposite direction. The feedback of the modulator to the front end of the integrators force the value of the integrator output to track the average of the input. RSW 8kΩ (typ) The modulator sampling frequency (MCLK) can be operated over a range of 20kHz to 1MHz. The frequency of MCLK can be increased to improve the performance of the converter or adjusted to comply with the clock requirements of the application. High Impedance > 1GΩ AIN+ CINT 12pF (typ) Switching Frequency = MCLK RSW 8kΩ (typ) AIN– VCM CINT 12pF (typ) High Impedance > 1GΩ FIGURE 3. Input Impedance of the ADS1201. ® ADS1201 6 REFERENCE CIRCUIT ence is used, the correct connection configuration is shown in Figure 5a. The capacitor in this circuit is absolutely required if low noise performance is desired. There are two reference circuits included in the ADS1201 converter: VREF (REFIN, REFOUT) and VBIAS. The circuitry for VREF is configured to allow the user to utilize the internal reference on the chip or provide an external reference to the converter (see Figure 5). The second reference, VBIAS, is derived from VREF, whether it is internal or external. VBIAS is exclusively an output reference. This ratiometric relationship between VREF and VBIAS reduces system errors when two separate bias voltages are required in the application. An external reference can be used to reduce the noise in the conversion process. If an external reference is used, care should be taken to insure that the selected reference has low noise performance. The appropriate connection circuit of an external reference is shown in Figure 5b. The reference must be configured with appropriate capacitors to reduce the high frequency noise that may be contributed by the reference. The input impedance of REFIN changes with the modulator clock frequency. The relationship is: REFERENCE INPUT (REFIN) The reference input (REFIN) of the ADS1201 can be configured so that the 2.5V (nominal) internal or external reference can be used in the conversion process. If the internal refer- Typical REFIN Input Im pedance = 1E12 50 • fMCLK fMCLK X2 X(t) X3 Integrator 1 X4 Integrator 2 MOUT fS VREF Comparator X6 D/A Converter FIGURE 4. Block Diagram of a Second-Order Modulator. +5V 1 AVDD REFEN 16 2 REFOUT MOUT 15 3 MCLK 14 REFIN External VREF 1µF 4 DVDD 13 NIC 1 AVDD REFEN 16 2 REFOUT MOUT 15 3 REFIN MCLK 14 4 NIC 1µF ADS1201 DVDD 13 ADS1201 5 AINP DGND 12 5 AINP DGND 12 6 AINN CAL 11 6 AINN CAL 11 7 AGND GAIN/OFFSET 10 7 AGND 8 VBIAS 9 8 VBIAS BIASEN (a) Internal Reference GAIN/OFFSET 10 BIASEN 9 (b) External Reference FIGURE 5. Two Voltage Reference Connection Alternatives for the ADS1201. ® 7 ADS1201 The reference input voltage can vary between 2V and 3V. Higher reference voltages will cause the full-scale range to increase while the internal circuit noise of the converter remains approximately the same. This will increase the LSB weight but not the internal noise, resulting in increased signal-to-noise ratio. Likewise, lower reference voltages will decrease the signal-to-noise ratio. reference are given in the Specifications table. Note that this reference is not designed to sink or to source more than 1mA of current. In addition, loading the reference with a dynamic or variable load is not recommended. This can result in small changes in reference voltage as the load changes. The internal reference, which generates +2.5V, can be disabled when an external reference is used. This internal reference is disabled with the REFEN pin. When the reference is disabled, the supply current (AVDD) of the converter will reduce by approximately 1.6mA. The VBIAS output voltage is dependent on the reference input (REFIN) voltage and is approximately 1.33 times as great. The output of VBIAS is used to bias input signals of greater than 5V. If a resistor network is used in combination with the VBIAS output, the signal range can be scaled and level shifted to match the input range of the ADS1201. Figure 6 shows a connection diagram which will allow the ADS1201 to accept a ±10V input signal (20V full-scale range). If BIASEN is HIGH, the voltage at VBIAS will be 3.3V (assumes a 2.5V nominal VREF). VOLTAGE BIAS OUTPUT (VBIAS) REFERENCE OUTPUT (VREFOUT) The ADS1201 contains an internal +2.5V reference. When using this feature, REFEN must be HIGH (see Figure 5). Tolerances, drift, noise, and other specifications for this REFEN REFOUT LOW High Impedance HIGH 2.5V (nominal) TABLE I. Reference Enable. 0.1µF 1 AVDD REFEN 16 2 REFOUT MOUT 15 Serial Data Out 3 REFIN MCLK 14 Clock In 4 NIC 1µF R1 3kΩ VIN+ DVDD 13 ADS1201 R2 3kΩ VIN– R3 1kΩ R4 1kΩ 0.1µF 5 AINP DGND 12 6 AINN CAL 11 7 AGND 8 VBIAS GAIN/OFFSET 10 BIASEN 9 FIGURE 6. ±10V Bipolar Input Configuration Using VBIAS. t1 t2 t3 t4 Clock Period 3125 ns t2 Clock HIGH 1562.5 ns t3 Clock LOW 1562.5 ns t4 Clock Rise Time 6 ns t5 Clock Fall Time 6 t6 DOUT Valid after Clock Rising Edge t6 MOUT Data Valid Data Valid Data Valid Data Valid FIGURE 7. Timing Diagram for the Digital Interface of the ADS1201. ® ADS1201 8 TYP UNITS DESCRIPTION t1 MCLK MIN MAX SYMBOL t5 ns 400 ns BIASEN VBIAS LOW High Impedance HIGH 1.33V • VREF An input differential signal of 0V will ideally produce a stream of ones and zeros that are HIGH 50% of the time and LOW 50% of the time. A differential input of 5V will produce a stream of ones and zeros that are HIGH 90% of the time. A differential input of –5V will produce a stream of ones and zeros that are HIGH 10% of the time. The input voltage versus the output modulator signal is shown in Figure 8. TABLE II. Bias Enable. When enabled, the VBIAS circuitry consumes approximately 1mA with no external load. The maximum current into or out of VBIAS should not exceed 10mA. OFFSET and GAIN CALIBRATION On power-up, external signals may be present before VBIAS is enabled. This can create a situation in which a negative voltage is applied to the analog inputs, reverse biasing the negative input protection diode of the ADS1201. This situation should not be a problem as long as the resistors R1 and R2 limit the current being sourced by each analog input to be under 10mA. A potential of 0V at the analog input pin (AINP or AINN) should be used in the calculation. The ADS1201 offers a self-calibration function that is implemented with the GAIN/OFFSET and CALEN pins. Both conditions provide an output stream of data, similar to normal operation where the converter is configured to sample an input signal at AIN. The offset and gain errors of the ADS1201 are calibrated independently. For best operation, the offset should be calibrated first, followed by the gain. The calibration implementation timing diagram is shown in Figure 9. The calibration mode pins control the calibration functions of the ADS1201. DIGITAL OUTPUT The timing diagram for the ADS1201 data retrieval is shown in Figure 7. MCLK initiates the modulator process for the ADS1201 and is used as a system clock by the ADS1201, as well as a framing clock for data out. The modulator output data, which is a serial stream, is available on the MOUT pin. Typically, MOUT is read on the falling edge of MCLK. Under any situation with MCLK, the duty cycle must be kept constant for reliable, repeatable results. Calibration should be performed once and then normal operation can be resumed. Calibration of offset and gain is recommended immediately after power-on and whenever there is a “significant” change in the operating environment. Significant changes in the operating environment include a change of the MCLK frequency, MCLK duty cycle, power Modulator Output +FS (Analog Input) –FS (Analog Input) Analog Input FIGURE 8. Analog Input versus Modulator Output of the ADS1201. t9 t8 CAL t8 GAIN/OFFSET t9 t10 t11 SYMBOL DESCRIPTION t8 CAL and GAIN/OFFSET Rise Time MIN 10 ns t9 CAL and GAIN/OFFSET Fall Time 10 ns t10 GAIN/OFFSET to CAL Setup Time 0 ns t11 GAIN/OFFSET to CAL Hold Time 2.5 TMCLK(1) ns TYP MAX UNITS NOTE: (1) TMCLK is the clock period of MCLK. FIGURE 9. Timing Diagram for the Calibration Feature of the ADS1201. ® 9 ADS1201 GAIN/OFFSET CALEN 0 1 Normal Mode 0 0 Offset Calibration, Analog inputs shorted to ground internally. 1 0 Full-Scale Calibration, Analog inputs are referenced to VREF internally. The analog supply should be well regulated and low noise. For designs requiring very high resolution from the ADS1201, power supply rejection will be a concern. The requirements for the digital supply are not strict. However, high frequency noise on DVDD can capacitively couple into the analog portion of the ADS1201. This noise can originate from switching power supplies, microprocessors or digital signal processors. TABLE III. Calibration Enable. For either supply, high frequency noise will generally be rejected by the external digital filter at integer multiples of MCLK. Just below and above these frequencies, noise will alias back into the pass-band of the digital filter, affecting the conversion result. supply, VREF, or temperature. The amount of change which could cause a re-calibration is dependent on the application and effective resolution of the system. The results of the calibration calculations are stored in two registers in the processor chip (see Figure 1). These two calibration results can then be used to calibrate the input signal results with one of the following formulas: Inputs to the ADS1201, such as AIN, REFIN, and MCLK, should not be present before the analog and digital supplies are on. Violating this condition could cause latch-up. If these signals are present before the supplies are on, series resistors should be used to limit the input current. Equivalent Calibrated Output Code = FSC (FO1 – FO2) /(FO3 – FO2) where FO1 = Filter output code of an applied input voltage FO2 = Filter output code of the offset calibration If one supply must be used to power the ADS1201, the system’s analog supply should be used to power both AVDD and DVDD. Experimentation may be the best way to determine the appropriate connection between AVDD and DVDD. FO3 = Filter output code of the gain calibration FSC = Desired full-scale output With a simple sinc filter, the calibrated A/D conversion would equal: GROUNDING Equivalent Calibrated Input Voltage = (N1 – N2) • VREF / (N3 – N2 ) where N1 = number of ones counted (or digital equivalent after filtering) over given time (tM) with an applied input voltage The analog and digital sections of the design should be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. AGND should be connected to the analog ground plane as well as all other analog grounds. DGND should be connected to the digital ground plane and all digital signals referenced to this plane. N2 = number of ones counted (or digital equivalent after filtering) during offset calibration where t12 = tM N3 = number of ones counted (or digital equivalent after filtering) during gain calibration where t13 = tM A system calibration can be performed by applying two known voltage levels to the input of the converter. In this situation, the GAIN/OFFSET and CALEN pins are not used. Rather, the digital output of these two known voltages are accumulated by the processor. With this data, the processor can determine the calibration register values that are appropriate for the application. The ADS1201 pinout is such that the converter is cleanly separated into an analog and digital portion. This should allow simple layout of the analog and digital sections of the design. For a signal converter system, AGND and DGND of the ADS1201 can be connected together. Do not join the ground planes, but connect the two with a moderate signal trace underneath the converter. For multiple converters, connect the two ground planes at one location as central to all of the converters as possible. In some cases, experimentation may be required to find the best point to connect the two planes together. Experimentation may be the best way to determine the appropriate connection between AGND and DGND. LAYOUT CONSIDERATIONS POWER SUPPLIES The ADS1201 requires the digital supply (DVDD) to be no greater than the analog supply (AVDD). Failure to observe this condition could cause permanent damage to the ADS1201. The best scheme is to power the analog section of the design and AVDD from one +5V line and the digital section and DVDD from a separate +5V line (from the same supply). If there are separate analog and digital power supplies for the ADS1201, a good design approach would be to have the analog supply come up first, followed by the digital supply. Another approach that can be used to control the analog and digital power supply differences is shown in Figure 10. In this circuit, a connection has been made between the ADS1201 supply pins via a 10Ω resistor. The combination of this resistor and the decoupling capacitors provides some filtering between DVDD and AVDD. DECOUPLING Good decoupling practices should be used for the ADS1201 and for all components in the design. All decoupling capacitors, specifically the 0.1µF ceramic capacitors, should be placed as close as possible to the pin being decoupled. A 1µF and 10µF capacitor, in parallel with the 0.1µF ceramic capacitor, should be used to decouple AVDD to AGND. At a minimum, a 0.1µF ceramic capacitor should be used to decouple DVDD to DGND, as well as for the digital supply on each digital component. ® ADS1201 10 +5V 10Ω + 10µF 1 AVDD REFEN 16 2 REFOUT MOUT 15 3 REFIN MCLK 14 4 NIC 0.1µF DVDD 13 ADS1201 0.1µF 5 AINP DGND 12 6 AINN CAL 11 7 AGND 8 VBIAS GAIN/OFFSET 10 BIASEN 9 FIGURE 10. Power Supply Connection Using One Power Plane and One Digital Plane. +5V Isolated Power 6kΩ 0.1µF 10kΩ DSP 8 100µA 7 100µA 1µF 1 AVDD REFEN 16 2 REFOUT MOUT 15 3 REFIN MCLK 14 4 NIC 2 SCLK 0.1µF 5 AINP DGND 12 6 AINN CAL 11 7 AGND 8 VBIAS SDATA REF200 5 4 +5V DVDD 13 ADS1201 1 MDATA Opto Coupler GAIN/OFFSET 10 BIASEN +5V Opto Coupler MCLK 9 3 FIGURE 11. Bridge Transducer Interface with Current Excitation. ® 11 ADS1201 +5V +5V Isolated Power 8 7 REF200 100µA 100µA 0.1µF DSP 1 2 1µF 1 AVDD REFEN 16 2 REFOUT MOUT 15 3 REFIN MCLK 14 4 NIC MDATA Opto Coupler +5V DVDD 13 ADS1201 SCLK 0.1µF 5 AINP DGND 12 6 AINN CAL 11 7 AGND 8 VBIAS SDATA PT100 12.5kΩ +5V GAIN/OFFSET 10 Opto Coupler MCLK 9 BIASEN FIGURE 12. PT100 Interface with Current Excitation. +5V 0.1µF 10kΩ DSP 3 2 1/2 OPA2237 1 1 AVDD REFEN 16 2 REFOUT MOUT 15 MDATA 3 REFIN MCLK 14 MCLK 4 NIC 0.1µF DVDD 13 ADS1201 RG 6 5 1/2 OPA2237 7 5 AINP DGND 12 6 AINN CAL 11 7 AGND 8 VBIAS GAIN/OFFSET 10 BIASEN FIGURE 13. Geophone Interface. ® ADS1201 12 SCLK 0.1µF 9 SDATA +5V +5V Isolated Power 0.1µF 10kΩ DSP 3 2 1/2 OPA2237 1 10kΩ 0.1µF 16 1 AVDD REFEN 2 REFOUT MOUT 15 3 REFIN MCLK 14 4 NIC 10kΩ 6 5 1/2 OPA2237 7 +5V DVDD 13 ADS1201 RG MDATA Opto Coupler SCLK 0.1µF 5 AINP DGND 12 6 AINN CAL 11 7 AGND 8 VBIAS SDATA +5V GAIN/OFFSET 10 BIASEN Opto Coupler MCLK 9 FIGURE 14. Single-Supply, High Accuracy Thermocouple Interface. HV+ Floating Positive Supply Gate Drive 0.1µF 5.1V DSP 0.1µF 1 AVDD REFEN 16 2 REFOUT MOUT 15 3 REFIN MCLK 14 4 NIC RSENSE Motor AINP 6 AINN 7 AGND 8 VBIAS +5V DVDD 13 ADS1201 5 RSENSE MDATA Opto Coupler SCLK 0.1µF DGND 12 SDATA +5V CAL 11 GAIN/OFFSET 10 BIASEN Opto Coupler MCLK 9 HV– FIGURE 15. Motor Controller Sensing Circuit. ® 13 ADS1201 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS1201U ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1201U Samples ADS1201U/1K ACTIVE SOIC DW 16 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1201U Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of