ADS1207IDGKT

ADS1207IDGKT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

  • 描述:

    ADS1207IDGKT - LOW-POWER, SYNCHRONOUS VOLTAGE-TO-FREQUENCY CONVERTER - Burr-Brown Corporation

  • 数据手册
  • 价格&库存
ADS1207IDGKT 数据手册
ADS1206 ADS1207 SBAS311 − MARCH 2004 Low Power, Synchronous Voltage to Frequency Converter FEATURES D Syncronous Operation D Frequency Set By External Clock D Maximum Input Frequency: D D D D D D Alternate Source for AD7740 D −40°C to +85°C Operating Temperature Range APPLICATIONS D Galvanic Isolation Measurement D High Voltage Measurement D Low-Cost Analog-to-Digital Conversion D Motor Control D Industrial Process Control D Instrumentation D Smart Transmitters D Portable Instruments − 1MHz for ADS1206 − 4MHz for ADS1207 Selectable High-Impedance Buffered Input 2% Internal, 2.5V Reference Voltage High-Current Output Driver Power Supply 3.3V or 5V Low Power : 3mW (typ) DESCRIPTION The ADS1206 and ADS1207 are a low-cost, high-performance, synchronous voltage-to-frequency converters (VFC). Both devices can operate from a single 3.0V to 3.6V or 4.5V to 5.5V power supply, consuming only 1mA. The output signal is synchronous with the input clock, CLKIN. The clock input is TTL- and CMOScompatible and the onboard clock generator can also accept an external crystal or resonator. The maximum input clock frequency for the ADS1206 is 1MHz and for the ADS1207 is 4MHz. The clock divider on the ADS1207 scales the input frequency to 2MHZ, which permits the core to operate at the higher rate. The high-impedance input is ideal for direct connection to high-impedance transducers or high-voltage resistive dividers. Counting output pulses over a 4ms period results in an effective 12-bit resolution for the ADS1206 using a 1MHz input clock. For the ADS1207 using a 4MHz input clock, the same result occurs over a 2ms period. Both devices are designed for use in medium-resolution measurements. They are available in an 8-lead VSSOP package. REFIN/OUT 1kΩ Reference Voltage 2.5V VIN x1 Modulator Buffer FOUT −2 ADS1207 Only BUF CLKOUT CLKIN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright  2004, Texas Instruments Incorporated www.ti.com PRODUCT PREVIEW ADS1206 ADS1207 www.ti.com SBAS311 − MARCH 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) MAXIMUM INTEGRAL LINEARITY ERROR (%FS) ±0.012 ±0.012 MAXIMUM GAIN ERROR (%) ±0.7 ±0.7 SPECIFIED TEMPERATURE RANGE −40°C to +85°C −40°C to +85°C PRODUCT ADS1206 ADS1207 PACKAGELEAD VSSOP-8 VSSOP-8 PACKAGE DESIGNATOR DGK DGK PACKAGE MARKING TBD TBD TBD TBD ORDERING NUMBER ADS1206IDGKT ADS1206IDGKR ADS1207IDGKT ADS1207IDGKR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000 (1) For the most current package and ordering information, refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1204 UNIT V V V V mA °C °C °C PRODUCT PREVIEW Supply Voltage, GND to VDD Analog Input Voltage with Respect to GND Reference Input Voltage with Respect to GND Digital Input Voltage with Respect to GND Input Current to Any Pin Except Supply Power Dissipation Operating Virtual Junction Temperature Range, TJ Operating Free-Air Temperature Range, TA Storage Temperature Range, TSTG −0.3 to 7 GND − 0.3 to VDD + 0.3 GND − 0.3 to VDD + 0.3 GND − 0.3 to VDD + 0.3 −20 to 20 See Dissipation Rating Table −40 to +150 −40 to +85 −65 to +150 Lead Temperature (1.6mm or 1/16-inch from case for 10s) +260 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage, GND to VDD Reference Input Voltage Analog Inputs External Clock BUF = 0 BUF = 1 ADS1206 ADS1207 Low-Voltage Levels 5V Logic Levels MIN 3.0 4.5 TBD 0 0.1 TBD TBD −40 NOM 5 2.5 MAX 3.6 5.5 VDD VREF VDD − 0.2 1 4 105 UNIT V V V V V MHz MHz °C Operating Junction Temperature Range, TJ (1) with reduced accuracy, minimum clock can go up to 500kHz. DISSIPATION RATING TABLE BOARD Low-K(2) High-K(3) PACKAGE DGK DGK TA ≤ 25°C POWER RATING 469.6mW 691.4mW DERATING FACTOR ABOVE TA = 25°C(1) 3.756mW/°C 5.531mW/°C TA = 70°C POWER RATING 300.5mW 442.5mW TA = 85°C POWER RATING 244.2mW 359.5mW (1) This is the inverse of the traditional junction-to-ambient thermal resistance (Rq JA). Thermal resistances are not production tested and are for informational purposes only. (2) The JEDEC Low-K (1s) board design used to derive this data was a 3-inch x 3-inch, two-layer board with 2-ounce copper traces on top of the board. (3) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board. 2 ADS1206 ADS1207 www.ti.com SBAS311 − MARCH 2004 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at −40°C to +85°C, VDD = 5V or VDD = 3V, VREF = internal +2.5V, CLKIN = 1MHz, unless otherwise noted. PARAMETER DC Accuracy INL DNL VOS TCVOS GERR TCGERR Integral linearity error(2) Differential nonlinearity(3) Offset error Offset error drift Gain error(4) Gain error drift Noise PSRR Power-supply rejection ratio 4.5V < VDD < 5.5V 3.0V < VDD < 3.6V BUF = 0 BUF = 1 BUF = 0 BUF = 1 BUF = 0 BUF = 1 0 0.1 3 3 8 5 100 1 FS sinewave, −3dB, BUF = 0 FS sinewave, −3dB, BUF = 1 ADS1206I ADS1207I 0.1 0.05 2.3 2.5 ±50 f = 0.1Hz to 10Hz, CL = 10µF f =10Hz to 10kHz, CL = 10µF VDD = 4.5V to 5.5V VDD = 3.0V to 3.6V to 0.1% at CL = 0 TBD 100 TBD −70 −60 1 30 2.5 5 ±200 VDD TBD TBD 0.9 0.45 2.7 ±8 10 100 BUF = 0, VIN = 0V BUF = 1, VIN = 0.1V Referenced to VREF ±7 ±7 5 ±0.1 20 TBD 55 65 VREF VDD − 0.2 BUF = 1 BUF = 0 TEST CONDITIONS ADS1206I, ADS1207I MIN TYP(1) MAX ±0.012 ±0.018 TBD ±35 ±35 20 ±0.7 UNITS % FSR % FSR % FSR mV mV µV/°C % FSR ppm/°C µVrms dB dB V V pF pF µA nA kΩ pF MHz MHz CLKIN CLKIN V % ppm/°C µVPP µVrms dB dB kΩ µs V pF µA Analog Input FSR Full-scale range Input capacitance Input current Differential input resistance Differential input capacitance BW Bandwidth Output Signal FOUT Output frequency span Voltage Reference Output VOUT dVOUT/dT Reference voltage output Initial accuracy Output voltage temperature drift Output voltage noise PSRR Power-supply rejection ratio Reference output resistance Turn-on settling time Voltage Reference Input VREF Reference voltage input Reference input capacitance Reference input current (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the transfer curve for VIN = 0V to VREF or 0.1V to VDD − 0.2V, expressed either as the number of LSBs or as a percent of measured input range. (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) Applicable for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. (6) Applicable for 3.0V nominal supply: VDD (min) = 3.0V and VDD (max) = 3.6V. 3 PRODUCT PREVIEW ADS1206 ADS1207 www.ti.com SBAS311 − MARCH 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at −40°C to +85°C, VDD = 5V or VDD = 3V, VREF = internal +2.5V, CLKIN = 1MHz, unless otherwise noted. PARAMETER Digital Inputs(5) Logic family VIH VIL IIN CI High-level input voltage Low-level input voltage Input current Input capacitance Logic family VOH VOL IO High-level output voltage Low-level output voltage Output sink current Output capacitance VDD = 4.5V, IOH = −100µA VDD = 4.5V, IOH = −2mA VDD = 4.5V, IOH = 2mA 1.5V < VOL < VDD 4.44 2.5 0.5 10 5 30 LVCMOS and LVTTL VDD = 3.6V VDD = 3.0V VI = VDD or GND 5 LVCMOS and LVTTL VDD = 3V, IOH = −100µA VDD = 3V, IOH = −2mA VDD = 3V, IOH = 100µA VDD = 3V, IOH = 2mA 10 5 30 Low-voltage levels 5V logic levels BUF = GND BUF = VDD VDD = 3.3V VDD = 5V 3.0 4.5 0.9 1.1 3.63 5.5 3.6 5.5 1.25 1.5 4.95 7.5 VDD−0.2 2.4 0.2 0.4 V V V V mA pF pF V V mA mA mW mW 2 −0.3 VDD+0.3 0.8 ±1 V V nA pF VI = VDD or GND 5 CMOS V V V mA pF pF 0.7×VDD −0.3 TEST CONDITIONS ADS1206I, ADS1207I MIN TYP(1) MAX CMOS VDD+0.3 0.3×VDD ±1 V V µA pF UNITS Digital Outputs(5) PRODUCT PREVIEW CO CL Load capacitance Digital Inputs(6) Logic family VIH VIL IIN CI High-level input Voltage Low-level input voltage Input current Input capacitance Logic family VOH VOL IO CO High-level output voltage Low-level output voltage Output sink current Output capacitance Digital Outputs(6) CL Load capacitance Power Supply VDD IDD Power-supply voltage Supply current Power dissipation (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the transfer curve for VIN = 0V to VREF or 0.1V to VDD − 0.2V, expressed either as the number of LSBs or as a percent of measured input range. (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) Applicable for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. (6) Applicable for 3.0V nominal supply: VDD (min) = 3.0V and VDD (max) = 3.6V. 4 ADS1206 ADS1207 www.ti.com SBAS311 − MARCH 2004 PIN ASSIGNMENTS VSSOP PACKAGE (TOP VIEW) TERMINAL NAME CLKOUT CLKOUT CLKIN GND REFIN/OUT 1 2 3 4 8 7 6 5 BUF FOUT VDD VIN Terminal Functions NO. 1 2 3 4 5 6 7 8 DESCRIPTION Clock output Master clock input Ground Reference voltage input or output Analog input Power supply, +3.3V or +5V nominal Modulator output Buffered mode select CLKIN GND REFIN/OUT VIN VDD FOUT BUF PARAMETER MEASUREMENT INFORMATION tC1 CLKIN tD1 FOUT tW2 tR1 tF1 tW1 Figure 1. Timing Diagram TIMING REQUIREMENTS: 5.0V over recommended operating free-air temperature range at −40°C to +85°C,, and VDD = 5V, unless otherwise noted. PARAMETER tC1 tW1 tD1 tW2 tR1 Input clock period Input clock high time FOUT rising edge delay after input clock rising edge FOUT high time FOUT rise time ADS1206 ADS1207 MIN 1000 250 (tC1/2) − 100 TBD tC1 − 20 TBD MAX TBD TBD (tC1/2) + 100 TBD tC1 + 20 TBD UNITS ns ns ns ns ns ns tF1 FOUT fall time TBD TBD ns NOTE: Applicable for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. TIMING REQUIREMENTS: 3.3V over recommended operating free-air temperature range at −40°C to +85°C,, and VDD = 3.3V, unless otherwise noted. PARAMETER tC1 tW1 tD1 tW2 tR1 Input clock period Input clock high time FOUT rising edge delay after input clock rising edge FOUT high time FOUT rise time ADS1206 ADS1207 MIN 1000 250 (tC1/2) − 100 TBD tC1 − 8 TBD MAX TBD TBD (tC1/2) + 100 TBD tC1 + 8 TBD UNITS ns ns ns ns ns ns tF1 FOUT fall time TBD TBD ns NOTE: Applicable for 3.3V nominal supply: VDD (min) = 3.0V and VDD (max) = 3.6V. All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. 5 PRODUCT PREVIEW PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device ADS1206IDGKR ADS1206IDGKT ADS1207IDGKR ADS1207IDGKT (1) Status (1) PREVIEW PREVIEW PREVIEW PREVIEW Package Type MSOP MSOP MSOP MSOP Package Drawing DGK DGK DGK DGK Pins Package Eco Plan (2) Qty 8 8 8 8 2500 250 None None None None Lead/Ball Finish Call TI Call TI Call TI Call TI MSL Peak Temp (3) Call TI Call TI Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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