ADS1218Y/250G4

          ADS1218 SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory FEATURES • • • • • • • • • • • • • • 24 BITS NO MISSING CODES 0.0015% INL 22 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) 4K BYTES OF FLASH MEMORY PROGRAMMABLE FROM 2.7V TO 5.25V PGA FROM 1 TO 128 SINGLE CYCLE SETTLING MODE PROGRAMMABLE DATA OUTPUT RATES UP TO 1kHz PRECISION ON-CHIP 1.25V/2.5V REFERENCE: ACCURACY: 0.2% DRIFT: 5ppm/°C EXTERNAL DIFFERENTIAL REFERENCE OF 0.1V TO 2.5V ON-CHIP CALIBRATION PIN-COMPATIBLE WITH ADS1216 SPI™ COMPATIBLE 2.7V TO 5.25V < 1mW POWER CONSUMPTION The eight input channels are multiplexed. Internal buffering can be selected to provide a very high input impedance for direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for the detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/A) converter provides an offset correction with a range of 50% of the FSR (Full-Scale Range). The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to 128 with an effective resolution of 19 bits at a gain of 128. The A/D conversion is accomplished with a second-order delta-sigma modulator and programmable sinc filter. The reference input is differential and can be used for ratiometric conversion. The on-board current DACs (Digital-to-Analog Converters) operate independently with the maximum current set by an external resistor. The serial interface is SPI-compatible. Eight bits of digital I/O are also provided that can be used for input or output. The ADS1218 is designed for high-resolution measurement applications in smart transmitters, industrial process control, weight scales, chromatography, and portable instrumentation. AGND AVDD RDAC IDAC2 8−Bit IDAC IDAC1 8−Bit IDAC APPLICATIONS • • • • • • • INDUSTRIAL PROCESS CONTROL LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTATION WEIGHT SCALES PRESSURE TRANSDUCERS VREFOUT VRCAP VREF+ VREF− XIN XOUT Clock Generator 1.25V or 2.5V Reference Offset DAC AIN0 AIN1 Registers AIN2 Program− AIN3 MUX BUF + PGA AIN4 2nd−Order Modulator mable Controller RAM Digital F ilter AIN5 4K Bytes FLASH AIN7 AINCOM POL DESCRIPTION The ADS1218 is a precision, wide dynamic range, delta-sigma, Analog-to-Digital (A/D) converter with 24-bit resolution and Flash memory operating from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to 24 bits of no missing code performance and effective resolution of 22 bits. WREN AIN6 Serial Interface Digital I/O Interface SCLK DIN DOUT CS DVDD DGND BUFEN D0 ... D7 PDWN DSYNC RESET DRDY Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2005, Texas Instruments Incorporated ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) AVDD to AGND DVDD to DGND Input Current Input Current AIN –0.3V to +6V –0.3V to +6V 100mA, Momentary 10mA, Continuous GND – 0.5V to AVDD + 0.5V AVDD to DVDD AGND to DGND –6V to +6V –0.3V to +0.3V Digital Input Voltage to GND –0.3V to DVDD + 0.3V Digital Output Voltage to GND –0.3V to DVDD + 0.3V Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10s) (1) 2 +150°C –40°C to +85°C –60°C to +100°C +300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP Buffer Off AGND – 0.1 Buffer On AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.5 V ANALOG INPUT (AIN0 – AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range (In+) – (In–), See Block Diagram ±VREF/PGA V Differential Input Impedance Buffer Off 5/PGA MΩ Input Current Buffer On 0.5 nA Fast Settling Filter –3dB 0.469 × fDATA Hz Sinc2 Filter –3dB 0.318 × fDATA Hz Sinc3 Filter –3dB 0.262 × fDATA Bandwidth Programmable Gain Amplifier User-Selectable Gain Ranges 1 Input Capacitance Input Leakage Current Modulator Off, T = +25°C Burnout Current Sources Hz 128 9 pF 5 pA 2 µA OFFSET DAC Offset DAC Range ±VREF/(2 × PGA) Offset DAC Monotonicity V 8 Offset DAC Gain Error Offset DAC Gain Error Drift Bits ±10 % 1 ppm/°C SYSTEM PERFORMANCE Resolution 24 No Missing Codes Integral Nonlinearity Offset Error (1) 24 Bits End Point Fit ±0.0015 % of FS Before Calibration Offset Drift (1) Gain Error After Calibration Gain Error Drift (1) Common-Mode Rejection Normal-Mode Rejection at DC 7.5 ppm of FS 0.02 ppm of FS/°C 0.005 % 0.5 ppm/°C 100 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Output Noise Power-Supply Rejection Bits sinc3 See Typical Characteristics at DC, dB = –20 log(∆VOUT/∆VDD) (2) 80 95 dB VOLTAGE REFERENCE INPUT Reference Input Range VREF REF IN+, REF IN– 0 VREF ≡ (REF IN+) – (REF IN–) 0.1 AVDD 2.5 2.6 V V Common-Mode Rejection at DC 120 dB Common-Mode Rejection fVREFCM = 60Hz, fDATA = 60Hz 120 dB VREF = 2.5V 1.3 µA Bias Current (3) (1) (2) (3) Calibration can minimize these errors. ∆VOUT is change in digital result. 12pF switched capacitor at fSAMP clock frequency. 3 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP MAX UNIT REF HI = 1 at +25°C 2.495 2.50 2.505 V ON-CHIP VOLTAGE REFERENCE Output Voltage REF HI = 0 Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration 1.25 V 8 mA 50 µA Sink or Source Indefinite 5 ppm/°C BW = 0.1Hz to 100Hz 10 µVPP Sourcing 100µA 3 Ω 50 µs RDAC = 150kΩ, Range = 1 0.5 mA RDAC = 150kΩ, Range = 2 1 mA RDAC = 150kΩ, Range = 3 2 mA RDAC = 15kΩ, Range = 3 20 mA Maximum Short-Circuit Current Duration RDAC = 10kΩ Indefinite Monotonicity RDAC = 150kΩ Drift Noise Output Impedance Startup Time IDAC Full-Scale Output Current RDAC = 0Ω Compliance Voltage 10 8 Bits 0 Output Impedance Minutes AVDD – 1 V See Typical Characteristics PSRR VOUT = AVDD/2 400 Absolute Error Individual IDAC 5 ppm/V % Absolute Drift Individual IDAC 75 ppm/°C Mismatch Error Between IDACs, Same Range and Code 0.25 % Mismatch Drift Between IDACs, Same Range and Code 15 ppm/°C POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current (IADC + IVREF + IDAC) ADC Current (IADC) AVDD 4.75 1 Digital Current Power Dissipation V nA PGA = 1, Buffer Off 175 275 µA PGA = 128, Buffer Off 500 750 µA PGA = 1, Buffer On 250 350 µA PGA = 128, Buffer On 900 1375 µA 250 375 µA Excludes Load Current 480 675 µA Normal Mode, DVDD = 5V 180 275 µA SLEEP Mode, DVDD = 5V 150 µA Read Data Continuous Mode, DVDD = 5V 230 µA PDWN = Low 1 nA PGA = 1, Buffer Off, REFEN = 0, IDACS Off, DVDD = 5V 1.8 VREF Current (IVREF) IDAC Current (IDAC) 5.25 PDWN = 0, or SLEEP 2.8 mW TEMPERATURE RANGE Operating –40 +85 °C Storage –60 +100 °C 4 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 75kΩ, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP Buffer Off AGND – 0.1 Buffer On AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.5 V ANALOG INPUT (AIN0 – AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range (In+) – (In–), See Block Diagram ±VREF/PGA V Input Impedance Buffer Off 5/PGA MΩ Input Current Buffer On 0.5 nA Fast Settling Filter –3dB 0.469 × fDATA Hz Sinc2 Filter –3dB 0.318 × fDATA Hz Sinc3 Filter –3dB 0.262 × fDATA Bandwidth Programmable Gain Amplifier User-Selectable Gain Ranges 1 Input Capacitance Input Leakage Current Modulator Off, T = +25°C Burnout Current Sources Hz 128 9 pF 5 pA 2 µA OFFSET DAC Offset DAC Range ±VREF/(2 × PGA) Offset DAC Monotonicity V 8 Offset DAC Gain Error Offset DAC Gain Error Drift Bits ±10 % 2 ppm/°C SYSTEM PERFORMANCE Resolution 24 Bits No Missing Codes Integral Nonlinearity Offset Error (1) End Point Fit Before Calibration Offset Drift (1) Gain Error After Calibration Gain Error Drift (1) Common-Mode Rejection Normal-Mode Rejection at DC Bits ±0.0015 % of FS 15 ppm of FS 0.04 ppm of FS/°C 0.010 % 1.0 ppm/°C 100 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB 100 dB fSIG = 60Hz, fDATA = 60Hz Output Noise Power-Supply Rejection 24 See Typical Characteristics at DC, dB = –20 log(∆VOUT/∆VDD) (2) 75 90 dB VOLTAGE REFERENCE INPUT Reference Input Range VREF REF IN+, REF IN– 0 AVDD VREF ≡ (REF IN+) – (REF IN–) 0.1 1.25 Common-Mode Rejection at DC Common-Mode Rejection Bias Current (3) (1) (2) (3) V V 120 dB fVREFCM = 60Hz, fDATA = 60Hz 120 dB VREF = 1.25V 0.65 µA Calibration can minimize these errors. ∆VOUT is change in digital result. 12pF switched capacitor at fSAMP clock frequency. 5 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 75kΩ, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP MAX REF HI = 0 at +25°C 1.245 1.25 1.255 UNIT ON-CHIP VOLTAGE REFERENCE Output Voltage V Short-Circuit Current Source 3 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration Sink or Source Indefinite 5 ppm/°C BW = 0.1Hz to 100Hz 10 µVPP Sourcing 100µA 3 Ω 50 µs RDAC = 75kΩ, Range = 1 0.5 mA RDAC = 75kΩ, Range = 2 1 mA RDAC = 75kΩ, Range = 3 2 mA RDAC = 15kΩ, Range = 3 20 mA Maximum Short-Circuit Current Duration RDAC = 10kΩ Indefinite Monotonicity RDAC = 75kΩ Drift Noise Output Impedance Startup Time IDAC Full-Scale Output Current RDAC = 0Ω Compliance Voltage 10 8 Bits 0 Output Impedance Minutes AVDD – 1 V See Typical Characteristics PSRR VOUT = AVDD/2 600 Absolute Error Individual IDAC 5 ppm/V % Absolute Drift Individual IDAC 75 ppm/°C Mismatch Error Between IDACs, Same Range and Code 0.25 % Mismatch Drift Between IDACs, Same Range and Code 15 ppm/°C POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current (IADC + IVREF + IDAC) ADC Current (IADC) AVDD 2.7 1 Digital Current Power Dissipation V nA PGA = 1, Buffer Off 160 250 µA PGA = 128, Buffer Off 450 700 µA PGA = 1, Buffer On 230 325 µA PGA = 128, Buffer On 850 1325 µA 250 375 µA Excludes Load Current 480 675 µA Normal Mode, DVDD = 3V 90 200 µA SLEEP Mode, DVDD = 3V 75 µA Read Data Continuous Mode, DVDD = 3V 113 µA PDWN = 0 1 nA PGA = 1, Buffer Off, REFEN = 0, IDACS Off, DVDD = 3V 0.8 VREF Current (IVREF) IDAC Current (IDAC) 3.3 PDWN = 0, or SLEEP 1.4 mW TEMPERATURE RANGE Operating –40 +85 °C Storage –60 +100 °C 6 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V PARAMETER CONDITIONS MIN TYP MAX UNIT Digital Input/Output Logic Family CMOS Logic Level VIH 0.8 × DVDD DVDD V VIL DGND 0.2 × DVDD V VOH IOH = 1mA DVDD – 0.4 VOL IOL = 1mA DGND V DGND + 0.4 V 10 µA Input Leakage IIH VI = DVDD IIL VI = 0 –10 1 5 MHz 1/fOSC 200 1000 ns Master Clock Rate: fOSC (1) Master Clock Period: tOSC (1) (1) µA For the Write RAM to Flash operation (WR2F), the SPEED bit in the SETUP register must be set appropriately and the device operating frequency must be: 2.3MHz < fOSC < 4.13MHz. FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNIT Operating Current Page Write Page Read DVDD = 5V, During WR2F Command 17 mA DVDD = 3V, During WR2F Command 9 mA DVDD = 5V, During RF2R Command 8 mA DVDD = 3V, During RF2R Command Endurance Data Retention DVDD for Erase/Write at +25°C 2 mA 100,000 Write Cycles 100 2.7 Years 5.25 V 7 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 PIN CONFIGURATION XIN 31 XOUT 32 PDWN DRDY 33 POL CS 34 DSYNC SCLK 35 TQFP DGND DIN 36 DVDD DOUT Top View 30 29 28 27 26 25 D0 37 24 RESET D1 38 23 BUFEN D2 39 22 DGND D3 40 21 DGND D4 41 20 DGND 19 DGND D5 42 ADS1218 D6 43 18 WREN D7 44 17 RDAC 5 6 7 8 9 10 11 12 AGND 4 AINCOM 3 AIN7 2 AIN4 1 AIN6 13 AVDD AIN5 VREF− 48 AIN3 14 VRCAP AIN2 VREF+ 47 AIN1 15 IDAC1 AIN0 VREFOUT 46 AGND 16 IDAC2 AVDD AGND 45 PIN DESCRIPTIONS PIN NUMBER NAME DESCRIPTION 1 AVDD 2 3 4 8 PIN NUMBER NAME DESCRIPTION Analog Power Supply 24 RESET Active Low, resets the entire chip. AGND Analog Ground 25 XIN AIN0 Analog Input 0 26 XOUT AIN1 Analog Input 1 27 PDWN Clock Input Clock Output, used with crystal or resonator. Active Low. Power Down. The power-down function shuts down the analog and digital circuits. 5 AIN2 Analog Input 2 6 AIN3 Analog Input 3 28 POL 7 AIN4 Analog Input 4 29 DSYNC Active Low, Synchronization Control 8 AIN5 Analog Input 5 30 DGND Digital Ground 9 AIN6 Analog Input 6 31 DVDD Digital Power Supply 10 AIN7 Analog Input 7 32 DRDY Active Low, Data Ready 11 AINCOM Analog Input Common 33 CS Active Low, Chip Select 12 AGND Analog Ground 34 SCLK 13 AVDD Analog Power Supply 35 DIN 14 VRCAP VREF Bypass CAP 36 DOUT Serial Data Output 15 IDAC1 Current DAC1 Output 37–44 D0-D7 Digital I/O 0–7 16 IDAC2 Current DAC2 Output 45 AGND Analog Ground 17 RDAC Current DAC Resistor 46 VREFOUT Serial Clock Polarity Serial Clock, Schmitt Trigger Serial Data Input, Schmitt Trigger Voltage Reference Output 18 WREN Active High, Flash Write Enable 47 VREF+ Positive Differential Reference Input 19–22 DGND Digital Ground 48 VREF– Negative Differential Reference Input 23 BUFEN Buffer Enable ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TIMING SPECIFICATIONS CS t3 t1 t2 t10 SCLK (POL = 0) SCLK (POL = 1) t4 DIN MSB t2 t6 t5 t 11 LSB (Command or Command and Data) DOUT t7 t8 t9 MSB(1) LSB(1) NOTE: (1) Bit Order = 0. TIMING SPECIFICATION TABLE SPEC DESCRIPTION t1 SCLK Period t2 SCLK Pulse Width, High and Low t3 MIN MAX 4 3 DRDY Periods 200 ns CS Low to first SCLK Edge; Setup Time 0 ns t4 DIN Valid to SCLK Edge; Setup Time 50 ns t5 Valid DIN to SCLK Edge; Hold Time 50 ns t6 Delay between last SCLK edge for DIN and first SCLK edge for DOUT: RDATA, RDATAC, RREG, WREG, RRAM 50 tOSC Periods CSREG, CSRAMX, CSRAM 200 tOSC Periods CSARAM, CSARAMX 1100 tOSC Periods t7 (1) SCLK Edge to Valid New DOUT t8 (1) SCLK Edge to DOUT, Hold Time 0 t9 Last SCLK Edge to DOUT Tri-State NOTE: DOUT goes tri-state immediately when CS goes High. 6 t10 CS Low time after final SCLK edge 0 ns t11 Final SCLK edge of one op code until first edge SCLK of next command: 4 tOSC Periods RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, CSARAM, CSREG, SLEEP, RDATA, RDATAC, STOPC DSYNC 50 ns 10 tOSC Periods ns 16 tOSC Periods 33,000 tOSC Periods CREG, CRAM 220 tOSC Periods RF2R 1090 tOSC Periods CREGA 1600 tOSC Periods CSFL WR2F 76,850 (SPEED = 0) 101,050 (SPEED = 1) SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL SELFCAL RESET (Command, SCLK, or Pin) (1) UNIT tOSC Periods tOSC Periods 4 tOSC Periods 7 DRDY Periods 14 DRDY Periods 2640 tOSC Periods Load = 20pF | | 10kΩ to DGND. 9 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ADS1218 Resets On Falling Edge SCLK Reset Waveform t 13 t13 SCLK t12 t 14 t16 t15 t17 RESET, DSYNC, PDWN DRDY TIMING SPECIFICATION TABLE SPEC 10 DESCRIPTION MIN MAX UNIT t12 SCLK Reset, First High Pulse 300 500 tOSC Periods t13 SCLK Reset, Low Pulse t14 SCLK Reset, Second High Pulse 550 750 tOSC Periods t15 SCLK Reset, Third High Pulse 1050 1250 tOSC Periods t16 Pulse Width 4 tOSC Periods t17 Data Not Valid During this Update Period 4 tOSC Periods 5 tOSC Periods ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA1 PGA2 PGA4 PGA1 PGA2 PGA8 20 20 19 19 18 PGA16 PGA32 PGA64 PGA128 17 16 15 PGA8 18 17 16 PGA32 PGA16 PGA64 PGA128 15 14 14 Sinc3 Filter 13 Sinc3 Filter, Buffer ON 13 12 12 0 500 1000 1500 Decimation Ratio = 2000 0 500 f MOD 1000 Decimation Ratio = fDATA 1500 fMOD 2000 fDATA Figure 1. Figure 2. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA1 21 PGA2 PGA4 PGA1 PGA2 PGA8 20 20 19 19 18 17 PGA16 PGA64 PGA32 PGA4 PGA128 16 18 17 16 15 15 14 Sinc3 Filter, 13 PGA32 14 VREF = 1.25V, Buffer OFF 1000 Decimation Ratio = Figure 3. 1500 fMOD f DATA 2000 PGA128 Sinc3 Filter, VREF = 1.25V, Buffer ON 12 500 PGA64 PGA16 13 12 0 PGA8 21 ENOB (rms) ENOB (rms) PGA4 21 ENOB (rms) ENOB (rms) 21 0 500 1000 Decimation Ratio = 1500 fMOD 2000 fDATA Figure 4. 11 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA1 PGA2 PGA4 PGA8 21 20 20 19 19 ENOB (rms) ENOB (rms) 21 18 17 PGA32 16 PGA64 PGA128 PGA16 15 18 17 16 15 14 14 Sinc2 Filter 13 Fast Settling Filter 13 12 12 0 500 1000 1500 Decimation Ratio = 2000 0 500 1000 fMOD Decimation Ratio = fDATA Figure 5. NOISE vs INPUT SIGNAL 0.5 CMRR (dB) Noise (rms, ppm of FS) 0.6 0.4 0.3 0.2 0.1 −0.5 0.5 1.5 130 120 110 100 90 80 70 60 50 40 30 20 10 0 2.5 1 10 VIN (V) 100 10k 100k Figure 8. PSRR vs FREQUENCY OFFSET vs TEMPERATURE 50 120 110 PGA16 PGA1 100 0 Offset (ppm of FS) 90 80 PSRR (dB) 1k Frequency of CM Signal (Hz) Figure 7. 70 60 50 40 30 −50 PGA64 −100 PGA128 −150 20 10 −200 0 1 10 100 1k 10k Frequency of Power Supply (Hz) Figure 9. 12 fDATA CMRR vs FREQUENCY 0.7 −1.5 2000 Figure 6. 0.8 0 −2.5 1500 fMOD 100k −50 −30 −10 10 30 Temperature (
C) Figure 10. 50 70 90 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. GAIN vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT SIGNAL 1.00010 10 8 1.00002 0.99998 0.99994 4 +85
C 2 0 −2 −4 +25
C −6 0.99990 0.99986 − 40
C 6 INL (ppm of FS) Gain (Normalized) 1.00006 −8 −50 −30 −10 10 30 50 70 −10 −2.5 90 −2 −1.5 −1 −0.5 Figure 11. 0.5 1 1.5 2 2.5 64 128 Figure 12. CURRENT vs TEMPERATURE ADC CURRENT vs PGA 900 250 IDIGITAL AVDD = 5V, Buffer = ON 800 Buffer = OFF 200 700 IANALOG 600 150 I ADC (µA) Current (µA) 0 VIN (V) Temperature (
C) IANALOG I DIGITAL 100 500 AVDD = 3V, Buffer = ON 400 Buffer = OFF 300 200 50 100 0 −50 −30 0 −10 10 30 50 70 90 0 1 Current (µA) HISTOGRAM OF OUTPUT DATA Normal fOSC = 4.91MHz 4000 Normal fOSC = 2.45MHz 200 150 100 Power Down SLEEP fOSC = 2.45MHz 3500 3000 2500 2000 1500 1000 500 0 0 3.0 4.0 VDD (V) Figure 15. 32 4500 Number of Occurrences SLEEP fOSC = 4.91MHz 50 16 Figure 14. SPEED = 0 250 8 Figure 13. DIGITAL CURRENT 300 4 PGA Setting 400 350 2 Temperature (
C) 5.0 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 ppm of FS Figure 16. 13 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. VREFOUT vs LOAD CURRENT OFFSET DAC – OFFSET vs TEMPERATURE 2.55 200 170 Offset (ppm of FSR) VREFOUT (V) 140 2.50 110 80 50 20 −10 −40 −70 2.45 −0.5 −100 0 0.5 1.0 1.5 2.0 2.5 −50 −30 −10 10 30 50 VREFOUT Current Load (mA) Temperature (
C) Figure 17. Figure 18. OFFSET DAC – GAIN vs TEMPERATURE 70 90 IDAC ROUT vs VOUT 1.00020 1.000 1.00016 +85
C 1.000 1.00008 IOUT (Normalized) Normalized Gain 1.00012 1.00004 1.00000 0.99996 0.99992 0.99988 +25
C 0.999 0.999 0.99984 −40
C 0.99980 0.99976 −50 −30 −10 0.998 10 30 50 70 90 0 1 2 3 Temperature (
C) VDD − VOUT (V) Figure 19. Figure 20. IDAC NORMALIZED vs TEMPERATURE 4 5 IDAC MATCHING vs TEMPERATURE 3000 1.01 2000 1000 IDAC Match (ppm) IOUT (Normalized) 1.005 1 0.995 0 −1000 −2000 −3000 −4000 0.99 −5000 0.985 −50 −30 −10 −6000 10 30 Temperature (
C) Figure 21. 14 50 70 90 −50 −30 −10 10 30 Temperature (
C) Figure 22. 50 70 90 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. IDAC INTEGRAL NONLINEARITY RANGE = 1, RDAC = 150kΩ, VREF = 2.5V 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 INL (LSB) DNL (LSB) IDAC DIFFERENTIAL NONLINEARITY RANGE = 1, RDAC = 150kΩ, VREF = 2.5V 0.1 0 −0.1 0.1 0 −0.1 −0.2 −0.2 −0.3 −0.3 −0.4 −0.4 −0.5 −0.5 0 32 64 96 128 160 192 224 255 0 32 64 96 128 160 IDAC Code IDAC Code Figure 23. Figure 24. 192 224 255 15 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 25. For example, if channel 1 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the input pins. AVDD Burnout Current Source On AIN2 BURNOUT CURRENT SOURCES INPUT BUFFER The input impedance of the ADS1218 without the buffer is 5MΩ/PGA. With the buffer enabled, the input voltage range is reduced and the analog power-supply current is higher. The buffer is controlled by ANDing the state of the BUFEN pin with the state of the BUFFER bit in the ACR register. See Application Report Input Currents for High-Resolution ADCs (SBAA090) for more information. AIN3 AIN4 AIN5 Burnout Current Source On AIN6 AGND IDAC1 AIN7 AINCOM Figure 25. Input Multiplexer Configuration TEMPERATURE SENSOR An on-chip diode provides temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diode is connected to the input of the A/D converter. All other channels are 16 In this mode, the output of IDAC1 is also connected to the output pin, so some current may flow into an external load from IDAC1, rather than the diode. See Application Report Measuring Temperature with the ADS1256, ADS1217, or ADS1218 (SBAA073) for more information. When the Burnout bit is set in the ACR configuration register, two current sources are enabled. The current source on the positive input channel sources approximately 2µA of current. The current source on the negative input channel sinks approximately 2µA. This allows for the detection of an open circuit (full-scale reading) or short circuit (0V differential reading) on the selected input differential pair. AIN0 AIN1 open. The anode of the diode is connected to the positive input of the A/D converter, and the cathode of the diode is connected to negative input of the A/D converter. The output of IDAC1 is connected to the anode to bias the diode and the cathode of the diode is also connected to ground to complete the circuit. IDAC1 AND IDAC2 The ADS1218 has two 8-bit current output DACs that can be controlled independently. The output current is set with RDAC, the range select bits in the ACR register, and the 8-bit digital value in the IDAC register. The output current = VREF/(8RDAC)(2RANGE–1)(DAC CODE). With VREFOUT = 2.5V and RDAC = 150kΩ to AGND the full-scale output can be selected to be 0.5mA, 1mA, or 2mA. The compliance voltage range is 0V to within 1V of AVDD. When the internal voltage reference of the ADS1218 is used, it is the reference for the IDAC. An external reference may be used for the IDACs by disabling the internal reference and tying the external reference input to the VREFOUT pin. ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 PGA VRCAP PIN The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5V full-scale range, the A/D converter can resolve to 1µV. With a PGA of 128, on a 40mV full-scale range, the A/D converter can resolve to 75nV. This pin provides a bypass cap for noise filtering on internal VREF circuitry only. As this is a sensitive pin, place the capacitor as close as possible and avoid any resistive loading. The recommended capacitor is a 1000pF ceramic cap. If an external VREF is used, this pin can be left unconnected. CLOCK GENERATOR PGA OFFSET DAC The input to the PGA can be shifted by half the full-scale input range of the PGA by using the ODAC register. The ODAC (Offset DAC) register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Using the ODAC register does not reduce the performance of the A/D converter. See Application Report The Offset DAC (SBAA077) for more information. The clock source for the ADS1218 can be provided from a crystal, oscillator, or external clock. When the clock source is a crystal, external capacitors must be provided to ensure startup and a stable clock frequency; see Figure 26 and Table 1. XIN C1 Crystal MODULATOR XOUT C2 The modulator is a single-loop second-order system. The modulator runs at a clock speed (fMOD) that is derived from the external clock (fOSC). The frequency division is determined by the SPEED bit in the SETUP register. Figure 26. Crystal Connection Table 1. Typical Clock Sources SPEED BIT fMOD 0 fOSC/128 CLOCK SOURCE FREQUENCY C1 C2 PART NUMBER 1 fOSC/256 Crystal 2.4576 0-20pF 0-20pF ECS, ECSD 2.45 - 32 Crystal 4.9152 0-20pF 0-20pF ECS, ECSL 4.91 VOLTAGE REFERENCE INPUT Crystal 4.9152 0-20pF 0-20pF ECS, ECSD 4.91 The ADS1218 uses a differential voltage reference input. The input signal is measured against the differential voltage VREF ≡ (VREF+) – (VREF–). For AVDD = 5V, VREF is typically 2.5V. For AVDD = 3V, VREF is typically 1.25V. Due to the sampling nature of the modulator, the reference input current increases with higher modulator clock frequency (fMOD) and higher PGA settings. Crystal 4.9152 0-20pF 0-20pF CTS, MP 042 4M9182 ON-CHIP VOLTAGE REFERENCE A selectable voltage reference (1.25V or 2.5V) is available for supplying the voltage reference input. To use, connect VREF– to AGND and VREF+ to VREFOUT. The enabling and voltage selection are controlled through bits REF EN and REF HI in the setup register. The 2.5V reference requires AVDD = 5V. When using the on-chip voltage reference, the VREFOUT pin should be bypassed with a 0.1µF capacitor to AGND. CALIBRATION The offset and gain errors in the ADS1218, or the complete system, can be reduced with calibration. Internal calibration of the ADS1218 is called self calibration. This is handled with three commands. One command does both offset and gain calibration. There is also a gain calibration command and an offset calibration command. Each calibration process takes seven tDATA periods to complete. It takes 14 tDATA periods to complete both an offset and gain calibration. Self-gain calibration is optimized for PGA gains less than 8. When using higher gains, system gain calibration is recommended. For system calibration, the appropriate signal must be applied to the inputs. The system offset command requires a zero differential input signal. It then computes an offset that will nullify offset in the system. The system gain command requires a positive full-scale differential input signal. It then computes a value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. 17 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 Calibration must be performed after power on, a change in decimation ratio, or a change of the PGA. For operation with a reference voltage greater than (AVDD– 1.5V), the buffer must also be turned off during calibration. At the completion of calibration, the DRDY signal goes low, which indicates the calibration is finished and valid data is available. See Application Report Calibration Routine and Register Value Generation for the ADS121x Series (SBAA099) for more information. DIGITAL FILTER The Digital Filter can use either the fast settling, sinc2, or sinc3 filter, as shown in Figure 27. In addition, the Auto mode changes the sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the fast settling filter for the next two conversions, the first of which should be discarded. It will then use the sinc2 followed by the sinc3 filter. This combines the low-noise advantage of the sinc3 filter with the quick response of the fast settling time filter. See Figure 28 for the frequency response of each filter. When using the fast setting filter, select a decimation value set by the DEC0 and M/DEC1 registers that is evenly divisible by four for the best gain accuracy. For example, choose 260 rather than 261. 18 Adjustable Digital Filter Sinc3 Modulator Output Sinc2 Data Out Fast Settling FILTER SETTLING TIME FILTER SETTLING TIME (Conversion Cycles) Sinc3 Sinc2 Fast 3(1) 2(1) 1(1) NOTE: (1) With Synchronized Channel Changes. AUTO MODE FILTER SELECTION CONVERSION CYCLE 1 Discard 2 3 4 Fast Sinc2 Sinc3 Figure 27. Filter Step Responses ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 SINC2 FILTER RESPONSE(1) (−3dB = 0.318 • f DATA = 19.11Hz) 0 0 −20 −20 −40 −40 Gain (dB) Gain (dB) SINC3 FILTER RESPONSE(1) (−3dB = 0.262 • fDATA = 15.76Hz) −60 −80 −60 −80 −100 −100 −120 −120 0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 Frequency (Hz) 120 150 180 210 240 270 300 Frequency (Hz) FAST SETTLING FILTER RESPONSE(1) (−3dB = 0.469 • fDATA = 28.125Hz) 0 −20 Gain (dB) −40 −60 −80 −100 −120 0 30 60 90 120 150 180 210 240 270 300 Frequency (Hz) NOTE: (1) fDATA = 60Hz. Figure 28. Filter Frequency Responses DIGITAL I/O INTERFACE SERIAL PERIPHERAL INTERFACE The ADS1218 has eight pins dedicated for digital I/O. The default power-up condition for the digital I/O pins are as inputs. All of the digital I/O pins are individually configurable as inputs or outputs. They are configured through the DIR control register. The DIR register defines whether the pin is an input or output, and the DIO register defines the state of the digital output. When the digital I/O are configured as inputs, DIO is used to read the state of the pin. If the digital I/O are not used, either 1) configure as outputs; or 2) leave as inputs and tie to ground; this prevents excess power dissipation. The Serial Peripheral Interface (SPI) allows a controller to communicate synchronously with the ADS1218. The ADS1218 operates in slave-only mode. Chip Select (CS) The chip select (CS) input of the ADS1218 must be externally asserted before a master device can exchange data with the ADS1218. CS must be low for the duration of the transaction. CS can be tied low. 19 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 Serial Clock (SCLK) REGISTER BANK SCLK, a Schmitt Trigger input, clocks data transfer on the DIN input and DOUT output. When transferring data to or from the ADS1218, multiple bits of data may be transferred back-to-back with no delay in SCLKs or toggling of CS. Make sure to avoid glitches on SCLK because they can cause extra shifting of the data. The operation of the device is set up through individual registers. The set of the 16 registers required to configure the device is referred to as a Register Bank, as shown in Figure 29. Configuration Register Bank 16 bytes SETUP MUX ACR IDAC1 IDAC2 ODAC DIO DIR DEC0 M/DEC1 OCR0 OCR1 OCR2 FSR0 FSR1 FSR2 Polarity (POL) The serial clock polarity is specified by the POL input. When SCLK is active high, set POL high. When SCLK is active low, set POL low. DATA READY The DRDY output is used as a status signal to indicate when data is ready to be read from the ADS1218. DRDY goes low when new data is available. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. RAM 128 Bytes Bank 0 16 bytes Bank 2 16 bytes DSYNC OPERATION FLASH 4k Bytes Page 0 128 bytes Bank 7 16 bytes DSYNC is used to provide for synchronization of the A/D conversion with an external event. Synchronization can be achieved either through the DSYNC pin or the DSYNC command. When the DSYNC pin is used, the filter counter is reset on the falling edge of DSYNC. The modulator is held in reset until DSYNC is taken high. Synchronization occurs on the next rising edge of the system clock after DSYNC is taken high. Page 31 128 bytes MEMORY Three types of memory are used on the ADS1218: registers, RAM, and Flash. 16 registers directly control the various functions (PGA, DAC value, Decimation Ratio, etc.) and can be directly read or written to. Collectively, the registers contain all the information needed to configure the part, such as data format, mux settings, calibration settings, decimation ratio, etc. Additional registers, such as conversion data, are accessed through dedicated instructions. The on-chip Flash can be used to store non-volatile data. The Flash data is separate from the configuration registers and therefore can be used for any purpose, in addition to device configuration. The Flash page data is read and written in 128 byte blocks through the RAM banks; for example, all RAM banks map to a single page of Flash, as shown in Figure 29. 20 Figure 29. Memory Organization RAM Reads and Writes to Registers and RAM occur on a byte basis. However, copies between registers and RAM occurs on a bank basis. The RAM is independent of the Registers; for example, the RAM can be used as general-purpose RAM. The ADS1218 supports any combination of eight analog inputs. With this flexibility, the device could easily support eight unique configurations—one per input channel. In order to facilitate this type of usage, eight separate register banks are available. Therefore, each configuration could be written once and recalled as needed without having to serially retransmit all the configuration data. Checksum commands are also included, which can be used to verify the integrity of RAM. ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 The RAM provides eight banks, with a bank consisting of 16 bytes. The total size of the RAM is 128 bytes. Copies between the registers and RAM are performed on a bank basis. Also, the RAM can be directly read or written through the serial interface on power-up. The banks allow separate storage of settings for each input. The RAM address space is linear; therefore, accessing RAM is done using an auto-incrementing pointer. Access to RAM in the entire memory map can be done consecutively without having to address each bank individually. For example, if you were currently accessing bank 0 at offset 0xF (the last location of bank 0), the next access would be bank 1 and offset 0x0. Any access after bank 7 and offset 0xF will wrap around to bank 0 and Offset 0x0. Although the Register Bank memory is linear, the concept of addressing the device can also be thought of in terms of bank and offset addressing. Looking at linear and bank addressing syntax, we have the following comparison: in the linear memory map, the address 0x14 is equivalent to bank 1 and offset 0x4. Simply stated, the most significant four bits represent the bank, and the least significant four bits represent the offset. The offset is equivalent to the register address for that bank of memory. FLASH Reads and Writes to Flash occur on a Page basis. Therefore, the entire contents of RAM is used for both Read and Write operations. The Flash is independent of the Registers; for example, the Flash can be used as general-purpose Flash. Upon power-up or reset, the contents of Flash Page 0 are loaded into RAM. Subsequently, the contents of RAM Bank 0 are loaded into the configuration register. Therefore, the user can customize the power-up configuration for the device. Care should be taken to ensure that data for Flash Page 0 is written correctly, in order to prevent unexpected operation upon power-up. The ADS1218 supports any combination of eight analog inputs and the Flash memory supports up to 32 unique Page configurations. With this flexibility, the device could support 32 unique configurations for each of the eight analog input channels. For instance, the on-chip temperature sensor could be used to monitor temperature, then different calibration coefficients could be recalled for each of the eight analog input channels based on the change in temperature. This would enable the user to recall calibration coefficients for every 4°C change in temperature over the industrial temperature range, which could be used to correct for drift errors. Checksum commands are also included, which can be used to verify the integrity of Flash. The following two commands can be used to manipulate the Flash. First, the contents of Flash can be written to with the WR2F (write RAM to Flash) command. This command first erases the designated Flash page and then writes the entire content of RAM (all banks) into the designated Flash page. Second, the contents of Flash can be read with the RF2R (read Flash to RAM) command. This command reads the designated Flash page into the entire contents of RAM (all banks). In order to ensure maximum endurance and data retention, the SPEED bit in the SETUP register must be set for the appropriate fOSC frequency. Writing to or erasing Flash can be disabled either through the WREN pin or the WREN register bit. If the WREN pin is low OR the WREN bit is cleared, then the WR2F command has no effect. This protects the integrity of the Flash data from being inadvertently corrupted. Accessing the Flash data either through read, write, or erase may affect the accuracy of the conversion result. Therefore, the conversion result should be discarded when accesses to Flash are done. 21 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 REGISTER MAP Table 2. Registers ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00H SETUP ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER 01H MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 02H ACR BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0 03H IDAC1 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 04H IDAC2 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0 05H ODAC SIGN OSET_6 OSET_5 OSET_4 OSET_3 OSET_2 OSET_1 OSET_0 06H DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0 07H DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0 08H DEC0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 09H M/DEC1 DRDY U/B SMODE1 SMODE0 WREN DEC10 DEC9 DEC8 0AH OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 0BH OCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 0CH OCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 0DH FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 0EH FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 0FH FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 DETAILED REGISTER DEFINITIONS SETUP (Address 00H) Setup Register Reset value is set by Flash memory page 0. Factory programmed to iii01110. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER bits 7-5 Factory Programmed Bits bit 4 SPEED: Modulator Clock Speed 0 : fMOD = fOSC/128 1 : fMOD = fOSC/256 NOTE: When writing to Flash memory using the WR2F command, SPEED must be set as follows: 2.30MHz < fOSC < 3.12MHz → SPEED = 0 3.13MHz < fOSC < 4.12MHz → SPEED = 1 bit 3 REF EN: Internal Voltage Reference Enable 0 = Internal Voltage Reference Disabled 1 = Internal Voltage Reference Enabled bit 2 REF HI: Internal Reference Voltage Select 0 = Internal Reference Voltage = 1.25V 1 = Internal Reference Voltage = 2.5V bit 1 BUF EN: Buffer Enable 0 = Buffer Disabled 1 = Buffer Enabled bit 0 BIT ORDER: Set Order Bits are Transmitted 0 = Most Significant Bit Transmitted First 1 = Least Significant Bit Transmitted First Data is always shifted into the part most significant bit first. Data is always shifted out of the part most significant byte first. This configuration bit only controls the bit order within the byte of data that is shifted out. 22 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 MUX (Address 01H) Multiplexer Control Register Reset value is set by Flash memory page 0. Factory programmed to 01H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 bits 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel Select 0000 = 0001 = 0010 = 0011 = AIN0 AIN1 AIN2 AIN3 0100 0101 0110 0111 = = = = AIN4 AIN5 AIN6 AIN7 0100 0101 0110 0111 = = = = AIN4 AIN5 AIN6 AIN7 1xxx = AINCOM (except when all bits are 1s) 1111 = Temperature Sensor Diode bits 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel Select 0000 = 0001 = 0010 = 0011 = AIN0 AIN1 AIN2 AIN3 1xxx = AINCOM (except when all bits are 1s) 1111 = Temperature Sensor Diode ACR (Address 02H) Analog Control Register Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0 bit 7 BOCS: Burnout Current Source 0 = Disabled 1 = Enabled IDAC Current  8RV 2 REF RANGE
1 (DAC Code) DAC bits 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for IDAC2 00 01 10 11 = = = = Off Range 1 Range 2 Range 3 bits 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for IDAC1 00 01 10 11 = = = = Off Range 1 Range 2 Range 3 bits 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier Gain Selection 000 001 010 011 =1 =2 =4 =8 100 = 101 = 110 = 111 = 16 32 64 128 23 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 IDAC1 (Address 03H) Current DAC 1 Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 The DAC code bits set the output of DAC1 from 0 to full-scale. The value of the full-scale current is set by this Byte, VREF, RDAC, and the DAC1 range bits in the ACR register. IDAC2 (Address 04H) Current DAC 2 Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0 The DAC code bits set the output of DAC2 from 0 to full-scale. The value of the full-scale current is set by this Byte, VREF, RDAC, and the DAC2 range bits in the ACR register. ODAC (Address 05H) Offset DAC Setting Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0 bit 7 Offset Sign 0 = Positive 1 = Negative bits 6-0 Offset  NOTE:   V REF
Code 127 2PGA The offset must be used after calibration or the calibration will notify the effects. DIO (Address 06H) Digital I/O Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 A value written to this register will appear on the digital I/O pins if the pin is configured as an output in the DIR register. Reading this register will return the value of the digital I/O pins. DIR (Address 07H) Direction control for digital I/O Reset value is set by Flash memory page 0. Factory programmed to FFH. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Each bit controls whether the Digital I/O pin is an output (= 0) or input (= 1). The default power-up state is as inputs. 24 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 DEC0 (Address 08H) Decimation Register (least significant 8 bits) Reset value is set by Flash memory page 0. Factory programmed to 80H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant 8 bits. The 3 most significant bits are contained in the M/DEC1 register. M/DEC1 (Address 09H) Mode and Decimation Register Reset value is set by Flash memory page 0. Factory programmed to 07H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DRDY U/B SMODE1 SMODE0 WREN DEC10 DEC09 DEC08 bit 7 DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin. bit 6 U/B: Data Format 0 = Bipolar 1 = Unipolar bits 5-4 U/B ANALOG INPUT DIGITAL OUTPUT 0 +FS Zero –FS 0x7FFFFF 0x000000 0x800000 1 +FS Zero –FS 0xFFFFFF 0x000000 0x000000 SMODE1: SMODE0: Settling Mode 00 01 10 11 bit 3 = Auto = Fast Settling filter = Sinc2 filter = Sinc3 filter WREN: Flash Write Enable 0 = Flash Writing Disabled 1 = Flash Writing Enabled This bit and the WREN pin must both be enabled in order to write to the Flash memory. bits 2-0 DEC10: DEC09: DEC08: Most Significant Bits of the Decimation Value OCR0 (Address 0AH) Offset Calibration Coefficient (least significant byte) Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 25 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 OCR1 (Address 0BH) Offset Calibration Coefficient (middle byte) Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 OCR2 (Address 0CH) Offset Calibration Coefficient (most significant byte) Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 FSR0 (Address 0DH) Full-Scale Register (least significant byte) Reset value is set by Flash memory page 0. Factory programmed to 24H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 FSR1 (Address 0EH) Full-Scale Register (middle byte) Reset value is set by Flash memory page 0. Factory programmed to 90H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 FSR2 (Address 0FH) Full-Scale Register (most significant byte) Reset value is set by Flash memory page 0. Factory programmed to 67H. 26 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 COMMAND DEFINITIONS The commands listed below control the operation of the ADS1218. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes (e.g., WREG requires command, count, and the data bytes). Commands that output data require a minimum of four fOSC cycles before the data is ready (e.g., RDATA). Operands: n = count (0 to 127) r = register (0 to 15) x = don’t care a = RAM bank address (0 to 7) f = Flash memory page address (0 to 31) Table 3. Command Summary COMMANDS DESCRIPTION COMMAND BYTE (1) 2ND COMMAND BYTE RDATA Read Data 0000 0001 (01H) — RDATAC Read Data Continuously 0000 0011 (03H) — STOPC Stop Read Data Continuously 0000 1111 (0FH) — RREG Read from REG Bank rrrr 0001 r r r r (1xH) xxxx_nnnn (# of reg–1) RRAM Read from RAM Bank aaa 0010 0aaa (2xH) xnnn_nnnn (# of bytes–1) — (1) CREG Copy REGs to RAM Bank aaa 0100 0aaa (4xH) CREGA Copy REGS to all RAM Banks 0100 1000 (48H) — WREG Write to REG rrrr 0101 r r r r (5xH) xxxx_nnnn (# of reg–1) WRAM Write to RAM Bank aaa 0110 0aaa (6xH) xnnn_nnnn (# of bytes–1) RF2R Read Flash page to RAM 100f f f f f (8, 9xH) — WR2F Write RAM to Flash page 101f f f f f (A, BxH) — CRAM Copy RAM Bank aaa to REG 1100 0aaa (CxH) — CSRAMX Calc RAM Bank aaa Checksum 1101 0aaa (DxH) — CSARAMX Calc all RAM Bank Checksum 1101 1000 (D8H) — CSREG Calc REG Checksum 1101 1111 (DFH) — CSRAM Calc RAM Bank aaa Checksum 1110 0aaa (ExH) — CSARAM Calc all RAM Banks Checksum 1110 1000 (E8H) — CSFL Calc Flash Checksum 1110 1100 (ECH) — SELFCAL Self Cal Offset and Gain 1111 0000 (F0H) — SELFOCAL Self Cal Offset 1111 0001 (F1H) — SELFGCAL Self Cal Gain 1111 0010 (F2H) — SYSOCAL Sys Cal Offset 1111 0011 (F3H) — SYSGCAL Sys Cal Gain 1111 0100 (F4H) — DSYNC Sync DRDY 1111 1100 (FCH) — SLEEP Put in SLEEP Mode 1111 1101 (FDH) — RESET Reset to Power-Up Values 1111 1110 (FEH) — The data input received by the ADS1218 is always MSB first. The data out format is set by the BIT ORDER bit in ACR reg. 27 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 RDATA Read Data Description: Read a single 24-bit ADC conversion result. On completion of read back, DRDY goes high. Operands: None Bytes: 1 Encoding: 0000 0001 Data Transfer Sequence: DRDY • • • (1) 0000 0001 DIN DOUT xxxx xxxx xxxx xxxx xxxx xxxx MSB Mid−Byte LSB RDATAC Read Data Continuous Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This command eliminates the need to send the Read Data Command on each DRDY. This mode may be terminated by either the STOP Read Continuous command or the RESET command. Operands: None Bytes: 1 Encoding: 0000 0011 Data Transfer Sequence: Command terminated when uuuu uuuu equals STOPC or RESET. DIN 0000 0011 • • • (1) u u uu u u u u uu uu u uu u u uu u uu u u • •• MSB DOUT DRDY Mid−Byte LSB • •• DIN u u uu u u uu u uu u uu uu u u uu u u uu MSB Mid−Byte LSB • •• DOUT NOTE: (1) For wait time, refer to timing specification. 28 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 STOPC Stop Continuous Description: Ends the continuous data output mode. Operands: None Bytes: 1 Encoding: 0000 1111 Data Transfer Sequence: DIN 0000 1111 RREG Read from Registers Description: Output the data from up to 16 registers starting with the register address specified as part of the instruction. The number of registers read will be one plus the second byte. If the count exceeds the remaining registers, the addresses will wrap back to the beginning. Operands: r, n Bytes: 2 Encoding: 0001 rrrr xxxx nnnn Data Transfer Sequence: Read Two Registers Starting from Register 01H (MUX) DIN 0001 0001 0000 0001 • • • (1) DOUT xxxx xxxx xxxx xxxx MUX ACR NOTE: (1) For wait time, refer to timing specification. RRAM Read from RAM Description: Up to 128 bytes can be read from RAM starting at the bank specified in the op code. All reads start at the address for the beginning of the RAM bank. The number of bytes to read will be one plus the value of the second byte. Operands: a, n Bytes: 2 Encoding: 0010 0aaa xnnn nnnn Data Transfer Sequence: Read Two RAM Locations Starting from 20H DIN DOUT 0010 0010 x000 0001 • • • (1) xxxx xxxx xxxx xxxx RAM Data 20H RAM Data 21H NOTE: (1) For wait time, refer to timing specification. 29 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CREG Copy Registers to RAM Bank Description: Copy the 16 control registers to the RAM bank specified in the op code. Refer to timing specifications for command execution time. Operands: a Bytes: 1 Encoding: 0100 0aaa Data Transfer Sequence: Copy Register Values to RAM Bank 3 DIN 1101 1111 • • • (1) xxxx xxxx Checksum DOUT NOTE: (1) For wait time, refer to timing specification. CREGA Copy Registers to All RAM Banks Description: Duplicate the 16 control registers to all the RAM banks. Refer to timing specifications for command execution time. Operands: None Bytes: 1 Encoding: 0100 1000 Data Transfer Sequence: DIN 0100 1000 WREG Write to Register Description: Write to the registers starting with the register specified as part of the instruction. The number of registers that will be written is one plus the value of the second byte. Operands: r, n Bytes: 2 Encoding: 0101 rrrr xxxx nnnn Data Transfer Sequence: Write Two Registers Starting from 06H (DIO) DIN 30 0101 0110 xxxx 0001 Data for DIO Data for DIR ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 WRAM Write to RAM Description: Write up to 128 RAM locations starting at the beginning of the RAM bank specified as part of the instruction. The number of bytes written is RAM is one plus the value of the second byte. Operands: a, n Bytes: 2 Encoding: 0110 0aaa xnnn nnnn Data Transfer Sequence: Write to Two RAM Locations starting from 10H DIN 0110 0001 x000 0001 Data for 10H RF2R Data for 11H Read Flash Memory Page to RAM Description: Read the selected Flash memory page to the RAM. Operands: f Bytes: 1 Encoding: 100f ffff Data Transfer Sequence: Read Flash Page 2 to RAM DIN 1000 0010 WR2F Write RAM to Flash Memory Description: Write the contents of RAM to the selected Flash memory page. Operands: f Bytes: 1 Encoding: 101f ffff Data Transfer Sequence: Write RAM to Flash Memory Page 31 DIN 1011 1111 31 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CRAM Copy RAM Bank to Registers Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers with the data from the RAM bank. Operands: a Bytes: 1 Encoding: 1100 0aaa Data Transfer Sequence: Copy RAM Bank 0 to the Registers DIN 1100 0000 CSRAMX Calculate RAM Bank Checksum Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum. Operands: a Bytes: 1 Encoding: 1101 0aaa Data Transfer Sequence: Calculate Checksum for RAM Bank 3 DIN 1101 0011 • • • (1) xxxx xxxx Checksum DOUT NOTE: (1) For wait time, refer to timing specification. CSARAMX Calculate the Checksum for all RAM Banks Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum. Operands: None Bytes: 1 Encoding: 1101 1000 Data Transfer Sequence: DIN DOUT 1101 1000 • • • (1) xxxx xxxx Checksum NOTE: (1) For wait time, refer to timing specification. 32 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CSREG Calculate the Checksum of Registers Description: Calculate the checksum of all the registers. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum. Operands: None Bytes: 1 Encoding: 1101 1111 Data Transfer Sequence: DIN 1101 1111 • • • (1) xxxx xxxx Checksum DOUT NOTE: (1) For wait time, refer to timing specification. CSRAM Calculate RAM Bank Checksum Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation; there is no masking of bits. Operands: a Bytes: 1 Encoding: 1110 0aaa Data Transfer Sequence: Calculate Checksum for RAM Bank 2 DIN 1110 0010 • • • (1) DOUT xxxx xxxx Checksum NOTE: (1) For wait time, refer to timing specification. CSARAM Calculate Checksum for all RAM Banks Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation; there is no masking of bits. Operands: None Bytes: 1 Encoding: 1110 1000 Data Transfer Sequence: DIN DOUT 1110 1000 • • • (1) xxxx xxxx Checksum NOTE: (1) For wait time, refer to timing specification. 33 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CSFL Calculate Checksum for all Flash Memory Pages Description: Calculate the checksum for all Flash memory pages. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation; there is no masking of bits. Operands: None Bytes: 1 Encoding: 1110 1100 Data Transfer Sequence: DIN 1110 1100 SELFCAL Offset and Gain Self Calibration Description: Starts the process of self calibration. The Offset Control Register (OCR) and the Full-Scale Register (FSR) are updated with new values after this operation. Operands: None Bytes: 1 Encoding: 1111 0000 Data Transfer Sequence: DIN 1111 0000 SELFOCAL Offset Self Calibration Description: Starts the process of self-calibration for offset. The Offset Control Register (OCR) is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0001 Data Transfer Sequence: DIN 1111 0001 SELFGCAL Gain Self Calibration Description: Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with new values after this operation. Operands: None Bytes: 1 Encoding: 1111 0010 Data Transfer Sequence: DIN 34 1111 0010 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 SYSOCAL System Offset Calibration Description: Starts the system offset calibration process. For a system offset calibration, the input should be set to 0V differential, and the ADS1218 computes the OCR register value that will compensate for offset errors. The Offset Control Register (OCR) is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0011 Data Transfer Sequence: DIN 1111 0011 SYSGCAL System Gain Calibration Description: Starts the system gain calibration process. For a system gain calibration, the differential input should be set to the reference voltage and the ADS1218 computes the FSR register value that will compensate for gain errors. The FSR is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0100 Data Transfer Sequence: DIN 1111 0100 DSYNC Sync DRDY Description: Synchronizes the ADS1218 to the serial clock edge. Operands: None Bytes: 1 Encoding: 1111 1100 Data Transfer Sequence: DIN 1111 1100 SLEEP Sleep Mode Description: Puts the ADS1218 into a low-power sleep mode. SCLK must be inactive while in sleep mode. To exit this mode, issue the WAKEUP command. Operands: None Bytes: 1 Encoding: 1111 1101 Data Transfer Sequence: DIN 1111 1101 35 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 WAKEUP Wakeup From Sleep Mode Description: Use this command to wake up from sleep mode. Operands: None Bytes: 1 Encoding: 1111 1011 Data Transfer Sequence: DIN 1111 1011 RESET Reset Registers Description: Copy the contents of Flash memory page 0 to the registers. This command will also stop the Read Continuous mode. Operands: None Bytes: 1 Encoding: 1111 1110 Data Transfer Sequence: DIN 1111 1110 Table 4. ADS1218 Command Map LSB MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 x (1) rdata x rdatac x x x x x x x x x x x stopc 0001 rreg 0 rreg 1 rreg 2 rreg 3 rreg 4 rreg 5 rreg 6 rreg 7 rreg 8 rreg 9 rreg A rreg B rreg C rreg D rreg E rreg F 0010 rram 0 rram 1 rram 2 rram 3 rram 4 rram 5 rram 6 rram 7 x x x x x x x x x 0011 x x x x x x x x x x x x x x x 0100 creg 0 creg 1 creg 2 creg 3 creg 4 creg 5 creg 6 creg 7 crega x x x x x x x 0101 wreg 0 wreg 1 wreg 2 wreg 3 wreg 4 wreg 5 wreg 6 wreg 7 wreg 8 wreg 9 wreg A wreg B wreg C wreg D wreg E wreg F 0110 wram 0 wram 1 wram 2 wram 3 wram 4 wram 5 wram 6 wram 7 x x x x x x x x 0111 x x x x x x x x x x x x x x x x 1000 rf2r 0 rf2r 1 rf2r 2 rf2r 3 rf2r 4 rf2r 5 rf2r 6 rf2r 7 rf2r 8 rf2r 9 rf2r A rf2r B rf2r C rf2r D rf2r E rf2r F 1001 rf2r 10 rf2r 11 rf2r 12 rf2r 13 rf2r 14 rf2r 15 rf2r 16 rf2r 17 rf2r 18 rf2r 19 rf2r 1A rf2r 1B rf2r 1C rf2r 1D rf2r 1E rf2r 1F 1010 wr2f 0 wr2f 1 wr2f 2 wr2f 3 wr2f 4 wr2f 5 wr2f 6 wr2f 7 wr2f 8 wr2f 9 wr2f A wr2f B wr2f C wr2f D wr2f E wr2f F 1011 wr2f 10 wr2f 11 wr2f 12 wr2f 13 wr2f 14 wr2f 15 wr2f 16 wr2f 17 wr2f 18 wr2f 19 wr2f 1A wr2f 1B wr2f 1C wr2f 1D wr2f 1E wr2f 1F 1100 cram 0 cram 1 cram 2 cram 3 cram 4 cram 5 cram 6 cram 7 x x x x x x x x 1101 csramx 0 csramx 1 csramx 2 csramx 3 csramx 4 csramx 5 csramx 6 csramx 7 csramx x x x x x x csreg 1110 csram 0 csram 1 csram2 csram 3 csram 4 csram 5 csram 6 csram 7 csramx x x x csfl x x x 1111 self cal self ocal self gcal sys ocal sys gcal x x x x x x x dsync sleep reset x (1) 36 x = Reserved ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 DEFINITION OF RULES Analog Input Voltage—the voltage at any one analog input relative to AGND. Analog Input Differential Voltage—given by the following equation: (AIN+) – (AIN–). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. The data from the A/D converter is output as codes, which then can be easily converted to other units, such as ppm or volts. The equations and table below show the relationship between bits or codes, ppm, and volts. −20 log(ppm) ENOB
6.02 BITS rms  For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 1, the positive full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when the differential is –2.5V. In each case, the actual input voltages must remain within the AGND to AVDD range. Conversion Cycle—the term conversion cycle usually refers to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time period. However, each digital output is actually based on the modulator results from several tDATA time periods. FILTER SETTING MODULATOR RESULTS Fast Settling 1 tDATA Time Period Sinc2 2 tDATA Time Period Sinc3 3 tDATA Time Period Data Rate—the rate at which conversions are completed. See definition for fDATA. Decimation Ratio—defines the ratio between the output of the modulator and the output Data Rate. Valid values for the Decimation Ratio are from 20 to 2047. Larger Decimation Ratios will have lower noise. Effective Resolution—the effective resolution of the ADS1218 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and Vrms (referenced to input). Computed directly from the converter’s output data, each is a statistical calculation. The conversion from one to the other is shown below. Effective number of bits (ENOB) or effective resolution is commonly used to define the usable resolution of the A/D converter. It is calculated from empirical data taken directly from the device. It is typically determined by applying a fixed known signal source to the analog input and computing the standard deviation of the data sample set. The rms noise defines the ±σ interval about the sample mean. BIPOLAR Vrms 2
V REF PGA 10 UNIPOLAR Vrms   6.02
ER 20   V REF PGA 10  6.02
ER 20 24 298nV 22 1.19µV 149nV 597nV 20 4.77µV 2.39µV 18 19.1µV 9.55µV 16 76.4µV 38.2µV 14 505µV 152.7µV 12 1.22mV 610µV fDATA—the frequency of the digital output data produced by the ADS1218. fDATA is also referred to as the Data Rate. f DATA  f f Decimation   mfactor
Decimation  Ratio Ratio MOD OSC fMOD—the frequency or speed at which the modulator of the ADS1218 is running. This depends on the SPEED bit as shown below: SPEED BIT fMOD 0 fOSC/128 1 fOSC/256 fOSC—the frequency of the crystal input signal at the XIN input of the ADS1218. fSAMP—the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the following equations: PGA SETTING SAMPLING FREQUENCY 1, 2, 4, 8 f SAMP
f OSC mfactor 8 f SAMP
2f OSC mfactor 16 f SAMP
8f OSC mfactor 32 f SAMP
16f OSC mfactor 64, 128 f SAMP
16f OSC mfactor 37 ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 Filter Selection—the ADS1218 uses a (sinx/x) filter or sinc filter. There are three different sinc filters that can be selected. A fast settling filter will settle in one tDATA cycle. The sinc2 filter will settle in two cycles and have lower noise. The sinc3 will achieve lowest noise and higher number of effective bits, but requires three cycles to settle. The ADS1218 will operate with any one of these filters, or it can operate in an auto mode, where it will first select the fast settling filter after a new channel is selected for two readings and will then switch to sinc2 for one reading, followed by sinc3 from then on. For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: [1.25V (positive full-scale) – (–1.25V (negative full-scale))] = 2.5V. Full-Scale Range (FSR)—as with most A/D converters, the full-scale range of the ADS1218 is defined as the input, which produces the positive full-scale digital output minus the input, which produces the negative full-scale digital output. The full-scale range changes with gain setting; see Table 5. where N is the number of bits in the digital output. Least Significant Bit (LSB) Weight—this is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. It is computed as follows: Full−Scale Range LSB Weight
2N tDATA—the inverse of fDATA, or the period between each data output. Table 5. Full-Scale Range versus PGA Setting 5V SUPPLY ANALOG INPUT (1) GAIN SETTING (1) (2) 38 FULL-SCALE RANGE DIFFERENTIAL INPUT VOLTAGES (2) PGA OFFSET RANGE 1 5V ±2.5V ±1.25V 2 2.5V ±1.25V ±0.625V 4 1.25V ±0.625V ±312.5mV 8 0.625V ±312.5mV ±156.25mV 16 312.5mV ±156.25mV ±78.125mV 34 156.25mV ±78.125mV ±39.0625mV 64 78.125mV ±39.0625mV ±19.531mV 128 39.0625mV ±19.531mV ±9.766mV GENERAL EQUATIONS FULL-SCALE RANGE DIFFERENTIAL INPUT VOLTAGES (2) PGA SHIFT RANGE 2V REF PGA
VREF PGA
VREF 2 PGA With a 2.5V reference. The ADS1218 allows common-mode voltage as long as the absolute input voltage on AIN+ or AIN– does not go below AGND or above AVDD. PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1218Y/250 ACTIVE TQFP PFB 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1218Y (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of