ADS1231
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SBAS414D – JULY 2009 – REVISED OCTOBER 2013
24-Bit Analog-to-Digital Converter
for Bridge Sensors
Check for Samples: ADS1231
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
The ADS1231 is a precision, 24-bit analog-to-digital
converter (ADC). With an onboard low-noise
amplifier, onboard oscillator, precision third-order 24bit delta-sigma (ΔΣ) modulator, and bridge power
switch, the ADS1231 provides a complete front-end
solution for bridge sensor applications including
weigh scales, strain gauges, and load cells.
1
2
•
•
•
•
•
•
•
Complete Front-End for Bridge Sensors
Internal Amplifier, Gain of 128
Internal Oscillator
Low-Side Power Switch for Bridge Sensor
Low Noise: 35nVrms
Selectable Data Rates: 10SPS or 80SPS
Simultaneous 50Hz and 60Hz Rejection at
10SPS
Input EMI Filter
External Voltage Reference up to 5V for
Ratiometric Measurements
Simple, Pin-Driven Control
Two-Wire Serial Digital Interface
Supply Range: 3V to 5.3V
Package: SOIC-16
Temperature Range: –40°C to +85°C
The low-noise amplifier has a gain of 128, supporting
a full-scale differential input of ±19.5mV. The ΔΣ ADC
has 24-bit resolution and is comprised of a third-order
modulator and fourth-order digital filter. Two data
rates are supported: 10SPS (with both 50Hz and
60Hz rejection) and 80SPS. The ADS1231 can be
put in a low-power standby mode or shut off
completely in power-down mode.
The ADS1231 is controlled by dedicated pins; there
are no digital registers to program. Data are output
over an easily-isolated serial interface that connects
directly to the MSP430 and other microcontrollers.
The ADS1231 is available in an SO-16 package and
is specified from –40°C to +85°C.
APPLICATIONS
•
•
•
•
Weigh Scales
Strain Gauges
Load Cells
Industrial Process Control
AVDD
CAP
CAP
VREFP
VREFN
DVDD
PDWN
AINP
AINN
EMI
Filter
G = 128
24-Bit
DS ADC
Internal
Oscillator
DRDY/DOUT
SCLK
SPEED
SW
GND
CLKIN
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
ADS1231
SBAS414D – JULY 2009 – REVISED OCTOBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
ADS1231
UNIT
AVDD to GND
–0.3 to +6
V
DVDD to GND
–0.3 to +6
V
100, momentary
mA
Input current
10, continuous
mA
Analog input voltage to GND
–0.3 to AVDD + 0.3
V
Digital input voltage to GND
–0.3 to DVDD + 0.3
V
Human body model (HBM)
JEDEC standard 22, test method A114-C.01, all pins
±2000
V
Charged device model (CDM)
JEDEC standard 22, test method C101, all pins
±500
V
ESD (2)
Maximum junction temperature
+150
°C
Operating temperature range
–40 to +85
°C
Storage temperature range
–60 to +150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAUTION: ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
THERMAL INFORMATION
ADS1231
THERMAL METRIC (1)
SOIC (D)
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance
79.5
θJCtop
Junction-to-case (top) thermal resistance
37.5
θJB
Junction-to-board thermal resistance
37.1
ψJT
Junction-to-top characterization parameter
5.6
ψJB
Junction-to-board characterization parameter
36.7
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C.
All specifications at AVDD = DVDD = VREFP = +5V, VCM = 2.5V and VREFN = GND, unless otherwise noted.
ADS1231
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale input voltage (AINP – AINN)
±0.5VREF / 128
V
VREF = AVDD = 5V
±19.5
mV
VREF = AVDD = 3V
±11.7
mV
Common-mode input range
GND + 1.5
Differential input current
AVDD – 1.5
V
±2
nA
LOW-SIDE POWER SWITCH
On-resistance (RON)
Ω
AVDD = 5V, ISW = 30mA
3.5
5
AVDD = 3V, ISW = 30mA
4
7
Ω
30
mA
Current through switch
SYSTEM PERFORMANCE
Resolution
No missing codes
24
Internal oscillator, SPEED = high
Data rate
SPS
Internal oscillator, SPEED = low
10
SPS
External clock, SPEED = high
fCLKIN / 61,440
SPS
External clock, SPEED = low
fCLKIN / 491,520
SPS
Full settling
4
Conversions
fDATA = 10SPS, AVDD = VREF = 5V
35
nV, rms
fDATA = 80SPS, AVDD = VREF = 5V
102
nV, rms
fDATA = 10SPS, AVDD = VREF = 5V
232
nV, P-P
fDATA = 80SPS, AVDD = VREF = 5V
622
nV, P-P
Differential input, end-point fit
±8
ppm
Digital filter settling time
Noise
Integral nonlinearity (INL)
Bits
80
Input offset error
10
μV
Input offset drift
±20
nV/°C
Gain error
1
%
Gain drift
±2
ppm/°C
Normal-mode rejection (1)
fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS,
internal oscillator
80
100
dB
fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS,
external clock (2)
90
110
dB
Common-mode rejection
At dc
Power-supply rejection
At dc
110
dB
90
100
dB
1.5
AVDD
VOLTAGE REFERENCE INPUT
Voltage reference input (VREF)
AVDD + 0.1
V
Negative reference input (VREFN)
VREF = VREFP – VREFN
GND – 0.1
VREFP – 1.5
V
Positive reference input (VREFP)
VREFN + 1.5
AVDD + 0.1
Voltage reference input current
V
10
nA
DIGITAL INPUT/OUTPUT (DVDD = 3V to 5.3V)
Logic levels
VIH
0.8 DVDD
DVDD + 0.1
V
VIL
GND
0.2 DVDD
V
VOH
IOH = 500μA
VOL
IOL = 500μA
0.2 DVDD
V
0 < VDIGITAL INPUT < DVDD
±10
μA
6
MHz
5
MHz
Input leakage
DVDD – 0.4
External clock input frequency (fCLKIN)
1
Serial clock input frequency (fSCLK)
(1)
(2)
V
4.9152
Specification is assured by the combination of design and final test.
fCLKIN = 4.9152MHz.
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ELECTRICAL CHARACTERISTICS (continued)
Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C.
All specifications at AVDD = DVDD = VREFP = +5V, VCM = 2.5V and VREFN = GND, unless otherwise noted.
ADS1231
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Power-supply voltage (AVDD, DVDD)
3
V
900
μA
Normal mode, AVDD = 5V
900
μA
Standby mode
0.1
μA
Power-down
0.1
μA
Normal mode, DVDD = 3V
60
μA
Normal mode, DVDD = 5V
95
μA
Standby mode, SCLK = high, DVDD = 3V
45
μA
Standby mode, SCLK = high, DVDD = 5V
65
μA
Power-down
0.2
μA
Normal mode, AVDD = DVDD = 3V
2.9
mW
Normal mode, AVDD = DVDD = 5V
5
mW
Analog supply current
Digital supply current
5.3
Normal mode, AVDD = 3V
Power dissipation, total
TEMPERATURE
Operating temperature range
–40
+85
°C
Specified temperature range
–40
+85
°C
4
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PIN CONFIGURATION
D PACKAGE
SO-16
(TOP VIEW)
DVDD
1
16
DRDY/DOUT
GND
2
15
SCLK
CLKIN
3
14
PDWN
SPEED
4
13
AVDD
CAP
5
12
SW
CAP
6
11
GND
AINP
7
10
VREFP
AINN
8
9
VREFN
PIN DESCRIPTIONS
NAME
TERMINAL
ANALOG/DIGITAL
INPUT/OUTPUT
DVDD
1
Digital
Digital power supply
GND
2
Supply
Ground for digital and analog supplies
CLKIN
3
Digital input
DESCRIPTION
External clock input: typically 4.9152MHz. Tie low to activate internal oscillator.
Data rate select:
SPEED
4
CAP
5
CAP
AINP
Digital input
SPEED
DATA RATE
0
10SPS
1
80SPS
Analog
Gain amplifier bypass capacitor connection
6
Analog
Gain amplifier bypass capacitor connection
7
Analog input
Positive analog input
AINN
8
Analog input
Negative analog input
VREFN
9
Analog input
Negative reference input
VREFP
10
Analog input
Positive reference input
GND
11
Supply
Ground for digital and analog supplies
SW
12
Analog
Low-side power switch
AVDD
13
Supply
Analog power supply
PDWN
14
Digital input
Power-down: holding this pin low powers down the entire converter and resets the ADC.
SCLK
15
Digital input
Serial clock: clock out data on the rising edge. Also used to initiate Standby mode. See the Standby
Mode section for more details.
DRDY/DOUT
16
Digital output
Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the first rising edge of SCLK.
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NOISE PERFORMANCE
The ADS1231 offers outstanding noise performance. Table 1 summarizes the typical noise performance with
inputs shorted externally for different data rates and voltage reference values.
The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as:
ENOB = ln (FSR/RMS noise)/ln(2)
The Noise-Free Bits are defined as:
Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2)
Where:
FSR (Full-Scale Range) = VREF/Gain.
Table 1. Noise Performance
DATA RATE
10
80
(1)
6
AVDD and VREF
(V)
RMS NOISE (1)
(nV)
PEAK-TO-PEAK NOISE (1)
(nV)
ENOB
(RMS)
NOISE-FREE BITS
5
35.2
231.9
20.1
17.4
3
33.5
199.2
19.4
16.8
5
102.1
622.1
18.5
15.9
3
80.3
549.6
18.2
15.4
Noise specifications are based on direct measurement of 1024 consecutive samples.
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = REFP = 5V, REFN = GND, and VCM = 2.5V unless otherwise noted.
NOISE vs TIME
NOISE vs TIME
300
300
Data Rate = 10SPS
200
200
150
150
100
50
0
−50
−100
−150
100
50
0
−50
−100
−150
−200
−200
−250
−250
−300
0
200
Data Rate = 80SPS
250
Conversion Data (nV)
Conversion Data (nV)
250
400
600
Time (Reading Number)
800
−300
1000
0
200
400
600
Time (Reading Number)
Figure 1.
NOISE HISTOGRAM
NOISE HISTOGRAM
250
Data Rate = 10SPS
Data Rate = 80SPS
225
400
200
350
175
# of Occurrences
# of Occurrences
450
300
250
200
150
150
125
100
75
100
50
50
25
0
−40−35−30−25−20−15−10 −5 0 5 10 15 20 25 30 35 40
24−bit LSBs
−40−35−30−25−20−15−10 −5 0 5 10 15 20 25 30 35 40
24−bit LSBs
Figure 3.
Figure 4.
NOISE vs INPUT VOLTAGE
NOISE vs INPUT VOLTAGE
150
150
Data Rate = 10SPS
Data Rate = 80SPS
125
RMS Noise (nV)
125
RMS Noise (nV)
1000
Figure 2.
500
0
800
100
75
50
25
0
−20
100
75
50
25
−15
−10
−5
0
5
Input Voltage (mV)
10
15
20
0
−20
Figure 5.
−15
−10
−5
0
5
Input Voltage (mV)
10
15
20
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = REFP = 5V, REFN = GND, and VCM = 2.5V unless otherwise noted.
GAIN ERROR vs TEMPERATURE
0.02
1500
0.015
1000
0.01
Gain Error (%)
Offset (nV)
OFFSET DRIFT vs TEMPERATURE
2000
500
0
-500
0.005
0
-0.005
-1000
-0.01
-1500
-0.015
-2000
-0.02
10
-40 -27.5 -15 -2.5
22.5
35
47.5
60
85
72.5
-40 -27.5 -15 -2.5
22.5
47.5
35
Temperature (°C)
Figure 7.
Figure 8.
INL vs INPUT VOLTAGE
3
60
72.5
85
72.5
85
DATA RATE vs TEMPERATURE
-20°C
-40°C
2
10.2
+25°C
+70°C
Data Rate = 10SPS
10.15
1
10.1
0
Data Rate (SPS)
Integral Nonlinearity (ppm)
10
Temperature (°C)
-1
-2
-3
-4
10.05
10
9.95
-5
9.9
-6
9.85
-7
-20
-15
0
-5
-10
5
10
15
20
9.8
−40 −27.5 −15 −2.5
Input Voltage (mV)
Figure 9.
ANALOG SUPPLY CURRENT vs TEMPERATURE
DIGITAL SUPPLY CURRENT vs TEMPERATURE
120
115
1000
Digital Supply Current (mA)
Analog Supply Current (mA)
60
Figure 10.
1200
800
600
400
200
110
105
100
95
90
85
0
80
-40 -27.5 -15 -2.5
10
22.5
35
47.5
60
72.5
85
-40 -27.5 -15 -2.5
Temperature (°C)
10
22.5
35
47.5
60
72.5
85
Temperature (°C)
Figure 11.
8
10 22.5 35 47.5
Temperature (°C)
Figure 12.
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OVERVIEW
The ADS1231 is a precision, 24-bit ADC that includes
a low-noise PGA, internal oscillator, third-order deltasigma (ΔΣ) modulator, and fourth-order digital filter.
The ADS1231 provides a complete front-end solution
for bridge sensor applications such as weigh scales,
strain gauges, and pressure sensors.
Data can be output at 10SPS for excellent 50Hz and
60Hz rejection, or at 80SPS when higher speeds are
needed. The ADS1231 is easy to configure, and all
digital control is accomplished through dedicated
pins; there are no registers to program. A simple twowire serial interface retrieves the data.
ANALOG INPUTS (AINP, AINN)
The input signal to be measured is applied to the
input pins AINP and AINN. The ADS1231 accepts
differential input signals, but can also measure
unipolar signals.
LOW-NOISE AMPLIFIER
The ADS1231 features a low-drift, low-noise amplifier
that provides a complete front-end solution for bridge
sensors. A simplified diagram of the amplifier is
shown in Figure 13. It consists of two chopperstabilized amplifiers (A1 and A2) and three accurately
matched resistors (R1, RF1, and RF2) that construct a
differential front-end stage with a gain of 128,
followed by gain stage A3 (Gain = 1). The inputs are
equipped with an EMI filter, as shown in Figure 13.
The cutoff frequency of the EMI filter is 20MHz. By
using AVDD as the reference input, the bipolar input
ranges from –19.5mV to +19.5mV. The inputs of the
ADS1231 are protected with internal diodes
connected to the power-supply rails. These diodes
clamp the applied signal to prevent it from damaging
the input circuitry.
External Capacitor
An external capacitor (CEXT) across the two ADS1231
CAP pins combines with the internal resistor RINT (onchip) to create a low-pass filter. The recommended
value for CEXT is 0.1μF which provides a corner
frequency of 720Hz. This low-pass filter serves two
purposes. First, the input signal is band-limited to
prevent aliasing by the ADC and to filter out the highfrequency noise. Second, it attenuates the chopping
residue from the amplifier to improve temperature drift
performance. NPO or C0G capacitors are
recommended. For optimal performance, place the
external capacitor very close to the CAP pins.
VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
The voltage reference used by the modulator is
generated from the voltage difference between
VREFP and VREFN: VREF = VREFP – VREFN. The
reference inputs use a structure similar to that of the
analog inputs. In order to increase the reference input
impedance, switching buffer circuitry is used to
reduce the input equivalent capacitance. The
reference drift and noise impact ADC performance. In
order to achieve best results, pay close attention to
the reference noise and drift specifications. A
simplified diagram of the circuitry on the reference
inputs is shown in Figure 14. The switches and
capacitors can be modeled approximately using an
effective impedance of ZEFF = 500MW.
VREFP
VREFN
AVDD
AVDD
CAP
ESD
Protection
AINP
EMI
Filter
RINT
CBUF
A1
R
Gain = 1
F1
R1
A3
RF2
ADC
Figure 14. Simplified Reference Input Circuitry
RINT
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the voltages
on the reference pins do not go below GND by more
than 100mV, and likewise, do not exceed AVDD by
100mV:
A2
AINN
ZEFF = 500MW
EMI
Filter
CAP
Figure 13. Simplified Diagram of the Amplifier
GND – 100mV < (VREFP or VREFN) < AVDD +
100mV
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LOW-SIDE POWER SWITCH (SW)
CLOCK SOURCE
The ADS1231 incorporates an internal switch for use
with an external bridge sensor, as shown in
Figure 15. The switch can be used in a return path for
the bridge power. By opening the switch, power
dissipation in the bridge is eliminated.
The ADS1231 can use the internal oscillator or an
external clock source to accommodate a wide variety
of applications. Figure 16 shows the equivalent
circuitry of the clock module. The CLK_DETECT
block determines whether an external clock signal is
applied to the CLKIN pin so that the internal oscillator
is bypassed or activated. When the CLKIN pin
frequency is above ~200kHz, the CLK_DETECT
circuit shuts down the internal oscillator and passes
the external clock signal to the ADC. When the
CLKIN pin frequency is below ~200kHz, the
CLK_DETECT block activates the internal oscillator.
When the internal oscillator is chosen, make sure to
connect the CLKIN pin to GND.
The switch is controlled by the ADS1231 conversion
status. During normal conversions, the switch is
closed (the SW pin is connected to GND). During
standby or power-down modes, the switch is opened
(the SW pin is high impedance). When using the
switch, it is recommended that the negative reference
input (VREFN) be connected directly to the bridge
ground terminal, as shown in Figure 15 for best
performance.
+VDD
CLKIN
ADS1231
CLK_DETECT
Internal
Oscillator
VREFP
S0
Bridge
Sensor
S1
MUX
AINP
EN
S
To ADC
AINN
Figure 16. Equivalent Circuitry of the Clock
Source
VREFN
SW
The allowable frequency range for the external clock
signal fCLKIN is specified in the Electrical
Characteristics table.
GND
Figure 15. Low-Side Power Switch
10
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FREQUENCY RESPONSE
0
Data Rate = 10SPS
4
-50
Gain (dB)
The ADS1231 uses a sinc digital filter with the
frequency response shown in Figure 17 for fCLKIN =
4.9152MHz. The frequency response repeats at
multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
-100
To help see the response at lower frequencies,
Figure 17(a) illustrates the nominal response out to
100Hz, when the data rate = 10SPS. Notice that
signals at multiples of 10Hz are rejected, and
therefore simultaneous rejection of 50Hz and 60Hz is
achieved.
-150
0
30
40
50
60
70
80
90
100
(a)
-50
Data Rate = 10SPS
Gain (dB)
The ADS1231 data rate and frequency response
scale directly with clock frequency. For example, if
fCLKIN increases from 4.9152MHz to 5.5296MHz when
the SPEED pin is tied high, the data rate increases
from 80SPS to 90SPS, while the notch also increases
from 80Hz to 90Hz. Note that these changes are only
possible when an external clock source is applied.
20
Frequency (Hz)
The benefit of using a sinc4 filter is that every
frequency notch has four zeros on the same location,
thus providing excellent normal-mode rejection of
line-cycle interference.
Figure 17(b) zooms in on the 50Hz and 60Hz notches
with the SPEED pin tied low (10SPS data rate).
10
-100
-150
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Frequency (Hz)
(b)
Figure 17. Nominal Frequency Response Out To
100Hz
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Table 2. Data Rate Settings
SETTLING TIME
Fast changes in the input signal require time to settle.
For example, an external multiplexer in front of the
ADS1231 can generate abrupt changes in input
voltage by simply switching the multiplexer input
channels. These sorts of changes in the input require
four data conversion cycles to settle. When
continuously converting, five readings may be
necessary in order to settle the data. If the change in
input occurs in the middle of the first conversion, four
more full conversions of the fully-settled input are
required to obtain fully-settled data. Discard the first
four readings because they contain only partiallysettled data. Figure 18 illustrates the settling time for
the ADS1231.
DATA RATE
SPEED PIN
Internal Oscillator
External Clock
0
10SPS
fCLKIN / 491,520
1
80SPS
fCLKIN / 61,440
DATA FORMAT
The ADS1231 outputs 24 bits of data in binary twos
complement format. The least significant bit (LSB)
has a weight of (0.5VREF/128)(223 – 1). The positive
full-scale input produces an output code of 7FFFFFh
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals exceeding full-scale. Table 3 summarizes the
ideal output codes for different input signals.
DATA RATE
Table 3. Ideal Output Code vs Input Signal
The ADS1231 data rate is set by the SPEED pin, as
shown in Table 2. When SPEED is low, the data rate
is nominally 10SPS. This data rate provides the
lowest noise, and also has excellent rejection of both
50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED
high selects a data rate of nominally 80SPS.
INPUT SIGNAL VIN
(AINP – AINN)
IDEAL OUTPUT
≥ +0.5VREF/128
7FFFFFh
(+0.5VREF/128)/(223 – 1)
000001h
0
000000h
(–0.5VREF/128)/(223 – 1)
FFFFFFh
≤ –0.5VREF/128
800000h
1. Excludes effects of noise, INL, offset, and gain
errors.
Abrupt Change in External VIN
VIN
Start of
Conversion
DRDY/DOUT
Conversion
including
unsettled VIN.
1st Conversion;
VIN settled, but
digital filter
unsettled.
2nd Conversion;
VIN settled, but
digital filter
unsettled.
3rd Conversion;
VIN settled, but
digital filter
unsettled.
4th Conversion;
VIN settled, but
digital filter
unsettled.
Conversion
Time
Figure 18. Settling Time in Continuous Conversion Mode
12
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DATA READY/DATA OUTPUT (DRDY/DOUT)
DATA RETRIEVAL
This digital output pin serves two purposes. First, it
indicates when new data are ready by going low.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins
outputting the conversion data, most significant bit
(MSB) first. Data are shifted out on each subsequent
SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an
additional SCLK. It then stays high until new data are
ready. This configuration is useful when polling on the
status of DRDY/DOUT to determine when to begin
data retrieval.
The ADS1231 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes
low, as shown in Figure 19. After DRDY/DOUT goes
low, begin shifting out the data by applying SCLKs.
Data are shifted out MSB first. It is not required to
shift out all 24 bits of data, but the data must be
retrieved before new data are updated (within tCONV)
or else the data will be overwritten. Avoid data
retrieval during the update period (tUPDATE). If only 24
SCLKs have been applied, DRDY/DOUT remains at
the state of the last bit shifted out until it is taken high
(see tUPDATE), indicating that new data are being
updated. To avoid having DRDY/DOUT remain in the
state of the last bit, the 25th SCLK can be applied to
force DRDY/DOUT high, as shown in Figure 20. This
technique is useful when a host controlling the device
is polling DRDY/DOUT to determine when data are
ready.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. This input has built-in hysteresis, but care
should still be taken to ensure a clean signal. Glitches
or slow-rising signals can cause unwanted additional
shifting. For this reason, it is best to make sure the
rise and fall times of SCLK are both less than 50ns.
Data
New Data Ready
Data Ready
MSB
DRDY/DOUT
23
LSB
22
21
0
tPD
tHT
tDS
tSCLK
tUPDATE
1
SCLK
24
tSCLK
tCONV
Figure 19. 24-Bit Data Retrieval Timing
SYMBOL
tDS
DESCRIPTION
MIN
DRDY/DOUT low to first SCLK rising edge
tSCLK
SCLK positive or negative pulse width
tPD (1)
SCLK rising edge to new data bit valid: propagation delay
tHT (1)
SCLK rising edge to old data bit valid: hold time
tUPDATE
tCONV
MAX
UNITS
ns
100
ns
50
20
ns
ns
90
μs
SPEED = 1
12.5
ms
SPEED = 0
100
ms
Data updating: no readback allowed
Conversion time (1/data rate)
TYP
0
(1) Minimum required from simulation.
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ADS1231
SBAS414D – JULY 2009 – REVISED OCTOBER 2013
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STANDBY MODE
When tSTANDBY has passed with SCLK held high,
Standby mode activates. DRDY/DOUT stays high
when Standby mode begins. SCLK must remain high
to stay in Standby mode. To exit Standby mode
(wake up), set SCLK low. The first data after exiting
Standby mode are valid.
Standby
mode
dramatically
reduces
power
consumption by shutting down most of the circuitry.
To enter Standby mode, simply hold SCLK high after
DRDY/DOUT goes low; see Figure 21. Standby mode
can be initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand.
Data
Data Ready
New Data Ready
DRDY/DOUT
23
22
21
0
1
SCLK
24
25
25th SCLK to Force DRDY/DOUT High
Figure 20. Data Retrieval with DRDY/DOUT Forced High Afterwards
Data Ready
Standby Mode
DRDY/DOUT
SCLK
23
22
21
1
0
Start Conversion
23
24
tDSS
tSTANDBY
tS_RDY
Figure 21. Standby Mode Timing (Can be used for single conversions)
SYMBOL
DESCRIPTION
tDSS (1)
SCLK high after DRDY/DOUT
goes low to activate Standby
mode
tSTANDBY
Standby mode activation time
tS_RDY
(1)
MAX
UNITS
SPEED = 1
MIN
12.44
ms
SPEED = 0
99.94
ms
SPEED = 1
12.5
SPEED = 0
100
Data ready after exiting Standby SPEED = 1
mode
SPEED = 0
TYP
ms
ms
52.6
ms
401.8
ms
(1) Based on an ideal internal oscillator.
14
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SBAS414D – JULY 2009 – REVISED OCTOBER 2013
POWER-DOWN MODE
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry. Power-Down mode can be
initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand.
Figure 23 shows the wake-up timing from PowerDown mode.
AVDD
DVDD
PDWN
³ 10ms
Figure 22. Power-Up Timing Sequence
Start
Conversion
Power-Down Mode
tPDWN
Data Ready
CLK Source
Wakeup
PDWN
DRDY/DOUT
tTS_RDY
tWAKEUP
SCLK
Figure 23. Wake-Up Timing from Power-Down Mode
SYMBOL
tWAKEUP (1) (2)
tPDWN
(1)
(2)
(1)
DESCRIPTION
MIN
Wake-up time after Power-Down mode
PDWN pulse width
26
TYP
UNITS
7.95
μs
μs
Based on an ideal internal oscillator.
Typical required from simulation.
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ADS1231
SBAS414D – JULY 2009 – REVISED OCTOBER 2013
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APPLICATION EXAMPLE
Weigh Scale System
Figure 24 shows a typical ADS1231 application as part of a weigh scale system.
3V to 5.3V
3V
(1)
1mF
13
AVDD
10
5
-
VREFP
CAP
DRDY/DOUT
0.1mF
6
SCLK
CAP
+
ADS1231
7
8
VDD
DVDD
(2)
Load
Cell
(1)
1mF
1
PDWN
SPEED
AINP
16
15
14
MSP430x4xx
4
AINN
9
VREFN
12
CLKIN
SW
3
GND
GND
2, 11
(1) Place a 0.1μF or higher capacitor as close as possible on both AVDD and DVDD.
(2) Place capacitor very close to the ADS1231 CAP pins for optimal performance.
Figure 24. Weigh Scale Example
16
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SBAS414D – JULY 2009 – REVISED OCTOBER 2013
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2010) to Revision D
Page
•
Changed "oscillator" to "clock" in data rate parameter of electrical characteristics .............................................................. 3
•
Changed all "fCLK" to "fCLKIN" throughout data sheet ............................................................................................................. 3
•
Deleted extra space in data rate parameter typical value (typo) .......................................................................................... 3
•
Changed "oscillator" to "clock" in data rate parameter of electrical characteristics .............................................................. 3
•
Deleted extra space in data rate parameter typical value (typo) .......................................................................................... 3
•
Changed location of noise parameter ................................................................................................................................... 3
•
Changed "oscillator" to "clock" in normal-mode rejection parameter of electrical characteristics ........................................ 3
•
Changed "AGND" to "GND" in negative reference input parameter min value .................................................................... 3
•
Added new external clock input frequency parameter .......................................................................................................... 3
•
Changed "oscillator" to "fCLKIN" in note 2 of electrical characteristics ................................................................................... 3
•
Changed pin 12 name from PSW to SW in pinout drawing ................................................................................................. 5
•
Changed pin 12 name from PSW to SW in Pin Descriptions table ...................................................................................... 5
•
Changed title of Figure 5 ...................................................................................................................................................... 7
•
Changed title of Figure 6 ...................................................................................................................................................... 7
•
Changed plot title and X-axis label of Figure 9 ..................................................................................................................... 8
•
Changed plot title and Y-axis label of Figure 11 ................................................................................................................... 8
•
Changed plot title and Y-axis label of Figure 12 ................................................................................................................... 8
•
Changed Clock Source section .......................................................................................................................................... 10
•
Added text to first sentence of Frequency Response section ............................................................................................ 11
•
Changed third paragraph of Frequency Response section ................................................................................................ 11
•
Added new text to end of Frequency Response section .................................................................................................... 11
•
Changed Table 2 ................................................................................................................................................................ 12
•
Changed pin numbers in Figure 24 to match the device pinout and added missing CLKIN pin ........................................ 16
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1231ID
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1231
ADS1231IDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1231
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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