ADS1232, ADS1234
ADS1234
SBAS350G – JUNE 2005 – ADS1232,
REVISED JANUARY
2021
SBAS350G – JUNE 2005 – REVISED JANUARY 2021
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ADS123x 2- and 4-Channel, 24-Bit, Delta-Sigma ADCs for Bridge Sensors
1 Features
3 Description
•
•
•
•
•
•
The ADS1232 and ADS1234 (ADS123x) are
precision, 24-bit, analog-to-digital converters (ADCs).
With a low-noise programmable gain amplifier (PGA),
a precision delta-sigma ADC, and internal oscillator,
the ADS123x provide a complete front-end solution
for bridge sensor applications including weigh scales,
strain gauges, and pressure sensors.
•
•
•
•
•
•
•
•
•
•
Complete front-end for bridge sensors
23.5-bits effective resolution at gain = 1
19.2-bits noise-free resolution at gain = 64
Low-noise PGA
Selectable gains of 1, 2, 64, and 128
RMS noise:
– 17 nV at 10 SPS at gain = 128
– 44 nV at 80 SPS at gain = 128
100-dB simultaneous 50-Hz and 60-Hz rejection
Flexible clocking:
– Low-drift internal oscillator
– Optional external crystal
Selectable 10-SPS or 80-SPS data rates
Easy ratiometric measurements:
– External voltage reference up to 5 V
Two-channel differential input with internal
temperature sensor (ADS1232)
Four-channel differential input (ADS1234)
Two-wire serial interface
Supply voltage range: 2.7 V to 5.3 V
Temperature range: –40°C to +105°C
Packages: TSSOP-24 (ADS1232) or TSSOP-28
(ADS1234)
An input multiplexer (MUX) accepts either two
(ADS1232) or four (ADS1234) differential inputs. The
ADS1232 also includes a temperature sensor to
monitor ambient temperature. The low-noise PGA has
a selectable gain of 1, 2, 64, or 128, supporting a fullscale differential input of ±2.5 V, ±1.25 V, ±39 mV, or
±19.5 mV.
The delta-sigma ADC provides a maximum of 23.5bits effective resolution, and supports two data rates:
10 SPS (providing 50-Hz and 60-Hz rejection) and 80
SPS. The ADS123x can be clocked externally using
an oscillator or a crystal, or by the internal oscillator.
Offset calibration is performed on-demand, and the
ADS123x can be put in a low-power standby mode or
shut off completely in power-down mode. The
ADS123x are operated through simple pin-driven
control—there are no digital registers to program.
2 Applications
•
•
•
Data are output over a two-wire serial interface that
connects directly to the MSP430 and other
microcontrollers.
Weigh scales
PLC weight modules
Pressure sensors
Device Information (1)
PART NUMBER
7.80 mm × 4.40 mm
ADS1234
TSSOP (28)
9.70 mm × 4.40 mm
AINP2
AINN2
ADS1234
Only
For all available packages, see the package option
addendum at the end of the data sheet.
CAP
REFP REFN
DVDD
GAIN [1:0]
Gain =
1, 2, 64, or 128
AINP1
AINN1
Input
Mux
BODY SIZE (NOM)
TSSOP (24)
(1)
AVDD
PACKAGE
ADS1232
PDWN
PGA
DRDY/DOUT
DS ADC
AINP3
AINN3
SCLK
Internal Oscillator
AINP4
AINN4
SPEED
External Oscillator
(1)
A1/TEMP
A0
AGND
CAP
CLKIN/XTAL1 XTAL2
DGND
NOTE: (1) A1 for ADS1234, TEMP for ADS1232.
Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SBAS350G – JUNE 2005 – REVISED JANUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................8
6.6 Typical Characteristics.............................................. 10
7 Parameter Measurement Information.......................... 15
7.1 Noise Performance................................................... 15
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................25
9 Application and Implementation.................................. 29
9.1 Application Information............................................. 29
9.2 Typical Application.................................................... 29
10 Power Supply Recommendations..............................32
10.1 Power-Supply Decoupling.......................................32
11 Layout........................................................................... 33
11.1 Layout Guidelines................................................... 33
11.2 Layout Example...................................................... 34
12 Device and Documentation Support..........................35
12.1 Receiving Notification of Documentation Updates..35
12.2 Support Resources................................................. 35
12.3 Trademarks............................................................. 35
12.4 Electrostatic Discharge Caution..............................35
12.5 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2008) to Revision G (January 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document .................1
• Added Device Information, ESD Ratings, Recommended Operating Conditions, and Thermal Information
tables, and Detailed Description, Application and Implementation, Power Supply Recommendations, Layout,
Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections...........1
• Deleted Ordering Information section; all ordering information available in package option addendum located
at end of data sheet............................................................................................................................................ 4
• Added analog input voltage specification to Absolute Maximum Ratings ..........................................................6
• Added digital input voltage specification to Absolute Maximum Ratings ........................................................... 6
• Deleted momentary input current specification from Absolute Maximum Ratings .............................................6
• Added input current note to Absolute Maximum Ratings ...................................................................................6
• Added common-mode voltage condition to Common-Mode Rejection specification in Electrical Characteristics
table.................................................................................................................................................................... 8
• Deleted power-supply rejection (gain = 1) MIN specification from Electrical Characteristics table ................... 8
• Changed power-supply rejection (gain = 1) TYP specification in Electrical Characteristics table ..................... 8
• Changed text in Analog Inputs (AINPX, AINNX) section.................................................................................. 16
• Added ADS1232 Input Channel Selection With A0 and TEMP table............................................................... 16
• Deleted link to Using the MSC121x as a High-Precision Intelligent Temperature Sensor ...............................17
• Changed 10 SPS –3-dB frequency from 3.32 Hz to 2.4 Hz, and 80 SPS –3-dB frequency from 11.64 Hz to 19
Hz..................................................................................................................................................................... 21
• Changed Power-Up Sequence section.............................................................................................................27
• Deleted Thermocouple application from Application Information .................................................................... 29
• Deleted RTDs and Thermistor application from Application Information ......................................................... 29
• Added weigh scale application to Application Information ...............................................................................29
Changes from Revision E (October 2007) to Revision F (February 2008)
Page
• Changed ΔV condition in Common-Mode Rejection specification in Electrical Characteristics table.................8
• Changed AVDD to deltaV in Power-Supply Rejection section in Electrical Characteristics table.......................8
2
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Changes from Revision D (September 2007) to Revision E (October 2007)
Page
• Corrected unit values in Electrical Characteristics table.....................................................................................8
Changes from Revision C (June 2006) to Revision D (September 2007)
Page
• Deleted Logic Level VIH row for CLKIN/XTAL test condition in Electrical Characteristics table..........................8
• Added offset drift and gain drift histogram plots (Figure 6-9 to Figure 6-16) to Typical Characteristics .......... 10
• Changed difference voltage output for PGA = 2 from 323.4mV to 223.4mV in Temperature Sensor section.. 17
• Added text to Voltage Reference Inputs section regarding reference and drift noise.......................................19
• Changed ZEFF equation.................................................................................................................................... 19
• Changed Simplified Reference Input Circuitry figure .......................................................................................19
• Changed Figure 8-4 .........................................................................................................................................20
• Changed text in Settling Time section.............................................................................................................. 22
• Changed Figure 8-7 .........................................................................................................................................22
• Changed Figure 8-8 .........................................................................................................................................22
• Deleted 2nd sentence of Serial Clock Input section......................................................................................... 23
• Added Power-Up Sequence section, with new text and two new figures......................................................... 27
• Changed Weigh-Scale Application figure ........................................................................................................ 29
Changes from Revision B (September 2005) to Revision C (June 2006)
Page
• Deleted last row from Absolute Maximum Ratings table.................................................................................... 6
• Changed Analog Inputs section of Electrical Characteristics table.....................................................................8
• Changed the typical value in last row of Voltage Reference Input section of Electrical Characteristics table.... 8
• Added note 1 to Table 7-1, Table 7-2, Table 7-3, and Table 7-4....................................................................... 15
• Changed fourth sentence in Temperature Sensor section................................................................................17
• Added fifth and sixth sentences to Temperature Sensor section......................................................................17
• Added fourth and fifth sentences to Low-Noise PGA section........................................................................... 18
• Changed Figure 8-2..........................................................................................................................................18
• Changed t11 to t10 in third paragraph of Standby Mode section........................................................................25
• Changed min and max variables of t10 row in table below Figure 8-12............................................................ 25
• Changed Wake-Up Timing From Power-Down Mode figure.............................................................................27
• Added last row and second footnote to table below Wake-Up Timing From Power-Down Mode figure...........27
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SBAS350G – JUNE 2005 – REVISED JANUARY 2021
5 Pin Configuration and Functions
DVDD
1
24
DRDY/DOUT
DVDD
1
28
DRDY/DOUT
DGND
2
27
SCLK
CLKIN/XTAL1
3
26
PDWN
SPEED
XTAL2
4
25
SPEED
20
GAIN1
DGND
5
24
GAIN1
19
GAIN0
DGND
6
23
GAIN0
7
18
AVDD
A1
7
22
AVDD
8
17
AGND
A0
8
21
AGND
CAP
9
16
REFP
CAP
9
20
REFP
DGND
2
23
SCLK
CLKIN/XTAL1
3
22
PDWN
XTAL2
4
21
DGND
5
DGND
6
TEMP
A0
CAP
10
15
REFN
CAP
10
19
REFN
AINP1
11
14
AINP2
AINP1
11
18
AINP2
AINN1
12
13
AINN2
AINN1
12
17
AINN2
AINP3
13
16
AINP4
AINN3
14
15
AINN4
Not to scale
Figure 5-1. ADS1232 PW Package, 24-Pin TSSOP,
Top View
Not to scale
Figure 5-2. ADS1234 PW Package, 28-Pin TSSOP,
Top View
Table 5-1. Pin Functions
PIN
NAME
A0
ADS1234
TYPE
8
8
Digital input
Input MUX select pins. See Table 8-1 and Table 8-2 for more information.
DESCRIPTION
Input MUX select pins. See Table 8-1 and Table 8-2 for more information.
A1
—
7
Digital input
AGND
17
21
Analog
AINN1
12
12
Analog input
Negative analog input channel 1
AINN2
13
17
Analog input
Negative analog input channel 2
AINN3
—
14
Analog input
Negative analog input channel 3
AINN4
—
15
Analog input
Negative analog input channel 4
AINP1
11
11
Analog input
Positive analog input channel 1
AINP2
14
18
Analog input
Positive analog input channel 2
AINP3
—
13
Analog input
Positive analog input channel 3
AINP4
—
16
Analog input
Positive analog input channel 4
AVDD
18
22
Analog
Analog power supply: 2.7 V to 5.3 V
9, 10
9, 10
Analog
PGA bypass, connect a 0.1-µF capacitor to pins 9 and 10
3
3
Digital input
2, 5, 6
2, 5, 6
Digital
24
28
Digital output
CAP
CLKIN/XTAL1
DGND
DRDY/DOUT
Analog ground
External crystal connection 1, or external clock input, or tie low to activate internal oscillator.
See the Clock Sources section for more information.
Digital ground
Dual-purpose output:
Data ready indicates valid data by going low.
Data output outputs data, MSB first, on the first rising edge of SCLK.
DVDD
1
1
Digital
GAIN0
19
23
Digital input
Gain select pins. See the Low-Noise PGA section for more information.
GAIN1
20
24
Digital input
Gain select pins. See the Low-Noise PGA section for more information.
REFN
15
19
Analog input
Negative reference input
REFP
16
20
Analog input
Positive reference input
Digital input
Power-down: hold this pin low to power down and reset the ADC. Toggle the pin at device
power-up. See the Power-Up Sequence section for more information.
PDWN
4
ADS1232
22
26
Digital power supply: 2.7 V to 5.3 V
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Table 5-1. Pin Functions (continued)
PIN
NAME
ADS1232
ADS1234
TYPE
DESCRIPTION
SCLK
23
27
Digital input
Serial clock: clock out data on the rising edge. Also used to initiate offset calibration and
standby modes. See the Offset Calibration Mode and Standby Mode With Offset-Calibration
sections for more information.
SPEED
21
25
Digital input
Data rate select. See the Data Rate section for more information.
TEMP
7
—
Digital input
Temperature sensor select. See Table 8-1 for more information.
XTAL2
4
4
Digital
External crystal connection 2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
Power-supply voltage
MIN
MAX
AVDD to AGND
–0.3
6
DVDD to DGND
–0.3
6
AGND to DGND
–0.3
0.3
UNIT
V
Analog input voltage
AINNx, AINPx, REFP, REFN
AGND – 0.3
AVDD + 0.3
V
Digital input voltage
A0, A1, CLKIN/XTAL1, XTAL2, DRDY/DOUT, GAIN0, GAIN1,
PWDN, SCLK, SPEED
DGND – 0.3
DVDD + 0.3
V
Input current
Continuous, all pins except power-supply pins(2)
10
mA
Temperature
(1)
(2)
–10
Junction, TJ
150
Storage, Tstg
–60
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input and output pins are diode-clamped to the internal power supplies. Limit the input current to 10 mA in the event the analog input
voltage exceeds AVDD + 0.3 V or AGND – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or DGND – 0.3 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Analog power supply
AVDD to AGND
2.7
5.3
V
Digital power supply
DVDD to DGND
2.7
5.3
V
ANALOG INPUTS
Full-scale input voltage
Common-mode input range
V(AINPx) – V(AINNx)
±0.5 VREF / Gain
V
Gain = 1 and 2
AGND – 0.1
AVDD + 0.1
Gain = 64 and 128
AGND + 1.5
AVDD – 1.5
V
VOLTAGE REFERENCE INPUTS
VREF
Voltage reference input
AVDD + 0.1
V
V(REFN)
Negative reference input
VREF = V(REFP) – V(REFN)
AGND – 0.1
1.5
AVDD
V(REFP) – 1.5
V
V(REFP)
Positive reference input
V(REFN) + 1.5
AVDD + 0.1
V
EXTERNAL CLOCK INPUT
fCLK
External clock frequency
0.2
4.9152
8
MHz
5
MHz
SERIAL INTERFACE CLOCK INPUT
f(SCLK)
Serial clock frequency
DIGITAL INPUTS
Input voltage
DGND
DVDD + 0.1
V
–40
105
°C
TEMPERATURE
TA
Operating ambient temperature
6.4 Thermal Information
THERMAL METRIC(1)
ADS1232
ADS1234
PW (TSSOP)
PW (TSSOP)
UNIT
24 PINS
28 PINS
RθJA
Junction-to-ambient thermal resistance
82.4
74.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
25.5
21.9
°C/W
RθJB
Junction-to-board thermal resistance
38.1
32.9
°C/W
ψJT
Junction-to-top characterization parameter
1.3
1.1
°C/W
ψJB
Junction-to-board characterization parameter
37.6
32.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = DVDD = V(REFP) = 5 V, V(REFN) = AGND, and fCLK = 4.9152 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Gain = 1
Differential input current
±3
Gain = 2
±6
Gain = 64, 128
nA
±3.5
SYSTEM PERFORMANCE
Resolution
fDATA
Input offset drift
(4)
CMRR
Common-mode rejection ratio
en
Input-referred noise
Power-supply rejection
10.3
fCLK / 491,520
4
–0.001
±0.0002
0.001
Gain = 1
–5
±0.2
5
Gain = 128
–1
±0.02
1
Gain = 1
±0.3
Gain = 128
±10
0.02
–0.1
±0.01
0.1
Gain = 128
±2.5
Internal oscillator, fDATA = 10 SPS
fIN = 50 Hz or 60 Hz, ±1 Hz
100
110
External oscillator, fDATA = 10 SPS
fIN = 50 Hz or 60 Hz, ±1 Hz
120
130
At DC, gain = 1, ΔV = 1 V, VCM = AVDD / 2
95
110
At DC, gain = 128, ΔV = 0.1 V, VCM = AVDD / 2
95
110
ppm of FS
nV/°C
±0.001
±0.2
% of FSR(1)
µV/°C
–0.02
Gain = 1
SPS
Conversions
±0.0004
Gain = 128
Gain drift
10
External oscillator, SPEED = low
Gain = 1
Gain error(3)
82.4
fCLK / 61,440
Differential input, end-point fit, gain = 64, 128
Input offset error(2)
PSRR
9.75
Bits
80
External oscillator, SPEED = high
Differential input, end-point fit, gain = 1, 2
Integral nonlinearity
Normal-mode rejection ratio
78
Full settling, readings synchronized with A0, A1
pins
Digital filter settling time
NMRR
24
Internal oscillator, SPEED = high
Internal oscillator, SPEED = low
Data rate
INL
No missing codes
%
ppm/°C
dB
dB
See the Noise Performance section
AVDD, at DC, gain = 1, ΔV = 1 V
85
AVDD, at DC, gain = 128, ΔV = 0.1 V
100
dB
120
VOLTAGE REFERENCE INPUT
Input current
10
nA
DIGITAL LOGIC LEVELS
8
VIH
High-level input voltage
VIL
Low-level input voltage
0.7 DVDD
V
0.2 DVDD
VOH
High-level output voltage
IOH = 1 mA
VOL
Low-level output voltage
IOL = 1 mA
DVDD – 0.4
Input leakage current
0 V < VIN < DVDD
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–10
V
V
0.2 DVDD
V
10
µA
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6.5 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = DVDD = V(REFP) = 5 V, V(REFN) = AGND, and fCLK = 4.9152 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Normal mode, AVDD = 3 V, gain = 1, 2
Normal mode, AVDD = 3 V, gain = 64, 128
I(AVDD)
I(DVDD)
PD
(1)
(2)
(3)
(4)
Analog supply current
Digital supply current
Power dissipation, total
Normal mode, AVDD = 5 V, gain = 1, 2
600
1300
1350
2500
650
1300
1350
2500
Standby mode
0.1
1
Power-down
0.1
1
Normal mode, DVDD = 3 V, gain = 1, 2
60
95
Normal mode, DVDD = 3 V, gain = 64, 128
75
120
Normal mode, DVDD = 5 V, gain = 1, 2
95
130
Normal mode, DVDD = 5 V, gain = 64, 128
75
120
Standby mode, SCLK = high, DVDD = 3 V
45
80
Standby mode, SCLK = high, DVDD = 5 V
65
80
Power-down
0.2
1.3
Normal mode, AVDD = DVDD = 3 V, gain = 1, 2
2
4.2
Normal mode, AVDD = DVDD = 5 V, gain = 1, 2
3.7
7.2
Normal mode, AVDD = DVDD = 3 V, gain = 64,
128
4.3
7.9
Normal mode, AVDD = DVDD = 5 V, gain = 64,
128
7.1
13.1
Standby mode, AVDD = DVDD = 5 V
0.3
0.4
Normal mode, AVDD = 5 V, gain = 64, 128
µA
µA
mW
FSR = full-scale range = VREF / Gain.
Input offset error specified after calibration. Recalibration minimizes these errors to the level of noise at any temperature.
Gain errors are calibrated at the factory (AVDD = 5 V, all gains, TA = 25°C).
Specification is assured by the combination of design and final production test.
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6.6 Typical Characteristics
at TA = 25°C, AVDD = DVDD = V(REFP) = 5 V, and V(REFN) = AGND (unless otherwise noted)
25
6
PGA = 1
Data Rate = 10SPS
5
20
15
3
Output Code (LSB)
Output Code (LSB)
4
2
1
−1
−2
−3
10
5
0
−5
−10
−4
−15
−5
−20
PGA = 128
Data Rate = 10SPS
−25
−6
0
200
400
600
800
0
1000
200
Time (Reading Number)
Figure 6-1. Noise Plot
300
800
1000
100
PGA = 128
Data Rate = 10SPS
90
80
70
200
Occurrence
Occurrence
600
Figure 6-2. Noise Plot
PGA = 1
Data Rate = 10SPS
250
400
Time (Reading Number)
150
100
60
50
40
30
20
50
10
0
0
0
−2
−4
4
2
−16
8
16
Output Code (LSB)
Figure 6-3. Noise Histogram
Figure 6-4. Noise Histogram
70
22.5
PGA = 1
Data Rate = 80SPS
17.5
0
−8
Output Code (LSB)
PGA = 128
Data Rate = 80SPS
50
Output Code (LSB)
Output Code(LSB)
12.5
7.5
2.5
−2.5
−7.5
30
10
−10
−30
−12.5
−50
−17.5
−70
−22.5
0
200
400
600
800
1000
0
Time (Reading Number)
Figure 6-5. Noise Plot
10
200
400
600
800
1000
Time (Reading Number)
Figure 6-6. Noise Plot
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6.6 Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = V(REFP) = 5 V, and V(REFN) = AGND (unless otherwise noted)
50
180
PGA = 1
Data Rate = 80SPS
45
40
140
35
120
Occurance
100
80
30
25
20
60
15
40
10
20
5
0
0
−12
0
−6
6
12
−40
0
−20
Output Code (LSB)
Figure 6-7. Noise Histogram
30
20
20
Offset Drift (nV/°C)
14
500
400
300
Figure 6-10. Offset Drift (25°C to 105°C)
20
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
18
16
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
14
Counts
12
Counts
200
Offset Drift (nV/°C)
Figure 6-9. Offset Drift (–40°C to +25°C)
16
100
-500
600
400
500
200
300
0
100
0
-100
0
-200
5
-300
5
-400
10
-500
10
-200
15
-300
15
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
-400
Counts
25
-600
Counts
35
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
25
18
40
Figure 6-8. Noise Histogram
35
30
20
Output Code (LSB)
0
Occurance
PGA = 128
Data Rate = 80SPS
-100
160
10
8
6
12
10
8
6
4
4
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
0
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
2
Gain Drift (ppm/°C)
Gain Drift (ppm/°C)
Figure 6-11. Gain Drift (–40°C to +25°C)
Figure 6-12. Gain Drift (25°C to 105°C)
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6.6 Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = V(REFP) = 5 V, and V(REFN) = AGND (unless otherwise noted)
30
20
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
25
16
14
Counts
20
Counts
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
18
15
10
12
10
8
6
4
5
2
0
Offset Drift (nV/°C)
25
30
15
20
10
0
5
-5
-10
-15
-20
-25
-30
50
40
30
20
10
0
-10
-20
-30
-40
-50
0
Offset Drift (nV/°C)
Figure 6-13. Offset Drift (–40°C to +25°C)
Figure 6-14. Offset Drift (25°C to 105°C)
25
20
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
20
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
18
16
Counts
Counts
14
15
10
12
10
8
6
5
4
2
0
5.5
6.0
5.0
4.0
4.5
3.0
3.5
2.0
2.5
1.0
1.5
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
Gain Drift (ppm/°C)
Gain Drift (ppm/°C)
Figure 6-15. Gain Drift (–40°C to +25°C)
Figure 6-16. Gain Drift (25°C to 105°C)
0.04
1000
PGA = 128
Data Rate = 10SPS
0.03
PGA = 128
Data Rate = 10SPS
Gain Error (%)
Offset (nV)
500
0
0.02
0.01
0
−500
−0.01
−0.02
−1000
−50
−30
−10
10
30
50
70
90
110
−50
−30
Figure 6-17. Offset vs Temperature
12
−10
10
30
50
70
90
110
Temperature (_C)
Temperature (_C)
Figure 6-18. Gain Error vs Temperature
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6.6 Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = V(REFP) = 5 V, and V(REFN) = AGND (unless otherwise noted)
1000
50
PGA = 1
Data Rate = 10SPS
PGA = 128
Data Rate = 10SPS
45
800
40
700
35
RMS Noise (nV)
600
500
400
300
30
25
20
15
200
10
100
5
0
−2.5 −2.0 −1.5 −1.0 −0.5
0
0.5
1.0
1.5
2.0
0
−19
2.5
−14.25 −9.5
2
10
8
15
6
234.375
10
4
156.25
2
78.125
0
0
1
5
0
0
−78.125
−4
−156.25
−15
−6
−234.375
−20
−8
−312.5
−5
−2
−10
−3
−4
−25
1.5
2.0
312.5
−2
−1
1.0
390.625
PGA = 128
2.5
−10
−19
−14.25 −9.5
0
−4.75
4.75
9.5
14.25
−390.625
19
VIN (mV)
VIN (V)
Figure 6-22. Integral Nonlinearity vs Input Signal
Figure 6-21. Integral Nonlinearity vs Input Signal
120
2000
Normal Mode, PGA = 64, 128
Normal Mode, PGA = 1, 2
100
1200
Normal Mode, PGA = 1, 2
800
400
Digital Current (µA)
1600
Analog Current (µA)
19
20
INL (ppmof FSR)
INL (ppm of FSR)
3
0.5
14.25
25
INL (µV)
PGA = 1
0
9.5
Figure 6-20. Noise vs Input Signal
5
−5
−2.5 −2.0 −1.5 −1.0 −0.5
4.75
VIN (mV)
Figure 6-19. Noise vs Input Signal
4
0
−4.75
VIN (V)
INL (nV)
RMS Noise (nV)
900
Normal Mode, PGA = 64, 128
80
Sleep Mode, All PGAs
60
40
20
0
0
−50
−30
−10
10
30
50
70
90
110
−50
−30
Temperature (_C)
−10
10
30
50
70
90
110
Temperature (_C)
Figure 6-23. Analog Supply Current vs Temperature
Figure 6-24. Digital Supply Current vs Temperature
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6.6 Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = V(REFP) = 5 V, and V(REFN) = AGND (unless otherwise noted)
10.06
SPEED = LOW
CLKIN/XTAL1 = LOW (Internal Oscillator)
Data Rate (SPS)
10.01
9.96
9.91
9.86
−50
−30
−10
10
30
50
70
90
110
Temperature (_C)
Figure 6-25. Data Rate vs Temperature
14
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7 Parameter Measurement Information
7.1 Noise Performance
The ADS123x offer outstanding noise performance that can be optimized for a given full-scale range using the
programmable gain amplifier (PGA). Table 7-1 through Table 7-4 summarize the typical noise performance with
inputs shorted externally for different gains, data rates, and voltage reference values. The RMS and peak-topeak noise data are referred to the input.
The effective resolution of the ADC is defined as:
Effective Resolution (Bits) = ln (FSR / RMS Noise) / ln (2)
(1)
The noise-free resolution of the ADC is defined as:
Noise-Free Resolution (Bits)= ln (FSR / Peak-to-Peak Noise) / ln (2)
(2)
where
•
FSR = full-scale range = VREF / gain
Table 7-1. AVDD = 5 V, VREF = 5 V, Data Rate = 10 SPS
GAIN
(1)
RMS NOISE
PEAK-TO-PEAK NOISE(1)
EFFECTIVE
RESOLUTION (Bits)
NOISE-FREE
RESOLUTION (Bits)
1
420 nV
1.79 µV
23.5
21.4
2
270 nV
900 nV
23.1
21.4
64
19 nV
125 nV
22.0
19.2
128
17 nV
110 nV
21.1
18.4
Peak-to-peak noise data are based on direct measurement.
Table 7-2. AVDD = 5 V, VREF = 5 V, Data Rate = 80 SPS
(1)
GAIN
RMS NOISE
PEAK-TO-PEAK NOISE(1)
EFFECTIVE
RESOLUTION (Bits)
NOISE-FREE
RESOLUTION (Bits)
1
1.36 µV
8.3 µV
21.8
19.2
2
850 nV
5.5 µV
21.5
18.8
64
48 nV
307 nV
20.6
18
128
44 nV
247 nV
19.7
17.2
Peak-to-peak noise data are based on direct measurement.
Table 7-3. AVDD = 3 V, VREF = 3 V, Data Rate = 10 SPS
(1)
GAIN
RMS NOISE
PEAK-TO-PEAK NOISE(1)
EFFECTIVE
RESOLUTION (Bits)
NOISE-FREE
RESOLUTION (Bits)
1
450 nV
2.8 µV
22.6
20
2
325 nV
1.8 µV
22.1
19.7
64
20 nV
130 nV
21.2
18.5
128
18 nV
115 nV
20.3
17.6
Peak-to-peak noise data are based on direct measurement.
Table 7-4. AVDD = 3 V, VREF = 3 V, Data Rate = 80 SPS
(1)
PEAK-TO-PEAK NOISE(1)
EFFECTIVE
RESOLUTION (Bits)
NOISE-FREE
RESOLUTION (Bits)
2.2 µV
12 µV
20.4
17.9
1.2 µV
6.8 µV
20.2
17.8
64
54 nV
340 nV
19.7
17.1
128
48 nV
254 nV
18.9
16.5
GAIN
RMS NOISE
1
2
Peak-to-peak noise data are based on direct measurement of 1024 samples.
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8 Detailed Description
8.1 Overview
The ADS1232 and ADS1234 (ADS123x) are highly integrated, 24-bit ADCs that include an input multiplexer,
low-noise PGA, third-order delta-sigma (ΔΣ) modulator, and fourth-order digital filter. With input-referred RMS
noise down to 17 nV, the ADS123x are ideally suited for measuring the very low signals produced by bridge
sensors in applications such as weigh scales, strain gauges, and pressure sensors.
Clocking can be supplied by an external oscillator, an external crystal, or by a precision internal oscillator. Data
can be output at 10 SPS for excellent 50-Hz and 60-Hz rejection, or at 80 SPS when higher speeds are needed.
The ADS123x are easy to configure, and all digital control is accomplished through dedicated pins; there are no
registers to program. A simple two-wire serial interface retrieves the data.
8.2 Functional Block Diagram
CAP
AVDD
ADS1234
Only
DVDD
GAIN [1:0]
Gain =
1, 2, 64, or 128
AINP1
AINN1
AINP2
AINN2
REFP REFN
Input
Mux
PGA
PDWN
DRDY/DOUT
DS ADC
AINP3
AINN3
SCLK
Internal Oscillator
AINP4
AINN4
SPEED
External Oscillator
(1)
A1/TEMP
A0
AGND
CAP
DGND
CLKIN/XTAL1 XTAL2
NOTE: (1) A1 for ADS1234, TEMP for ADS1232.
8.3 Feature Description
8.3.1 Analog Inputs (AINPX, AINNX)
The input signal to be measured is applied to the input pins AINPx and AINNx. The positive internal input is
generalized as AINP, and the negative internal input generalized as AINN. The signal is selected through the
input MUX, which is controlled by pins A0 and TEMP (ADS1232) and pins A0 and A1 (ADS1234), as shown in
Table 8-1 and Table 8-2.
The ADS123x accept differential input signals, but can also accept single-ended signals. When measuring
single-ended signals, it is permissible to connect the negative input (AINNx) to ground only for gain = 1 or 2.
When using gain = 64 or 128, connect AINNx to a level-shift voltage equal to mid-AVDD supply to comply with
the input range requirement. Connect the signal to the positive input (AINPx). When the ADS123x are configured
this way, only half of the converter full-scale range is used because only positive digital output codes are
produced.
The analog and reference inputs are protected by ESD diodes. See Figure 8-3 for the similar connection of the
ESD diodes for the analog inputs.
Table 8-1. ADS1232 Input Channel Selection With A0 and TEMP
MUX PINS
16
SELECTED ANALOG INPUTS
TEMP
A0
POSITIVE INPUT
NEGATIVE INPUT
0
0
AINP1
AINN1
0
1
AINP2
AINN2
1
x
Temperature sensor
Temperature sensor
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Table 8-2. ADS1234 Input Channel Selection With A0 and A1
MUX PINS
SELECTED ANALOG INPUTS
A1
A0
POSITIVE INPUT
NEGATIVE INPUT
0
0
AINP1
AINN1
0
1
AINP2
AINN2
1
0
AINP3
AINN3
1
1
AINP4
AINN3
8.3.2 Temperature Sensor (ADS1232 Only)
On-chip diodes provide temperature-sensing capability. By setting the TEMP pin high, the selected analog inputs
are disconnected and the inputs to the ADC are connected to the anodes of two diodes scaled to 1x and 80x in
current and size, as shown in Figure 8-1. By measuring the difference in voltage of these diodes, temperature
changes can be inferred from a baseline temperature. Typically, the difference in diode voltage is 111.7 mV at
25°C with a temperature coefficient of 379 µV/°C. With PGA gain = 1 and 2, the difference voltage output from
the PGA is 111.7 mV and 223.4 mV, respectively. The temperature sensor function is impossible to use with PGA
gain = 64 and 128.
ADS1232Only
AVDD
10I
1I
AINP
AINN
1X
8X
AINP1
AINN1
AINP2
AINN2
AINP3
AINN3
AINP4
AINN4
ADS1234Only
A1
A0
Figure 8-1. Measurement of the Temperature Sensor in the Input Multiplexer
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8.3.3 Low-Noise PGA
The ADS123x feature a low-drift, low-noise PGA that provides a complete front-end solution for bridge sensors.
A simplified diagram of the PGA is shown in Figure 8-2. The PGA consists of two chopper-stabilized amplifiers
(A1 and A2) and three accurately matched resistors (R1, RF1, and RF2), which construct a differential front-end
stage with a gain of 64, followed by gain stage A3. The PGA inputs are equipped with an EMI filter, as shown in
Figure 8-2. The cut-off frequency of the EMI filter is 19.6 MHz. If the PGA gain is set to 1 or 2, the gain-of-64
stage is bypassed and shut down to save power. With the combination of both gain stages, the PGA gain can be
set to 64 or 128. The PGA gain of the ADS123x is set to 1, 2, 64, or 128 by pins GAIN1 (MSB) and GAIN0
(LSB). Table 8-3 shows the gain setting of the PGA.
Table 8-3. PGA Gain
GAIN[1:0] INPUT PINS
PGA GAIN
00
1
01
2
10
64
11
128
By using AVDD as the reference input, the bipolar input ranges from ±2.5 V to ±19.5 mV, while the unipolar
ranges from 2.5 V to 19.5 mV. When the PGA gain is set to 1 or 2, the absolute inputs can go rail-to-rail without
significant performance degradation. However, the inputs of the ADS123x are protected with internal diodes
connected to the power-supply rails. These diodes clamp the applied signal to prevent damage to the input
circuitry. On the other hand, when the PGA gain is set to 64 or 128, the operating input range is limited to (AGND
+ 1.5 V) to (AVDD – 1.5 V), in order to prevent saturating the differential front-end circuitry and degrading
performance.
CAP
450W
RINT
AINP
18pF
A1
Gain of 1 or 2
RF1
R1
A3
RF2
ADC
RINT
A2
450W
AINN
18pF
CAP
Figure 8-2. Simplified Diagram of the PGA
8.3.3.1 PGA Bypass Capacitor
By applying a 0.1-µF external capacitor (CEXT) across two PGA output pins (pins 9 and 10) and the combination
of the internal 2-kΩ resistor (RINT), a low-pass filter, with a corner frequency of 720 Hz, is created to band limit
the signal path prior to the modulator input. This low-pass filter serves two purposes. First, the input signal is
band-limited to prevent aliasing, as well as to filter high-frequency noise. Second, the low-pass filter attenuates
the chopping residue from the PGA (for gains of 64 and 128 only) to improve temperature drift performance.
High-quality capacitors (such as high-k ceramic or tantalum capacitors) are not required for a general
application. However, high-quality capacitors, such as C0G dielectric ceramic or poly, are recommended for
high-linearity applications.
18
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8.3.4 Voltage Reference Inputs (REFP, REFN)
The voltage reference used by the modulator is generated from the voltage difference between pins REFP and
REFN: VREF = V(REFP) – V(REFN). The reference inputs use a structure similar to that of the analog inputs. In
order to increase the reference input impedance, a switching buffer circuitry is used to reduce the input
equivalent capacitance. The reference drift and noise impact ADC performance. In order to achieve best results,
pay close attention to the reference noise and drift specifications. A simplified diagram of the circuitry on the
reference inputs is shown in Figure 8-3. The switches and capacitors can be modeled with an effective
impedance of:
Z EFF +
1
2f MODC BUF
where
•
•
fMOD = modulator sampling frequency = fCLK / 64 = (76.8 kHz)
CBUF = input capacitance of the buffer
For the ADS123x:
Z EFF +
1
+ 500MW
(2)(76.8kHz)(13fF)
REFP
REFN
ESD
Diodes
AGND
AVDD
SW
SW
CBUF
ZEFF = 500 M
(fMOD = 76.8 kHz)
SW
Figure 8-3. Simplified Reference Input Circuitry
ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on
the reference pins do not go below AGND by more than 100 mV; and likewise, do not exceed AVDD by 100 mV:
AGND – 100 mV < V(REFP) or V(REFN) < AVDD + 100 mV
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8.3.5 Clock Sources
The ADS123x can use an external clock source, external crystal, or internal oscillator to accommodate a wide
variety of applications. Figure 8-4 shows the equivalent circuitry of the clock source. The CLK_DETECT block
determines whether a crystal oscillator or external clock signal is applied to the CLKIN/XTAL1 pin so that the
internal oscillator is bypassed or activated. When the CLKIN/XTAL1 pin frequency is above approximately 200
kHz, the CLK_DETECT output goes low and shuts down the internal oscillator. When the CLKIN/XTAL1 pin
frequency is below approximately 200 kHz, the CLK_DETECT output goes high and activates the internal
oscillator. Connect the CLKIN/XTAL1 pin to ground when the internal oscillator is chosen.
CLKIN/XTAL1
Crystal
Oscillator
CLK_DETECT
Internal
Oscillator
XTAL2
S0
EN
S1
MUX
S
To ADC
Figure 8-4. Equivalent Circuitry of the Clock Source
For crystal operation, connect the 4.9152-MHz crystal across the CLKIN/XTAL1 and XTAL2 pins. Table 8-4
shows the recommended crystal part numbers. As a result of the low-power design of the internal parallelresonant circuit, both the CLKIN/XTAL1 and XTAL2 pins are only for use with the external crystal; do not use
these pins as clock output drivers for external circuitry. No external capacitors are used with the crystal. Place
the crystal as close as possible to the device pins in order to reduce board stray capacitance and in order to help
ensure proper crystal operation.
Table 8-4. Recommended Crystals
MANUFACTURER
FREQUENCY
PART NUMBER
ECS
4.9152 MHz
ECS-49-20-1
ECS
4.9152 MHz
ECS-49-20-4
An external clock oscillator can be used by driving the CLKIN/XTAL1 pin from the oscillator output and leave
XTAL2 disconnected.
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8.3.6 Digital Filter Frequency Response
The ADS123x use a sinc4 digital filter with the frequency response (fCLK = 4.9152 MHz) shown in Figure 8-5. The
frequency response repeats at multiples of the modulator sampling frequency of 76.8 kHz. The overall response
is that of a low-pass filter with a –3-dB cutoff frequency of 2.4 Hz with the SPEED pin tied low (10-SPS data rate)
and 19 Hz with the SPEED pin tied high (80-SPS data rate).
0
fCLK = 4.9152MHz
- 20
- 40
Gain (dB)
- 60
- 80
- 100
- 120
- 140
- 160
- 180
- 200
0
38.4
76.8
Frequency (kHz)
Figure 8-5. Digital Filter Frequency Response
To better demonstrate the response at lower frequencies, Figure 8-6(a) illustrates the response out to 100 Hz,
when the data rate = 10 SPS. Notice that signals at multiples of 10 Hz are rejected, and therefore, simultaneous
rejection of 50 Hz and 60 Hz interference is achieved.
The benefit of using a sinc4 filter is that every frequency notch has four zeros at the same location. This
response, combined with the low-drift internal oscillator, provides an excellent normal-mode rejection of linecycle interference.
Figure 8-6(b) shows the plot enlarged for both 50-Hz and 60-Hz notches with the SPEED pin tied low (10-SPS
data rate). With only a ±3% variation of the internal oscillator, over 100 dB of normal-mode rejection is achieved.
–50
0
Data Rate = 10 SPS
Data Rate = 10 SPS
Gain (dB)
Gain (dB)
–50
–100
–100
–150
–150
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
0
10
20
30
40
50
60
Frequency (Hz)
Frequency (Hz)
(b)
(a)
70
80
90
100
Figure 8-6. Digital Filter Frequency Response to 100 Hz
The ADS123x data rate and frequency response scale directly with clock frequency. For example, if fCLK
increases from 4.9152 MHz to 6.144 MHz when the SPEED pin is tied high, the data rate increases from 80 SPS
to 100 SPS, while filter notches also increase from 80 Hz to 100 Hz. Frequency scaling is only possible when the
external clock source is applied.
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8.3.7 Settling Time
After changing the input multiplexer, the first data are fully settled. In both ADS123x devices, the digital filter is
allowed to settle after toggling either the A1 or A0 pin. Toggling any of these digital pins holds the DRDY/DOUT
line high until the digital filter is fully settled. For example, if A0 changes from low to high, selecting a different
input channel, DRDY/DOUT immediately goes high, and DRDY/DOUT goes low when fully settled data are
ready for retrieval. There is no need to discard any data. Figure 8-7 shows the timing of the DRDY/DOUT line as
the input multiplexer changes.
In certain instances, large or abrupt input changes require four data cycles to settle. One example of such a
change is an external multiplexer in front of the ADS123x, which can cause large changes in input voltage simply
by switching input channels. Another example is toggling the TEMP pin, which switches the internal AINP, AINN
signals to connect to either the external AINPx, AINNx pins or to the TEMP diode (see Figure 8-1).
To acquire fully settled data after an input step change, five readings are required. Five readings are required
because if the change in input occurs in the middle of the first conversion, four additional full conversions of the
fully settled input are required to get fully settled data. Discard the first four readings because they contain only
partially settled data. Figure 8-8 illustrates the settling time for the ADS123x in continuous conversion mode.
A1 or A0
t1
DRDY/DOUT
tS
Figure 8-7. Example of Settling Time After Changing the Input Multiplexer
Table 8-5. Timing Requirements for Figure 8-7
PARAMETER(1)
(1)
tS
Setup time for changing the A1 or A0 pins
t1
Settling time (DRDY/DOUT
held high)
MIN
MAX
UNIT
40
50
μs
SPEED = 1
51
51
ms
SPEED = 0
401
401
ms
Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
Toggled TEMP Pin or Abrupt Change in External VIN
VIN
Start of
conversion.
DRDY/DOUT
1st conversion;
includes
unsettled VIN.
2nd conversion;
VIN settled, but
digital filter
unsettled.
3rd conversion;
VIN settled, but
digital filter
unsettled.
4th conversion;
VIN settled, but
digital filter
unsettled.
5th conversion;
VIN and digital
filter both
settled.
Conversion
Time
Figure 8-8. Settling Time in Continuous Conversion Mode
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8.3.8 Data Rate
The ADS123x data rate is set by the SPEED pin, as shown in Table 8-6. When SPEED is low, the data rate is
nominally 10 SPS. This data rate provides the lowest noise, and also has excellent rejection of both 50-Hz and
60-Hz line-cycle interference. For applications requiring fast data rates, setting SPEED high selects a data rate
of 80 SPS.
Table 8-6. Data Rate Settings
DATA RATE
SPEED
PIN
INTERNAL OSCILLATOR
OR 4.9152-MHz CRYSTAL
EXTERNAL
OSCILLATOR
0
10 SPS
fCLK / 491,520
1
80 SPS
fCLK / 61,440
8.3.9 Data Format
The ADS123x output 24 bits of data in binary two’s complement format. The least significant bit (LSB) has a
weight of 0.5 VREF / (223 – 1). The positive full-scale input produces an output code of 7FFFFFh and the negative
full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding fullscale. Table 8-7 summarizes the ideal output codes for different input signals.
Table 8-7. Ideal Output Code Versus Input Signal (1)
(1)
INPUT SIGNAL VIN
(AINP – AINN)
IDEAL OUTPUT CODE
≥ 0.5 VREF / Gain
7FFFFFh
(0.5 VREF / Gain) / (223 – 1)
000001h
0
000000h
(–0.5 VREF / Gain) / (223 – 1)
FFFFFFh
≤ –0.5 VREF / Gain
800000h
Excludes effects of noise, INL, offset, and gain errors.
8.3.10 Data Ready and Data Output (DRDY/DOUT)
This digital output pin serves two purposes. First, DRDY/DOUT indicates when new data are ready by going low.
Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the
conversion data, most significant bit (MSB) first. Data are shifted out on each subsequent SCLK rising edge.
After all 24 bits have been retrieved, the pin can be forced high with an additional SCLK. DRDY/DOUT then
remains high until new data are ready. This configuration is useful when polling on the status of DRDY/DOUT to
determine when to begin data retrieval.
8.3.11 Serial Clock Input (SCLK)
This digital input shifts serial data out with each rising edge. This input has built-in hysteresis, but care must be
taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this
reason, make sure the rise-and-fall times of SCLK are less than 50 ns.
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8.3.12 Data Retrieval
The ADS123x continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low,
as shown in Figure 8-9. After DRDY/DOUT goes low, begin shifting out the data by applying SCLKs. Data are
shifted out MSB first. Not all 24 bits of data are required to be shifted out, but the data must be retrieved before
new data are updated (within t7) or else the data are overwritten. Avoid data retrieval during the update period
(t6). DRDY/DOUT remains at the state of the last bit shifted out until taken high (see t6), indicating that new data
are being updated. To avoid having DRDY/DOUT remain in the state of the last bit, the user can shift SCLK to
force DRDY/DOUT high, as shown in Figure 8-10. This technique is useful when a host controlling the device is
polling DRDY/DOUT to determine when data are ready.
Data
Data Ready
New Data Ready
MSB
DRDY/DOUT
23
LSB
22
21
0
t4
t5
t3
t2
t6
1
SCLK
24
t3
t7
Figure 8-9. Data Retrieval Timing
Table 8-8. Timing Requirements for Figure 8-9
PARAMETER
(1)
MIN
t2
DRDY/DOUT low to first SCLK rising edge
t3
SCLK positive or negative pulse width
t4
SCLK rising edge to new data bit valid: propagation
delay
t5
SCLK rising edge to old data bit valid: hold time
t6 (1)
Data updating: no readback allowed
t7 (1)
Conversion time (1/data rate)
TYP
MAX
UNIT
0
ns
100
ns
50
ns
0
ns
39
µs
SPEED = 1
12.5
SPEED = 0
100
ms
Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to the CLK period.
Data
Data Ready
New Data Ready
DRDY/DOUT
23
1
SCLK
22
21
0
24
25
25th SCLK to Force DRDY/DOUT High
Figure 8-10. Data Retrieval With DRDY/DOUT Forced High Afterwards
24
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8.4 Device Functional Modes
In addition to the active conversion mode, the device has other functional modes: offset calibration mode (to
calibrate the ADC internal offset), standby mode (saving power when not converting), and a power-down mode
(for complete device shutdown).
8.4.1 Offset Calibration Mode
Offset calibration can be initiated at any time to remove the ADS123x offset error. To initiate offset calibration,
apply at least two additional SCLKs after retrieving 24 bits of data. Figure 8-11 shows the timing pattern. The
25th SCLK sends DRDY/DOUT high. The falling edge of the 26th SCLK begins the calibration cycle. Additional
SCLK pulses can be sent after the 26th SCLK; however, minimize activity on SCLK during offset calibration for
best results. The analog input pins are disconnected within the ADC and the appropriate signal is applied
internally to perform the calibration.
When the calibration is completed, DRDY/DOUT goes low, indicating that new data are ready. The first
conversion after a calibration is fully settled and valid for use. The offset calibration takes exactly the same time
as specified in (t8) right after the falling edge of the 26th SCLK.
Data Ready After Calibration
DRDY/DOUT
23
22
21
0
23
Calibration Begins
SCLK
1
24
25
26
t8
Figure 8-11. Offset-Calibration Timing
Table 8-9. Timing Requirements for Figure 8-11
PARAMETER
t8 (1)
(1)
First data ready after calibration
MIN
MAX
SPEED = 1 (80 SPS)
101.28
101.29
SPEED = 0 (10 SPS)
801.02
801.03
UNIT
ms
Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to the CLK period. Expect a ±3% variation when
the internal oscillator is used.
8.4.2 Standby Mode
Standby mode dramatically reduces power consumption by shutting down most of the circuitry. In standby mode,
the entire analog circuitry is powered down and only the clock source circuitry is awake to reduce the wake-up
time from the standby mode. To enter standby mode, simply hold SCLK high after DRDY/DOUT goes low; see
Figure 8-12. Standby mode can be initiated at any time during readback; all 24 bits of data are not required to be
retrieved beforehand.
When t10 has passed with SCLK held high, standby mode activates. DRDY/DOUT stays high when standby
mode begins. SCLK must remain high to stay in standby mode. To exit standby mode (wakeup), set SCLK low.
The first data after exiting standby mode is valid.
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Data Ready
Standby Mode
DRDY/DOUT
SCLK
23
22
21
0
1
Start Conversion
23
24
t9
t10
t11
Figure 8-12. Standby Mode Timing (Can be Used for Single Conversions)
Table 8-10. Timing Requirements for Figure 8-12
PARAMETER
t9 (1)
t10 (1)
t11 (1)
(1)
SCLK high after DRDY/DOUT goes
low to activate standby mode
Standby mode activation time
Data ready after exiting standby mode
SPEED = 1
MIN
MAX
UNIT
0
12.44
ms
99.94
SPEED = 0
0
SPEED = 1
12.46
SPEED = 0
99.96
SPEED = 1
52.51
52.51
SPEED = 0
401.8
401.8
ms
ms
Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to the CLK period. Expect a ±3% variation when
an internal oscillator is used.
8.4.3 Standby Mode With Offset-Calibration
Offset-calibration can be set to run immediately after exiting standby mode. This feature is useful when the
ADS123x is put in standby mode for long periods of time, and offset-calibration is desired afterwards to
compensate for temperature or supply voltage changes.
To force an offset-calibration with standby mode, shift 25 SCLKs and take the SCLK pin high to enter standby
mode. Offset-calibration then begins after wake-up; Figure 8-13 shows the appropriate timing. Note the extra
time needed after wake-up for calibration before data are ready. The first data after standby mode with offsetcalibration is fully settled and can be used right away.
Data Ready After Calibration
Standby Mode
DRDY/DOUT
SCLK
23
22
21
0
1
24
23
Begin Calibration
25
t10
t12
Figure 8-13. Standby Mode With Offset-Calibration Timing (Can be Used for Single Conversions)
Table 8-11. Timing Requirements for Figure 8-13
PARAMETER
t12 (1)
(1)
26
Data ready after exiting standby mode SPEED = 1
and calibration
SPEED = 0
MIN
MAX
UNIT
103
103
ms
803
803
Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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8.4.4 Power-Down Mode
Power-down mode shuts down the entire ADC circuitry and reduces the total power consumption close to zero.
To enter power-down mode, hold the PDWN pin low. Power-down mode also resets the entire circuitry to free the
ADC circuitry from locking up to an unknown state. Power-down mode can be initiated at any time during
readback; not all 24 bits of data must be retrieved beforehand. Figure 8-14 shows the wake-up timing from
power-down mode.
Start
Conversion
Data Ready
Power-Down Mode
t14
PDWN
CLK Soure
Wakeup
DRDY/DOUT
t13
t11
SCLK
Figure 8-14. Wake-Up Timing From Power-Down Mode
Table 8-12. Timing Requirements for Figure 8-14
PARAMETER
t13
Wake-up time after power-down mode
MIN
TYP
UNIT
Internal clock
7.95
µs
External clock
0.16
µs
5.6
ms
Crystal
t14 (2)
(1)
(2)
oscillator(1)
PDWN pulse duration
26
µs
No capacitors on CLKIN/XTAL1 or XTAL2 outputs.
Value given for fCLK = 4.9152 MHz. For different fCLK frequencies, the scale is proportional to the CLK period except for a ±3% variation
when an internal oscillator is used.
8.4.5 Power-Up Sequence
When powering up the ADS123x, follow the prescribed PWDN pin sequence as shown in Figure 8-15. At powerup, hold the PWDN pin low until after AVDD and DVDD have stabilized above the minimum specified voltage
levels. After an initial delay where PWDN must be held low (t15), take PWDN high then toggle PWDN low to high
with pulse durations (t16 and t17) as shown in Figure 8-15 and Table 8-13. The ADC then begins operation as
shown in Figure 8-14 and Table 8-12. Control PDWN by the host processor to provide the required power-on
timing.
AVDD
DVDD
PWDN
t15
t16
t17
Figure 8-15. Power-Up Timing Sequence
Table 8-13. Power-up Timing Requirements for Figure 8-15
MIN(1)
UNIT
Delay time, PWDN high after AVDD, DVDD stable
10
µs
t16
Pulse duration, PWDN high
26
µs
t17
Pulse duration, PWDN low
26
µs
PARAMETER
t15
(1)
fCLK = 4.9152 MHz. For fCLK < 4.9152 MHz, adjust the PWDN delay time and pulse duration accordingly.
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8.4.6 Summary of Serial Interface Waveforms
Figure 8-16 summarizes the serial interface waveforms.
DRDY/DOUT
23
22
21
0
MSB
SCLK
LSB
1
24
(a) Data Retrieval
DRDY/DOUT
23
SCLK
22
21
0
1
24
25
(b) Data Retrieval with DRDY/DOUT Forced High Afterwards
Data Ready
After Calibration
DRDY/DOUT
23
SCLK
22
21
0
1
24
Calibration Begins
25
26
(c) Offset−Calibration Timing
Data Ready
Standby Mode
23
DRDY/DOUT
22
21
0
Start
Conversion
SCLK
1
24
(d) Standby Mode/Single Conversions
Data Ready
After Calibration
Standby Mode
DRDY/DOUT
23
22
21
0
Calibration Begins
SCLK
1
24
25
(e) Standby Mode/Single Conversions with Offset Calibration
Figure 8-16. Summary of Serial Interface Waveforms
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The ADS123x devices are high-resolution, 24-bit ADCs with an integrated low-noise PGA. Best performance is
achieved by following the guidelines and recommendations described in the Typical Application section.
9.2 Typical Application
Figure 9-1 shows a circuit diagram of the ADS1232 as part of a weigh scale system. In this setup, the ADS1232
is configured to channel 1 input, gain = 128, and 10 SPS data rate. Gain = 128 is selected by tying the GAIN[1:0]
pins to logic high (3 V in this example). Input channel 1 and data rate = 10 SPS are selected by tying input
channel select pins A0 and TEMP to ground, and by tying the data rate select pin SPEED to ground. The
unused channel 2 inputs are tied to ground.
The internal oscillator is selected by grounding the CLKIN/XTAL1 pin. The other clock options are 1) 4.9152-MHz
crystal across the CLKIN/XTAL1 and XTAL2 pins, or 2) apply a clock to the CLKIN/XTAL1 pin (pin XTAL2
unconnected). The PWDN pin of the ADC is routed to the controller because this pin must be toggled after the
ADC is powered. The bridge excitation voltage is connected to the ADC reference input pins (REFP, REFN). Not
shown in Figure 9-1 are R-C input filters for the signal and reference inputs. If these filters are used, match the
filter time constants to maintain cancellation of noise common to both signal and reference inputs.
5V
3V
0.1mF
18
1
AVDD
VDD
DVDD
20
ADS1232
16
9
0.1mF
10
-
REFP
GAIN1
GAIN0
CAP
DRDY/DOUT
CAP
+
SCLK
PDWN
11
12
14
13
19
Gain = 128
AINP1
XTAL2
24
23
22
4
MSP430x4xx
or Other
Microprocessor
AINN1
AINP2
CLKIN/XTAL1
AINN2
SPEED
3
21
8
A0
7
15
REFN
AGND
17
TEMP
DGND
2, 5, 6
GND
Figure 9-1. Weigh-Scale Application
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9.2.1 Design Requirements
Table 9-1 summarizes the design performance goals. Table 9-2 summarizes the system design parameters.
Table 9-1. Design Goals
DESIGN GOAL
Noise-free resolution
VALUE
80,000 counts / 130,000 counts (post averaging)
Sample rate
10 SPS
Input step settling time
500 ms / 900 ms (post averaging)
50-Hz and 60-Hz noise rejection
>100 dB
Table 9-2. Design Parameters
DESIGN PARAMETERS
DESIGN VALUE
Bridge resistance
1 kΩ
Bridge excitation voltage
5V
Load cell sensitivity
2 mV/V
Bridge full-scale output
10 mV
ADC analog power supply
5V
Host controller and ADC digital power supply
3V
9.2.2 Detailed Design Procedure
Common performance metrics of a weigh scale are noise-free resolution (or counts) and offset and gain stability
(drift) after calibrating the weigh scale. Table 7-1 to Table 7-4 illustrate ADC noise performance expressed as an
input-referred quantity over gain, data rate, and analog supply voltage.
In this design example, the ADC analog supply voltage (5 V) is used as the bridge excitation voltage. 5-V
excitation optimizes the bridge signal output compared to 3-V excitation and also has the benefit of optimizing
the ADC conversion noise. Gain = 128 is selected because it also provides optimal noise performance. The front
end circuitry of the ADC easily accommodates the 10-mV bridge output. In summary, the ADC configuration that
yields the highest resolution while achieving the sample rate and settling time requirements is AVDD = 5 V,
bridge excitation = 5 V, gain = 128, and sample rate = 10 SPS.
Signal-to-noise performance is improved by using a higher gauge-factor bridge (example 3 mV/V bridge), or by
increasing the excitation voltage. If the excitation voltage > 5 V, a voltage divider is required to reduce the
voltage at the ADC reference inputs.
Noise-free counts are improved by post averaging the data (for example, a moving-average filter performed in
the microcontroller). A moving average filter reduces noise by a factor of √N, where N is the number of readings
averaged. However, a moving average filter increases the input step settling time due to the latency caused by
averaging.
The other key performance attributes are DC offset and gain drift, and 50-Hz and 60-Hz noise rejection. Figure
6-14 and Figure 6-16 illustrate the distributions of offset and gain drift performance. 50-Hz and 60-Hz noise
rejection is described in Figure 8-6. The ADC provides over 100-dB rejection with ±3% variation of the ADC
clock frequency.
9.2.3 Application Curves
To evaluate the ADC's noise performance, four fixed-value, 1-kΩ low-drift precision resistors are connected in a
bridge arrangement to simulate a bridge sensor. The simulator provides the same thermal noise generated by a
physical bridge. One of the four bridge resistors is modified to 1.008 kΩ in order to provide a 10-mV output
signal. The 10-mV signal is typical of a 2-mV/V load cell using 5-V excitation.
30
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Figure 9-2 shows the ADC performance with data taken over a 60-second period. The 60-second period reveals
true ADC peak-to-peak noise performance. Figure 9-3 shows the same conversion data processed by an
external moving average filter (average x4). The noise-free resolution of the ADC is approximately 85,000
counts. Over the same 60-second period, the moving average filter improves noise-free resolution to 135,000
counts. The noise-free resolution (bits) corresponding to unfiltered and filtered data are 16.3 bits and 17.1 bits.
See Equation 2 to calculate noise-free resolution in bits. In order to evaluate the actual noise-free resolution of
the system, the 10-mV signal is used in the calculation, rather than the full input range of the ADC (39 mV =
VREF / 128),
As shown in the noise plots, the moving average filter reduces noise by approximately one-half. As a
consequence of the post filter operation, the input step settling time increases from 500 ms to 900 ms (500 ms
because of the ADC settling response time, 400 ms because of the post-averaging filter).
10.00665
10.00665
10 SPS
V IN = 10 mV
eN = 118 nV p-p
10.00660
Conversion Data (mV)
Conversion Data (mV)
10.00660
10 SPS
V IN = 10 mV
eN = 72 nV p-p
10.00655
10.00650
10.00655
10.00650
10.00645
10.00645
10.00640
10.00640
0
10
20
30
Time (s)
40
50
60
0
D160
Figure 9-2. Unfiltered Conversion Data
10
20
30
Time (s)
40
50
60
D161
Figure 9-3. Filtered Conversion Data
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10 Power Supply Recommendations
At device power-on, follow the PWDN pin toggle sequence as detailed in the Power-Up Sequence section.
The ADC has an analog power supply (AVDD) and digital power supply (DVDD). The supply range is 2.7 V to
5.25 V. The analog and digital supplies can be tied together, however the digital power supply must be clean and
free of glitches and transients, which can be generated by the operation of LEDs, relays, and so forth. The
bridge excitation voltage is often the same as the ADC supply voltage, so it is important the supply voltage is
free of transients.
Voltage ripple produced by switching power supplies can also degrade ADC performance. The use a lowdropout regulator (LDOs) can reduce voltage ripple caused by switching power supplies.
10.1 Power-Supply Decoupling
Good power-supply decoupling is important in order to achieve rated performance. The power supplies must be
decoupled close to the power-supply pins using short, direct connections to ground. For both analog and digital
power supplies, connect a 0.1-µF capacitor (X7R-dielectric ceramic) from the power-supply pins to the ground
plane.
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11 Layout
Good layout practices are crucial to realize the full-performance of the ADC. Poor grounding can quickly degrade
the noise performance. The following layout guidelines help provide the best results.
11.1 Layout Guidelines
For best performance, dedicate a PCB layer to a ground plane and do not route any other signal traces on this
layer. However, depending on space limitations, a dedicated ground plane may not be practical. If a continuous
ground plane is not possible, connect the individual plane segments in one place at the ADC.
Route digital traces away from the PGA output pins (CAP) and away from all analog inputs and associated
components in order to minimize interference. Maintain differential trace routing for the input signal and
reference signal to minimize RFI susceptibility.
Use C0G capacitors for analog and reference input filters and the PGA output capacitor in high-linearity
applications. High-K type capacitors (such as Y5V and X7R) should be avoided. Place supply bypass and the
PGA bypass capacitors as close as possible to the device pins using short, direct traces. For optimum
performance, use low-impedance connections (such as multiple vias) on the ground-side connections of the
bypass capacitors.
Avoid long traces on DRDY/DOUT, because high trace capacitance can lead to increased ADC noise. Use a
series resistor or a local buffer if long traces are used. When applying an external clock, be sure the clock is free
of overshoot and glitches. A source-termination resistor placed at the clock buffer helps control reflections and
overshoot. Glitches present on the clock signal can lead to increased noise and possible mis-operation and must
be avoided.
Figure 11-1 illustrates a PCB layout example. Separate 5-V analog and a 3.3-V digital supplies are shown. The
ADC configuration is through hard-tie of the control pins as shown in Table 11-1.
Table 11-1. Layout Example Pin Connections
MODE
PIN CONTROL
VOLTAGE
Data rate = 10 SPS
SPEED
0V
Gain = 128
GAIN[1:0]
3.3 V
Input = channel 1
A0, TEMP
0V
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11.2 Layout Example
3.3 V
47
0.1 µF
ADC Clock Options:
DVDD
1
24
DRDY/DOUT
DGND
2
23
SCLK
CLKIN/XTAL1
3
22
PWDN
XTAL2
4
21
SPEED
DGND
5
20
GAIN1
DGND
6
19
GAIN0
TEMP
7
18
AVDD
A0
8
17
AGND
CAP
9
16
REFP
CAP
10
15
REFN
AINP1
11
14
AINP2
12
13
AINN2
Option 1: To enable INTERNAL
oscillator, tie CLKIN/XTAL1 to
GND
Option 2: Connect EXTERNAL
clock source to CLKIN/XTAL1
Option 3: Connect crystal
directly between CLKIN/XTAL1
and XTAL2
ADS1232
47
To microcontroller
47
5V
0.1 µF
0.1 µF
AINN1
10 nF
10 nF
_
Signal Input
+
100
100
100
100
_
+
Reference Input
_
+
Excitation Output
Figure 11-1. ADS1232 Layout Example
34
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: ADS1232 ADS1234
ADS1232, ADS1234
www.ti.com
SBAS350G – JUNE 2005 – REVISED JANUARY 2021
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: ADS1232 ADS1234
35
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS1232IPW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1232IPWG4
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1232IPWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1232IPWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1234IPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1234
ADS1234IPWG4
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1234
ADS1234IPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1234
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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