ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
24-Bit Analog-to-Digital Converter
For Bridge Sensors
FEATURES
DESCRIPTION
1
•
•
•
•
2
•
•
•
•
•
•
•
•
•
•
•
Complete Front-End for Bridge Sensors
Up to 23.5 Effective Bits
Onboard, Low-Noise PGA
RMS Noise:
17nV at 10SPS (PGA = 128)
44nV at 80SPS (PGA = 128)
19.2-Bit Noise-Free Resolution at Gain = 64
Over 100dB Simultaneous 50Hz and 60Hz
Rejection
Flexible Clocking:
Low-Drift Onboard Oscillator (±3%)
Optional External Crystal
Selectable Gains of 1, 2, 64, and 128
Easy Ratiometric Measurements–
External Voltage Reference up to 5V
Selectable 10SPS or 80SPS Data Rates
Two-Channel Differential Input with Built-In
Temperature Sensor (ADS1232)
Four-Channel Differential Input (ADS1234)
Simple Serial Digital Interface
Supply Range: 2.7V to 5.3V
–40°C to +105°C Temperature Range
The ADS1232 and ADS1234 are precision 24-bit
analog-to-digital converters (ADCs). With an onboard,
low-noise programmable gain amplifier (PGA),
precision delta-sigma ADC and internal oscillator, the
ADS1232/4 provide a complete front-end solution for
bridge sensor applications including weigh scales,
strain gauges and pressure sensors.
The input multiplexer accepts either two (ADS1232)
or four (ADS1234) differential inputs. The ADS1232
also includes an onboard temperature sensor to
monitor ambient temperature. The onboard, low-noise
PGA has a selectable gain of 1, 2, 64, or 128
supporting a full-scale differential input of ±2.5V,
±1.25V, ±39mV, or ±19.5mV. The delta-sigma ADC
has 23.5-bit effective resolution and is comprised of a
3rd-order modulator and 4th-order digital filter. Two
data rates are supported: 10SPS (with both 50Hz and
60Hz rejection) and 80SPS. The ADS1232/4 can be
clocked externally using an oscillator or a crystal.
There is also an internal oscillator available that
requires no external components. Offset calibration is
performed on-demand and the ADS1232/4 can be
put in a low-power standby mode or shut off
completely in power-down mode. All of the features of
the ADS1232/4 are operated through simple
pin-driven control. There are no digital registers to
program in order to simplify software development.
Data are output over an easily-isolated serial
interface that connects directly to the MSP430 and
other microcontrollers.
APPLICATIONS
•
•
•
•
Weigh Scales
Strain Gauges
Pressure Sensors
Industrial Process Control
The ADS1232 is available in a TSSOP-24 package
and the ADS1234 is in a TSSOP-28. Both are fully
specified from -40°C to +105°C.
CAP
AVDD
ADS1234
Only
DVDD
GAIN [1:0]
Gain =
1, 2, 64, or 128
AINP1
AINN1
AINP2
AINN2
REFP REFN
Input
Mux
PGA
PDWN
DRDY/DOUT
DS ADC
AINP3
AINN3
SCLK
Internal Oscillator
AINP4
AINN4
SPEED
External Oscillator
(1)
A1/TEMP
A0
AGND
CAP
CLKIN/XTAL1 XTAL2
DGND
NOTE: (1) A1 for ADS1234, TEMP for ADS1232.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
data sheet, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
ADS1232, ADS1234
UNIT
–0.3 to +6
V
DVDD to DGND
–0.3 to +6
V
AGND to DGND
–0.3 to +0.3
V
100, Momentary
mA
AVDD to AGND
Input Current
Input Current
10, Continuous
mA
Analog Input Voltage to AGND
–0.3 to AVDD + 0.3
V
Digital Input Voltage to DGND
–0.3 to DVDD + 0.3
V
+150
°C
Operating Temperature Range
–40 to +105
°C
Storage Temperature Range
–60 to +150
°C
Maximum Junction Temperature
(1)
2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
All specifications at TA = –40°C to +105°C, AVDD = DVDD = VREFP = +5V, and VREFN = AGND, unless otherwise noted.
ADS1232, ADS1234
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Analog Inputs
Full-Scale Input Voltage
(AINP – AINN)
Common-Mode Input Range
±0.5VREF/Gain
AINxP or AINxN with respect to GND,
Gain = 1, 2
Gain = 64, 128
AGND – 0.1
Differential Input Current
AVDD + 0.1
AGND + 1.5V
Gain = 1
Gain = 2
Gain = 64, 128
V
AVDD – 1.5V
V
V
±3
nA
±6
nA
±3.5
nA
System Performance
Resolution
Data Rate
Digital Filter Settling Time
Integral Nonlinearity (INL)
Input Offset Error (2)
Input Offset Drift
Gain Error
(3)
Gain Drift
Normal-Mode Rejection (4)
Common-Mode Rejection
No Missing Codes
24
Internal Oscillator, SPEED = High
78
Internal Oscillator, SPEED = Low
9.75
82.4
SPS
10
10.3
SPS
External Oscillator, SPEED = High
fCLK/61,440
External Oscillator, SPEED = Low
fCLK/491,520
Full Settling
SPS
SPS
4
Differential Input, End-Point Fit
Gain = 1, 2
±0.0002
Differential Input, End-Point Fit
Gain = 64, 128
±0.0004
Gain = 1
Gain = 128
% of FSR (1)
% of FSR
ppm of FS
±0.02
±1
ppm of FS
Gain = 128
±10
Gain = 128
±0.001
±5
±0.3
Gain = 1
Conversions
±0.2
Gain = 1
µV/°C
nV/°C
±0.001
±0.02
±0.01
±0.1
%
%
Gain = 1
±0.2
ppm/°C
Gain = 128
±2.5
ppm/°C
Internal Oscillator, fDATA = 10SPS
fIN = 50Hz or 60Hz, ±1Hz
100
110
dB
External Oscillator, fDATA = 10SPS
fIN = 50Hz or 60Hz, ±1Hz
120
130
dB
at DC, Gain = 1, ΔV = 1V
95
110
dB
at DC, Gain = 128, ΔV = 0.1V
95
110
dB
Input-Referred Noise
Power-Supply Rejection
Bits
80
See Noise Performance Tables
at DC, Gain = 1, ΔV = 1V
100
120
dB
at DC, Gain = 128, ΔV = 0.1V
100
120
dB
1.5
AVDD
Voltage Reference Input
Voltage Reference Input (VREF)
AVDD + 0.1V
V
Negative Reference Input (VREFN)
VREF = VREFP – VREFN
AGND – 0.1
VREFP – 1.5
V
Positive Reference Input (VREFP)
VREFN + 1.5
AVDD + 0.1
V
Voltage Reference
Input Current
(1)
(2)
(3)
(4)
10
nA
FSR = full-scale range = VREF/Gain.
Offset calibration can minimize these errors to the level of noise at any temperature.
Gain errors are calibrated at the factory (AVDD = +5V, all gains, TA = +25°C).
Specification is assured by the combination of design and final production test.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
3
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40°C to +105°C, AVDD = DVDD = VREFP = +5V, and VREFN = AGND, unless otherwise noted.
ADS1232, ADS1234
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital
Logic Levels
VIH
0.7 DVDD
DVDD + 0.1
V
VIL
DGND
0.2 DVDD
V
VOH
IOH = 1mA
VOL
IOL = 1mA
Input Leakage
DVDD – 0.4
V
0 < VIN < DVDD
External Clock Input Frequency
(fCLKIN)
0.2
4.9152
Serial Clock Input Frequency (fSCLK)
0.2 DVDD
V
±10
µA
8
MHz
5
MHz
Power Supply
Power-Supply Voltage
(AVDD, DVDD)
Analog Supply Current
Digital Supply Current
Power Dissipation, Total
4
2.7
5.3
V
Normal Mode, AVDD = 3V,
Gain = 1, 2
600
1300
µA
Normal Mode, AVDD = 3V,
Gain = 64, 128
1350
2500
µA
Normal Mode, AVDD = 5V,
Gain = 1, 2
650
1300
µA
Normal Mode, AVDD = 5V,
Gain = 64, 128
1350
2500
µA
Standby Mode
0.1
1
µA
Power-Down
0.1
1
µA
Normal Mode, DVDD = 3V,
Gain = 1, 2
60
95
µA
Normal Mode, DVDD = 3V,
Gain = 64, 128
75
120
µA
Normal Mode, DVDD = 5V,
Gain = 1, 2
95
130
µA
Normal mode, DVDD = 5V,
Gain = 64, 128
75
120
µA
Standby Mode, SCLK = High, DVDD = 3V
45
80
µA
Standby Mode, SCLK = High, DVDD = 5V
65
80
µA
Power-Down
0.2
1.3
µA
Normal Mode, AVDD = DVDD = 3V,
Gain = 1, 2
2
4.2
mW
Normal Mode, AVDD = DVDD = 5V,
Gain = 1, 2
3.7
7.2
mW
Normal Mode, AVDD = DVDD = 3V,
Gain = 64, 128
4.3
7.9
mW
Normal Mode, AVDD = DVDD = 5V,
Gain = 64, 128
7.1
13.1
mW
Standby Mode, AVDD = DVDD = 5V
0.3
0.4
mW
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
NOISE PERFORMANCE
The ADS1232/4 offer outstanding noise performance that can be optimized for a given full-scale range using the
on-chip programmable gain amplifier. Table 1 through Table 4 summarize the typical noise performance with
inputs shorted externally for different gains, data rates, and voltage reference values.
The RMS and Peak-to-Peak noise are referred to the input. The Effective Number of Bits (ENOB) is defined as:
• ENOB = ln (FSR/RMS noise)/ln(2)
The Noise-Free Bits are defined as:
• Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2)
Where FSR (Full-Scale Range) = VREF/Gain
Table 1. AVDD = 5V, VREF = 5V, Data Rate = 10SPS
(1)
GAIN
RMS NOISE
PEAK-TO-PEAK NOISE (1)
ENOB (RMS)
NOISE-FREE BITS
1
420nV
1.79µV
23.5
21.4
2
270nV
900nV
23.1
21.4
64
19nV
125nV
22.0
19.2
128
17nV
110nV
21.1
18.4
Peak-to-peak noise data are based on direct measurement.
Table 2. AVDD = 5V, VREF = 5V, Data Rate = 80SPS
(1)
GAIN
RMS NOISE
PEAK-TO-PEAK NOISE (1)
ENOB (RMS)
NOISE-FREE BITS
1
1.36µV
8.3µV
21.8
19.2
2
850nV
5.5µV
21.5
18.8
64
48nV
307nV
20.6
18
128
44nV
247nV
19.7
17.2
Peak-to-peak noise data are based on direct measurement.
Table 3. AVDD = 3V, VREF = 3V, Data Rate = 10SPS
(1)
GAIN
RMS NOISE
PEAK-TO-PEAK NOISE (1)
ENOB (RMS)
NOISE-FREE BITS
1
450nV
2.8µV
22.6
20
2
325nV
1.8µV
22.1
19.7
64
20nV
130nV
21.2
18.5
128
18nV
115nV
20.3
17.6
Peak-to-peak noise data are based on direct measurement.
Table 4. AVDD = 3V, VREF = 3V, Data Rate = 80SPS
(1)
GAIN
RMS NOISE
PEAK-TO-PEAK NOISE (1)
ENOB (RMS)
NOISE-FREE BITS
1
2.2µV
12µV
20.4
17.9
2
1.2µV
6.8µV
20.2
17.8
64
54nV
340nV
19.7
17.1
128
48nV
254nV
18.9
16.5
Peak-to-peak noise data are based on direct measurement of 1024 samples.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
5
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
PIN CONFIGURATION
DVDD
1
28
DRDY/DOUT
DGND
2
27
SCLK
CLKIN/XTAL1
3
26
PDWN
DVDD
1
24
DRDY/DOUT
DGND
2
23
SCLK
CLKIN/XTAL1
3
22
PDWN
XTAL2
4
25
SPEED
XTAL2
4
21
SPEED
DGND
5
24
GAIN1
DGND
5
20
GAIN1
DGND
6
23
GAIN0
DGND
6
19
GAIN0
A1
7
22
AVDD
ADS1232
6
ADS1234
TEMP
7
18
AVDD
A0
8
21
AGND
A0
8
17
AGND
CAP
9
20
REFP
CAP
9
16
REFP
CAP
10
19
REFN
CAP
10
15
REFN
AINP1
11
18
AINP2
AINP1
11
14
AINP2
AINN1
12
17
AINN2
AINN1
12
13
AINN2
AINP3
13
16
AINP4
AINN3
14
15
AINN4
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
PIN DESCRIPTIONS
TERMINAL
NAME
ADS1232
ADS1234
ANALOG/DIGITAL
INPUT/OUTPUT
DVDD
1
1
Digital
Digital Power Supply: 2.7V to 5.3V
DGND
2
2
Digital
Digital Ground
CLKIN/
XTAL1
3
3
Digital/Digital Input
XTAL2
4
4
Digital
External crystal connection
DGND
5
5
Digital
Digital Ground
DGND
6
6
Digital
Digital Ground
TEMP
7
–
Digital Input
DESCRIPTION
External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator. Can also use
external crystal across CLKIN/XTAL1 and XTAL2 pins. See text for more details.
Onboard Temperature Diode Enable
Input Mux Select Input pin (MSB)
Input Mux Select Input pin (LSB):
A1
A0
–
8
7
8
CAP
9
9
CAP
10
AINP1
11
AINN1
Digital Input
A1
A0
Channel
0
0
AIN1
0
1
AIN2
1
0
AIN3
1
1
AIN4
Analog
Gain Amp Bypass Capacitor Connection
10
Analog
Gain Amp Bypass Capacitor Connection
11
Analog Input
Positive Analog Input Channel 1
12
12
Analog Input
Negative Analog Input Channel 1
AINP3
–
13
Analog Input
Positive Analog Input Channel 3
AINN3
–
14
Analog Input
Negative Analog Input Channel 3
AINN4
–
15
Analog Input
Negative Analog Input Channel 4
AINP4
–
16
Analog Input
Positive Analog Input Channel 4
AINN2
13
17
Analog Input
Negative Analog Input Channel 2
AINP2
14
18
Analog Input
Positive Analog Input Channel 2
REFN
15
19
Analog Input
Negative Reference Input
REFP
16
20
Analog Input
Positive Reference Input
AGND
17
21
Analog
Analog Ground
AVDD
18
22
Analog
Analog Power Supply, 2.7V to 5.3V
Gain Select
GAIN0
GAIN1
19
20
23
24
Digital Input
GAIN1
GAIN0
GAIN
0
0
1
0
1
2
1
0
64
1
1
128
Data Rate Select:
SPEED
21
25
Digital Input
SPEED
DATA RATE
0
10SPS
1
80SPS
PDWN
22
26
Digital Input
Power-Down: Holding this pin low powers down the entire converter and resets the ADC.
SCLK
23
27
Digital Input
Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep
modes. See text for more details.
DRDY/
DOUT
24
28
Digital Output
Dual-Purpose Output:
Data Ready: Indicates valid data by going low.
Data Output: Outputs data, MSB first, on the first rising edge of SCLK.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
7
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = VREFP = 5V, and VREFN = AGND, unless otherwise noted.
NOISE PLOT
NOISE PLOT
25
6
PGA = 1
Data Rate = 10SPS
5
20
15
3
Output Code (LSB)
Output Code (LSB)
4
2
1
−1
−2
−3
10
5
0
−5
−10
−4
−15
−5
−20
PGA = 128
Data Rate = 10SPS
−25
−6
0
200
400
600
800
0
1000
200
Figure 1.
Figure 2.
1000
NOISE HISTOGRAM
PGA = 128
Data Rate = 10SPS
90
80
70
200
Occurrence
Occurrence
800
100
PGA = 1
Data Rate = 10SPS
250
600
Time (Reading Number)
NOISE HISTOGRAM
300
400
Time (Reading Number)
150
100
60
50
40
30
20
50
10
0
0
−2
−4
0
−16
4
2
−8
8
Output Code (LSB)
Figure 3.
Figure 4.
NOISE PLOT
16
NOISE PLOT
70
22.5
PGA = 1
Data Rate = 80SPS
17.5
0
Output Code (LSB)
PGA = 128
Data Rate = 80SPS
50
Output Code (LSB)
Output Code(LSB)
12.5
7.5
2.5
−2.5
−7.5
−12.5
10
−10
−30
−50
−17.5
−70
−22.5
0
8
30
200
400
600
800
1000
0
200
400
600
Time (Reading Number)
Time (Reading Number)
Figure 5.
Figure 6.
800
1000
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = VREFP = 5V, and VREFN = AGND, unless otherwise noted.
NOISE HISTOGRAM
NOISE HISTOGRAM
50
180
PGA = 1
Data Rate = 80SPS
45
40
140
35
120
Occurance
100
80
30
25
20
60
15
40
10
20
5
0
0
−12
−6
0
6
−40
12
Figure 8.
OFFSET DRIFT (+25°C to +105°C)
30
20
Offset Drift (nV/°C)
Offset Drift (nV/°C)
Figure 9.
Figure 10.
GAIN DRIFT (–40°C to +25°C)
500
400
300
200
GAIN DRIFT (+25°C to +105°C)
20
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
18
16
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
14
Counts
12
Counts
100
-500
500
600
300
400
100
200
0
0
-100
0
-200
5
-300
5
-400
10
-500
10
0
15
-100
15
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
-200
Counts
20
-600
Counts
PGA = 1
Data Rate = 10SPS
90 Samples from 3 Lots
25
14
40
35
25
16
20
Figure 7.
OFFSET DRIFT (–40°C to +25°C)
18
0
Output Code (LSB)
35
30
−20
Output Code (LSB)
-300
Occurance
PGA = 128
Data Rate = 80SPS
-400
160
10
8
6
12
10
8
6
4
4
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
0
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
2
Gain Drift (ppm/°C)
Gain Drift (ppm/°C)
Figure 11.
Figure 12.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
9
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = VREFP = 5V, and VREFN = AGND, unless otherwise noted.
OFFSET DRIFT (–40°C to +25°C)
OFFSET DRIFT (+25°C to +105°C)
30
20
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
25
16
14
Counts
20
Counts
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
18
15
10
12
10
8
6
4
5
2
0
Offset Drift (nV/°C)
Offset Drift (nV/°C)
Figure 13.
Figure 14.
GAIN DRIFT (–40°C to +25°C)
30
20
25
15
5
10
0
-5
-10
-15
-20
-25
-30
50
40
30
20
10
0
-10
-20
-30
-40
-50
0
GAIN DRIFT (+25°C to +105°C)
25
20
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
20
PGA = 128
Data Rate = 10SPS
90 Samples from 3 Lots
18
16
Counts
Counts
14
15
10
12
10
8
6
5
4
2
0
Gain Drift (ppm/°C)
Gain Drift (ppm/°C)
Figure 15.
Figure 16.
OFFSET vs TEMPERATURE
6.0
5.5
4.5
5.0
3.5
4.0
2.5
3.0
1.5
2.0
1.0
0
0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
GAIN ERROR vs TEMPERATURE
0.04
1000
PGA = 128
Data Rate = 10SPS
0.03
PGA = 128
Data Rate = 10SPS
Gain Error (%)
Offset (nV)
500
0
0.02
0.01
0
−500
−0.01
−1000
10
−50
−30
−10
−0.02
10
30
50
70
90
110
−50
−30
−10
10
30
50
Temperature (_C)
Temperature (_C)
Figure 17.
Figure 18.
70
90
110
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = VREFP = 5V, and VREFN = AGND, unless otherwise noted.
NOISE vs INPUT SIGNAL
NOISE vs INPUT SIGNAL
1000
PGA = 1
Data Rate = 10SPS
800
40
700
35
500
400
300
30
25
20
15
200
10
100
5
0
0.5
1.0
1.5
2.0
0
−19
2.5
−14.25 −9.5
−4.75
0
4.75
9.5
VIN (V)
VIN (mV)
Figure 19.
Figure 20.
INTEGRAL NONLINEARITY
vs INPUT SIGNAL
INTEGRAL NONLINEARITY
vs INPUT SIGNAL
14.25
19
8
3
15
6
234.375
2
10
4
156.25
1
5
2
78.125
0
0
0
0
PGA = 1
−1
−5
−2
−10
−3
INL (ppmof FSR)
10
20
4
INL (µV)
25
5
390.625
PGA = 128
312.5
INL (nV)
600
0
−2.5 −2.0 −1.5 −1.0 −0.5
INL (ppm of FSR)
PGA = 128
Data Rate = 10SPS
45
RMS Noise (nV)
RMS Noise (nV)
900
50
−2
−78.125
−4
−156.25
−15
−6
−234.375
−4
−20
−8
−312.5
−5
−2.5 −2.0 −1.5 −1.0 −0.5
−25
0
0.5
1.0
1.5
2.0
2.5
−10
−19
−14.25 −9.5
−4.75
VIN (V)
0
4.75
14.25
−390.625
19
VIN (mV)
Figure 21.
Figure 22.
ANALOG CURRENT
vs TEMPERATURE
DIGITAL CURRENT
vs TEMPERATURE
120
2000
Normal Mode, PGA = 64, 128
Normal Mode, PGA = 1, 2
100
1200
Normal Mode, PGA = 1, 2
800
400
Digital Current (µA)
1600
Analog Current (µA)
9.5
Normal Mode, PGA = 64, 128
80
Sleep Mode, All PGAs
60
40
20
0
0
−50
−30
−10
10
30
50
70
90
110
−50
−30
−10
10
30
50
70
90
110
Temperature (_C)
Temperature (_C)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = VREFP = 5V, and VREFN = AGND, unless otherwise noted.
DATA RATE
vs TEMPERATURE
10.06
SPEED = LOW
CLKIN/XTAL1 = LOW (Internal Oscillator)
Data Rate (SPS)
10.01
9.96
9.91
9.86
−50
−30
−10
10
30
50
70
90
110
Temperature (_C)
Figure 25.
12
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OVERVIEW
TEMPERATURE SENSOR (ADS1232 only)
The ADS1232 and ADS1234 are highly integrated,
24-bit ADCs that include an input multiplexer,
low-noise PGA, third-order delta-sigma (ΔΣ)
modulator, and fourth-order digital filter. With
input-referred RMS noise down to 17nV, the
ADS1232/4 are ideally suited for measuring the very
low signals produced by bridge sensors in
applications such as weigh scales, strain gauges, and
pressure sensors.
On-chip
diodes
provide
temperature-sensing
capability. By setting the TEMP pin high, the selected
analog inputs are disconnected and the inputs to the
ADC are connected to the anodes of two diodes
scaled to 1x and 80x in current and size, as shown in
Figure 26. By measuring the difference in voltage of
these diodes, temperature changes can be inferred
from a baseline temperature. Typically, the difference
in diode voltage is 111.7mV at 25°C with a
temperature coefficient of 379µV/°C. With PGA = 1
and 2, the difference voltage output from the PGA will
be 111.7mV and 223.4mV, respectively. With PGA =
64 and 128, it is impossible to use the temperature
sensor function. A similar structure is used in the
MSC1210 for temperature measurement. For more
information, see TI application report SBAA100,
Using the MSC121x as a High-Precision Intelligent
Temperature Sensor, available for download at
www.ti.com.
Clocking can be supplied by an external oscillator, an
external crystal, or by a precision internal oscillator.
Data can be output at 10SPS for excellent 50Hz and
60Hz rejection, or at 80SPS when higher speeds are
needed. The ADS1232/4 are easy to configure, and
all digital control is accomplished through dedicated
pins; there are no registers to program. A simple
two-wire serial interface retrieves the data.
ANALOG INPUTS (AINPx, AINNx)
The input signal to be measured is applied to the
input pins AINPx and AINNx. The positive internal
input is generalized as AINP, and the negative
internal input generalized as AINN. The signal is
selected through the input mux, which is controlled by
pins A0 and A1 (ADS1234 only), as shown in
Table 5. For the ADS1232, the A1 pin is replaced by
the TEMP pin to activate the onboard diodes (see the
Temperature Sensor section for more details). The
ADS1232/4 accept differential input signals, but can
also measure unipolar signals. When measuring
unipolar (or single-ended signals) with respect to
ground, connect the negative input (AINNx) to ground
and connect the input signal to the positive input
(AINPx). Note that when the ADS1232/4 are
configured this way, only half of the converter
full-scale range is used, since only positive digital
output codes are produced.
ADS1232 Only
AVDD
10I
1I
AINP
AINN
1X
8X
AINP1
AINN1
AINP2
Table 5. Input Channel Selection with A0 and A1
(ADS1234 only)
AINN2
MUX PINS
AINN3
A1
A0
SELECTED ANALOG INPUTS
POSITIVE INPUT
AINP3
NEGATIVE INPUT
AINP4
AINN4
0
0
AINP1
AINN1
0
1
AINP2
AINN2
1
0
AINP3
AINN3
1
1
AINP4
AINN3
ADS1234 Only A1
A0
Figure 26. Measurement of the Temperature
Sensor in the Input Multiplexer
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LOW-NOISE PGA
Bypass Capacitor
The ADS1232/4 features a low-drift, low-noise PGA
that provides a complete front-end solution for bridge
sensors. A simplified diagram of the PGA is shown in
Figure 27. It consists of two chopper-stabilized
amplifiers (A1 and A2) and three accurately-matched
resistors (R1, RF1, and RF2), which construct a
differential front-end stage with a gain of 64, followed
by gain stage A3. The PGA inputs are equipped with
an EMI filter, as shown in Figure 27. The cut-off
frequency of the EMI filter is 19.6MHz. If the PGA is
set to 1 or 2, the gain-of-64 stage is bypassed and
shut down to save power. With the combination of
both gain stages, the PGA can be set to 64 or 128.
The PGA of the ADS1232/4 can be set to 1, 2, 64, or
128 with pins GAIN1 (MSB) and GAIN0 (LSB). By
using AVDD as the reference input, the bipolar input
ranges from ±2.5V to ±19.5mV, while the unipolar
ranges from 2.5V to 19.5mV. When the PGA is set to
1 or 2, the absolute inputs can go rail-to-rail without
significant performance degradation. However, the
inputs of the ADS1232/4 are protected with internal
diodes connected to the power-supply rails. These
diodes will clamp the applied signal to prevent it from
damaging the input circuitry. On the other hand, when
the PGA is set to 64 or 128, the operating input range
is limited to (AGND + 1.5V) to (AVDD – 1.5V), in
order to prevent saturating the differential front-end
circuitry and degrading performance.
By applying a 0.1µF external capacitor (CEXT) across
two capacitor pins and the combination of the internal
2kΩ resistor RINT on-chip, a low-pass filter (with a
corner frequency of 720Hz) is created to bandlimit the
signal path prior to the modulator input. This low-pass
filter serves two purposes. First, the input signal is
bandlimited to prevent aliasing as well as to filter out
the high-frequency noise. Second, it attenuates the
chopping residue from the PGA (for gains of 64 and
128 only) to improve temperature drift performance. It
is not required to use high quality capacitors (such as
ceramic or tantalum capacitors) for a general
application. However, high quality capacitors such as
poly are recommended for high linearity applications.
CAP
450W
RINT
AINP
18pF
A1
A3
RF2
ADC
Where:
fMOD = modulator sampling frequency (76.8kHz)
CBUF = input capacitance of the buffer
For the ADS1232/4:
RINT
450W
The voltage reference used by the modulator is
generated from the voltage difference between REFP
and REFN: VREF = REFP – REFN. The reference
inputs use a structure similar to that of the analog
inputs. In order to increase the reference input
impedance, a switching buffer circuitry is used to
reduce the input equivalent capacitance. The
reference drift and noise impact ADC performance. In
order to achieve best results, pay close attention to
the reference noise and drift specifications. A
simplified diagram of the circuitry on the reference
inputs is shown in Figure 28. The switches and
capacitors can be modeled with an effective
impedance of:
1
Z EFF +
2f MODC BUF
Gain of 1 or 2
RF1
R1
VOLTAGE REFERENCE INPUTS
(REFP, REFN)
A2
AINN
18pF
CAP
Figure 27. Simplified Diagram of the PGA
14
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Z EFF +
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
1
+ 500MW
(2)(76.8kHz)(13fF)
CLKIN/XTAL1
Crystal
Oscillator
CLK_DETECT
VREFP
VREFN
Internal
Oscillator
XTAL2
AVDD
S0
EN
S1
S
MUX
AVDD
To ADC
ESD
Protection
CBUF
ZEFF = 500MΩ(1)
(1) f MOD = 76.8kHz
Figure 28. Simplified Reference Input Circuitry
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the voltages
on the reference pins do not go below GND by more
than 100mV, and likewise, do not exceed AVDD by
100mV:
GND – 100mV < (REFP or REFN) < AVDD + 100mV
Figure 29. Equivalent Circuitry of the Clock
Source
When the clock source is a crystal, simply connect
the 4.9152MHz crystal across the CLKIN/XTAL1 and
XTAL2 pins. Table 6 shows the recommended part
numbers. Due to the low-power design of the parallel
resonant driver circuitry onboard, both the
CLKIN/XTAL1 and XTAL2 pins are only for use with
external crystals; they should not be used as clock
output drivers for external circuitry. No external
capacitors are used with the crystal; it is
recommended to place the crystal close to the part in
order to reduce board stray capacitance for both the
CLKIN/XTAL1 and XTAL2 pins and to insure proper
operation.
Table 6. Recommended Crystals
CLOCK SOURCES
The ADS1232/4 can use an external clock source,
external crystal, or internal oscillator to accommodate
a wide variety of applications. Figure 29 shows the
equivalent circuitry of the clock source. The
CLK_DETECT block determines whether the crystal
oscillator/external clock signal is applied to the
CLKIN/XTAL1 pin so that the internal oscillator is
bypassed or activated. When the CLKIN/XTAL1 pin
frequency is above ~200kHz, the CLK_DETECT
output goes low and shuts down the internal
oscillator. When the XIN pin frequency is below
~200kHz, the CLK_DETECT output goes high and
activates the internal oscillator. It is highly
recommended to hard-wire the CLKIN/XTAL1 pin to
ground when the internal oscillator is chosen.
MANUFACTURER
FREQUENCY
PART NUMBER
ECS
4.9152MHz
ECS-49-20-1
ECS
4.9152MHz
ECS-49-20-4
An external oscillator may be used by driving the
CLKIN/XTAL1
pin
directly.
The
Electrical
Characteristics table shows the allowable frequency
range.
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FREQUENCY RESPONSE
4
The ADS1232/4 use a sinc digital filter with the
frequency response (fCLK = 4.9152MHz) shown in
Figure 30. The frequency response repeats at
multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
Figure 31(b) shows the zoom in plot for both 50Hz
and 60Hz notches with the SPEED pin tied low
(10SPS data rate). With only a ±3% variation of the
internal oscillator, over 100dB of normal-mode
rejection is achieved.
0
Data Rate = 10SPS
Gain (dB)
−50
0
−20
fCLK = 4.9152MHz
−100
−40
Gain (dB)
−60
−80
−150
−100
0
10
20
30
40
50
60
−120
Frequency (Hz)
−140
(a)
−160
70
80
90
100
−50
Data Rate = 10SPS
−180
−200
38.4
76.8
Frequency (kHz)
Figure 30. Frequency Response
To help see the response at lower frequencies,
Figure 31(a) illustrates the response out to 100Hz,
when the data rate = 10SPS. Notice that signals at
multiples of 10Hz are rejected, and therefore
simultaneous rejection of 50Hz and 60Hz is achieved.
Gain (dB)
0
−100
−150
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Frequency (Hz)
(b)
4
The benefit of using a sinc filter is that every
frequency notch has four zeros on the same location.
This response, combined with the low drift internal
oscillator, provides an excellent normal-mode
rejection of line-cycle interference.
16
Figure 31. Frequency Response Out To 100Hz
The ADS1232/4 data rate and frequency response
scale directly with clock frequency. For example, if
fCLK increases from 4.9152MHz to 6.144MHz when
the SPEED pin is tied high, the data rate increases
from 80SPS to 100SPS, while notches also increase
from 80Hz to 100Hz. Note that this is only possible
when the external clock source is applied.
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SETTLING TIME
After changing the input multiplexer, the first data are
fully settled. In both the ADS1232/4, the digital filter is
allowed to settle after toggling either the A1 or A0 pin.
Toggling any of these digital pins will hold the
DRDY/DOUT line high until the digital filter is fully
settled. For example, if A0 changes from low to high,
selecting a different input channel, DRDY/DOUT
immediately goes high, and DRDY/DOUT goes low
when fully-settled data are ready for retrieval. There
is no need to discard any data. Figure 32 shows the
timing of the DRDY/DOUT line as the input
multiplexer changes.
switching input channels. Another example would be
toggling the TEMP pin, which switches the internal
AINP, AINN signals to connect to either the external
AINPx, AINNx pins or to the TEMP diode (see
Figure 26).
Note that when settling data, five readings may be
required. If the change in input occurs in the middle
of the first conversion, four more full conversions of
the fully-settled input are required to get fully-settled
data. Discard the first four readings because they
contain only partially-settled data.Figure 33 illustrates
the settling time for the ADS1232/4 in Continuous
Conversion mode.
In certain instances, large and/or abrupt changes in
input will require four data cycles to settle. One
example of such a change would be an external
multiplexer in front of the ADS1232/4, which can
cause large changes in input voltage simply by
A1 or A0
t1
DRDY/DOUT
tS
Figure 32. Example of Settling Time After Changing the Input Multiplexer
SYMBOL
(1)
DESCRIPTION (1)
MIN
MAX
UNITS
tS
Setup time for changing the A1 or A0 pins
40
50
µs
t1
Settling time (DRDY/DOUT
held high)
SPEED = 1
51
51
ms
SPEED = 0
401
401
ms
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
Toggled TEMP Pin or Abrupt Change in External VIN
VIN
Start of
conversion.
DRDY/DOUT
1st conversion;
includes
unsettled VIN.
2nd conversion;
VIN settled, but
digital filter
unsettled.
3rd conversion;
VIN settled, but
digital filter
unsettled.
4th conversion;
VIN settled, but
digital filter
unsettled.
5th conversion;
VIN and digital
filter both
settled.
Conversion
Time
Figure 33. Settling Time in Continuous Conversion Mode
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DATA RATE
DATA READY/DATA OUTPUT (DRDY/DOUT)
The ADS1232/4 data rate is set by the SPEED pin,
as shown in Table 7. When SPEED is low, the data
rate is nominally 10SPS. This data rate provides the
lowest noise, and also has excellent rejection of both
50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED
high selects a data rate of nominally 80SPS.
This digital output pin serves two purposes. First, it
indicates when new data are ready by going low.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins
outputting the conversion data, most significant bit
(MSB) first. Data are shifted out on each subsequent
SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an
additional SCLK. It will then stay high until new data
are ready. This configuration is useful when polling
on the status of DRDY/DOUT to determine when to
begin data retrieval.
Table 7. Data Rate Settings
DATA RATE
SPEED
PIN
Internal Oscillator
or 4.9152MHz Crystal
External
Oscillator
0
10SPS
fCLKIN / 491,520
1
80SPS
fCLKIN / 61,440
DATA FORMAT
The ADS1232/4 output 24 bits of data in binary two’s
complement format. The least significant bit (LSB)
has a weight of 0.5VREF/(223 – 1). The positive
full-scale input produces an output code of 7FFFFFh
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals exceeding full-scale. Table 8 summarizes the
ideal output codes for different input signals.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. This input has built-in hysteresis, but care
should still be taken to ensure a clean signal. Glitches
or slow-rising signals can cause unwanted additional
shifting. For this reason, it is best to make sure the
rise-and-fall times of SCLK are less than 50ns.
Table 8. Ideal Output Code vs Input Signal (1)
(1)
18
INPUT SIGNAL VIN
(AINP – AINN)
IDEAL OUTPUT CODE
≥ +0.5VREF/Gain
7FFFFFh
(+0.5VREF/Gain)/(223 – 1)
000001h
0
000000h
(–0.5VREF/Gain)/(223 – 1)
FFFFFFh
≤ –0.5VREF/Gain
800000h
Excludes effects of noise, INL, offset, and gain errors.
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DATA RETRIEVAL
indicating that new data are being updated. To avoid
having DRDY/DOUT remain in the state of the last
bit, the user can shift SCLK to force DRDY/DOUT
high, as shown in Figure 35. This technique is useful
when a host controlling the device is polling
DRDY/DOUT to determine when data are ready.
The ADS1232/4 continuously convert the analog
input signal. To retrieve data, wait until DRDY/DOUT
goes low, as shown in Figure 34. After this occurs,
begin shifting out the data by applying SCLKs. Data
are shifted out MSB first. It is not required to shift out
all 24 bits of data, but the data must be retrieved
before new data are updated (within t7) or else it will
be overwritten. Avoid data retrieval during the update
period (t6). DRDY/DOUT remains at the state of the
last bit shifted out until it is taken high (see t6),
Data
Data Ready
New Data Ready
MSB
DRDY/DOUT
23
LSB
22
21
0
t4
t5
t2
t3
t6
1
SCLK
24
t3
t7
Figure 34. Data Retrieval Timing
SYMBOL
(1)
DESCRIPTION
MIN
t2
DRDY/DOUT low to first SCLK rising edge
t3
SCLK positive or negative pulse width
t4
SCLK rising edge to new data bit valid: propagation
delay
t5
TYP
MAX
UNITS
0
ns
100
ns
50
ns
SCLK rising edge to old data bit valid: hold time
0
ns
t6 (1)
Data updating: no readback allowed
39
µs
t7 (1)
Conversion time (1/data rate)
SPEED = 1
12.5
ms
SPEED = 0
100
ms
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period.
Data
Data Ready
New Data Ready
DRDY/DOUT
23
1
SCLK
22
21
0
24
25
25th SCLK to Force DRDY/DOUT High
Figure 35. Data Retrieval with DRDY/DOUT Forced High Afterwards
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OFFSET CALIBRATION
When the calibration is completed, DRDY/DOUT
goes low, indicating that new data are ready. The
analog input pins are disconnected within the ADC
and the appropriate signal is applied internally to
perform the calibration. The first conversion after a
calibration is fully settled and valid for use. The offset
calibration takes exactly the same time as specified in
(t8) right after the falling edge of the 26th SCLK.
Offset calibration can be initiated at any time to
remove the ADS1232/4 inherited offset error. To
initiate offset calibration, apply at least two additional
SCLKs after retrieving 24 bits of data. Figure 36
shows the timing pattern. The 25th SCLK will send
DRDY/DOUT high. The falling edge of the 26th SCLK
will begin the calibration cycle. Additional SCLK
pulses may be sent after the 26th SCLK; however,
activity on SCLK should be minimized during offset
calibration for best results.
Data Ready After Calibration
DRDY/DOUT
23
22
21
0
23
Calibration Begins
SCLK
1
24
25
26
t8
Figure 36. Offset-Calibration Timing
SYMBOL
t8 (1)
(1)
20
DESCRIPTION
First data ready after calibration
MIN
MAX
UNITS
SPEED = 1
101.28
101.29
ms
SPEED = 0
801.02
801.03
ms
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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STANDBY MODE
Standby
mode
dramatically
reduces
power
consumption by shutting down most of the circuitry. In
Standby mode, the entire analog circuitry is powered
down and only the clock source circuitry is awake to
reduce the wake-up time from the Standby mode. To
enter Standby mode, simply hold SCLK high after
DRDY/DOUT goes low; see Figure 37. Standby mode
can be initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand.
When t10 has passed with SCLK held high, Standby
mode will activate. DRDY/DOUT stays high when
Standby mode begins. SCLK must remain high to
stay in Standby mode. To exit Standby mode
(wakeup), set SCLK low. The first data after exiting
Standby mode is valid.
Data Ready
Standby Mode
DRDY/DOUT
23
22
21
0
23
Start Conversion
SCLK
1
24
t9
t10
t11
Figure 37. Standby Mode Timing (can be used for single conversions)
SYMBOL
t9 (1)
t10 (1)
t11 (1)
(1)
DESCRIPTION
SCLK high after DRDY/DOUT goes low SPEED = 1
to activate Standby mode
SPEED = 0
Standby mode activation time
Data ready after exiting Standby mode
MIN
MAX
UNITS
0
12.44
ms
0
99.94
ms
SPEED = 1
12.46
SPEED = 0
99.96
ms
SPEED = 1
52.51
52.51
ms
SPEED = 0
401.8
401.8
ms
ms
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
21
ADS1232
ADS1234
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SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
STANDBY MODE WITH
OFFSET-CALIBRATION
Offset-calibration can be set to run immediately after
exiting Standby mode. This is useful when the
ADS1232/4 is put in Standby mode for long periods
of time, and offset-calibration is desired afterwards to
compensate for temperature or supply voltage
changes.
To force an offset-calibration with Standby mode, shift
25 SCLKs and take the SCLK pin high to enter
Standby mode. Offset-calibration then begins after
wake-up; see Figure 38 for the appropriate timing.
Note the extra time needed after wake-up for
calibration before data are ready. The first data after
Standby mode with offset-calibration is fully settled
and can be used right away.
Data Ready After Calibration
Standby Mode
DRDY/DOUT
SCLK
23
22
21
0
1
24
Begin Calibration
23
25
t12
t10
Figure 38. Standby Mode with Offset-Calibration Timing (can be used for single conversions)
SYMBOL
t12 (1)
(1)
22
DESCRIPTION
Data ready after exiting Standby mode
and calibration
MIN
MAX
UNITS
SPEED = 1
103
103
ms
SPEED = 0
803
803
ms
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
POWER-UP SEQUENCE
AVDD
DVDD
When powering up the ADS1232/34, AVDD and
DVDD must be powered up before the PDWN pin
goes high, as shown in Figure 39. If PDWN is not
controlled by a microprocessor, a simple RC delay
circuit must be implemented, as shown in Figure 40.
PDWN
³10ms
Figure 39. Power-Up Timing Sequence
POWER-DOWN MODE
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry to free the ADC circuitry
from locking up to an unknown state. Power-Down
mode can be initiated at any time during readback; it
is not necessary to retrieve all 24 bits of data
beforehand. Figure 41 shows the wake-up timing
from Power-Down mode.
DVDD(1)
1kW
2.2nF
Connect to
ADS1232/34
PDWN pin
NOTE: (1) AVDD must be powered up at least
10ms before PDWN goes high.
Figure 40. RC Delay Circuit
Start
Conversion
Data Ready
Power-Down Mode
t14
PDWN
CLK Soure
Wakeup
DRDY/DOUT
t13
t11
SCLK
Figure 41. Wake-Up Timing from Power-Down Mode
SYMBOL
t13
t14 (2)
(1)
(2)
DESCRIPTION
Wake-up time after Power-Down mode
TYP
UNITS
Internal clock
7.95
µs
External clock
0.16
µs
Crystal oscillator (1)
5.6
ms
26 (min)
µs
PDWN pulse width
No capacitors on CLKIN/XTAL1 or XTAL2 outputs.
Value given for fCLK = 4.9152MHz. For different fCLK frequencies, the scale is proportional to the CLK period except for a ±3% variation
when an internal oscillator is used.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
23
ADS1232
ADS1234
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SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
APPLICATION EXAMPLES
Therefore:
Weigh-Scale System
Noise−Free Counts + ǒ2 (18.4)1)Ǔ 10mV + 177, 385
39mV
ǒ
Figure 42 shows a typical ADS1232 hook-up as part
of a weigh-scale system. In this setup, the ADS1232
is configured to channel one input with a gain of 128
at a 10SPS data rate. Note that the internal oscillator
is used by grounding the CLKIN/XTAL1 pin. The user
can also apply either a 4.9152MHz crystal across the
CLKIN/XTAL1 and XTAL2 pins, or simply apply a
clock to the CLKIN/XTAL1 pin. For a typical 2mV/V
load cell, the maximum output signal is approximately
10mV for a single +5V excitation voltage. The
ADS1232/4 can achieve 18.4 noise-free bits at
10SPS when the PGA = 128 (refer to Table 1). With
the extra software filtering/averaging (typically done
by a microprocessor), an extra bit can be expected.
FS
ǒFS
Ǔ
Noise−Free Counts + ǒ2 BITEffǓ
LC
Ǔ
With +5V supply voltage, 177,385 noise-free counts
can be expected from the ADS1232/4 with the
onboard PGA set to 128.
Thermocouple
See Figure 43 for the ADS1232 in a thermocouple
application. In this example, a type k thermocouple is
used; the temperature range is from –260°C to
+900°C when the gain is set to 64 to maximize the
full input range of the ADS1232. R1 and a
REF1004-2.5V are used to set the common-mode
voltage
to
2.5V
for
ungrounded
junction
thermocouples. With a gain of 128, the ADS1232
input has a typical noise of 17nVRMS for extremely
high-resolution applications.
AD
Where:
BITEFF = effective noise-free bits (18.4 + 1 bit
from software filtering/averaging)
FSLC = full-scale output of the load cell (10mV)
FSAD = full-scale input of the ADS1232/4 (39mV
when PGA = 128)
24
If either a wider temperature range application is
required (up to +1350°C, for example), or a grounded
junction thermocouple is used, pin 1 of the
thermocouple can be grounded (see Figure 44).
When the gain is set to 2, the ADS1232 input has a
typical 500nV offset error and a noise level of
270nVRMS, which is good for all kinds of low-voltage
output sensors. Note that to calculate the actual
thermocouple temperature, the ADS1232 internal
temperature sensor can be accessed in order to
measure the cold junction temperature along with the
thermocouple reading.
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
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SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
5V
3V
0.1mF
18
1
AVDD
VDD
DVDD
20
ADS1232
16
REFP
19
GAIN0
Gain = 128
9
CAP
24
DRDY/DOUT
0.1mF
10
CAP
23
SCLK
+
-
GAIN1
22
PDWN
11
AINP1
12
MSP430x4xx
or Other
Microprocessor
4
XTAL2
AINN1
14
13
AINP2
CLKIN/XTAL1
AINN2
SPEED
3
21
8
A0
7
15
REFN
TEMP
AGND
17
GND
DGND
2, 5, 6
Figure 42. Weigh Scale Application
5V
3V
0.1mF
R1
50kW
18
1
AVDD
ADS1232
16
REF1004- 2.5V
9
0.1mF
10
2
REFP
VDD
DVDD
20
GAIN1
GAIN0
1
12
14
Thermocouple Type k
13
Gain = 128
CAP
DRDY/DOUT
CAP
SCLK
PDWN
11
19
AINP1
XTAL2
24
23
22
4
MSP430x4xx
or Other
Microprocessor
AINN1
AINP2
CLKIN/XTAL1
AINN2
SPEED
A0
15
REFN
AGND
17
TEMP
3
21
8
7
DGND
2, 5, 6
GND
Figure 43. Ungrounded Junction Thermocouple Application
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
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ADS1232
ADS1234
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SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
5V
3V
R1
50kW
0.1mF
18
1
AVDD
19
ADS1232
16
9
REF1004- 2.5V
REFP
GAIN0
GAIN1
DRDY/DOUT
10
CAP
SCLK
PDWN
11
1
12
Thermocouple Type k
14
13
20 Gain = 2
CAP
0.1mF
2
VDD
DVDD
AINP1
XTAL2
24
23
22
4
MSP430x4xx
or Other
Microprocessor
AINN1
AINP2
CLKIN/XTAL1
AINN2
SPEED
A0
3
21
8
7
15
REFN
AGND
17
TEMP
DGND
2, 5, 6
GND
Figure 44. Grounded Junction Thermocouple Application
26
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
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SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
RTDs and Thermistors
Figure 45 shows a typical schematic for a style 2
(three-wire) RTD application. R1 and R2 are used to
excite the RTD as well as establish the
common-mode voltage of the ADS1232 PGA.
By using both differential channels of the ADS1232,
the temperature change in lead resistance, RL, can
be eliminated. This condition is accomplished by
using the following formula:
(AINP1 – AINN1) – 2(AINP2 – AINN2).
5V
3V
0.1mF
18
1
AVDD
VDD
DVDD
20
ADS1232
16
9
0.1mF
10
R1
33kW
REFP
GAIN1
GAIN0
Gain = 128
CAP
DRDY/DOUT
CAP
SCLK
PDWN
RL
14
11
RL
RTD
13
RL
12
AINP2
XTAL2
24
23
22
4
MSP430x4xx
or Other
Microprocessor
AINP1
AINN2
CLKIN/XTAL1
AINN1
SPEED
R2
33kW
A0
3
21
8
7
15
REFN
AGND
17
NOTE: RL is lead resistance.
19
TEMP
DGND
2, 5, 6
GND
Figure 45. Style 2 (Three-Wire) RTD Schematic
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Product Folder Link(s): ADS1232 ADS1234
27
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
SUMMARY OF SERIAL INTERFACE WAVEFORMS
DRDY/DOUT
23
22
21
0
MSB
SCLK
LSB
1
24
(a) Data Retrieval
DRDY/DOUT
23
SCLK
22
21
0
1
24
25
(b) Data Retrieval with DRDY/DOUT Forced High Afterwards
Data Ready
After Calibration
DRDY/DOUT
23
SCLK
22
21
0
1
24
Calibration Begins
25
26
(c) Offset−Calibration Timing
Data Ready
Standby Mode
23
DRDY/DOUT
22
21
0
Start
Conversion
SCLK
1
24
(d) Standby Mode/Single Conversions
Data Ready
After Calibration
Standby Mode
DRDY/DOUT
23
22
21
0
Calibration Begins
SCLK
1
24
25
(e) Standby Mode/Single Conversions with Offset Calibration
Figure 46. Summary of Serial Interface Waveforms
28
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
ADS1232
ADS1234
www.ti.com
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
Revision History
Changes from Revision E (October 2007) to Revision F ............................................................................................... Page
•
•
Changed AVDD to deltaV in Common-Mode Rejection section in Electrical Characteristics table....................................... 3
Changed AVDD to deltaV in Power-Supply Rejection section in Electrical Characteristics table ......................................... 3
Changes from Revision D (September 2007) to Revision E .......................................................................................... Page
•
Corrected unit values in Electrical Characteristics table........................................................................................................ 3
Changes from Revision C (June 2006) to Revision D .................................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Deleted Logic Level VIH row for CLKIN/XTAL test condition in Electrical Characteristics..................................................... 3
Added offset drift and gain drift histogram plots to Typical Characteristics (Figure 9 to Figure 16)...................................... 9
Changed difference voltage output for PGA = 2 from 323.4mV to 223.4mV in Temperature Sensor section.................... 13
Added text to Voltage Reference Inputs section regarding reference and drift noise ......................................................... 14
Changed ZEFF equation........................................................................................................................................................ 15
Changed Figure 28 ............................................................................................................................................................. 15
Changed Figure 29 ............................................................................................................................................................. 15
Deleted last sentence of Clock Sources section ................................................................................................................. 15
Changed text in Settling Time section ................................................................................................................................. 17
Changed Figure 32 ............................................................................................................................................................. 17
Changed Figure 33 ............................................................................................................................................................. 17
Deleted 2nd sentence of Serial Clock Input section ............................................................................................................ 18
Added Power-Up Sequence section, with new text and two new figures (Figure 39 and Figure 40). ................................ 23
Changed Figure 42 ............................................................................................................................................................. 25
Changed Figure 43 ............................................................................................................................................................. 25
Changed Figure 44 ............................................................................................................................................................. 26
Changed Figure 45 ............................................................................................................................................................. 27
Changes from Revision B (September 2005) to Revision C .......................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
Deleted last row from Absolute Maximum Ratings table. ...................................................................................................... 2
Changed Analog Inputs section of Electrical Characteristics table ....................................................................................... 3
Changed the typical value in last row of Voltage Reference Input section of Electrical Characteristics table ...................... 3
Added footnote 1 to Table 1, Table 2, Table 3, and Table 4................................................................................................. 5
Changed fourth sentence in Temperature Sensor section of Overview. ............................................................................. 13
Added fifth and sixth sentences to Temperature Sensor section of Overview. ................................................................... 13
Added fourth and fifth sentences to Low-Noise PGA section of Overview.......................................................................... 14
Changed Figure 27. ............................................................................................................................................................. 14
Changed t11 to t10 in third paragraph of Standby Mode section of Overview. ..................................................................... 21
Changed min and max variables of t10 row in table below Figure 37. ................................................................................. 21
Changed Figure 41. ............................................................................................................................................................. 23
Added last row and second footnote to table below Figure 41............................................................................................ 23
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
29
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1232IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1232IPWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1232IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1232IPWRG4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1232
ADS1234IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1234
ADS1234IPWG4
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1234
ADS1234IPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1234
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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