ADS1245IDGSTG4

ADS1245 SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Low-Power, 24-Bit Analog-to-Digital Converter FEATURES DESCRIPTION D D D D D D D D D D D D D D D The ADS1245 is a 24-bit, delta-sigma analog-to-digital converter (ADC). It offers excellent performance and very low power in an MSOP-10 package and is well suited for demanding high-resolution measurements, especially in portable and other space- and power-constrained systems. 20-Bit Effective Resolution High-Impedance Buffered Input ±2.5V Differential Input Range Pin-Compatible with ADS1244 0.0006% INL (typ), 0.0015% INL (max) Simple Two-Wire Serial Interface Simultaneous 50Hz and 60Hz Rejection Single Conversions with Sleep Mode Single-Cycle Settling Self-Calibration Well Suited for Multi-Channel Systems Easily Connects to the MSP430 Current Consumption: 158µA Analog Supply: 2.5V to 5.25V Digital Supply: 1.8V to 3.6V A third-order delta-sigma (∆Σ) modulator and digital filter form the basis of the ADC. The analog modulator has a ±2.5V differential input range. The digital filter rejects both 50Hz and 60Hz signals, completely settles in one cycle, and outputs data at 15 samples per second (SPS). A simple, two-wire serial interface provides all the necessary control. Data retrieval, self-calibration, and Sleep mode are handled with a few simple waveforms. When only single conversions are needed, the ADS1245 can be shut down (Sleep mode) while idle between measurements to dramatically reduce the overall power dissipation. Multiple ADS1245s can be connected together to create a synchronously sampling multichannel measurement system. The ADS1245 is designed to easily connect to microcontrollers, such as the MSP430. APPLICATIONS D D D D The buffered input presents an impedance of 3GΩ, minimizing measurement errors when using high-impedance sources. The ADS1245 is compatible with ADS1244 and offers a direct upgrade path for designs requiring higher input impedance. Hand-Held Instrumentation Portable Medical Equipment Industrial Process Control Test and Measurement Systems The ADS1245 supports 2.5V to 5.25V analog supplies and 1.8V to 3.6V digital supplies. Power is typically less than 470µW in normal operation and less than 1µW during Sleep mode. VREFP VREFN AVDD DVDD CLK DRDY/DOUT AINP Buffer 3rd−Order Modulator Digital Filter AINN Serial Interface SCLK GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright  2003, Texas Instruments Incorporated
          
             
 !     !    www.ti.com  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ORDERING INFORMATION PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS1245 MSOP-10 DGS −40°C to +85°C BHI ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS1245IDGST Tape and Reel, 250 ADS1245IDGSR Tape and Reel, 2500 (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN ASSIGNMENTS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) AVDD to GND DVDD to GND ADS1245 UNIT −0.3 to +6 V DGS PACKAGE MSOP (TOP VIEW) −0.3 to +3.6 V Input Current 100, momentary mA Input Current 10, continuous mA Analog Input Voltage to GND −0.5 to AVDD + 0.5 V GND 1 10 CLK Analog Input Voltage to GND −0.3 to DVDD + 0.3 V VREFP 2 9 SCLK Digital Output Voltage to GND −0.3 to DVDD + 0.3 V VREFN 3 8 DRDY/DOUT +150 °C 4 7 DVDD −40 to +85 °C AINN Operating Temperature Range Storage Temperature Range −60 to +150 °C AINP 5 6 AVDD Maximum Junction Temperature ADS1245 Lead Temperature (soldering, 10s) +300 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 2 Terminal Functions TERMINAL NAME NO. DESCRIPTION GND 1 Analog and digital ground VREFP 2 Positive reference input VREFN 3 Negative reference input AINN 4 Negative analog input AINP 5 Positive analog input AVDD 6 Analog power supply, 2.5V to 5.25V DVDD 7 Digital power supply, 1.8V to 3.6V DRDY/DOUT 8 Dual-purpose output: Data ready: indicates valid data by going low. Data output: outputs data, MSB first, on the first rising edge of SCLK. SCLK 9 Serial clock input: clocks out data on the rising edge. Used to initiate calibration and Sleep mode (see text for more details). CLK 10 System clock input: typically 2.4576MHz  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise noted. PARAMETER Analog Input Full-scale input voltage range Absolute input range Differential input impedance System Performance Resolution Data rate Integral nonlinearity (INL) Offset error Offset error drift(3) Gain error(4) Gain error drift(3) Common-mode rejection Normal-mode rejection TEST CONDITIONS AINP − AINN AINP, AINN with respect to GND fCLK = 2.4576MHz No missing codes fCLK = 2.4576MHz Differential input signal, end point fit At DC fCM(5) = 50 ± 1Hz, fCLK = 2.4576MHz fCM = 60 ± 1Hz, fCLK = 2.4576MHz fSIG(6) = 50 ± 1Hz, fCLK = 2.4576MHz fSIG = 60 ± 1Hz, fCLK = 2.4576MHz MIN Voltage Reference Input Reference input voltage (VREF) Negative reference input (VREFN) Positive reference input (VREFP) Voltage reference impedance Digital Input/Output VIH (CLK, SCLK) VIL (CLK, SCLK) Logic levels VOH (DRDY, DOUT) VOL (DRDY, DOUT) Input leakage (CLK, SCLK) CLK frequency (fCLK) CLK duty cycle DVDD current Total power dissipation UNIT AVDD − 1.25 V V GΩ 3 24 90 100 100 60 70 15 ±0.0006 1 0.01 0.005 0.5 100 ±0.0015 14 At DC, ∆AVDD = 5% At DC, ∆AVDD = 5% VREF ≡ VREFP − VREFN 0.1 fCLK = 2.4576MHz IOH = 1mA IOL = 1mA 0 < (CLK, SCLK) < DVDD 1.25 30 2.7 1.8 Sleep mode AVDD = 3V AVDD = 5V Sleep mode, CLK stopped Sleep mode, 2.4576MHZ CLK running DVDD = 3V AVDD = DVDD = 3V 0.1 152 158 0.1 1.6 5 0.47 % AVDD(7) VREFP − 0.5 AVDD + 0.1 V V V MΩ 5.25 0.2 DVDD DVDD DVDD + 0.4 ±10 6 70 V V V V 1 0.8 DVDD GND DVDD − 0.4 GND ppm of FSR ppm/°C dB dB dB dB dB ppm of FSR, RMS dB dB 100 100 0.5 GND − 0.1 VREFN + 0.5 Bits SPS(1) %FSR(2) ppm of FSR/°C 2 Power Supply AVDD DVDD AVDD current MAX ±2VREF GND + 0.1 Input referred noise Analog power-supply rejection Digital power-supply rejection TYP 5.25 3.6 1 µA MHz % V V µA µA 250 µA µA 5 10 µA µA mW (1) SPS = samples per second. (2) FSR = full-scale range = 4VREF. (3) Recalibration can reduce these errors to the level of the noise. (4) Achieving specified gain error performance requires that calibration be performed with reference voltage input between (GND + 0.1V) and (AVDD − 1.25V). See Voltage Reference Inputs section. (5) fCM is the frequency of the common-mode input. (6) fSIG is the frequency of the input signal. (7) It will not be possible to reach the digital output full-scale code when VIN > 2VREF. 3  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE 220 12 210 200 10 DVDD = +3V, fCLK = 4.9152MHz 180 AVDD = +5V, fCLK = 4.9152MHz Current (µA) Current (µA) 190 170 160 150 6 4 AVDD = +3V, fCLK = 2.4576MHz 140 8 130 2 120 110 100 DVDD = +1.8V, fCLK = 2.4576MHz 0 −45 −25 −5 15 35 55 75 −45 95 −5 15 Figure 2 75 95 DIGITAL CURRENT vs DIGITAL SUPPLY 16 162 14 160 Current (µA) 12 158 fCLK = 4.9152Hz 156 154 152 fCLK = 4.9152MHz 10 8 6 4 fCLK = 2.4576MHz 150 fCLK = 2.4576MHz 2 148 2.5 3.0 3.5 4.0 4.5 5.0 0 5.5 Analog Supply (V) −45 −25 −5 15 35 55 75 95 Digital Supply (V) Figure 3 Figure 4 INTEGRAL NONLINEARITY vs ANALOG SUPPLY VREF = 1.25; fOSC = 2.4576MHz VCM = 2.4 or (( AVDD − 1.8)/2 + 0.3), whichever is smaller INTEGRAL NONLINEARITY vs VIN 30 12.5 10.0 25 T = +25_C 7.5 20 INL (ppm of FSR) INL (ppm of FSR) 55 Figure 1 ANALOG CURRENT vs ANALOG SUPPLY T = − 40_C 15 10 T = +25_ C 5.0 2.5 T = +85_ C 0 −2.5 −5.0 −7.5 5 0 2.5 3.0 3.5 T = −40_C −10.0 T = +85_ C 4.0 AVDD (V) Figure 5 4 35 Temperature (_C) 164 Current (µA) −25 Temperature (_ C) 4.5 5.0 5.5 −12.5 −2.5 −1.5 −0.5 0.5 VIN (V) Figure 6 1.5 2.5  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. GAIN vs TEMPERATURE 1.00006 4 1.00005 3 1.00004 2 Gain (Normalized) Normalized Offset (ppm of FSR) OFFSET vs TEMPERATURE 5 1 0 −1 −2 1.00002 1.00001 1.00000 0.99999 0.99998 0.99997 −3 0.99996 −4 −5 1.00003 −45 −25 −5 15 35 55 75 95 0.99995 0.99994 −45 −25 −5 Temperature (_C) 15 35 55 75 95 Temperature (_ C) Figure 7 Figure 8 NOISE vs TEMPERATURE NOISE vs INPUT SIGNAL 3.0 3.2 Noise (ppm of FSR, RMS) Noise (ppm of FSR, RMS) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 2.5 2.0 1.5 1.0 0.5 1.4 1.2 −2.5 0 −1.5 −0.5 0.5 1.5 −45 2.5 −25 VIN (V) −5 15 35 55 75 95 Temperature (_C) Figure 9 Figure 10 COMMON−MODE REJECTION RATIO vs FREQUENCY HISTOGRAM OF OUTPUT DATA 900 160 140 700 120 CMRR (dB) 600 500 400 300 200 100 80 60 40 100 20 0 −14 −12 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of Occurences 800 ppm of FSR Figure 11 0 1 10 100 1k 10k 100k Frequency (Hz) Figure 12 5  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. DIGITAL POWER−SUPPLY REJECTION RATIO vs FREQUENCY 140 140 120 120 100 100 PSRR (dB) PSRR (dB) ANALOG POWER−SUPPLY REJECTION RATIO vs FREQUENCY 80 60 60 40 40 20 20 0 0 1 10 100 1k Frequency (Hz) Figure 13 6 80 10k 100k 1 10 100 1k Frequency (Hz) Figure 14 10k 100k  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 OVERVIEW The ADS1245 is an ADC comprised of a 3rd-order modulator followed by a digital filter. The modulator measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). Figure 15 shows a conceptual diagram. The differential reference is scaled internally so that the full-scale input range is ±2VREF. The digital filter receives the modulator signal and provides a low-noise digital output. The filter also sets the frequency response of the converter and provides 50Hz and 60Hz rejection while settling in a single conversion cycle. A two-wire serial interface indicates conversion completion and provides the user with the output data. VREFP VREFN The ADS1245 accepts differential input signals, but can also measure unipolar signals. Note that the analog inputs (listed in the Electrical Characteristics table as Absolute Input Range) must remain between GND + 0.1V to AVDD − 1.25V. Exceeding this range will degrade linearity and result in performance outside specified limits. VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN: VREF = VREFP – VREFN. A simplified diagram of the circuitry on the reference inputs is shown in Figure 17. The switches and capacitors can be modeled with an effective impedance equal to: ǒt Σ SAMPLE 2 Ǔń25pF + 1MW for f CLK + 2.4576MHz CLK VREF 2 2VREF AINP AINN X1 X1 Σ VIN VREFP Digital Filter and Serial Interface Modulator VREFN DRDY/DOUT SCLK AVDD AVDD S1 Figure 15. Conceptual Diagram of the ADS1245 S1 ESD Protection 25pF ANALOG INPUTS (AINP, AINN) The input signal to be measured is applied to the input pins AINP and AINN. The ADS1245 features a low-drift chopper-stabilized buffer to achieve very high input impedance. The input impedance can be modeled by resistors, as shown in Figure 16. The impedance scales inversely with fCLK frequency. For example, if the frequency of fCLK is reduced by a factor of two, the impedances ZeffA and ZeffB will double. S2 tSAMPLE = 128/fCLK ON S1 OFF ON S2 OFF AVDD/2 Zeff A = 280GΩ Figure 17. Simplified Reference Input Circuitry Zeff B = 3.46GΩ The ADS1245 is specified for operation with VREF = 1.25V, resulting in a full−scale input value of ±2.5V. However, the buffered analog inputs can accept voltages within the range of 0.10V to 3.75V, resulting in a maximum VIN of ±3.65V. Input voltages can be accurately measured over this entire range if a voltage reference of 1.825V is provided. In any case, digital output codes will clip to the full scale value if the absolute input voltage range exceeds 2VREF. AINP AINN Zeff A = 280GΩ AVDD/2 fCLK = 2.4576MHz. Figure 16. Effective Analog Input Impedances 7  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 For best performance, bypass the voltage reference inputs with a 0.1µF capacitor between VREFP and VREFN. Place the capacitor as close as possible to the pins. ESD diodes protect the inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below GND by more than 100mV, and likewise do not exceed AVDD by 100mV. CLOCK INPUT (CLK) This digital input supplies the system clock to the ADS1245. The recommended CLK frequency is 2.4576MHz. This places the notches of the digital filter at 50Hz and 60Hz and sets the data rate at 15SPS. The CLK frequency can be increased to speed up the data rate, but the frequency notches will move proportionally in frequency. CLK must be left running during normal operation. It can be turned off during Sleep Mode to save power, but this is not required. The CLK input can be driven with 5V logic, regardless of the DVDD or AVDD voltage. Minimize the overshoot and undershoot on CLK for the best analog performance. A small resistor in series with CLK (10Ω to 100Ω) can often help. CLK can be generated from a number of sources including stand-alone crystal oscillators and microcontrollers. The MSP430, an ultra low power microcontroller, is especially well-suited for this task. Using the MSP430 FLL clock generator available on the 4xx family, it is easy to produce a 2.4576MHz clock from a 32.768kHz crystal. subsequent SCLK rising edge. After all 24 bits have been retrieved, the pin can be forced high with an additional SCLK. It will then stay high until new data is ready. This is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. SERIAL CLOCK INPUT (SCLK) This digital input shifts serial data out with each rising edge. As with CLK, this input may be driven with 5V logic regardless of the DVDD or AVDD voltage. There is hysteresis built into this input, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise-and-fall times of SCLK are less than 50ns. FREQUENCY RESPONSE The ADS1245 frequency response for fCLK = 2.4576MHz is shown in Figure 18. The frequency response repeats at multiples of 19.2kHz. The overall response is that of a low-pass filter with a –3dB cutoff frequency of 13.7Hz. As can be seen, the ADS1245 does a good job attenuating out to 19kHz. For the best resolution, limit the input bandwidth to below this value to keep higher frequency noise from affecting performance. Often, a simple RC filter on the ADS1245 analog inputs is all that is needed. 0 f CLK = 2.4576MHz −20 −40 Gain (dB) To achieve optimal gain error performance, the reference input should be maintained within the range GND + 0.1V to AVDD − 1.25V when performing a self-calibration. A calibration based on a reference input outside this voltage range will result in gain errors exceeding specified values, but not more than 0.5%. Errors due to drift will remain within specified limits regardless of the calibration procedure. −60 −80 −100 DATA READY/DATA OUTPUT (DRDY/DOUT) The digital output pin on the ADS1245 serves two purposes. It indicates when new data is ready by going low. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, MSB first. Data is shifted out on each 8 −120 −140 0 9.6 Frequency (kHz) Figure 18. Frequency Response 19.2  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 To help see the response at lower frequencies, Figure 19 illustrates the response out to 180Hz. Notice that both 50Hz and 60Hz signals are rejected. This feature is very useful for eliminating power line cycle interference during measurements. Figure 20 shows the ADS1245 response around these frequencies. SETTLING TIME 0 −60 The ADS1245 has single-cycle settling. That is, the output data is fully settled after a single conversion—there is no need to wait for additional conversions before retrieving the data when there is a change on the analog inputs. −80 In order to realize single-cycle settling, synchronize −20 Gain (dB) −40 fCLK = 2.4576MHz −100 −120 −140 −160 180 150 160 170 130 140 110 120 90 100 60 70 80 40 50 20 30 0 10 −180 Frequency (Hz) Figure 19. Frequency Response to 180Hz changes on the analog inputs to the conversion beginning, which is indicated by the falling edge of DRDY/DOUT. For example, when using a multiplexer in front of the ADS1245, change the multiplexer inputs when DRDY/DOUT goes low. Increasing the time between the conversion beginning and the change on the analog inputs (tDELAY) results in a settling error in the conversion data, as shown in Figure 21. The settling error versus delay time is shown in Figure 22. If the input change is delayed to the point where the settling error is too high, simply ignore the first data result and wait for the second conversion, which will be fully settled. −40 10.000000 −50 1.000000 Settling Error (%) f CLK = 2.4576MHz −60 Gain (dB) The ADS1245 data rate and frequency response scale directly with CLK frequency. For example, if fCLK increases from 2.4576MHz to 4.9152MHz, the data rate increases from 15sps to 30sps while the notches in the response at 50Hz and 60Hz move out to 100Hz and 120Hz. −70 −80 −90 −100 0.100000 fCLK = 2.4576MHz 0.010000 0.001000 0.000100 0.000010 −110 0.000001 −120 0 45 50 55 60 65 2 4 6 8 10 12 Delay Time, tDELAY (ms) 14 16 Frequency (Hz) Figure 20. Frequency Response Near 50Hz and 60Hz Figure 21. Settling Error vs Delay Time 9  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Begin New Conversion, Previous Conversion Data New Conversion Complete Complete Previous Conversion DRDY/DOUT tDELAY VIN Figure 22. Analog Input Change Timing POWER−UP Self-calibration is performed at power-up to minimize offset and gain errors. In order for the self-calibration at power-up to work properly, make sure that both AVDD and DVDD increase monotonically and are settled by t1, as shown in Figure 23. SCLK must be held low during this time. Once calibration is complete, DRDY/DOUT goes low, indicating data is ready for retrieval. The time required before the first data is ready (t6) depends on how fast AVDD and DVDD ramp to their final value (t1). For most ramp rates, t1 + t2 ≈ 350ms (fCLK = 2.4576MHz). If the system environment is not stable during power-up (the temperature is varying or the supply voltages are moving around), it is recommended that a self-calibration be issued after everything is stable. AVDD and DVDD Data ready after power−up calibration. DRDY/DOUT SCLK t1 t2 SYMBOL DESCRIPTION t1 (1) t2 (1) MIN MAX UNITS AVDD and DVDD settling time. Wait time for calibration and first data conversion. 100 316 ms ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. Figure 23. Power-Up Timing 10  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 DATA FORMAT DATA RETRIEVAL The ADS1245 outputs 24 bits of data in Binary Two’s Complement format. The least significant bit (LSB) has a weight of (2VREF)/(223 − 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 8000000h. The output clips at these codes for signals exceeding full-scale. Table 1 summarizes the ideal output codes for different input signals. The ADS1245 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as shown in Figure 24. After this occurs, begin shifting out the data by applying SCLKs. Data is shifted out most significant bit (MSB) first. It is not required to shift out all the 24 bits of data, but the data must be retrieved before the new data is updated (see t3) or else it will be overwritten. Avoid data retrieval during the update period. DRDY/DOUT remains at the state of the last bit shifted out until it is taken high (see t7), indicating that new data is being updated. Table 1. Ideal Output Code vs Input Signal INPUT SIGNAL VIN (AINP − AINN) IDEAL OUTPUT CODE(1) ≥ +2VREF 7FFFFFH ) 2VREF (223) * 1 0 000001H * 2VREF (223) * 1 FFFFFF H 000000H ǒ(2 2 * 1Ǔ 800000H 23 v * 2VREF To avoid having DRDY/DOUT remain in the state of the last bit, shift a 25th SCLK to force DRDY/DOUT high; see Figure 25. This technique is useful when a host controlling the ADS1245 is polling DRDY/DOUT to determine when data is ready. 23) NOTE: (1) Excludes effects of noise, INL, offset, and gain errors. Data Data is ready. New data is ready. MSB DRDY/DOUT 23 LSB 22 21 0 t5 t3 t6 t4 t7 1 SCLK 24 t4 t8 SYMBOL DESCRIPTION t3 DRDY/DOUT low to first SCLK rising edge. t4 t5 (1) t6 t7 t8 (2) NOTES: MIN MAX UNITS 0 ns SCLK positive or negative pulse width. SCLK rising edge to new data bit valid; propagation delay. 100 ns 50 ns SCLK rising edge to old data bit valid: hold time. Data updating, no read back allowed. Conversion time (1/data rate). 0 152 ns 152 66.667 66.667 µs ms (1) Load on DRDY/DOUT = 20pF||100kΩ. (2) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. For example, for fCLK = 4.9152MHz, t8→33.333ms. Figure 24. Data Retrieval Timing 11  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Data Data is ready. New data is ready. DRDY/DOUT 23 22 21 0 1 SCLK 24 25 25th SCLK to force DRDY/DOUT high Figure 25. Data Retrieval with DRDY/DOUT Forced High Afterwards SELF-CALIBRATION When the calibration is complete, DRDY/DOUT will go low, indicating that new data is ready. There is no need to alter the analog input signal applied to the ADS1245 during calibration; the inputs pins are disconnected within the ADC and the appropriate signals are automatically applied internally. The first conversion after a calibration is fully settled and valid for use. The time required for a calibration depends on two independent signals: the falling edge of SCLK and an internal clock derived from CLK. Variations in the internal calibration values will change the time required for calibration (t9) within the range given by the MIN/MAX specs. t12 and t13 described in the next section are likewise affected. The user can initiate self-calibration at any time, though in many applications the ADS1245 drift performance is good enough that the self-calibration performing automatically at power-up is all that is needed. To initiate a self-calibration, apply at least two additional SCLKs after retrieving 24 bits of data. Figure 26 shows the timing pattern. The 25th SCLK will send DRDY/DOUT high. The falling edge of the 26th SCLK will begin the calibration cycle. Additional SCLK pulses may be sent after the 26th SCLK, but minimizing activity on SCLK during calibration provides best results. Data ready after calibration DRDY/DOUT 23 22 21 0 23 Cal begins SCLK 1 24 25 26 t9 SYMBOL DESCRIPTION t9 (1) First data ready after calibration. MIN MAX UNITS 209 210 ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. Figure 26. Self-Calibration Timing 12  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SLEEP MODE Sleep Mode with Self-Calibration Sleep mode dramatically reduces power consumption (typically < 1µW with CLK stopped) by shutting down all of the active circuitry. To enter Sleep mode, simply hold SCLK high after DRDY/DOUT goes low, as shown in Figure 27. Sleep Mode can be initiated at any time during read-back; it is not necessary to retrieve all 24 bits of data beforehand. Once t11 has passed with SCLK held high, Sleep mode will activate. DRDY/DOUT stays high once Sleep mode begins. SCLK must remain high to stay in Sleep mode. To exit Sleep mode (wakeup), set SCLK low. The first data after exiting Sleep Mode is valid. It is not necessary to stop CLK during Sleep mode, but doing so will further reduce the digital supply current. Self-calibration can be set to run immediately after exiting Sleep mode. This is useful when the ADS1245 is put in Sleep mode for long periods of time and self-calibration is desired afterwards to compensate for temperature or supply voltage changes. To force a self-calibration with Sleep mode, shift 25 bits out before taking SCLK high to enter Sleep mode. Self-calibration begins after wakeup. Figure 28 shows the appropriate timing. Note the extra time needed after wakeup for calibration before data is ready. The first data after Sleep mode with self-calibration is fully settled and can be used. Data ready after wakeup Sleep Mode DRDY/DOUT 23 22 21 0 23 Wakeup SCLK 1 24 t10 t 11 SYMBOL t12 DESCRIPTION SCLK HIGH after DRDY/DOUT goes low to activate Sleep Mode. t10(1) t11(1) Sleep Mode activation time. t12(1) Data ready after wakeup. MIN MAX UNITS 0 63.7 ms 66.5 66.5 ms 71 72 ms NOTES: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. Figure 27. Sleep-Mode Timing; Can Be Used for SIngle Conversions Data ready after wakeup and calibration Sleep Mode DRDY/DOUT 23 22 21 0 23 Wakeup and begin cal. SCLK 1 24 25 t11 SYMBOL t13(1) DESCRIPTION Data ready after wakeup and calibration. t13 MIN MAX UNITS 210 211 ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. Figure 28. Sleep-Mode with Self-Calibration on Wakeup Timing; Can Be Used for SIngle Conversions 13  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SINGLE CONVERSIONS When only single conversions are needed, Sleep mode can be used to start and stop the ADS1245. To make a single conversion, first enter the Sleep Mode holding SCLK high. Now, when ready to start the conversion, take SCLK low. The ADS1245 will wake up and begin the conversion. Wait for DRDY/DOUT to go low, and then retrieve the data. Afterwards, take SCLK high to stop the ADS1245 from converting and re−enter Sleep mode. Continue to hold SCLK high until ready to start the next conversion. Operating in this fashion greatly reduces power consumption since the ADS1245 is shut down while idle between conversions. Self−calibrations can be performed prior to the start of the single conversions by using the waveform shown in Figure 28. to +5V logic +5V SN74LVCC3245A 0.1µF + 0.1µF + R1 from +5V logic from +5V logic 10 9 8 7 6 CLK SCLK DRDY/DOUT DVDD AVDD ADS1245 GND VREFP VREFN AINN AINP 1 2 3 4 5 SINGLE-SUPPLY OPERATION It is possible to operate the ADS1245 with a single supply. For a 3V supply, simply connect AVDD and DVDD together. Figure 29 shows an example of the ADS1245 running on a single 5V supply. An external resistor, R1, is used to drop 5V supply down to a desired voltage level of DVDD. For example, if the desired DVDD supply voltage is 3V and AVDD is 5V, the value of R1 should be: R 1 + (5V * 3V)ń5mA [ 400kW (1) where 5mA is a typical digital current consumption when DVDD = 3V (refer to the typical characteristic Digital Current vs Digital Supply). A buffer on DRDY/DOUT can provide level−shifting if required. DVDD can be set to a desired voltage by choosing a proper value of R1, but keep in mind that DVDD must be set between 1.8V and 3.6V. Note that the maximum logic high output of DRDY/DOUT is equal to DVDD, but both CLK and SCLK inputs can be driven with 5V logic regardless of the DVDD or AVDD voltage. Use 0.1mF capacitors to bypass both AVDD and DVDD. 14 Figure 29. Example of the ADS1244 Running on a Single 5V Supply MULTI-CHANNEL SYSTEMS Multiple ADS1245s can be operated in parallel to measure multiple input signals. Figure 30 shows an example of a two-channel system. For simplicity, the supplies and reference circuitry were not included. The same CLK signal should be applied to all devices. To be able to synchronize the ADS1245s, connect the same SCLK signal to all devices as well. When ready to synchronize, place all the devices in Sleep mode. Afterwards, a wakeup command will synchronize all the ADS1245s; that is, they will sample the input signals simultaneously The DRDY/DOUT outputs will go low at approximately the same time after synchronization. The falling edges, indicating that new data is ready, will vary with respect to each other no more than timing specification t14. This variation is due to possible differences in the ADS1245 internal calibration settings. To account for this when using multiple devices, either wait for t14 to pass after seeing one device DRDY/DOUT go low, or wait until all DRDY/DOUTs have gone low before retrieving data.  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ADS1245 1 GND CLK 10 2 VREFP SCLK 9 3 VREFN DRDY/DOUT 8 4 AINN DVDD 7 5 AINP AVDD 6 OUT1 IN1 ADS1245 1 GND CLK 10 2 VREFP SCLK 9 3 VREFN DRDY/DOUT 8 4 AINN DVDD 7 5 AINP AVDD 6 OUT2 IN2 CLK and SCLK Sources OUT1 t14 OUT2 SYMBOL DESCRIPTION t14 Difference between DRDY/ DOUTs going low in multichannel systems. MIN MAX UNITS ± 500 µs Figure 30. Example of Using Multiple ADS1245s in Parallel 15  "#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SUMMARY OF SERIAL INTERFACE WAVEFORMS DRDY/DOUT 23 22 21 0 MSB LSB 1 SCLK 24 a. Data Retrieval DRDY/DOUT 23 SCLK 22 21 0 1 24 25 b. Data Retrieval with DRDY/DOUT Forced High Afterwards Data ready after calibration DRDY/DOUT 23 22 21 0 Begin calibration SCLK 1 24 25 26 c. Self-Calibration Data ready Sleep Mode 23 DRDY/DOUT 22 21 0 Wakeup and start conversion SCLK 1 24 d. Sleep Mode/Single Conversions Data ready after wakeup and calibration Sleep Mode DRDY/DOUT 23 22 21 0 Wakeup and begin cal. SCLK 1 24 25 e. Sleep Mode/Single Conversions with Self-Calibration on Wakeup Figure 31. Summary of Serial Interface Waveforms 16 PACKAGE OPTION ADDENDUM www.ti.com 25-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1245IDGST ACTIVE VSSOP DGS 10 250 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BHI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of