ADS1251U/2K5G4

ADS1251 ADS 125 1 SBAS184D – MARCH 2001 – REVISED JUNE 2009 24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS—NO MISSING CODES ● 19 BITS EFFECTIVE RESOLUTION UP TO 20kHz DATA RATE ● LOW NOISE: 1.5ppm ● DIFFERENTIAL INPUTS ● INL: 15ppm (max) ● EXTERNAL REFERENCE (0.5V to 5V) ● POWER-DOWN MODE ● SYNC MODE ● LOW POWER: 8mW at 20kHz 5mW at 10kHz The ADS1251 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from a single +5V supply. The delta-sigma architecture features wide dynamic range, and 24 bits of no missing code performance. Effective resolution of 19 bits (1.5ppm of rms noise) is achieved at conversion rates up to 20kHz. The ADS1251 is designed for high-resolution measurement applications in cardiac diagnostics, smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. The converter includes a flexible, 2-wire synchronous serial interface for low-cost isolation. The ADS1251 is a single-channel converter and is offered in an SO-8 package. It is pin-compatible with the faster ADS1252 (41.7kHz data rate). APPLICATIONS ● ● ● ● ● ● CARDIAC DIAGNOSTICS DIRECT THERMOCOUPLE INTERFACES BLOOD ANALYSIS INFRARED PYROMETERS LIQUID/GAS CHROMATOGRAPHY PRECISION PROCESS CONTROL ADS1251 VREF CLK +VIN –VIN 4th-Order ∆Σ Modulator Digital Filter Serial Interface SCLK DOUT/DRDY +VDD GND Control Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2001-2009, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Input: Current ............................................... ±100mA, Momentary ±10mA, Continuous Voltage .................................... GND – 0.3V to VDD + 0.3V VDD to GND ............................................................................ –0.3V to 6V VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Operating Temperature ...................................................... –40°C to 85°C Power Dissipation .......................................................................... 500mW This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING SO-8 D –40°C to +85°C ADS1251U ADS1251U Rails, 100 " " " " ADS1251U/2K5 Tape and Reel, 2500 ADS1251 " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PRODUCT FAMILY PRODUCT ADS1250 ADS1251 ADS1252 ADS1253 ADS1254 # OF INPUTS 1 1 1 4 4 MAXIMUM DATA RATE Differential Differential Differential Differential Differential 25.0kHz 20.8kHz 41.7kHz 20.8kHz 20.8kHz COMMENTS Includes PGA from 1 to 8 Includes Separate Analog and Digital Supplies ELECTRICAL CHARACTERISTICS All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. ADS1251U PARAMETER ANALOG INPUT Full-Scale Input Voltage Absolute Input Voltage Differential Input Impedance Input Capacitance Input Leakage DYNAMIC CHARACTERISTICS Data Rate Bandwidth Serial Clock (SCLK) System Clock Input (CLK) ACCURACY Integral Nonlinearity THD Noise Resolution No Missing Codes Common-Mode Rejection Gain Error Offset Error Gain Sensitivity to VREF Power-Supply Rejection Ratio CONDITIONS +VIN – (–VIN) +VIN or –VIN to GND CLK = 3.84kHz CLK = 1MHz CLK = 8MHz TYP MAX ±VREF –0.3 VDD 430 1.7 210 6 5 At +25°C At TMIN to TMAX 50 1 20.8 –3dB, CLK = 8MHz 4.24 8 8 ±0.0002 105 1.5 Differential Input 1kHz Input; 0.1dB below FS 60Hz, AC 24 24 90 70 PERFORMANCE OVER TEMPERATURE Offset Drift Gain Drift 2 MIN 98 0.1 ±30 1:1 80 0.07 0.4 ±0.0015 2.5 1 ±100 UNITS V V MΩ MΩ kΩ pF pA nA kHz kHz MHz MHz % of FSR dB ppm of FSR, rms Bits Bits dB % of FSR ppm of FSR dB ppm/°C ppm/°C ADS1251 www.ti.com SBAS184D ELECTRICAL CHARACTERISTICS (Cont.) All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. ADS1251U PARAMETER CONDITIONS VOLTAGE REFERENCE VREF Load Current DIGITAL INPUT/OUTPUT Logic Family Logic Level: VIH VIL VOH VOL Input (SCLK, CLK) Hysteresis Data Format MIN TYP MAX UNITS 0.5 4.096 32 VDD V µA +VDD + 0.3 +0.8 V V V V V CMOS +4.0 –0.3 +4.5 IOH = –500µA IOL = 500µA 0.4 0.6 Offset Binary Two’s Complement POWER-SUPPLY REQUIREMENTS Operation Quiescent Current Operating Power Power-Down Current +4.75 +5 1.5 7.5 0.4 VDD = +5VDC TEMPERATURE RANGE Operating Storage –40 –60 PIN CONFIGURATION VDC mA mW µA +85 +100 °C °C PIN DESCRIPTIONS Top View SO +VIN 1 8 VREF –VIN 2 7 GND +VDD 3 6 SCLK CLK 4 5 DOUT/DRDY PIN NAME 1 +VIN Analog Input: Positive Input of the Differential Analog Input 2 –VIN Analog Input: Negative Input of the Differential Analog Input. 3 +VDD Input: Power-Supply Voltage, +5V 4 CLK Digital Input: Device System Clock. The system clock is in the form of a CMOScompatible clock. This is a Schmitt-Trigger input. 5 DOUT/DRDY Digital Output: Serial Data Output/Data Ready. This output indicates that a new output word is available from the ADS1251 data output register. The serial data is clocked out of the serial data output shift register using SCLK. 6 SCLK Digital Input: Serial Clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock operates independently from the system clock, therefore, it is possible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW. Holding SCLK HIGH will either initiate a modulator reset for synchronizing multiple converters or enter power-down mode. This is a Schmitt-Trigger input. 7 GND Input: Ground 8 VREF Analog Input: Reference Voltage Input ADS1251U ADS1251 SBAS184D +5.25 2 10 1 www.ti.com PIN DESCRIPTION 3 TYPICAL CHARACTERISTICS At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. RMS NOISE vs DATA RATE EFFECTIVE RESOLUTION vs DATA OUTPUT RATE 20.0 1.6 Effective Resolution (Bits) RMS Noise (ppm of FS) 2.0 1.2 0.8 0.4 0 19.5 19.0 18.5 18.0 10 100 1k 10k 100k 100 1k Data Rate (Hz) RMS NOISE vs TEMPERATURE 1.8 Effective Resolution (Bits) RMS Noise (ppm of FS) 19.5 1.6 1.4 1.2 19.0 18.5 18.0 1.0 –40 –20 0 20 40 60 80 100 –40 –20 0 Temperature (°C) 20 40 60 80 100 Temperature (°C) RMS NOISE vs VREF VOLTAGE RMS NOISE vs VREF VOLTAGE 18 14 16 12 RMS Noise (ppm of FS) 14 RMS Noise (µV) 100k EFFECTIVE RESOLUTION vs TEMPERATURE 2.0 12 10 8 6 4 10 8 6 4 2 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 VREF Voltage (V) VREF Voltage (V) 4 10k Data Output Rate (Hz) ADS1251 www.ti.com SBAS184D TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. INTEGRAL NONLINEARITY vs TEMPERATURE RMS NOISE vs INPUT VOLTAGE 4.0 2.0 RMS Noise (ppm of FS) 3.5 3.0 INL (ppm of FS) 1.5 1.0 2.5 2.0 1.5 1.0 0.5 0.5 0 0 –5 –4 –3 –2 –1 0 1 2 3 4 –40 5 –20 0 20 40 60 80 100 80 100 7 8 Temperature (°C) Input Voltage (V) OFFSET vs TEMPERATURE INTEGRAL NONLINEARITY vs DATA OUTPUT RATE 40 5 35 Offset (ppm of FS) INL (ppm of FS) 4 3 2 30 25 20 15 10 1 5 0 0 100 1k 10k –40 100k 0 20 40 60 Temperature (°C) GAIN ERROR vs TEMPERATURE POWER-SUPPLY REJECTION RATIO vs CLK FREQUENCY 650 –60 –65 625 –70 600 PSRR (dB) Gain Error (ppm of FS) –20 Data Output Rate (Hz) 575 550 –75 –80 –85 –90 525 –95 500 –100 –40 –20 0 20 40 60 80 100 1 Temperature (°C) 3 4 5 6 Clock Frequency (MHz) ADS1251 SBAS184D 2 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. COMMON-MODE REJECTION RATIO vs COMMON-MODE FREQUENCY –60 –60 –65 –65 –70 –70 –75 –75 CMRR (dB) CMRR at 60Hz (dB) COMMON-MODE REJECTION RATIO vs CLK FREQUENCY –80 –85 –80 –85 –90 –90 –95 –95 –100 –100 –105 –105 1 2 3 4 5 6 7 8 10 100 Clock Frequency (MHz) 1k 10k 100k Common-Mode Signal Frequency (Hz) CURRENT vs TEMPERATURE POWER DISSIPATION vs CLK FREQUENCY 1.65 9 8 Power Dissipation (mW) Current (mA) 1.60 1.55 1.50 1.45 7 6 5 4 3 2 1 1.40 0 –20 0 20 40 60 80 100 0 2 3 4 5 6 7 Clock Frequency (MHz) VREF CURRENT vs CLK FREQUENCY TYPICAL FFT (1kHz input at 0.1dB less than full-scale) 35 0 30 –20 25 20 15 10 5 8 –40 –60 –80 –100 –120 –140 –160 0 0.1 1 0 10 1 2 3 4 5 6 7 8 9 10 11 Frequency (kHz) Clock Frequency (MHz) 6 1 Temperature (°C) Relative Magnitude (dB) VREF Current (µA) –40 ADS1251 www.ti.com SBAS184D THEORY OF OPERATION The ADS1251 is a precision, high-dynamic range, 24-bit, delta-sigma, A/D converter capable of achieving very high-resolution digital results at high data rates. The analog input signal is sampled at a rate determined by the frequency of the system clock (CLK). The sampled analog input is modulated by the delta-sigma A/D modulator, which is followed by a digital filter. A Sinc5 digital low-pass filter processes the output of the delta-sigma modulator and writes the result into the data-output register. The DOUT/DRDY pin is pulled LOW, indicating that new data are available to be read by the external microcontroller/microprocessor. As shown in the block diagram on the front page, the main functional blocks of the ADS1251 are the 4th-order delta-sigma modulator, a digital filter, control logic, and a serial interface. Each of these functional blocks is described in the following sections. ANALOG INPUT The ADS1251 contains a fully differential analog input. In order to provide low system noise, common-mode rejection of 98dB, and excellent power-supply rejection, the design topology is based on a fully differential switched-capacitor architecture. The bipolar input voltage range is from –4.096 to +4.096V, when the reference input voltage equals +4.096V. The bipolar range is with respect to –VIN, and not with respect to GND. clock frequency of 8MHz, the data output rate is 20.8kHz with a –3dB frequency of 4.24kHz. The –3dB frequency scales with the system clock frequency. To ensure the best linearity of the ADS1251, and to maximize the elimination of even-harmonic noise errors, a fully differential signal is recommended. For more information about the ADS1251 input structure, refer to application note SBAA086 found at www.ti.com. BIPOLAR INPUT Each of the differential inputs of the ADS1251 must stay between –0.3V and VDD. With a reference voltage at less than half of VDD, one input can be tied to the reference voltage, and the other input can range from 0V to 2 • VREF. By using a three op amp circuit featuring a single amplifier and four external resistors, the ADS1251 can be configured to accept bipolar inputs referenced to ground. The conventional ±2.5V, ±5V, and ±10V input ranges can be interfaced to the ADS1251 using the resistor values shown in Figure 1. R1 The differential input impedance of the analog input changes with the ADS1251 system clock frequency (CLK). The relationship is: 10kΩ 20kΩ Impedance (Ω) = (8MHz/CLK) • 210,000 –IN See application note Understanding the ADS1251, ADS1253, and ADS1254 Input Circuitry (SBAA086), available for download from TI’s web site www.ti.com. VREF OPA4350 OPA4350 REF 2.5V Second, the current into or out of the analog inputs must be limited. Under no conditions should the current into or out of the analog inputs exceed 10mA. Third, to prevent aliasing of the input signal, the bandwidth of the analog-input signal must be band-limited; the bandwidth is a function of the system clock frequency. With a system ADS1251 R2 With regard to the analog-input signal, the overall analog performance of the device is affected by three items. First, the input impedance can affect accuracy. If the source impedance of the input signal is significant, or if there is passive filtering prior to the ADS1251, a significant portion of the signal can be lost across this external impedance. The magnitude of the effect is dependent on the desired system performance. BIPOLAR INPUT R1 R2 ±10V ±5V ±2.5V 2.5kΩ 5kΩ 10kΩ 5kΩ 10kΩ 20kΩ FIGURE 1. Level-Shift Circuit for Bipolar Input Ranges. ADS1251 SBAS184D +IN OPA4350 Bipolar Input www.ti.com 7 DELTA-SIGMA MODULATOR REFERENCE INPUT The ADS1251 operates from a nominal system clock frequency of 8MHz. The modulator frequency is fixed in relation to the system clock frequency. The system clock frequency is divided by 6 to derive the modulator frequency (fMOD). Therefore, with a system clock frequency of 8MHz, the modulator frequency is 1.333MHz. Furthermore, the oversampling ratio of the modulator is fixed in relation to the modulator frequency. The oversampling ratio of the modulator is 64, and with the modulator frequency running at 1.333MHz, the data rate is 20.8kHz. Using a slower system clock frequency will result in a lower data output rate, as shown in Table I. The reference input takes an average current of 32µA with a 8MHz system clock. This current will be proportional to the system clock. A buffered reference is recommended for the ADS1251. The recommended reference circuit is shown in Figure 2. Reference voltages higher than 4.096V will increase the fullscale range, while the absolute internal circuit noise of the converter remains the same. This will decrease the noise in terms of ppm of full-scale, which increases the effective resolution (see typical characteristic RMS Noise vs VREF Voltage). DIGITAL FILTER CLK (MHz) DATA OUTPUT RATE (Hz) 8(1) 7.372800(1) 6.144000(1) 6.000000(1) 4.915200(1) 3.686400(1) 3.072000(1) 2.457600(1) 1.843200(1) 0.921600 0.460800 0.384000 0.192000 0.038400 0.023040 0.019200 0.011520 0.009600 0.007680 0.006400 0.005760 0.004800 0.003840 20,833 19,200 16,000 15,625 12,800 9600 8000 6400 4800 2400 1200 1000 500 100 60 50 30 25 20 16.67 15 12.50 10 The digital filter of the ADS1251, referred to as a Sinc5 filter, computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as averaging the modulator results in a weighted form and presenting this average as the digital output. The digital output rate, or data rate, scales directly with the system clock frequency. This allows the data output rate to be changed over a very wide range (five orders of magnitude) by changing the system clock frequency. However, it is important to note that the –3dB point of the filter is 0.2035 times the data output rate, so the data output rate should allow for sufficient margin to prevent attenuation of the signal of interest. As the conversion result is essentially an average, the data-output rate determines the location of the resulting notches in the digital filter (see Figure 3). Note that the first notch is located at the data output rate frequency, and subsequent notches are located at integer multiples of the data output rate; this allows for rejection of not only the fundamental frequency, but also harmonic frequencies. In this manner, the data output rate can be used to set specific notch frequencies in the digital filter response. NOTE: (1) Standard Clock Oscillator. TABLE I. CLK Rate versus Data Output Rate. For example, if the rejection of power-line frequencies is desired, then the data output rate can simply be set to the power-line frequency. For 50Hz rejection, the system clock +5V +5V 0.10µF 7 0.1µF 2 1 REF3040 2 3 OPA350 + + 3 To VREF Pin 8 of the ADS1251 6 10kΩ 0.1µF 10µF 0.10µF 10µF 0.1µF 4 FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1251. 8 ADS1251 www.ti.com SBAS184D frequency must be 19.200kHz, and this sets the data output rate to 50Hz (see Table I and Figure 4). For 60Hz rejection, the system CLK frequency must be 23.040kHz, and this sets the data output rate to 60Hz (see Table I and Figure 5). If both 50Hz and 60Hz rejection is required, then the system CLK must be 3.840kHz; this sets the data output rate to 10Hz and rejects both 50Hz and 60Hz (see Table I and Figure 6). There is an additional benefit in using a lower data output rate. It provides better rejection of signals in the frequency band of interest. For example, with a 50Hz data output rate, a significant signal at 75Hz may alias back into the passband at 25Hz. This is due to the fact that rejection at 75Hz may only be 66dB in the stopband—frequencies higher than the first notch frequency (see Figure 4). However, setting the data output rate to 10Hz provides 135dB rejection at 75Hz (see Figure 6). A similar benefit is gained at frequencies near the data output rate (see Figures 7, 8, 9, and 10). For example, with a 50Hz data output rate, rejection at 55Hz may only be 105dB (see Figure 7). With a 10Hz data output rate, however, rejection at 55Hz will be 122dB (see Figure 8). If a slower data output rate does not meet the system requirements, then the analog front-end can be designed to provide the needed attenuation to prevent aliasing. Additionally, the data output rate may be increased and additional digital filtering may be done in the processor or controller. Application note SBAA103, A Spreadsheet to Calculate the Frequency Response of the ADS1250-54, available for download from TI’s web site at www.ti.com, provides a simple tool for calculating the ADS1250 frequency response for any CLK frequency. The digital filter is described by the following transfer function:  π • f • 64  sin    fMOD  H(f) =  π•f  64 • sin    fMOD  5 ( )     CONTROL LOGIC The control logic is used for communications and control of the ADS1251. Power-Up Sequence Prior to power-up, all digital and analog input pins must be LOW. At the time of power-up, these signal inputs can be biased to a voltage other than 0V; however, they should never exceed +VDD. Once the ADS1251 powers up, the DOUT/DRDY line will pulse LOW on the first conversion for which the data is valid from the analog input signal. DOUT/DRDY The DOUT/DRDY output signal alternates between two modes of operation. The first mode of operation is the Data Ready mode (DRDY) to indicate that new data have been loaded into the data output register and are ready to be read. The second mode of operation is the Data Output (DOUT) mode and is used to serially shift data out of the Data Output Register (DOR). See Figure 11 for the time domain partitioning of the DRDY and DOUT function. See Figure 12 for the basic timing of DOUT/DRDY. During the time defined by t2, t3, and t4, the DOUT/DRDY pin functions in DRDY mode. The state of the DOUT/DRDY pin or  1 – z –64 H(z) =   64 • 1 – z –1  The digital filter requires five conversions to fully settle. The modulator has an oversampling ratio of 64; therefore, it requires 5 • 64, or 320 modulator results (or clocks) to fully settle. As the modulator clock is derived from the system CLK (modulator clock = CLK ÷ 6), the number of system clocks required for the digital filter to fully settle is 5 • 64 • 6, or 1920 CLKs. This means that any significant step change at the analog input requires five full conversions to settle. However, if the step change at the analog input occurs asynchronously to the DOUT/DRDY pulse, six conversions are required to ensure full settling. 5 ADS1251 SBAS184D www.ti.com 9 DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) NORMALIZED DIGITAL FILTER RESPONSE 0 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 1 2 3 4 5 6 7 8 9 10 0 50 100 FIGURE 3. Normalized Digital Filter Response. 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) 250 300 DIGITAL FILTER RESPONSE 0 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 50 100 150 200 250 0 300 10 20 30 Frequency (Hz) 40 50 60 70 80 90 100 Frequency (Hz) FIGURE 5. Digital Filter Response (60Hz). FIGURE 6. Digital Filter Response (10Hz Multiples). DIGITAL FILTER RESPONSE DIGITAL FILTER RESPONSE 0 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) 200 FIGURE 4. Digital Filter Response (50Hz). DIGITAL FILTER RESPONSE –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 45 46 47 48 49 50 51 52 53 54 55 45 Frequency (Hz) 46 47 48 49 50 51 52 53 54 55 Frequency (Hz) FIGURE 7. Expanded Digital Filter Response (50Hz with a 50Hz data output rate). 10 150 Frequency (Hz) Frequency (Hz) FIGURE 8. Expanded Digital Filter Response (50Hz with a 10Hz data output rate). ADS1251 www.ti.com SBAS184D DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 Gain (dB) Gain (dB) DIGITAL FILTER RESPONSE 0 –80 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 55 56 57 58 59 60 61 62 63 64 55 65 56 57 58 59 60 61 62 63 64 65 Frequency (Hz) Frequency (Hz) FIGURE 9. Expanded Digital Filter Response (60Hz with a 60Hz data output rate). FIGURE 10. Expanded Digital Filter Response (60Hz with a 10Hz data output rate). is HIGH prior to the internal transfer of new data to the DOR. The result of the A/D conversion is written to the DOR from the Most Significant Bit (MSB) to the Least Significant Bit (LSB) in the time defined by t1 (see Figures 11 and 12). The DOUT/DRDY line then pulses LOW for the time defined by t2, and then drives the line HIGH for the time defined by t3 to indicate that new data are available to be read. At this point, the function of the DOUT/DRDY pin changes to DOUT mode. Data are shifted out on the pin after t7. If the MSB is high (because of a negative result) the DOUT/DRDY signal will stay HIGH after the end of time t3. The device communicating with the ADS1251 can provide SCLKs to the ADS1251 after the time defined by t6. The normal mode of reading data from the ADS1251 is for the device reading the ADS1251 to latch the data on the rising edge of SCLK (because data are shifted out of the ADS1251 on the falling edge of SCLK). In order to retrieve valid data, the entire DOR must be read before the DOUT/DRDY pin reverts back to DRDY mode. The internal data pointer for shifting data out on DOUT/DRDY is reset on the falling edge of the time defined by t1 and t4. This ensures that the first bit of data shifted out of the ADS1251 after DRDY mode is always the MSB of new data. If SCLKs are not provided to the ADS1251 during the DOUT mode, the MSB of the DOR is present on the DOUT/DRDY line until the beginning of the time defined by t4. If an incomplete read of the ADS1251 takes place while in DOUT mode (that is, less than 24 SCLKs were provided), the state of the last bit read is present on the DOUT/DRDY line until the beginning of the time defined by t4. If more than 24 SCLKs are provided during DOUT mode, the DOUT/DRDY line stays LOW until the time defined by t4. SYNCHRONIZING MULTIPLE CONVERTERS The normal state of SCLK is LOW; however, by holding SCLK HIGH, multiple ADS1251s can be synchronized. This is accomplished by holding SCLK HIGH for at least four, but less than 20, consecutive DOUT/DRDY cycles (see Figure 13). After the ADS1251 circuitry detects that SCLK has been held HIGH for four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses LOW for one CLK cycle and then is held HIGH, and the modulator is held in a reset state. The modulator will be released from reset and synchronization occurs on the falling edge of SCLK. With multiple converters, the falling edge transition of SCLK must occur simultaneously on all devices. It is important to note that prior to synchronization, the DOUT/DRDY pulse of multiple ADS1251s in the system could have a difference in timing up to one DRDY period. Therefore, to ensure synchronization, the SCLK must be held HIGH for at least five DRDY cycles. The first DOUT/DRDY pulse after the falling edge of SCLK occurs at t14. The first DOUT/DRDY pulse indicates valid data. ADS1251 SBAS184D www.ti.com 11 POWER-DOWN MODE SERIAL INTERFACE The normal state of SCLK is LOW; however, by holding SCLK HIGH, the ADS1251 will enter power-down mode. This is accomplished by holding SCLK HIGH for at least 20 consecutive DOUT/DRDY periods (see Figure 14). After the ADS1251 circuitry detects that SCLK has been held HIGH for four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses LOW for one CLK cycle and then is held HIGH, and the modulator is held in a reset state. If SCLK is held HIGH for an additional 16 DOUT/DRDY periods, the ADS1251 enters power-down mode. The part will be released from power-down mode on the falling edge of SCLK. It is important to note that the DOUT/DRDY pin is held HIGH after four DOUT/DRDY cycles, but power-down mode is not entered for an additional 16 DOUT/DRDY periods. The first DOUT/DRDY pulse after the falling edge of SCLK occurs at t16 and indicates valid data. Subsequent DOUT/DRDY pulses will occur normally. The ADS1251 includes a simple serial interface which can be connected to microcontrollers and digital signal processors in a variety of ways. Communications with the ADS1251 can commence on the first detection of the DOUT/DRDY pulse after power up. SYMBOL tDRDY DRDY Mode DOUT Mode t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 It is important to note that the data from the ADS1251 is a 24-bit result transmitted MSB-first in Offset Binary Twos Complement format, as shown in Table III. The data must be clocked out before the ADS1251 enters DRDY mode to ensure reception of valid data, as described in the DOUT/DRDY section of this data sheet. DIFFERENTIAL VOLTAGE INPUT DIGITAL OUTPUT (HEX) +Full-Scale Zero –Full-Scale 7FFFFFH 000000H 800000H TABLE III. ADS1251 Data Format (Offset Binary Twos Complement). DESCRIPTION MIN Conversion Cycle DRDY Mode DOUT Mode DOR Write Time DOUT/DRDY LOW Time DOUT/DRDY HIGH Time (Prior to Data Out) DOUT/DRDY HIGH Time (Prior to Data Ready) Rising Edge of CLK to Falling Edge of DOUT/DRDY End of DRDY Mode to Rising Edge of First SCLK End of DRDY Mode to Data Valid (Propagation Delay) Falling Edge of SCLK to Data Valid (Hold Time) Falling Edge of SCLK to Next Data Out Valid (Propagation Delay) SCLK Setup Time for Synchronization or Power Down DOUT/DRDY Pulse for Synchronization or Power Down Rising Edge of SCLK Until Start of Synchronization Synchronization Time Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode Rising Edge of SCLK Until Start of Power Down Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode Falling Edge of Last DOUT/DRDY to Start of Power Down TYP MAX UNITS 384 • CLK 36 • CLK 348 • CLK 6 • CLK 6 • CLK 6 • CLK 24 • CLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 30 30 30 5 30 30 3 • CLK 1537 • CLK 0.5 • CLK 7679 • CLK 6143.5 • CLK 2042.5 • CLK 7681 • CLK 2318.5 • CLK 6144.5 • CLK TABLE II. Digital Timing. DOUT Mode DRDY Mode t2 t4 DOUT/DRDY DOUT Mode DATA DRDY Mode t3 DATA DATA t1 FIGURE 11. DOUT/DRDY Partitioning. 12 ADS1251 www.ti.com SBAS184D ADS1251 SBAS184D www.ti.com 13 t4 t1 t10 t2 t3 t10 t2 FIGURE 14. Power-Down Mode. DOUT/DRDY SCLK CLK t3 FIGURE 13. Synchronization Mode. DOUT/DRDY SCLK CLK FIGURE 12. DOUT/DRDY Timing. DOUT/DRDY SCLK CLK tDRDY DOUT Mode DATA DOUT Mode DATA tDRDY t2 t4 t4 DRDY Mode t5 4 tDRDY 4 tDRDY t12 t3 t15 t11 MSB t7 t6 DATA DATA t8 t9 tDRDY t11 t11 t17 t13 t16 Power-Down Occurs Here t14 Synchronization Begins Here Synchronization Mode Starts Here DOUT Mode LSB t2 t2 t3 t3 tDRDY DOUT Mode DATA tDRDY DOUT Mode DATA t4 t4 SYSTEM CONSIDERATIONS ISOLATION The serial interface of the ADS1251 provides for simple isolation methods. The CLK signal can be local to the ADS1251, which then only requires two signals (SCLK and DOUT/DRDY) to be used for isolated data acquisition. LAYOUT The recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system. Achieving 24 bits of noise performance is a great deal more difficult than achieving 12 bits of noise performance. In general, a system can be broken up into four different stages: • Analog Processing POWER SUPPLY The power supply must be well-regulated and low-noise. For designs requiring very high resolution from the ADS1251, power-supply rejection will be a concern. Avoid running digital lines under the device as they may couple noise onto the die. High-frequency noise can capacitively couple into the analog portion of the device and will alias back into the passband of the digital filter, affecting the conversion result. This clock noise will cause an offset error. GROUNDING The analog and digital sections of the system design should be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. GND should be connected to the analog ground plane, as well as all other analog grounds. Do not join the analog and digital ground planes on the board, but instead connect the two with a moderate signal trace. For multiple converters, connect the two ground planes at one location as central to all of the converters as possible. In some cases, experimentation may be required to find the best point to connect the two planes together. The printed circuit board can be designed to provide different analog/digital ground connections via short jumpers. The initial prototype can be used to establish which connection works best. • Analog Portion of the ADS1251 • Digital Portion of the ADS1251 • Digital Processing For the simplest system consisting of minimal analog signal processing (basic filtering and gain), a microcontroller, and one clock source, one can achieve high resolution by powering all components from a common power supply. In addition, all components could share a common ground plane. Thus, there would be no distinctions between analog power and ground, and digital power and ground. The layout should still include a power plane, a ground plane, and careful decoupling. In a more extreme case, the design could include: • Multiple ADS1251s • Extensive Analog Signal Processing • One or More Microcontrollers, Digital Signal Processors, or Microprocessors • Many Different Clock Sources • Interconnections to Various Other Systems High resolution will be very difficult to achieve for this design. The approach would be to break the system into as many different parts as possible. For example, each ADS1251 may have its own analog processing front end. DECOUPLING DEFINITION OF TERMS Good decoupling practices should be used for the ADS1251 and for all components in the design. All decoupling capacitors, and specifically the 0.1µF ceramic capacitors, should be placed as close as possible to the pin being decoupled. A 1µF to 10µF capacitor, in parallel with a 0.1µF ceramic capacitor, should be used to decouple VDD to GND. An attempt has been made to use consistent terminology in this data sheet. In that regard, the definition of each term is provided here: 14 Analog-Input Differential Voltage—for an analog signal that is fully differential, the voltage range can be compared to that of an instrumentation amplifier. For example, if both analog inputs of the ADS1251 are at 2.048V, the differential voltage is 0V. If one analog input is at 0V and the other ADS1251 www.ti.com SBAS184D analog input is at 4.096V, then the differential voltage magnitude is 4.096V. This is the case regardless of which input is at 0V and which is at 4.096V. The digital-output result, however, is quite different. The analog-input differential voltage is given by the following equation: The 2 • VREF figure in each calculation represents the fullscale range of the ADS1251. This means that both units are absolute expressions of resolution—the performance in different configurations can be directly compared, regardless of the units. +VIN – (–VIN) fMOD—frequency of the modulator and the frequency the input is sampled. A positive digital output is produced whenever the analoginput differential voltage is positive, whereas a negative digital output is produced whenever the differential is negative. For example, a positive full-scale output is produced when the converter is configured with a 4.096V reference, and the analog-input differential is 4.096V. The negative fullscale output is produced when the differential voltage is –4.096V. In each case, the actual input voltages must remain within the –0.3V to +VDD range. Actual Analog-Input Voltage—the voltage at any one analog input relative to GND. Full-Scale Range (FSR)—as with most A/D converters, the full-scale range of the ADS1251 is defined as the input which produces the positive full-scale digital output minus the input which produces the negative full-scale digital output. For example, when the converter is configured with a 4.096V reference, the differential full-scale range is: fMOD = CLK Frequency 6 fDATA—Data output rate. fDATA = fMOD CLK Frequency = 64 384 Noise Reduction—for random noise, the ER can be improved with averaging. The result is the reduction in noise by the factor √N, where N is the number of averages, as shown in Table IV. This can be used to achieve true 24-bit performance at a lower data rate. To achieve 24 bits of resolution, more than 24 bits must be accumulated. A 36-bit accumulator is required to achieve an ER of 24 bits. The following uses VREF = 4.096V, with the ADS1251 outputting data at 20kHz, a 4096 point average will take 204.8ms. The benefits of averaging will be degraded if the input signal drifts during that 200ms. [4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V Least Significant Bit (LSB) Weight—this is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. It is computed as follows: LSB Weight = N (Number of Averages) NOISE REDUCTION FACTOR ER IN µVrms ER IN BITS rms 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 1 1.414 2 2.82 4 5.66 8 11.3 16 22.6 32 45.25 64 16µV 11.3µV 8µV 5.66µV 4µV 2.83µV 2µV 1.41µV 1µV 0.71µV 0.5µV 0.35µV 0.25µV 19.26 19.75 20.26 20.76 21.26 21.76 22.26 22.76 23.26 23.76 24.26 24.76 25.26 Full−ScaleRange 2 • VREF = N 2N – 1 2 –1 where N is the number of bits in the digital output. Conversion Cycle—as used here, a conversion cycle refers to the time period between DOUT/DRDY pulses. Effective Resolution (ER)—of the ADS1251, in a particular configuration, can be expressed in two different units: bits rms (referenced to output) and µVrms (referenced to input). Computed directly from the converter’s output data, each is a statistical calculation based on a given number of results. Noise occurs randomly; the rms value represents a statistical measure, which is one standard deviation. The ER in bits can be computed as follows: TABLE IV. Averaging for Noise Reduction.  2 • VREF  20 • log   Vrms noise  ER in bits rms = 6.02 ADS1251 SBAS184D www.ti.com 15 Revision History DATE REVISION PAGE SECTION 6/09 D 2 Product Family Table 9/07 C 12 Table II DESCRIPTION Changed ADS1251 maximum data rate from 26.8kHz to 20.8kHz. Changed t11 from 1 • CLK to 3 • CLK. .NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 16 ADS1251 www.ti.com SBAS184D PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1251U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1251U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR ADS 1251U ADS1251U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR ADS 1251U ADS1251UG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1251U ADS 1251U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of