ADS1254-EP
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SBAS497 – APRIL 2010
24-Bit, 20-kHz, LOW POWER ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS1254-EP
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
24 Bits, No Missing Codes
19 Bits Effective Resolution Up to
20-kHz Data Rate
Four Differential Inputs
External Reference (0.5 V to 5 V)
Power Down Mode
Sync Mode
Low Power: 4 mW at 20 kHz
Separate Digital Interface Supply
(1.8 V to 3.6 V)
Cardiac Diagnostics
Direct Thermocouple Interfaces
Blood Analysis
Infrared Pyrometers
Liquid/Gas Chromatography
Precision Process Control
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
The ADS1254 is a precision, wide dynamic range, delta-sigma, analog-to-digital converter (ADC) with 24-bit
resolution. The delta-sigma architecture is used for wide dynamic range and to ensure 24 bits of no missing
codes performance. An effective resolution of 19 bits is achieved for conversion rates up to 20 kHz.
The ADS1254 is designed for high-resolution measurement applications in cardiac diagnostics, smart
transmitters, industrial process control, weight scales, chromatography, and portable instrumentation. The
converter includes a flexible, two-wire synchronous serial interface for low-cost isolation.
The ADS1254 is a multi-channel converter and is offered in an SSOP-20 package.
ADS1254
VREF
CH1+
CH1–
CLK
CH2+
CH2–
Mux
CH3+
4th-Order
∆Σ
Modulator
Digital
Filter
Serial
Interface
CH3–
SCLK
DOUT/DRDY
AV DD
CH4+
AGND
CH4–
Control
DVDD
DGND
CHSEL0 CHSEL1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
ADS1254-EP
SBAS497 – APRIL 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
–55°C to 115°C
(1)
(2)
Package
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
ADS1254WDBQEP
ADS1254EP
SSOP-DBQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted). (1)
UNIT
AVDD to AGND
–0.3 to 6
V
DVDD to AVDD
–6 to 6
V
DVDD to DGND
–0.3 to 6
V
–0.3 to VDD + 0.3
V
VREF voltage to AGND
Analog input current
Momentary
±100
Continuous
±10
Analog input voltage
mA
GND – 0.3 to VDD + 0.3
V
Digital input voltage to DGND
–0.3 to VDD + 0.3
V
Digital output voltage to DGND
–0.3 to VDD + 0.3
V
Lead temperature
300
°C
Power dissipation
500
mW
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –55°C to 115°C.
All specifications at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, CLK = 8 MHz, and VREF = 4.096 V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP (1)
MAX
UNIT
±VREF
V
Analog Input
Input voltage range
Input impedance
AGND
CLK = 3,840 Hz
260
CLK = 1 MHz
1
CLK = 8 MHz
125
Input capacitance
MΩ
kΩ
6
5
pF
50
pA
5
nA
20.8
kHz
Serial clock (SCLK)
8
MHz
System clock input (CLK)
8
MHz
Input leakage
At +25°C
At TA = –55°C to 115°C
Dynamic Characteristics
Data rate
Bandwidth
(1)
2
–3 dB
4.24
kHz
Applies to full-differential signals.
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ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –55°C to 115°C.
All specifications at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, CLK = 8 MHz, and VREF = 4.096 V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP (1)
MAX
±0.0002
±0.0015
UNIT
Accuracy
At +25°C
Integral non-linearity (2)
At TA = –55°C to 115°C
THD
Noise
±0.0078
1-kHz Input; 0.1 dB below FS
105
At +25°C
1.8
At TA = –55°C to 115°C
% of FSR
dB
2.7
85
ppm of FSR,
rms
Resolution
24
Bits
No missing codes
24
Bits
Common-mode rejection
At +25°C, 60 Hz, AC
90
At TA = –55°C to 115°C
64
102
dB
Gain error
At TA = –55°C to 115°C
0.1
1
% of FSR
Offset error
At TA = –55°C to 115°C
±30
±100
ppm of FSR
Gain sensitivity to VREF
1:1
Power-supply rejection ratio
At +25°C
70
At TA = –55°C to 115°C
60
88
dB
Voltage Reference
VREF
0.5
Load current
4.096
VDD
V
32
µA
Digital Input/Output
Logic family
Logic Levels
CMOS
VIH
0.65 DVDD
DVDD + 0.3
V
VIL
–0.3
0.35 DVDD
V
VOH
IOH = –500 µA
VOL
IOL = 500 µA
DVDD – 0.4
V
0.4
Input (SCLK, CLK, CHSEL0, CHSEL1) hysteresis
V
0.6
Data format
V
Offset binary two's compliment
Power Supply Requirements
Power supply voltage
Quiescent current
DVDD
1.8
AVDD
4.75
5.25
AVDD = 5 V
At TA = –55°C to 115°C
0.8
1.15
DVDD = 1.8 V
At TA = –55°C to 115°C
0.2
0.4
Operating power
Power-down current
3.6
5
4.3
6.5
At +25°C
0.4
1
At TA = –55°C to 115°C
1
VDC
mA
mW
µA
Temperature Range
Operating
–55
115
°C
Storage
–65
150
°C
(2)
Applies to full-differential signals.
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PIN CONFIGURATION
CH1+
1
20
CH4+
CH1–
2
19
CH4–
CH2+
3
18 VREF
CH2–
4
17 AGND
CH3+
5
16
CHSEL0
CHSEL1
ADS1254EP
CH3–
6
15
AV DD
7
14 SCLK
CLK
8
13 DOUT/DRDY
12 DGND
DVDD 9
NC
11
10
NC
PIN ASSIGNMENTS
4
PIN #
NAME
DESCRIPTION
1
CH1+
Analog input: Positive input of the differential analog input
2
CH1-
Analog input: Negative input of the differential analog input
3
CH2+
Analog input: Positive input of the differential analog input
4
CH2-
Analog input: Negative input of the differential analog input
5
CH3+
Analog input: Positive input of the differential analog input
6
CH3-
Analog input: Negative input of the differential analog input
7
AVDD
Input: Analog power supply voltage, 5 V
8
CLK
Digital input: Device system clock. The system clock is in the form of a CMOS-compatible clock. This is a Schmitt-Trigger input.
9
DVDD
Input: Digital power supply voltage
10
NC
No connection
11
NC
No connection
12
DGND
13
DOUT/DRDY
14
SCLK
15
CHSEL1
Digital input: Used to select analog input channel. This is a Schmitt-Trigger Input.
16
CHSEL0
Digital input: Used to select analog input channel. This is a Schmitt-Trigger Input.
17
AGND
18
VREF
Analog input: Reference voltage input
19
CH4-
Analog input: Negative input of the differential analog input
20
CH4+
Analog input: Positive input of the differential analog input
Input: Digital ground
Digital output: Serial data output/data ready. This output indicates that a new output word is available from the ADS1254 data
output register. The serial data is clocked out of the serial data output shift register using SCLK.
Digital input: Serial clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock operates independently
from the system clock; therefore, it is possible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW.
Holding SCLK HIGH will either initiate a modulator reset for synchronizing multiple converters or enter powerdown mode. This
is a Schmitt-Trigger input.
Input: Analog ground
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TYPICAL CHARACTERISTICS
At TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729 MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = 2.048 V, and VREFN = –2.048 V, unless otherwise
noted.
EFFECTIVE RESOLUTION
vs
DATA OUTPUT RATE
2.0
20.0
1.9
19.8
1.8
19.6
Effective Resolution (Bits)
RMS Noise (ppm of FS)
RMS NOISE
vs
DATA OUTPUT RATE
1.7
1.6
1.5
1.4
1.3
1.2
1.1
19.4
19.2
19.0
18.8
18.6
18.4
18.2
1.0
18.0
100
10k
1k
100k
100k
Data Ouput Rate (Hz)
Figure 1.
Figure 2.
RMS NOISE
vs
TEMPERATURE
EFFECTIVE RESOLUTION
vs
TEMPERATURE
2.0
20.0
1.8
19.8
1.6
19.6
Effective Resolution (Bits)
RMS Noise (ppm of FS)
10k
1k
100
Data Ouput Rate (Hz)
1.4
1.2
1.0
0.8
0.6
0.4
19.4
19.2
19.0
18.8
18.6
18.4
18.2
0.2
18.0
0.0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (° C)
Temperature (° C)
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729 MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = 2.048 V, and VREFN = –2.048 V, unless otherwise
noted.
RMS NOISE
vs
VREF VOLTAGE
RMS NOISE
vs
VREF VOLTAGE
18
14
16
12
RMS Noise (ppm of FS)
RMS Noise (mV)
14
12
10
8
6
4
10
8
6
4
2
2
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
5
0.5
1
1.5
VREF Voltage (V)
3
3.5
Figure 6.
RMS NOISE
vs
INPUT VOLTAGE
INTEGRAL NON-LINEARITY
vs
TEMPERATURE
4
4.5
5
2.5
2.0
1.5
INL (ppm of FS)
RMS Noise (ppm of FS)
2.5
Figure 5.
2.0
1.0
1.5
1.0
0.5
0.5
0
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
–40
Input Voltage (V)
–20
0
20
40
60
80
100
Temperature ( °C)
Figure 7.
6
2
VREF Voltage (V)
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729 MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = 2.048 V, and VREFN = –2.048 V, unless otherwise
noted.
INTEGRAL NON-LINEARITY
vs
DATA OUTPUT RATE
OFFSET
vs
TEMPERATURE
20
6
18
DC Offset (ppm of FS)
INL (ppm of FS)
5
4
3
2
1
16
14
12
10
8
6
4
2
0
0
10k
1k
100
100k
–40
–20
0
Data Output Rate (Hz)
20
40
60
80
100
6
7
8
Temperature (°C)
Figure 9.
Figure 10.
GAIN ERROR
vs
TEMPERATURE
PSR
vs
CLK FREQUENCY
600
–0
–10
–20
–30
560
PSR (dB)
Gain Error (ppm of FS)
580
540
520
–40
–50
–60
–70
–80
500
–90
480
–100
–60
–40
–20
0
20
40
60
80
100
1
Temperature ( °C)
2
3
4
5
Clock Frequency (MHz)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729 MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = 2.048 V, and VREFN = –2.048 V, unless otherwise
noted.
CMR
vs
COMMOM-MODE FREQUENCY
–50
–70
–60
–75
–70
–80
CMR (dB)
CMR at 60 Hz (dB)
CMR AT 60 Hz
vs
CLK FREQUENCY
–80
–85
–90
–90
–95
–100
–100
–110
0
1
2
3
4
5
6
7
8
–105
10
100
Figure 13.
Figure 14.
CURRENT
vs
TEMPERATURE
POWER DISSIPATION
vs
CLK FREQUENCY
0.9
4.5
0.8
4.0
0.7
3.5
0.6
AV DD (5V)
DVDD (1.8V)
0.5
0.4
0.3
0.2
0.1
0
–40
3.0
100k
Analog (5V)
Digital (3.3V)
Digital (1.8V)
2.5
2.0
1.5
1.0
0.5
0
–20
0
20
40
60
80
100
0
1
2
3
4
5
6
7
8
Clock Frequency (MHz)
Temperature (°C)
Figure 15.
8
10k
1k
Common-Mode Signal Frequency (Hz)
Power Dissipation (mW)
Current (mA)
Clock Frequency (MHz)
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729 MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = 2.048 V, and VREFN = –2.048 V, unless otherwise
noted.
TYPICAL FFT
(1-kHz INPUT AT 0.1 dB LESS THAN FULL SCALE)
35
0
30
–20
Relative Magnitude (dB)
VREF Current (mA)
VREF CURRENT
vs
CLK FREQUENCY
25
20
15
10
5
–40
–60
–80
–100
–120
–140
0
–160
0
1
2
3
4
5
6
7
8
0
1
Clock Frequency (MHz)
2
3
4
5
6
7
8
9
10
11
Input Signal Frequency (kHz)
Figure 17.
Figure 18.
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THEORY OF OPERATION
The ADS1254 is a precision, high-dynamic range, 24-bit, delta-sigma, ADC capable of achieving very
high-resolution digital results at high data rates. The analog-input signal is sampled at a rate determined by the
frequency of the system clock (CLK). The sampled analog input is modulated by the delta-sigma analog-to-digital
modulator, which is followed by a digital filter. A Sinc5 digital low-pass filter processes the output of the
delta-sigma modulator and writes the result into the data-output register. The DOUT/DRDY pin is pulled LOW,
indicating that new data is available to be read by the external microcontroller/microprocessor. As shown in the
block diagram, the main functional blocks of the ADS1254 are the fourth-order delta-sigma modulator, a digital
filter, control logic, and a serial interface. Each of these functional blocks is described below.
ANALOG INPUT
The ADS1254 contains a fully differential analog input. In order to provide low system noise, common-mode
rejection of 102 dB, and excellent power-supply rejection, the design topology is based on a fully differential
switched-capacitor architecture. The bipolar input voltage range is from –4.096V to 4.096 V, when the reference
input voltage equals 4.096 V. The bipolar range is with respect to –VIN, and not with respect to GND.
Figure 19 shows the basic input structure of the ADS1254. The impedance is directly related to the sampling
frequency of the input capacitor that is set by the CLK rate. Higher CLK rates result in lower impedance, and
lower CLK rates result in higher impedance.
RSW
(1300Ω typical)
Internal
Circuitry
AIN
Modulator Frequency
= fMOD
CINT
(6pF typical)
VCM
Figure 19. Analog-Input Structure
The input impedance of the analog input changes with the ADS1254 system clock frequency (CLK). The
relationship is:
AIN Impedance (W) =
MHz
(8¾
CLK )
· 125,000
(1)
With regard to the analog-input signal, the overall analog performance of the device is affected by three items:
first, the input impedance can affect accuracy. If the source impedance of the input signal is significant, or if there
is passive filtering prior to the ADS1254, a significant portion of the signal can be lost across this external
impedance. The magnitude of the effect is dependent on the desired system performance.
Second, the current into or out of the analog inputs must be limited. Under no conditions should the current into
or out of the analog inputs exceed 10 mA.
Third, to prevent aliasing of the input signal, the analog-input signal must be band limited. The bandwidth of the
ADC is a function of the system clock frequency. With a system clock frequency of 8 MHz, the data-output rate is
20.8 kHz with a –3-dB frequency of 4.24 kHz. The –3-dB frequency scales with the system clock frequency.
To ensure the best linearity of the ADS1254, a fully differential signal is recommended.
INPUT MULTIPLEXER
The CHSEL1 and CHSEL0 pins are used to select the analog input channel, as shown in Table 1. The
recommended method for changing channels is to change them after the conversion from the previous channel
has been completed and read. When a channel is changed, internal logic senses the change on the falling edge
of CLK and resets the conversion process. The conversion data from the new channel is valid on the first DRDY
after the channel change.
When multiplexing inputs, it is possible to achieve sample rates close to 4 kHz. This is due to the fact that it
requires five internal conversion cycles for the data to fully settle; the data also must be read before the channel
is changed. The DRDY signal indicates a valid result after the five cycles have occurred.
10
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Table 1. Bipolar Input Channel Selection
CHSEL1
CHSEL0
CHANNEL
0
0
CH1
0
1
CH2
1
0
CH3
1
1
CH4
Each of the differential inputs of the ADS1254 must stay between AGND and AVDD. With a reference voltage at
less than half of AVDD, one input can be tied to the reference voltage, and the other input can range from AGND
to 2 x VREF. By using a three op amp circuit featuring a single amplifier and four external resistors, the ADS1254
can be configured to accept bipolar inputs referenced to ground. The conventional ±2.5-V, ±5-V, and ±10-V input
ranges can be interfaced to the ADS1254 using the resistor values shown in Figure 20.
R1
10kW
+IN
OPA4350
20kW
Bipolar
Input
–IN
ADS1254
VREF
R2
OPA4350
OPA4350
BIPOLAR INPUT
R1
R2
±10V
±5V
±2.5V
2.5kW
5kW
10kW
5kW
10kW
20kW
REF
2.5V
Figure 20. Level Shift Circuit for Bipolar Input Ranges
DELTA-SIGMA MODULATOR
The ADS1254 operates from a nominal system clock frequency of 8 MHz. The modulator frequency is fixed in
relation to the system clock frequency. The system clock frequency is divided by six to derive the modulator
frequency. Therefore, with a system clock frequency of 8 MHz, the modulator frequency is 1.333 MHz.
Furthermore, the oversampling ratio of the modulator is fixed in relation to the modulator frequency. The
oversampling ratio of the modulator is 64, and with the modulator frequency running at 1.333 MHz, the data rate
is 20.8 kHz. Using a slower system clock frequency will result in a lower data output rate, as shown in Figure 21.
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CLK (MHz)
DATA OUTPUT RATE (Hz)
8(1)
20,833
19,200
16,000
15,625
12,800
9,600
8,000
6,400
4,800
2,400
1,200
1,000
500
100
60
50
30
25
20
16.67
15
12.50
10
7.372800(1)
6.144000(1)
6.000000(1)
4.915200(1)
3.686400(1)
3.072000(1)
2.457600(1)
1.843200(1)
0.921600
0.460800
0.384000
0.192000
0.038400
0.023040
0.019200
0.011520
0.009600
0.007680
0.006400
0.005760
0.004800
0.003840
NOTE: (1) Standard Clock Oscillator.
Figure 21. CLK Rate vs Data Output Rate
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REFERENCE INPUT
Reference input takes an average current of 32 mA with a 8-MHz system clock. This current will be proportional
to the system clock. A buffered reference is recommended for the ADS1254. The recommended reference circuit
is shown in Figure 22.
Reference voltages higher than 4.096 V will increase the full-scale range, while the absolute internal circuit noise
of the converter remains the same. This will decrease the noise in terms of ppm of full scale, which increases the
effective resolution (see Figure 6).
+5V
+5V
0.10mF
7
4.99kΩ
2
To V REF
Pin 18 of
the ADS1254
6
10kΩ
3
OPA350
1
+
10mF
+
10mF
LM404-4.1
0.10mF
0.1mF
4
Figure 22. Recommended External Voltage Reference Circuit for
Best Low-Noise Operation with the ADS1254
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DIGITAL FILTER
The digital filter of the ADS1254, referred to as a sinc5 filter, computes the digital result based on the most
recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as
simply averaging the modulator results in a weighted form and presenting this average as the digital output. The
digital output rate, or data rate, scales directly with the system CLK frequency. This allows the data output rate to
be changed over a very wide range (five orders of magnitude) by changing the system CLK frequency. However,
it is important to note that the –3-dB point of the filter is 0.2035 times the data output rate, so the data output rate
should allow for sufficient margin to prevent attenuation of the signal of interest.
Since the conversion result is essentially an average, the data-output rate determines the location of the resulting
notches in the digital filter (see Figure 23). Note that the first notch is located at the data-output rate frequency,
and subsequent notches are located at integer multiples of the data-output rate to allow for rejection of not only
the fundamental frequency, but also harmonic frequencies. In this manner, the data-output rate can be used to
set specific notch frequencies in the digital filter response.
For example, if the rejection of power-line frequencies is desired, then the data-output rate can simply be set to
the power-line frequency. For 50-Hz rejection, the system CLK frequency should be 19.200 kHz, this will set the
data-output rate to 50 Hz (see Figure 21 and Figure 24). For 60-Hz rejection, the system CLK frequency should
be 23.040 kHz; this will set the data-output rate to 60 Hz (see Figure 21 and Figure 25). If both 50-Hz and 60-Hz
rejection are required, then the system CLK should be 3.840 kHz; this will set the data-output rate to 10 Hz and
reject both 50 Hz and 60 Hz (See Figure 21 and Figure 26).
There is an additional benefit in using a lower data-output rate. It provides better rejection of signals in the
frequency band of interest. For example, with a 50-Hz data-output rate, a significant signal at 75 Hz may alias
back into the passband at 25 Hz. This is due to the fact that rejection at 75 Hz may only be 66 dB in the
stopband—frequencies higher than the firstnotch frequency (see Figure 24). However, setting the dataoutput rate
to 10 Hz will provide 135-dB rejection at 75 Hz (see Figure 26). A similar benefit is gained at frequencies near
the data-output rate (see Figure 27, Figure 28, Figure 29 and Figure 30). For example, with a 50-Hz data-output
rate, rejection at 55 Hz may only be 105 dB (see Figure 27). However, with a 10-Hz data-output rate, rejection at
55 Hz will be 122 dB (see Figure 28). If a slower data-output rate does not meet the system requirements, then
the analog front end can be designed to provide the needed attenuation to prevent aliasing. Additionally, the
data-output rate may be increased and additional digital filtering may be done in the processor or controller.
14
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The digital filter is described by the following transfer function:
½
(
)
( )
p · f · 64
sin ¾
fMOD
½H(f)½ = ¾
p·f
¾
64 · sin fMOD
5
½
(2)
or
H(z) =
(
-64
5
)
1-z
¾
-1
64 · (1 - z )
(3)
0
0
–20
–20
–40
–40
–60
–60
–80
Gain (dB)
Gain (dB)
The digital filter requires five conversions to fully settle. The modulator has an oversampling ratio of 64; therefore,
it requires 5 x 64, or 320 modulator results, or clocks, to fully settle. Since the modulator clock is derived from the
system clock (CLK) (modulator clock = CLK ÷ 6), the number of system clocks required for the digital filter to fully
settle is 5 x 64 x 6, or 1920 CLKs. This means that any significant step change at the analog input requires five
full conversions to settle. However, if the step change at the analog input occurs asynchronously to the
DOUT/DRDY pulse, six conversions are required to ensure full settling.
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
–200
–200
0
1
2
3
4
5
6
7
8
9
0
10
50
100
Figure 23. Normalized Digital Filter Response
200
300
250
Figure 24. Digital Filter Response (50 Hz)
0
0
–20
–20
–40
–40
–60
–60
–80
Gain (dB)
Gain (dB)
150
Frequency (Hz)
Frequency (Hz)
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
–200
–200
0
50
100
150
200
250
300
0
10
Frequency (Hz)
20
30
40
50
60
70
80
90
100
Frequency (Hz)
Figure 25. Digital Filter Response (60 Hz)
Figure 26. Digital Filter Response (10 Hz)
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0
0
–20
–20
–40
–40
–60
–60
–80
Gain (dB)
Gain (dB)
SBAS497 – APRIL 2010
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
–200
–200
45
46
47
48
49
50
51
52
53
54
45
55
46
47
48
Frequency (Hz)
Figure 27. Expanded Digital Filter Response (50 Hz
With a 50-Hz Data Output Rate)
50
51
52
53
54
55
Figure 28. Expanded Digital Filter Response (50 Hz
With a 10-Hz Data Output Rate)
0
0
–20
–20
–40
–40
–60
–60
–80
Gain (dB)
Gain (dB)
49
Frequency (Hz)
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
–200
–200
55
56
57
58
59
60
61
62
63
64
65
55
56
Frequency (Hz)
57
58
59
60
61
62
63
64
65
Frequency (Hz)
Figure 29. Expanded Digital Filter Response (6 0Hz
With a 60-Hz Data Output Rate)
Figure 30. Expanded Digital Filter Response (60 Hz
With a 10-Hz Data Output Rate)
CONTROL LOGIC
The control logic is used for communications and control of the ADS1254.
Power-Up Sequence
Prior to power-up, all digital and analog-input pins must be LOW. During power-up, these signal inputs should
never exceed AVDD or DVDD.
Once the ADS1254 powers up, the DOUT/DRDY line will pulse LOW on the first conversion for which the data is
valid from the analog input signal.
DOUT/DRDY
The DOUT/DRDY output signal alternates between two modes of operation. The first mode of operation is the
Data Ready mode (DRDY) to indicate that new data has been loaded into the data-output register and is ready to
be read. The second mode of operation is the Data Output (DOUT) mode and is used to serially shift data out of
the Data Output Register (DOR). The time domain partitioning of the DRDY and DOUT function as shown in
Figure 31Figure 12.
See Figure 32 for the basic timing of DOUT/DRDY. During the time defined by t2, t3, and t4, the DOUT/DRDY pin
functions in DRDY mode. The state of the DOUT/DRDY pin would be HIGH prior to the internal transfer of new
data to the DOR. The result of the ADC would be written to the DOR from MSB to LSB in the time defined by t1
(see Figure 31 and Figure 32). The DOUT/DRDY line would then pulse LOW for the time defined by t2, and then
drive the line HIGH for the time defined by t3 to indicate that new data was available to be read. At this point, the
function of the DOUT/DRDY pin would change to DOUT mode. Data would be shifted out on the pin after t7. If
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the MSB is high (because of a negative result) the DOUT/DRDY signal will stay HIGH after the end of time t3.
The device communicating with the ADS1254 can provide SCLKs to the ADS1254 after the time defined by t6.
The normal mode of reading data from the ADS1254 would be for the device reading the ADS1254 to latch the
data on the rising edge of SCLK (since data is shifted out of the ADS1254 on the falling edge of SCLK). In order
to retrieve valid data, the entire DOR must be read before the DOUT/DRDY pin reverts back to DRDY mode.
If SCLKs were not provided to the ADS1254 during the DOUT mode, the MSB of the DOR would be present on
the DOUT/DRDY line until the beginning of the time defined by t4. If an incomplete read of the ADS1254 took
place while in DOUT mode (that is, fewer than 24 SCLKs were provided), the state of the last bit read would be
present on the DOUT/DRDY line until the beginning of the time defined by t4. If more than 24 SCLKs were
provided during DOUT mode, the DOUT/DRDY line would stay LOW until the time defined by t4.
The internal data pointer for shifting data out on DOUT/DRDY is reset on the falling edge of the time defined by
t1 and t4. This ensures that the first bit of data shifted out of the ADS1254 after DRDY mode is always the MSB
of new data.
DRDY Mode
DOUT Mode
t2
t4
t3
DATA
DOUT/DRDY
DRDY Mode
DOUT Mode
DATA
DATA
t1
Figure 31. DOUT/DRDY Partitioning
t18
DATA
DOUT/DRDY
DATA
CHSEL0, CHSEL1
MUX CHANGE
Figure 32. Multiplexer Operation
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW; however, by holding SCLK HIGH, multiple ADS1254s can be synchronized.
This is accomplished by holding SCLK HIGH for at least four, but less than twenty, consecutive DOUT/DRDY
cycles (see Figure 33). After the ADS1254 circuitry detects that SCLK has been held HIGH for four consecutive
DOUT/DRDY cycles, the DOUT/DRDY pin will pulse LOW for 3 CLK cycles and then be held HIGH, and the
modulator will be held in a reset state. The modulator will be released from reset and synchronization will occur
on the falling edge of SCLK. With multiple converters, the falling edge transition of SCLK must occur
simultaneously on all devices. It is important to note that prior to synchronization, the DOUT/DRDY pulse of
multiple ADS1254s in the system could have a difference in timing up to one DRDY period. Therefore, to ensure
synchronization, the SCLK should be held HIGH for at least five DRDY cycles. The first DOUT/DRDY pulse after
the falling edge of SCLK will occur at t14. The first DOUT/DRDY pulse indicates valid data.
CLK
t6
t5
SCLK
t7
t1
t8
t9
MSB
DOUT/DRDY
t4
t2
LSB
t3
DRDY Mode
DOUT Mode
tDRDY
Figure 33. DOUT/DRDY Timing
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POWER-DOWN MODE
The normal state of SCLK is LOW, however, by holding SCLK HIGH, the ADS1254 will enter power-down mode.
This is accomplished by holding SCLK HIGH for at least twenty consecutive DOUT/DRDY periods (see
Figure 34). After the ADS1254 circuitry detects that SCLK has been held HIGH for four consecutive
DOUT/DRDY cycles, the DOUT/DRDY pin will pulse LOW for 3 CLK cycles and then be held HIGH, and the
modulator will be held in a reset state. If SCLK is held HIGH for an additional sixteen DOUT/DRDY periods, the
ADS1254 will enter power-down mode. The part will be released from powerdown mode on the falling edge of
SCLK. It is important to note that the DOUT/DRDY pin will be held HIGH after four DOUT/DRDY cycles, but
power-down mode will not be entered for an additional sixteen DOUT/DRDY periods. The first DOUT/DRDY
pulse after the falling edge of SCLK will occur at t16 and will indicate valid data. Subsequent DOUT/DRDY pulses
will occur normally.
Synchronization Mode Starts Here
CLK
t10
Synchronization Begins Here
SCLK
t12
DATA
DOUT/DRDY
t2
DOUT
Mode
t3
DATA
DATA
t11
t4
tDRDY
t2
t13
DOUT
Mode
t3
t14
t4
tDRDY
4 tDRDY
Figure 34. Synchronization Mode
Power Down Occurs Here
CLK
t10
t17
SCLK
t15
DATA
DOUT/DRDY
t2
DOUT
Mode
t3
DATA
t11
t4
DATA
t11
t2
t16
tDRDY
DOUT
Mode
t3
t4
tDRDY
4 tDRDY
Figure 35. Power-Down Mode
SERIAL INTERFACE
The ADS1254 includes a simple serial interface that can be connected to microcontrollers and digital signal
processors in a variety of ways. Communications with the ADS1254 can commence on the first detection of the
DOUT/DRDY pulse after power up.
It is important to note that the data from the ADS1254 is a 24-bit result transmitted MSB-first in offset two’s
complement format, as shown in Table 2.
The data must be clocked out before the ADS1254 enters DRDY mode to ensure reception of valid data, as
described in the DOUT/DRDY section of this data sheet.
Table 2. ADS1254 Data Format (Offset Two's Complement)
18
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full Scale
7FFFFFH
Zero
000000H
–Full Scale
800000H
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Table 3. Digital Timing (1)
SYMBOL
DESCRIPTION
tOSC
CLK period
tDRDY
Conversion cycle
DRDY Mode
MIN
TYP
MAX
UNIT
125
ns
384 x tOSC
ns
DRDY mode
36 x tOSC
ns
DOUT Mode
DOUT mode
348 x tOSC
ns
t1
DOR write time
6 x tOSC
ns
t2
DOUT/DRDY LOW time
6 x tOSC
ns
t3
DOUT/DRDY HIGH time (prior to data out)
6 x tOSC
ns
t4
DOUT/DRDY HIGH time (prior to data ready)
t5
Rising edge of CLK to falling edge of DOUT/DRDY
t6
End of DRDY mode to rising edge of first SCLK
t7
End of DRDY mode to data valid (propagation delay)
t8
Falling edge of SCLK to data valid (hold time)
t9
Falling edge of SCLK to next data out valid (propagation delay)
t10
SCLK setup time for synchronization or power down
t11
DOUT/DRDY pulse for synchronization or power down
t12
Rising edge of SCLK until start of synchronization
t13
Synchronization time
t14
Falling edge of CLK (after SCLK goes low) until start of DRDY
mode
t15
Rising edge of SCLK until start of power down
t16
Falling edge of CLK (after SCLK goes low) until start of DRDY
mode
2318.5 x tOSC
ns
t17
Falling edge of last DOUT/DRDY to start of power down
6144.5 x tOSC
ns
t18
DOUT/DRDY high time after mux change
2043.5 x tOSC
ns
(1)
24 x tOSC
ns
60
30
ns
ns
60
5
ns
ns
60
30
ns
ns
3 x tOSC
ns
1537 x CLK
7679 x CLK
ns
0.5 x CLK
6143.5 x CLK
ns
2042.5 x CLK
7681 x CLK
ns
ns
30 pF load
ISOLATION
The serial interface of the ADS1254 provides for simple isolation methods. The CLK signal can be local to the
ADS1254, which then only requires two signals (SCLK and DOUT/DRDY) to be used for isolated data
acquisition. The channel select signals (CHSEL0, CHSEL1) will also need to be isolated unless a counter is used
to auto multiplex the channels.
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LAYOUT
POWER SUPPLY
The power supply should be well regulated and low noise. For designs requiring very high resolution from the
ADS1254, power-supply rejection will be a concern. Avoid running digital lines under the device as they may
couple noise onto the die. High-frequency noise can capacitively couple into the analog portion of the device and
will alias back into the passband of the digital filter, affecting the conversion result. This clock noise will cause an
offset error.
GROUNDING
The analog and digital sections of the system design should be carefully and cleanly partitioned. Each section
should have its own ground plane with no overlap between them. AGND should be connected to the analog
ground plane, as well as all other analog grounds. Do not join the analog and digital ground planes on the board,
but instead connect the two with a moderate signal trace. For multiple converters, connect the two ground planes
at one location as central to all of the converters as possible. In some cases, experimentation may be required to
find the best point to connect the two planes together. The printed circuit board can be designed to provide
different analog/digital ground connections via short jumpers. The initial prototype can be used to establish which
connection works best.
DECOUPLING
Good decoupling practices should be used for the ADS1254 and for all components in the design. All decoupling
capacitors, and specifically the 0.1-mF ceramic capacitors, should be placed as close as possible to the pin being
decoupled. A 1-mF to 10-mF capacitor, in parallel with a 0.1-mF ceramic capacitor, should be used to decouple
supply to ground.
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SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding will change depending on the requirements and specific
design of the overall system. Achieving 24 bits of noise performance is a great deal more difficult than achieving
12 bits of noise performance. In general, a system can be broken up into four different stages:
• Analog processing
• Analog portion of the ADS1254
• Digital portion of the ADS1254
• Digital processing
For the simplest system consisting of minimal analog signal processing (basic filtering and gain), a
microcontroller, and one clock source, one can achieve high resolution by powering all components by a
common power supply. In addition, all components could share a common ground plane. Thus, there would be
no distinctions between analog power and ground, and digital power and ground. The layout should still include a
power plane, a ground plane, and careful decoupling. In a more extreme case, the design could include:
• Multiple ADS1254s
• Extensive analog signal processing
• One or more microcontrollers, digital signal processors, or microprocessors
• Many different clock sources
• Interconnections to various other systems
High resolution will be very difficult to achieve for this design. The approach would be to break the system into as
many different parts as possible. For example, each ADS1254 may have its own analog processing front end.
DEFINITION OF TERMS
An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the
definition of each term is given as follows:
Analog-Input Differential Voltage - For an analog signal that is fully differential, the voltage range can be
compared to that of an instrumentation amplifier. For example, if both analog inputs of the ADS1254 are at 2.048
V, the differential voltage is 0 V. If one analog input is at 0 V and the other analog input is at 4.096 V, then the
differential voltage magnitude is 4.096 V. This is the case regardless of which input is at 0 V and which is at
4.096 V. The digital-output result, however, is quite different. The analog-input differential voltage is given by
Equation 4:
+VIN - (-VIN)
(4)
A positive digital output is produced whenever the analog-input differential voltage is positive, while a negative
digital output is produced whenever the differential is negative. For example, a positive full-scale output is
produced when the converter is configured with a 4.096-V reference, and the analog-input differential is 4.096 V.
The negative full-scale output is produced when the differential voltage is –4.096 V. In each case, the actual
input voltages must remain within the –0.3 V to AVDD range.
Actual Analog-Input Voltage - The voltage at any one analog input relative to AGND.
Full-Scale Range (FSR) - As with most ADCs, the full-scale range of the ADS1254 is defined as the input that
produces the positive full-scale digital output minus the input that produces the negative full-scale digital output.
For example, when the converter is configured with a 4.096-V reference, the differential full-scale range is:
[4.096 V (positive full scale) - (-4.096 V) (negative full scale)] = 8.192 V
(5)
Least Significant Bit (LSB) Weight - This is the theoretical amount of voltage that the differential voltage at the
analog input would have to change in order to observe a change in the output data of one least significant bit. It
is computed as follows:
Full-scale range 2 · VREF
LSB weight = ¾
= ¾
N
N
2 -1
2 -1
(6)
where N is the number of bits in the digital output.
Conversion Cycle - As used here, a conversion cycle refers to the time period between DOUT/DRDY pulses.
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Effective Resolution (ER) - ER of the ADS1254 in a particular configuration can be expressed in two different
units: bits rms (referenced to output) and mVrms (referenced to input). Computed directly from the converter's
output data, each is a statistical calculation based on a given number of results. Noise occurs randomly; the rms
value represents a statistical measure that is one standard deviation. The ER in bits can be computed as follows:
2 · VREF
20 · log ¾
Vrms noise
ER in bits rms = ¾
6.02
)
(
(7)
The 2 x VREF figure in each calculation represents the full-scale range of the ADS1254. This means that both
units are absolute expressions of resolution - the performance in different configurations can be directly
compared, regardless of the units.
fMOD - Frequency of the modulator and the frequency the input is sampled.
CLK frequency
fMOD = ¾
6
(8)
fDATA - Data output rate.
fMOD CLK frequency
¾
fDATA = ¾
64 =
384
(9)
Noise Reduction - For random noise, the ER can be improved with averaging. The result is the reduction in
noise by the factor √N, where N is the number of averages, as shown in Table 4. This can be used to achieve
true 24-bit performance at a lower data rate. To achieve 24 bits of resolution, more than 24 bits must be
accumulated. A 36-bit accumulator is required to achieve an ER of 24 bits. Table 4 uses VREF = 4.096 V, with the
ADS1254 outputting data at 20 kHz, a 4096 point average will take 204.8 ms. The benefits of averaging will be
degraded if the input signal drifts during that 200 ms.
Table 4. Averaging
N
(NUMBER OF
AVERAGES)
22
NOISE REDUCTION FACTOR
ER
(µVrms)
ER
(BITS rms)
1
1
14.6
19.1
2
1.414
10.3
19.6
4
2
7.3
20.1
8
2.82
5.16
20.6
16
4
3.65
21.1
32
5.66
2.58
21.6
64
8
1.83
22.1
128
11.3
1.29
22.6
256
16
0.91
23.1
512
22.6
0.65
23.6
1024
32
0.46
24.1
2048
45.25
0.32
24.6
4096
64
0.23
25.1
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PACKAGE OPTION ADDENDUM
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12-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS1254WDBQEP
LIFEBUY
Package Type Package Pins Package
Drawing
Qty
SSOP
DBQ
20
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
0 to 0
ADS1254EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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