ADS1256IDBR

ADS1255 ADS1256 SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Very Low Noise, 24-Bit Analog-to-Digital Converter FEATURES D 24 Bits, No Missing Codes DESCRIPTION The ADS1255 and ADS1256 are extremely low-noise, 24-bit analog-to-digital (A/D) converters. They provide complete high-resolution measurement solutions for the most demanding applications. − All Data Rates and PGA Settings Up to 23 Bits Noise-Free Resolution ±0.0010% Nonlinearity (max) D D D Data Output Rates to 30kSPS D Fast Channel Cycling The converter is comprised of a 4th-order, delta-sigma (ΔΣ) modulator followed by a programmable digital filter. A flexible input multiplexer handles differential or single-ended signals and includes circuitry to verify the integrity of the external sensor connected to the inputs. The selectable input buffer greatly increases the input impedance and the low-noise programmable gain amplifier (PGA) provides gains from 1 to 64 in binary steps. The programmable filter allows the user to optimize between a resolution of up to 23 bits noise-free and a data rate of up to 30k samples per second (SPS). The converters offer fast channel cycling for measuring multiplexed inputs and can also perform one-shot conversions that settle in just a single cycle. − 18.6 Bits Noise-Free (21.3 Effective Bits) at 1.45kHz D One-Shot Conversions with Single-Cycle Settling D Flexible Input Multiplexer with Sensor Detect − Four Differential Inputs (ADS1256 only) − Eight Single-Ended Inputs (ADS1256 only) Chopper-Stabilized Input Buffer Low-Noise PGA: 27nV Input-Referred Noise D D D Self and System Calibration for All PGA Communication is handled over an SPI-compatible serial interface that can operate with a 2-wire connection. Onboard calibration supports both self and system correction of offset and gain errors for all the PGA settings. Bidirectional digital I/Os and a programmable clock output driver are provided for general use. The ADS1255 is packaged in an SSOP-20, and the ADS1256 in an SSOP-28. Settings 5V Tolerant SPI™-Compatible Serial Interface Analog Supply: 5V Digital Supply: 1.8V to 3.6V Power Dissipation − As Low as 38mW in Normal Mode − 0.4mW in Standby Mode APPLICATIONS D Scientific Instrumentation D Industrial Process Control D Medical Equipment D Test and Measurement D Weigh Scales AVDD VREFP VREFN AIN0 AIN2 AIN3 AIN4 AIN5 DVDD Clock Generator AIN1 ADS1256 Only D D D D Mux and Sensor Detect XTAL1/CLKIN XTAL2 1:64 Buffer PGA 4th−Order Modulator Programmable Digital Filter Control RESET SYNC/PDWN DRDY AIN6 General Purpose Digital I/O AIN7 AINCOM Serial Interface SCLK DIN DOUT CS AGND D3 D2 D1 D0/CLKOUT DGND ADS1256 Only Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. Copyright © 2003−2013, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1255, ADS1256 UNIT AVDD to AGND −0.3 to +6 V DVDD to DGND −0.3 to +3.6 V AGND to DGND Input Current V mA 10, Continuous mA −0.3 to AVDD + 0.3 V DIN, SCLK, CS, RESET, SYNC/PDWN, XTAL1/CLKIN to DGND −0.3 to +6 V D0/CLKOUT, D1, D2, D3 to DGND −0.3 to DVDD + 0.3 V Analog inputs to AGND Digital inputs −0.3 to +0.3 100, Momentary Maximum Junction Temperature +150 °C Operating Temperature Range −40 to +105 °C Storage Temperature Range −60 to +150 °C +300 °C Lead Temperature (soldering, 10s) (1) 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted. PARAMETER Analog Inputs TEST CONDITIONS MIN TYP Full-scale input voltage (AINP − AINN) Absolute input voltage (AIN0-7, AINCOM to AGND) ±2VREF/PGA V AGND − 0.1 AVDD + 0.1 V Buffer on AGND AVDD − 2.0 V 1 64 Buffer off, PGA = 1, 2, 4, 8, 16 Sensor detect current sources UNIT Buffer off Programmable gain amplifier Differential input p impedance p MAX 150/PGA kΩ Buffer off, PGA = 32, 64 4.7 kΩ Buffer on, fDATA ≤ 50Hz(1) 80 MΩ SDCS[1:0] = 01 0.5 μA SDCS[1:0] = 10 2 μA SDCS[1:0] = 11 10 μA System Performance Resolution 24 Bit No missing codes All data rates and PGA settings 24 Bit Data rate (fDATA) fCLKIN = 7.68MHz 2.5 Integral nonlinearity Offset error Offset drift Gain error Gain drift Common-mode rejection Differential input, PGA = 1 ±0.0003 Differential input, PGA = 64 30,000 SPS(2) ±0.0010 %FSR(3) %FSR ±0.0007 After calibration On the level of the noise PGA = 1 ±100 nV/°C PGA = 64 ±4 nV/°C After calibration, PGA = 1, Buffer on ±0.005 % After calibration, PGA = 64, Buffer on ±0.03 % PGA = 1 ±0.8 ppm/°C PGA = 64 ±0.8 ppm/°C 110 dB fCM(4) = 60Hz, fDATA = 30kSPS(5) 95 Noise See Noise Performance Tables AVDD power-supply rejection ±5% Δ in AVDD DVDD power-supply rejection ±10% Δ in DVDD 60 70 dB 100 dB Voltage Reference Inputs Reference input voltage (VREF) Negative reference input (VREFN) Positive reference input (VREFP) Voltage reference impedance VREF ≡ VREFP − VREFN 2.6 V AGND − 0.1 VREFP − 0.5 V AGND VREFP − 0.5 V Buffer off VREFN + 0.5 AVDD + 0.1 V Buffer on(6) VREFN + 0.5 AVDD − 2.0 Buffer off Buffer on(6) 0.5 fCLKIN = 7.68MHz 2.5 18.5 V kΩ Digital Input/Output VIH DIN, SCLK, XTAL1/CLKIN, SYNC/PDWN, CS, RESET 0.8 DVDD D0/CLKOUT, D1, D2, D3 VIL VOH IOH = 5mA VOL IOL = 5mA 5.25 V 0.8 DVDD DVDD V DGND 0.2 DVDD V 0.8 DVDD Input hysteresis V 0.2 DVDD V ±10 μA 0.5 Input leakage 0 < VDIGITAL INPUT < DVDD Master clock rate External crystal between XTAL1 and XTAL2 External oscillator driving CLKIN V 2 7.68 10 MHz 0.1 7.68 10 MHz 3 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.75 5.25 V 1.8 3.6 V 2 μA Power-Supply AVDD DVDD Power-down mode AVDD current Standby mode 20 Normal mode, PGA = 1, Buffer off 7 10 mA Normal mode, PGA = 64, Buffer off 16 22 mA Normal mode, PGA = 1, Buffer on 13 19 mA Normal mode, PGA = 64, Buffer on 36 50 mA 2 μA Power-down mode DVDD current Power dissipation μA Standby mode, CLKOUT off, DVDD = 3.3V 95 Normal mode, CLKOUT off, DVDD = 3.3V 0.9 2 mA Normal mode, PGA = 1, Buffer off, DVDD = 3.3V 38 57 mW Standby mode, DVDD = 3.3V 0.4 μA mW Temperature Range Specified −40 +85 °C Operating −40 +105 °C Storage −60 +150 °C (1) (2) (3) (4) (5) (6) 4 See text for more information on input impedance. SPS = samples per second. FSR = full-scale range = 4VREF/PGA. fCM is the frequency of the common-mode input signal. Placing a notch of the digital filter at 60Hz (setting fDATA = 60SPS, 30SPS, 15SPS, 10SPS, 5SPS, or 2.5SPS) will further improve the common-mode rejection of this frequency. The reference input range with Buffer on is restricted only if self-calibration or gain self-calibration is to be used. If using system calibration or writing calibration values directly to the registers, the entire Buffer off range can be used. ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 PIN ASSIGNMENTS SSOP PACKAGE AVDD 1 28 D3 (TOP VIEW) AGND 2 27 D2 AVDD 1 20 D1 VREFN 3 26 D1 AGND 2 19 D0/CLKOUT VREFP 4 25 D0/CLKOUT VREFN 3 18 SCLK AINCOM 5 24 SCLK VREFP 4 17 DIN AIN0 6 23 DIN AINCOM 5 16 DOUT AIN1 7 AIN0 6 15 DRDY AIN2 8 AIN1 7 14 CS AIN3 9 SYNC, PDWN 8 13 XTAL1/CLKIN AIN4 10 19 XTAL1/CLKIN RESET 9 12 XTAL2 AIN5 11 18 XTAL2 11 DGND AIN6 12 17 DGND AIN7 13 16 DVDD ADS1255 DVDD 10 ADS1256 SYNC, PDWN 14 22 DOUT 21 DRDY 20 CS 15 RESET Terminal Functions TERMINAL NO. ANALOG/DIGITAL INPUT/OUTPUT Analog NAME ADS1255 ADS1256 AVDD 1 1 AGND 2 2 Analog VREFN 3 3 Analog input Negative reference input VREFP 4 4 Analog input Positive reference input AINCOM 5 5 Analog input Analog input common AIN0 6 6 Analog input Analog input 0 AIN1 7 7 Analog input Analog input 1 AIN2 — 8 Analog input Analog input 2 AIN3 — 9 Analog input Analog input 3 AIN4 — 10 Analog input Analog input 4 AIN5 — 11 Analog input Analog input 5 AIN6 — 12 Analog input Analog input 6 AIN7 — 13 Analog input Analog input 7 SYNC/PDWN 8 14 Digital input(1)(2): active low Digital input(1)(2): DESCRIPTION Analog power supply Analog ground RESET 9 15 DVDD 10 16 Digital Digital power supply DGND 11 17 Digital Digital ground XTAL2 12 18 Digital(3) XTAL1/CLKIN 13 19 Digital/Digital input(2) Digital input(1)(2): active low Synchronization / power down input active low Reset input Crystal oscillator connection Crystal oscillator connection / external clock input CS 14 20 DRDY 15 21 Digital output: active low Chip select Data ready output DOUT 16 22 Digital output Serial data output DIN 17 23 Digital input(1)(2) Serial data input SCLK 18 24 Digital input(1)(2) Serial clock input D0/CLKOUT 19 25 Digital IO(4) IO(4) Digital I/O 1 Digital I/O 0 / clock output D1 20 26 Digital D2 — 27 Digital IO(4) Digital I/O 2 D3 — 28 Digital IO(4) Digital I/O 3 (1) Schmitt-Trigger digital input. (2) 5V tolerant digital input. (3) Leave disconnected if external clock input is applied to XTAL1/CLKIN. (4) Schmitt-Trigger digital input when the digital I/O is configured as an input. 5 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 PARAMETER MEASUREMENT INFORMATION CS t3 t2H t1 t10 SCLK t4 t5 t6 t2L t11 DIN t7 t8 t9 DOUT Figure 1. Serial Interface Timing TIMING CHARACTERISTICS FOR FIGURE 1 SYMBOL DESCRIPTION t1 SCLK period t2H SCLK pulse width: high t2L SCLK pulse width: low MIN time(3) τDATA(2) 9 τDATA ns 200 ns 0 ns CS low to first SCLK: setup t4 Valid DIN to SCLK falling edge: setup time 50 ns t5 Valid DIN to SCLK falling edge: hold time 50 ns t6 Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC, RREG Commands 50 τCLKIN t7 SCLK rising edge to valid new DOUT: propagation delay(4) t8 SCLK rising edge to DOUT invalid: hold time 0 t9 Last SCLK falling edge to DOUT high impedance NOTE: DOUT goes high impedance immediately when CS goes high 6 t10 CS low after final SCLK falling edge 8 τCLKIN 4 τCLKIN 24 τCLKIN Final SCLK falling edge of command to first SCLK rising edge of next command. τCLKIN = master clock period = 1/fCLKIN. τDATA = output data period 1/fDATA. (3) CS can be tied low. (4) DOUT load = 20pF ⎥⎥ 100kΩ to DGND. 6 10 t3 t11 (2) UNIT τCLKIN(1) 200 RREG, WREG, RDATA (1) MAX 4 RDATAC, SYNC RDATAC, RESET, STANDBY, SELFOCAL, SYSOCAL, SELFGCAL, SYSGCAL, SELFCAL 50 ns ns 10 τCLKIN Wait for DRDY to go low ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 t 13 SCLK t13 t 12 t 14 t15 Figure 2. SCLK Reset Timing TIMING CHARACTERISTICS FOR FIGURE 2 SYMBOL (1) DESCRIPTION MIN MAX UNIT t12 SCLK reset pattern, first high pulse 300 500 τCLKIN(1) t13 SCLK reset pattern, low pulse t14 SCLK reset pattern, second high pulse t15 SCLK reset pattern, third high pulse τCLKIN 5 τCLKIN 550 750 τCLKIN 1050 1250 τCLKIN MIN MAX = master clock period = 1/fCLKIN. CLKIN t16B t 16 RESET, SYNC/PDWN SYNC/PDWN Figure 3. RESET and SYNC/PDWN Timing TIMING CHARACTERISTICS FOR FIGURE 3 SYMBOL (1) DESCRIPTION t16 RESET, SYNC/PDWN, pulse width t16B SYNC/PDWN rising edge to CLKIN rising edge UNIT τCLKIN(1) 4 −25 25 MIN MAX ns τCLKIN = master clock period = 1/fCLKIN. t17 DRDY Figure 4. DRDY Update Timing TIMING CHARACTERISTICS FOR FIGURE 4 SYMBOL t17 (1) DESCRIPTION Conversion data invalid while being updated (DRDY shown with no data retrieval) 16 UNIT τCLKIN(1) τCLKIN = master clock period = 1/fCLKIN. 7 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted. OFFSET DRIFT HISTOGRAM 25 PGA = 1 OFFSET DRIFT HISTOGRAM 30 90 Units from 3 Production Lots Percent of Population 15 10 5 20 15 10 5 0 −500 −450 −400 −350 −300 −250 −200 −150 −100 −50 0 50 100 150 200 250 300 350 400 450 500 −20 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12 14 16 18 20 0 Offset Drift (nV/_C) Offset Drift (nV/_C) GAIN ERROR HISTOGRAM PGA = 1 GAIN ERROR HISTOGRAM 25 90 Units from 3 Production Lots 20 15 10 5 15 10 5 0 −0.0100 −0.0095 −0.0090 −0.0085 −0.0080 −0.0075 −0.0070 −0.0065 −0.0060 −0.0055 −0.0050 −0.0045 −0.0040 −0.0035 −0.0030 −0.0025 −0.0020 −0.0015 −0.0010 −0.0005 0 0 Gain Error (%) Gain Error (%) GAIN DRIFT HISTOGRAM 25 PGA = 1 GAIN DRIFT HISTOGRAM 25 90 Units from 3 Production Lots PGA = 64 90 Units from 3 Production Lots 20 Percent of Population Percent of Population 20 15 10 5 15 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0 8 90 Units from 3 Production Lots 20 Percent of Population Percent of Population 25 PGA = 64 −0.060 −0.057 −0.054 −0.051 −0.048 −0.045 −0.042 −0.039 −0.036 −0.033 −0.030 −0.027 −0.024 −0.021 −0.018 −0.015 −0.012 −0.009 −0.006 −0.003 0 30 90 Units from 3 Production Lots 25 20 Percent of Population PGA = 64 Gain Drift (ppm/_C) Gain Drift (ppm/_C) ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted. NOISE HISTOGRAM Buffer = Off 256 Readings 60 40 20 −5 −4 −3 −2 −1 0 1 2 3 4 15 10 5 0 5 Output Code (LSB) Output Code (LSB) NOISE HISTOGRAM Percent of Population 20 PGA = 1 Data Rate = 1kSPS NOISE HISTOGRAM 25 Buffer = Off 4096 Readings 20 Percent of Population 25 15 10 5 0 5 −150 −135 −120 −105 −90 −75 −60 −45 −30 −15 0 15 30 45 60 75 90 105 120 135 150 −20 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12 14 16 18 20 0 Output Code (LSB) NOISE HISTOGRAM 25 Buffer = Off 4096 Readings 20 Percent of Population PGA = 1 Data Rate = 30kSPS 15 10 5 Output Code (LSB) PGA = 64 Data Rate = 30kSPS Buffer = Off 4096 Readings 15 10 5 0 0 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 Percent of Population Buffer = Off 4096 Readings 10 NOISE HISTOGRAM 20 PGA = 64 Data Rate = 1kSPS 15 Output Code (LSB) 25 Buffer = Off 256 Readings −20 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12 14 16 18 20 0 20 PGA = 64 Data Rate = 2.5SPS −600 −540 −480 −420 −360 −300 −240 −180 −120 −60 0 60 120 180 240 300 360 420 480 540 600 Percent of Population 80 PGA = 1 Data Rate = 2.5SPS NOISE HISTOGRAM 25 Percent of Population 100 Output Code (LSB) 9 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted. EFFECTIVE NUMBER OF BITS vs INPUT VOLTAGE 23 EFFECTIVE NUMBER OF BITS vs TEMPERATURE 23 PGA = 1 21 Data Rate = 30kSPS 20 Data Rate = 1kSPS 22 ENOB (rms) ENOB (rms) PGA = 1 Data Rate = 1kSPS 22 19 21 Data Rate = 30kSPS 20 19 18 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 18 5.0 −50 −30 −10 10 Input Voltage, VIN (V) ⎟ INL⎟ (% of FSR) INL (% of FSR) +125_ C +85_C +25_ C −0.0002 0.0007 Buffer Off 0.0006 0.0005 0.0004 Buffer On 0.0003 0.0001 P GA = 1 −5 −4 −3 −2 −1 0 1 2 3 4 0 5 1 2 4 Input Voltage, VIN (V) 8 16 32 64 PGA Setting ANALOG SUPPLY CURRENT vs TEMPERATURE ANALOG SUPPLY CURRENT vs PGA 40 50 PGA = 64, Buffer On 45 35 Analog Current (mA) 40 Analog Current (mA) 110 0.0002 −0.0004 35 30 25 PGA = 64, Buffer Off 20 PGA = 1, Buffer On 15 PGA = 1, Buffer Off 10 Buffer On 30 25 Buffer Off 20 15 10 5 5 −50 −30 −10 10 30 50 Temperature (_C) 10 90 0.0008 − 40_C 0 0 70 0.0009 0.0004 −0.0006 50 INTEGRAL NONLINEARITY vs PGA INTEGRAL NONLINEARITY vs INPUT SIGNAL 0.0006 0.0002 30 Temperature (_C) 70 90 110 0 1 2 4 8 PGA Setting 16 32 64 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 OVERVIEW The ADS1255 and ADS1256 are very low-noise A/D converters. The ADS1255 supports one differential or two single-ended inputs and has two general-purpose digital I/Os. The ADS1256 supports four differential or eight single-ended inputs and has four general-purpose digital I/Os. Otherwise, the two units are identical and are referred to together in this data sheet as the ADS1255/6. Figure 5 shows a block diagram of the ADS1256. The input multiplexer selects which input pins are connected to the A/D converter. Selectable current sources within the input multiplexer can check for open- or short-circuit conditions on the external sensor. A selectable onboard input buffer greatly reduces the input circuitry loading by providing up to 80MΩ of impedance. A low-noise PGA provides a gain of 1, 2, 4, 8, 16, 32, or 64. The ADS1255/6 converter is comprised of a 4th-order, delta-sigma modulator followed by a programmable digital filter. The modulator measures the amplified differential input signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP − VREFN). The differential reference is scaled internally by a factor of two so that the full-scale input range is ±2VREF (for PGA = 1). The digital filter receives the modulator signal and provides a low-noise digital output. The data rate of the filter is programmable from 2.5SPS to 30kSPS and allows tradeoffs between resolution and speed. Communication is done over an SPI-compatible serial interface with a set of simple commands providing control of the ADS1255/6. Onboard registers store the various settings for the input multiplexer, sensor detect current sources, input buffer enable, PGA setting, data rate, etc. Either an external crystal or clock oscillator can be used to provide the clock source. General-purpose digital I/Os provide static read/write control of up to four pins. One of the pins can also be used to supply a programmable clock output. VREFP VREFN Σ VREF AIN0 2 AIN1 ADS1256 Only AIN2 AIN3 AIN4 AIN5 AIN6 A/D Converter Input Multiplexer AINP and Sensor AINN Detect Clock Generator XTAL2 2VREF Buffer PGA 1:64 Σ VIN • PGA 4th−Order Modulator Programmable Digital Filter Control AIN7 AINCOM XTAL1/CLKIN RESET SYNC/PDWN DRDY General Purpose Digital I/O SPI Serial Interface SCLK DIN DOUT CS D3 D2 D1 D0/CLKOUT ADS1256 Only Figure 5. Block Diagram 11 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 NOISE PERFORMANCE The ADS1255/6 offer outstanding noise performance that can be optimized by adjusting the data rate or PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. The PGA reduces the input-referred noise when measuring lower level signals. Table 1 through Table 6 summarize the typical noise performance with the inputs shorted externally. In all six tables, the following conditions apply: T = +25°C, AVDD = 5V, DVDD = 1.8V, VREF = 2.5V, and fCLKIN = 7.68MHz. Table 1 to Table 3 reflect the device input buffer enabled. Table 1 shows the rms value of the input-referred noise in volts. Table 2 shows the effective number of bits of resolution (ENOB), using the noise data from Table 1. ENOB is defined as: Table 2. Effective Number of Bits (ENOB, rms) with Buffer On DATA RATE (SPS) 1 2 4 8 16 32 64 2.5 25.3 24.9 24.9 24.4 23.8 23.0 22.2 5 25.0 24.8 24.5 24.0 23.3 22.7 21.8 10 24.8 24.5 24.1 23.5 22.9 22.3 21.3 15 24.6 24.2 23.8 23.2 22.5 21.8 21.0 25 24.3 24.0 23.4 23.0 22.2 21.5 20.7 30 24.2 23.8 23.3 22.8 22.1 21.5 20.5 50 23.9 23.6 23.0 22.5 21.8 21.1 20.3 60 23.8 23.4 22.9 22.4 21.7 21.0 20.2 100 23.4 23.0 22.5 22.0 21.4 20.8 19.8 PGA 500 22.3 21.9 21.5 20.9 20.3 19.6 18.7 1000 21.7 21.3 20.8 20.2 19.8 19.2 18.3 2000 21.2 20.9 20.4 19.7 19.3 18.8 17.9 3750 20.8 20.5 20.0 19.4 19.0 18.4 17.4 where FSR is the full-scale range. Table 3 shows the noise-free bits of resolution. It is calculated with the same formula as ENOB except the peak-to-peak noise value is used instead of rms noise. Table 4 through Table 6 show the same noise data, but with the input buffer disabled. 7500 20.4 20.1 19.6 19.0 18.5 17.9 17.0 15,000 20.1 19.7 19.3 18.7 18.2 17.7 16.7 30,000 19.8 19.5 19.1 18.5 18.0 17.4 16.5 Table 1. Input Referred Noise (μV, rms) with Buffer On DATA RATE (SPS) 1 2 4 8 16 32 64 2.5 23.0 22.6 22.1 21.7 21.3 20.8 19.7 5 22.3 22.4 21.9 21.3 20.7 20.3 19.3 10 22.3 22.0 21.6 21.0 20.4 19.9 18.9 15 22.0 21.7 21.3 20.7 20.1 19.3 18.7 25 21.7 21.4 21.1 20.5 19.7 19.2 18.5 30 21.8 21.3 20.8 20.4 19.8 19.0 18.1 50 21.3 21.1 20.4 19.9 19.4 18.8 17.9 60 21.3 20.9 20.5 19.8 19.3 18.8 17.8 100 20.9 20.7 20.2 19.6 19.1 18.5 17.4 500 20.1 19.6 19.1 18.6 18.0 17.3 16.3 1000 19.0 18.6 18.1 17.5 17.2 16.5 15.6 2000 18.5 18.1 17.8 17.0 16.6 16.1 15.3 3750 18.1 17.8 17.3 16.6 16.2 15.7 14.7 7500 17.7 17.3 16.9 16.2 15.8 15.3 14.4 15,000 17.3 17.0 16.5 15.9 15.5 14.9 13.9 30,000 17.1 16.7 16.4 15.9 15.4 14.6 13.8 lnǒFSRńRMS NoiseǓ ENOB + ln(2) DATA RATE (SPS) 1 2 4 8 16 32 64 2.5 0.247 0.156 0.080 0.056 0.043 0.037 0.033 5 0.301 0.175 0.102 0.076 0.061 0.045 0.044 10 0.339 0.214 0.138 0.106 0.082 0.061 0.061 15 0.401 0.264 0.169 0.126 0.107 0.085 0.073 25 0.494 0.305 0.224 0.149 0.134 0.102 0.093 30 0.533 0.335 0.245 0.176 0.138 0.104 0.106 50 0.629 0.393 0.292 0.216 0.168 0.136 0.122 60 0.692 0.438 0.321 0.233 0.184 0.146 0.131 100 0.875 0.589 0.409 0.305 0.229 0.170 0.169 500 1.946 1.250 0.630 0.648 0.497 0.390 0.367 1000 2.931 1.891 1.325 1.070 0.689 0.512 0.486 2000 4.173 2.589 1.827 1.492 0.943 0.692 0.654 3750 5.394 3.460 2.376 1.865 1.224 0.912 0.906 7500 7.249 4.593 3.149 2.436 1.691 1.234 1.187 15,000 9.074 5.921 3.961 2.984 2.125 1.517 1.515 30,000 10.728 6.705 4.446 3.280 2.416 1.785 1.742 12 PGA Table 3. Noise-Free Resolution (bits) with Buffer On PGA ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Table 4. Input Referred Noise (μV, rms) with Buffer Off DATA RATE (SPS) 1 2 4 8 16 32 2.5 0.247 0.149 0.097 0.058 0.036 5 0.275 0.176 0.109 0.070 0.046 10 0.338 0.201 0.129 0.084 15 0.401 0.221 0.150 0.109 25 0.485 0.279 0.177 30 0.559 0.315 50 0.644 60 Table 6. Noise-Free Resolution (bits) with Buffer Off 64 DATA RATE (SPS) 1 2 4 8 16 32 64 0.031 0.027 2.5 23.0 22.4 22.0 21.9 21.3 21.1 20.0 0.039 0.038 5 22.4 22.1 21.9 21.5 21.2 20.4 19.4 0.063 0.048 0.047 10 22.3 22.1 21.7 21.5 20.8 20.3 19.2 0.070 0.063 0.057 15 22.0 21.8 21.4 20.8 20.6 19.9 19.0 0.136 0.093 0.076 0.076 25 21.8 21.7 21.1 20.7 20.3 19.5 18.6 0.202 0.142 0.107 0.093 0.082 30 21.6 21.4 21.1 20.4 20.0 16.4 18.5 0.390 0.238 0.187 0.129 0.108 0.103 50 21.3 21.3 20.7 20.1 19.8 19.1 18.2 0.688 0.417 0.281 0.204 0.134 0.109 0.111 60 21.2 21.0 20.6 20.1 19.8 19.1 18.1 100 0.815 0.530 0.360 0.233 0.169 0.123 0.122 100 21.1 20.5 20.3 19.9 19.5 19.0 17.9 PGA PGA 500 1.957 1.148 0.772 0.531 0.375 0.276 0.259 500 20.0 19.7 19.3 18.9 18.3 17.8 16.9 1000 2.803 1.797 1.191 0.940 0.518 0.392 0.365 1000 19.0 18.7 18.4 17.7 17.5 16.9 15.9 2000 4.025 2.444 1.615 1.310 0.700 0.526 0.461 2000 18.5 18.3 17.9 17.4 17.0 16.4 15.6 3750 5.413 3.250 2.061 1.578 0.914 0.693 0.625 3750 18.1 17.8 17.5 17.0 16.7 16.1 15.2 7500 7.017 4.143 2.722 1.998 1.241 0.914 0.857 7500 17.7 17.6 17.0 16.6 16.2 15.7 14.8 15,000 8.862 5.432 3.378 2.411 1.569 1.149 1.051 15,000 17.4 17.1 16.8 16.3 15.9 15.3 14.4 30,000 10.341 6.137 3.873 2.775 1.805 1.313 1.211 30,000 17.1 17.0 16.6 16.0 15.6 15.0 14.4 Table 5. Effective Number of Bits (ENOB, rms) with Buffer Off DATA RATE (SPS) 1 2 4 8 16 32 64 2.5 25.3 25.0 24.6 24.4 24.0 23.2 22.5 5 25.1 24.8 24.5 24.1 23.7 22.9 22.0 10 24.8 24.6 24.2 23.8 23.2 22.6 21.7 15 24.6 24.4 24.0 23.4 23.1 22.2 21.4 25 24.3 24.1 23.8 23.1 22.7 22.0 21.0 30 24.1 23.9 23.6 23.1 22.5 21.7 20.9 50 23.9 23.6 23.3 22.7 22.2 21.5 20.5 60 23.8 23.5 23.1 22.5 22.1 21.5 20.4 100 23.5 23.2 22.7 22.4 21.8 21.3 20.3 500 22.3 22.1 21.6 21.2 20.7 20.1 19.2 1000 21.8 21.4 21.0 20.3 20.2 19.6 18.7 2000 21.2 21.0 20.6 19.9 19.8 19.2 18.4 3750 20.8 20.6 20.2 19.6 19.4 18.8 17.9 7500 20.4 20.2 19.8 19.3 18.9 18.4 17.5 15,000 20.1 19.8 19.5 19.0 18.6 18.1 17.2 30,000 19.9 19.6 19.3 18.8 18.4 17.9 17.0 PGA 13 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 INPUT MULTIPLEXER Figure 6 shows a simplified diagram of the input multiplexer. This flexible block allows any analog input pin to be connected to either of the converter differential inputs. That is, any pin can be selected as the positive input (AINP); likewise, any pin can be selected as the negative input (AINN). The pin selection is controlled by the multiplexer register. The ADS1256 offers nine analog inputs, which can be configured as four independent differential inputs, eight single-ended inputs, or a combination of differential and single-ended inputs. The ADS1255 offers three analog inputs, which can be configured as one differential input or two single-ended inputs. When using the ADS1255 and programming the input, make sure to select only the available inputs when programming the input multiplexer register. In general, there are no restrictions on input pin selection. However, for optimum analog performance, the following recommendations are made: 1. For differential measurements use AIN0 through AIN7, preferably adjacent inputs. For example, use AIN0 and AIN1. Do not use AINCOM. 2. For single-ended measurements use AINCOM as common input and AIN0 through AIN7 as single-ended inputs. 3. Leave any unused analog inputs floating. This minimizes the input leakage current. ESD diodes protect the analog inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AGND by more than 100mV, and likewise do not exceed AVDD by more than 100mV: −100mV < (AIN0 − 7 and AINCOM) < AVDD + 100mV. When using ADS1255/6 for single-ended measurements, it is important to note that common input AINCOM does not need to be tied to ground. For example, AINCOM can be tied to a midpoint reference such as +2.5V or even AVDD. AVDD AIN0 AVDD AIN1 AVDD AVDD AIN2 AIN3 Sensor Detect Current Source AVDD AVDD AINP AIN4 AIN5 AIN6 AVDD AINN Input Buffer AVDD Sensor Detect Current Source AVDD AGND AIN7 ADS1256 Only AINCOM Input Multiplexer AVDD AGND Figure 6. Simplified Diagram of the Input Multiplexer 14 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 OPEN/SHORT SENSOR DETECTION ANALOG INPUT BUFFER The sensor detect current sources (SDCS) provide a means to verify the integrity of the external sensor connected to the ADS1255/6. When enabled, the SDCS supply a current (ISDC) of approximately 0.5μA, 2μA, or 10μA to the sensor through the input multiplexer. The SDCS bits in the ADCON register enable the SDCS and set the value of ISDC. To dramatically increase the input impedance presented by the ADS1255/6, the low-drift chopper-stabilized buffer can be enabled via the BUFEN bit in the STATUS register. The input impedance with the buffer enabled can be modeled by a resistor, as shown in Figure 8. Table 7 lists the values of Zeff for the different data rate settings. The input impedance scales inversely with the frequency of CLKIN. For example, if fCLKIN is reduced by half to 3.84MHz, Zeff for a data rate of 50SPS will double from 80MΩ to 160MΩ. Figure 7 shows a simplified diagram of ADS1255/6 input structure with the external sensor modeled as resistance RSENS between two input pins. When the SDCS are enabled, they source ISDC to the input pin connected to AINP and sink ISDC from the input pin connected to AINN. The two 25Ω series resistors, RMUX, model the ADS1255/6 internal resistances. The signal measured with the SDCS enabled equals the total IR drop: ISDC × (2RMUX + RSENS). Note that when the sensor is a direct short (that is, RSENS = 0), there will still be a small signal measured by the ADS1255/6 when the SDCS are enabled: ISDC × 2RMUX. AIN0 AIN1 AIN2 ADS1256 Only When the SDCS are enabled, the ADS1255/6 automatically turns on the analog input buffer regardless of the BUFEN bit setting. This is done to prevent the input circuitry from loading the SDCS. AINP must stay below 3V to be within the absolute input range of the buffer. To ensure this condition is met, a 3V clamp will start sinking current from AINP to AGND if AINP exceeds 3V. Note that this clamp is activated only when the SDCS are enabled. AIN3 AIN4 AIN5 AINP Input Multiplexer AIN6 Zeff AINN AIN7 AINCOM Figure 8. Effective Impedance with Buffer On Table 7. Input Impedance with Buffer On AVDD Sensor Detect Current Source RMUX 25Ω AINP 3V Clamp RSENS Input Buffer RMUX 25Ω AINN DATA RATE (SPS) Zeff (MΩ) 30,000 10 15,000 10 7,500 10 3,750 10 2,000 10 1,000 20 500 40 100 40 60 40 ≤ 50 80 NOTE: fCLKIN = 7.68MHz. Sensor Detect Current Source NOTE: Arrows indicate switch positions when the SDCS are enabled. Figure 7. Sensor Detect Circuitry With the buffer enabled, the voltage on the analog inputs with respect to ground (listed in the Electrical Characteristics as Absolute Input Voltage) must remain between AGND and AVDD − 2.0V. Exceeding this range reduces performance, in particular the linearity of the ADS1255/6. This same voltage range, AGND to AVDD − 2.0V, applies to the reference inputs when performing a self gain calibration with the buffer enabled. 15 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 The ADS1255/6 is a very high resolution converter. To further complement its performance, the low-noise PGA provides even more resolution when measuring smaller input signals. For the best resolution, set the PGA to the highest possible setting. This will depend on the largest input signal to be measured. The ADS1255/6 full-scale input voltage equals ±2VREF/PGA. Table 8 shows the full-scale input voltage for the different PGA settings for VREF = 2.5V. For example, if the largest signal to be measured is 1.0V, the optimum PGA setting would be 4, which gives a full-scale input voltage of 1.25V. Higher PGAs cannot be used since they cannot handle a 1.0V input signal. and CA2 discharge to approximately AVDD/2 and CB discharges to 0V. This two-phase sample/discharge cycle repeats with a period of τSAMPLE. This time is a function of the PGA setting as shown in Table 9 along with the values of the capacitor CA1 = CA2 = CA and CB. AVDD/2 AIN0 AIN2 Table 8. Full-Scale Input Voltage vs PGA Setting PGA SETTING FULL-SCALE INPUT VOLTAGE VIN(1) (VREF = 2.5V) 1 ±5V 2 ±2.5V (1) 4 ±1.25V 8 ±0.625V 16 ±312.5mV 32 ±156.25mV 64 ±78.125mV The input voltage (VIN) is the difference between the positive and negative inputs. Make sure neither input violates the absolute input voltage with respect to ground, as listed in the Electrical Characteristics. The PGA is controlled by the ADCON register. Recalibrating the A/D converter after changing the PGA setting is recommended. The time required for self-calibration is dependent on the PGA setting. See the Calibration section for more details. The analog current and input impedance (when the buffer is disabled) vary as a function of PGA setting. MODULATOR INPUT CIRCUITRY The ADS1255/6 modulator measures the input signal using internal capacitors that are continuously charged and discharged. Figure 9 shows a simplified schematic of the ADS1255/6 input circuitry with the input buffer disabled. Figure 10 shows the on/off timings of the switches of Figure 9. S1 switches close during the input sampling phase. With S1 closed, CA1 charges to AINP, CA2 charges to AINN, and CB charges to (AINP – AINN). For the discharge phase, S1 opens first and then S2 closes. CA1 16 S2 AIN1 ADS1256 Only PROGRAMMABLE GAIN AMPLIFIER (PGA) AIN3 AIN4 AIN5 CA1 AINP S1 Input Multiplexer CB S1 AINN AIN6 S2 AIN7 CA2 AINCOM AVDD/2 Figure 9. Simplified Input Structure with Buffer Off τ SAMPLE S1 S2 ON OFF ON OFF Figure 10. S1 and S2 Switch Timing for Figure 9 Table 9. Input Sampling Time, τSAMPLE, and CA and CB vs PGA PGA SETTING τSAMPLE(1) CA CB 1 fCLKIN/4 (521ns) 2.1pF 2.4pF 2 fCLKIN/4 (521ns) 4.2pF 4.9pF 4 fCLKIN/4 (521ns) 8.3pF 9.7pF (1) 8 fCLKIN/4 (521ns) 17pF 19pF 16 fCLKIN/4 (521ns) 33pF 39pF 32 fCLKIN/2 (260ns) 33pF 39pF 64 fCLKIN/2 (260ns) 33pF 39pF τSAMPLE for fCLKIN = 7.68MHz. ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 The charging of the input capacitors draws a transient current from the sensor driving the ADS1255/6 inputs. The average value of this current can be used to calculate an effective impedance Zeff where Zeff = VIN / IAVERAGE. Figure 11 shows the input circuitry with the capacitors and switches of Figure 9 replaced by their effective impedances. These impedances scale inversely with the CLKIN frequency. For example, if fCLKIN is reduced by a factor of two, the impedances will double. They also change with the PGA setting. Table 10 lists the effective impedances with the buffer off for fCLKIN = 7.68MHz. VREFP AVDD VREFN AVDD ESD Protection Self Gain Calibration Zeff = 18.5kΩ(1) AIN1 ADS1256 Only AIN2 AIN3 AIN4 AIN5 AINP AINN AVDD/2 AIN0 AINP Input Multiplexer AIN N AIN6 ZeffA = τ SAMPLE /CA ZeffB = τ SAMPLE /CB ZeffA = τ SAMPLE /CA AIN7 AINCOM (1) fCLKIN = 7.68MHz Figure 12. Simplified Reference Input Circuitry AVDD/2 Figure 11. Analog Input Effective Impedances with Buffer Off Table 10. Analog Input Impedances with Buffer Off PGA SETTING ZeffA (kΩ) ZeffB (kΩ) 1 260 220 2 130 110 4 65 55 8 33 28 16 16 14 32 8 7 64 8 7 NOTE: fCLKIN = 7.68MHz. VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1255/6 A/D converter is the differential voltage between VREFP and VREFN: VREF = VREFP − VREFN. The reference inputs use a structure similar to that of the analog inputs with the circuitry on the reference inputs of Figure 12. The load presented by the switched capacitor can be modeled with an effective impedance (Zeff) of 18.5kΩ for fCLKIN = 7.68MHz. The temperature coefficient of the effective impedance of the voltage reference inputs is approximately 35ppm/°C. ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 100mV, and likewise do not exceed AVDD by 100mV: −100mV < (VREFP or VREFN) < AVDD + 100mV During self gain calibration, all the switches in the input multiplexer are opened, VREFN is internally connected to AINN, and VREFP is connected to AINP. The input buffer may be disabled or enabled during calibration. When the buffer is disabled, the reference pins will be driving the circuitry shown in Figure 9 during self gain calibration, resulting in increased loading. To prevent this additional loading from introducing gain errors, make sure the circuitry driving the reference pins has adequate drive capability. When the buffer is enabled, the loading on the reference pins will be much less, but the buffer will limit the allowable voltage range on VREFP and VREFN during self or self gain calibration as the reference pins must remain within the specified input range of the buffer in order to establish proper gain calibration. A high-quality reference voltage capable of driving the switched capacitor load presented by the ADS1255/6 is essential for achieving the best performance. Noise and drift on the reference degrade overall system performance. It is especially critical that special care be given to the circuitry generating the reference voltages and their layout when operating in the low-noise settings (that is, with low data rates) to prevent the voltage reference from limiting performance. See the Applications section for more details. 17 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DIGITAL FILTER The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rate. The filter is comprised of two sections, a fixed filter followed by a programmable filter. Figure 13 shows the block diagram of the analog modulator and digital filter. Data is supplied to the filter from the analog modulator at a rate of fCLKIN/4. The fixed filter is a 5th-order sinc filter with a decimation value of 64 that outputs data at a rate of fCLKIN/256. The second stage of the filter is a programmable averager (1st-order sinc filter) with the number of averages set by the DRATE register. The data rate is a function of the number of averages (Num_Ave) and is given by Equation 1. Data Rate + Modulator Rate = fCLKIN/4 Analog Modulator 1 ǒf256 ǓǒNum_Ave Ǔ DataRate + sinc5 Filter CLKIN f CLKIN 256 DataRate + ǒ Ǔǒ f CLKIN 256 1 Num_Ave (1) Ǔ Programmable Averager Num_Ave (set by DRATE) Digital Filter Figure 13. Block Diagram of the Analog Modulator and Digital Filter Table 11. Number of Averages and Data Rate for Each Valid DRATE Register Setting DRATE DR[7:0] NUMBER OF AVERAGES FOR PROGRAMMABLE FILTER (Num_Ave) DATA RATE(1) (SPS) 11110000 1 (averager bypassed) 30,000 11100000 2 15,000 11010000 4 7500 11000000 8 3750 10110000 15 2000 10100001 30 1000 10010010 60 500 10000010 300 100 01110010 500 60 01100011 600 50 01010011 1000 30 01000011 1200 25 00110011 2000 15 00100011 3000 10 00010011 6000 5 00000011 12,000 2.5 (1) for fCLKIN = 7.68MHz. FREQUENCY RESPONSE The low-pass digital filter sets the overall frequency response for the ADS1255/6. The filter response is the product of the responses of the fixed and programmable filter sections and is given by Equation 2. · ŤH (f)Ť + Ǔ ȧ ȧ sinǒ · Ǔ ȧ ȧ sinǒ · ȧ ȧ ·ȧ ȧ ȧ64 · sinǒ · Ǔȧ ȧNum_Ave · sinǒ · Ǔȧ ȧ ȧȧ ȧ |H(f)| + ŤH sinc 5(f)Ť 5 256p f f CLKIN 4p Table 11 shows the averaging and corresponding data rate for each of the 16 valid DRATE register settings when fCLKIN = 7.68MHz. Note that the data rate scales directly with the CLKIN frequency. For example, reducing fCLKIN from 7.68MHz to 3.84MHz reduces the data rate for DR[7:0] = 11110000 from 30,000SPS to 15,000SPS. f Averager 256p Num_Ave f f f CLKIN CLKIN (2) 256p f f CLKIN The digital filter attenuates noise on the modulator output, including noise from within the ADS1255/6 and external noise present on the ADS1255/6 input signal. Adjusting the filtering by changing the number of averages used in the programmable filter changes the filter bandwidth. With a higher number of averages, bandwidth is reduced and more noise is attenuated. The low-pass filter has notches (or zeros) at the data output rate and multiples thereof. At these frequencies, the filter has zero gain. This feature can be useful when trying to eliminate a particular interference signal. For example, to eliminate 60Hz (and the harmonics) pickup, set the data rate equal to 2.5SPS, 5SPS, 10SPS, 15SPS, 30SPS, or 60SPS. To help illustrate the filter characteristics, 18 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Figure 14 and Figure 15 show the responses at the data rate extremes of 30kSPS and 2.5SPS respectively. Table 12 summarizes the first-notch frequency and −3dB bandwidth for the different data rate settings. Table 12. First Notch Frequency and −3dB Filter Bandwidth DATA RATE (SPS) FIRST NOTCH (Hz) −3dB BANDWIDTH (Hz) 30,000 30,000 6106 15,000 15,000 4807 7500 7500 3003 3750 3750 1615 2000 2000 878 1000 1000 441 500 500 221 −80 100 100 44.2 −100 60(1) 60 26.5 50(2) 50 22.1 30(1) 30 13.3 25(2) 25 11.1 15(1) 15 6.63 10(3) 10 4.42 5(3) 5 2.21 2.5(3) 2.5 1.1 0 fDATA = 30kSPS −20 Gain (dB) −40 −60 −120 −140 0 15 30 45 60 75 90 105 120 Frequency (kHz) Figure 14. Frequency Response for Data Rate = 30kSPS NOTE: fCLKIN = 7.68MHz. (1) Notch at 60Hz. (2) Notch at 50Hz. (3) Notch at 50Hz and 60Hz. 0 −6 fDATA = 2.5SPS −12 Gain (dB) −18 −24 −30 −36 −42 −48 −54 −60 0 5 10 15 20 25 30 35 40 45 50 Frequency (Hz) 55 60 The digital filter low-pass characteristic repeats at multiples of the modulator rate of fCLKIN/4. Figure 16 and Figure 17 show the responses plotted out to 7.68MHz at the data rate extremes of 30kSPS and 2.5SPS. Notice how the responses near DC, 1.92MHz, 3.84MHz, 5.76MHz, 7.68MHz, are the same. The digital filter will attenuate high-frequency noise on the ADS1255/6 inputs up to the frequency where the response repeats. If significant noise on the inputs is present above this frequency, make sure to remove with external filtering. Fortunately, this can be done on the ADS1255/6 with a simple RC filter, as shown in the Applications Section (see Figure 25). Figure 15. Frequency Response for Data Rate = 2.5SPS 19 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Table 13. Settling Time vs Data Rate 0 fD A T A = 3 0 k S P S DATA RATE (SPS) SETTLING TIME (t18) (ms) 30,000 0.21 15,000 0.25 7500 0.31 −80 3750 0.44 −100 2000 0.68 1000 1.18 f −20 C L K IN = 7 .6 8 M H z Gain (dB) −40 −60 −120 −140 0 1.92 3.84 5.76 7.68 Frequency (MHz) Figure 16. Frequency Response Out to 7.68MHz for Data Rate = 30kSPS 0 f D A T A = 2 .5 S P S f −20 C L K IN = 7 .6 8 M H z Gain (dB) 2.18 100 10.18 60 16.84 50 20.18 30 33.51 25 40.18 15 66.84 10 100.18 5 200.18 2.5 400.18 NOTE: fCLKIN = 7.68MHz. NOTE: One−shot mode requires a small additional delay to power up the device from standby. −40 −60 −80 Settling Time Using Synchronization −100 −120 −140 0 1.92 3.84 5.76 7.68 Frequency (MHz) Figure 17. Frequency Response Out to 7.68MHz for Data Rate = 2.5SPS SETTLING TIME The ADS1255/6 features a digital filter optimized for fast settling. The settling time (time required for a step change on the analog inputs to propagate through the filter) for the different data rates is shown in Table 13. The following sections highlight the single-cycle settling ability of the filter and show various ways to control the conversion process. 20 500 The SYNC/PDWN pin allows direct control of conversion timing. Simply issue a Sync command or strobe the SYNC/PDWN pin after changing the analog inputs (see the Synchronization section for more information). The conversion begins when SYNC/PDWN is taken high, stopping the current conversion and restarting the digital filter. As soon as SYNC/PDWN goes low, the DRDY output goes high and remains high during the conversion. After the settling time (τ18), DRDY goes low, indicating that data is available. The ADS1255/6 settles in a single cycle—there is no need to ignore or discard data after synchronization. Figure 18 shows the data retrieval sequence following synchronization. ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Step 3: Read the data from the previous conversion using the RDATA command. AINP −AINN Step 4: When DRDY goes low again, repeat the cycle by first updating the multiplexer register, then reading the previous data. SYNC/PDWN t 18 Table 14 gives the effective overall throughput (1/t19) when cycling the input multiplexer. The values for throughput (1/t19) assume the multiplexer was changed with a 3-byte WREG command and fSCLK = fCLKIN/4. DRDY DIN RDATA Table 14. Multiplexer Cycling Throughput Settled Data DOUT Figure 18. Data Retrieval After Synchronization Settling Time Using the Input Multiplexer DATA RATE (SPS) CYCLING THROUGHPUT (1/t19) (Hz) 30,000 4374 15,000 3817 7500 3043 3750 2165 2000 1438 1000 837 500 456 100 98 60 59 50 50 30 30 25 25 15 15 10 10 5 5 2.5 2.5 The most efficient way to cycle through the inputs is to change the multiplexer setting (using a WREG command to the multiplexer register MUX) immediately after DRDY goes low. Then, after changing the multiplexer, restart the conversion process by issuing the SYNC and WAKEUP commands, and retrieve the data with the RDATA command. Changing the multiplexer before reading the data allows the ADS1256 to start measuring the new input channel sooner. Figure 19 demonstrates efficient input cycling. There is no need to ignore or discard data while cycling through the channels of the input multiplexer because the ADS1256 fully settles before DRDY goes low, indicating data is ready. Step 1: When DRDY goes low, indicating that data is ready for retrieval, update the multiplexer register MUX using the WREG command. For example, setting MUX to 23h gives AINP = AIN2, AINN = AIN3. NOTE: fCLKIN = 7.68MHz. Step 2: Restart the conversion process by issuing a SYNC command immediately followed by a WAKEUP command. Make sure to follow timing specification t11 between commands. t 18 t19 DRDY DIN WREG 23h to MUX reg SYNC WAKEUP SYNC WAKEUP RDATA Data from MUX = 01h DOUT 01h MUX Register AINP = AIN0, AINN = AIN1 WREG 45h to MUX reg RDATA 23h AINP = AIN2, AINN = AIN3 Data from MUX = 23h 45h AINP = AIN4, AIN N = AIN5 Figure 19. Cycling the ADS1256 Input Multiplexer 21 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 If there is a step change on the input signal while continuously converting, performing a synchronization operation to start a new conversion is recommended. Otherwise, the next data will represent a combination of the previous and current input signal and should therefore be discarded. Figure 21 shows an example of readback in this situation. Settling Time Using One-Shot Mode A dramatic reduction in power consumption can be achieved in the ADS1255/6 by performing one-shot conversions using the STANDBY command; the sequence for this is shown in Figure 20. Issue the WAKEUP command from Standby mode to begin a one-shot conversion. When using one−shot mode, an additional delay is required for the modulator to power up and settle. This delay may be up to 64 modulator clocks (64 x 4 x τCLKIN) or 33.3μs for a 7.68MHz master clock. Following the settling time (t18 + 256 x τCLKIN), DRDY will go low, indicating that the conversion is complete and data can be read using the RDATA command. The ADS1255/6 settles in a single cycle—there is no need to ignore or discard data. When using one−shot mode, an additional delay is required for the modulator to power up and settle. This delay may be up to 64 modulator clocks (64 x 4 x τCLKIN or 33.3μs for a 7.68MHz master clock. Following the data read cycle, issue another STANDBY command to reduce power consumption. When ready for the next measurement, repeat the cycle starting with another WAKEUP command. Table 15. Data Settling Delay vs Data Rate Settling Time while Continuously Converting After a synchronization, input multiplexer change, or wakeup from Standby mode, the ADS1255/6 will continuously convert the analog input. The conversions coincide with the falling edge of DRDY. While continuously converting, it is often more convenient to consider settling times in terms of DRDY periods, as shown in Table 15. The DRDY period equals the inverse of the data rate. Standby Mode ADS1255/6 Status DATA RATE (SPS) SETTLING TIME (DRDY Periods) 30,000 5 15,000 3 7500 2 3750 1 2000 1 1000 1 500 1 100 1 60 1 50 1 30 1 25 1 15 1 10 1 5 1 2.5 1 Standby Mode Performing One−Shot Conversion t18 + 256 x τCLKIN DRDY DIN STANDBY RDATA WAKEUP DOUT STANDBY Settled Data Figure 20. One-Shot Conversions Using the STANDBY Command New VIN VIN = AINP − AINN DRDY DIN DOUT Old VIN Old VIN Data Mix of Old and New VIN Data Fully Settled New VIN Data RDATA Settled Data Figure 21. Step Change on VIN while Continuously Converting for Data Rates ≤ 3750SPS 22 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DATA FORMAT CLOCK OUTPUT (D0/CLKOUT) The ADS1255/6 output 24 bits of data in Binary Two’s Complement format. The LSB has a weight of 2VREF/(PGA(223 − 1)). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 16 summarizes the ideal output codes for different input signals. The clock output pin can be used to clock another device, such as a microcontroller. This clock can be configured to operate at frequencies of fCLKIN, fCLKIN/2, or fCLKIN/4 using CLK1 and CLK0 in the ADCON register. Note that enabling the output clock and driving an external load will increase the digital power dissipation. Standby mode does not affect the clock output status. That is, if Standby is enabled, the clock output will continue to run during Standby mode. If the clock output function is not needed, it should be disabled by writing to the ADCON register after power-up or reset. Table 16. Ideal Output Code vs Input Signal INPUT SIGNAL VIN (AINP − AINN) ) 2V REF w PGA 7FFFFFh ) 2V REF 000001h PGA(2 23 * 1) 0 000000h * 2V REF FFFFFFh PGA(2 23 * 1) v (1) ǒ * 2V REF 2 23 PGA 2 23 * 1 IDEAL OUTPUT CODE(1) Ǔ 800000h Excludes effects of noise, INL, offset, and gain errors. CLOCK GENERATION The master clock source for the ADS1255/6 can be provided using an external crystal or clock generator. When the clock is generated using a crystal, external capacitors must be provided to ensure start-up and a stable clock frequency, as shown in Figure 22. Any crystal should work with the ADS1255/6. Table 17 lists two crystals that have been verified to work. Long leads should be minimized with the crystal placed close to the ADS1255/6 pins. For information on ceramic resonators, see application note SBAA104, Using Ceramic Resonators with the ADS1255/6, available for download at www.ti.com. GENERAL-PURPOSE DIGITAL I/O (D0-D3) The ADS1256 has 4 pins dedicated for digital I/O and the ADS1255 has 2 digital I/O pins. All of the digital I/O pins are individually configurable as either inputs or outputs through the IO register. The DIR bits of the IO register define whether each pin is an input or output, and the DIO bits control the status of the pins. Reading back the DIO register shows the state of the digital I/O pins, whether they are configured as inputs or outputs by the DIR bits. When digital I/O pins are configured as inputs, the DIO register is used to read the state of these pins. When configured as outputs, DIO sets the output value. On the ADS1255, the digital I/O pins D2 and D3 do not exist and the settings of the IO register bits that control operation of D2 and D3 have no effect on that device. During Standby and Power-Down modes, the GPIO remain active. If configured as outputs, they continue to drive the pins. If configured as inputs, they must be driven (not left floating) to prevent excess power dissipation. The digital I/O pins are set as inputs after power-up or a reset, except for D0/CLKOUT, which is enabled as a clock output. If the digital I/O pins are not used, either leave them as inputs tied to ground or configure them as outputs. This prevents excess power dissipation. C1 XTAL1/CLKIN Crystal C2 XTAL2 C1, C2: 5pF to 20pF Figure 22. Crystal Connection Table 17. Sample Crystals MANUFACTURER FREQUENCY PART NUMBER Citizen 7.68MHz CIA/53383 ECS 8.0MHz ECS-80-5-4 When using a crystal, neither the XTAL1/CLKIN nor XTAL2 pins can be used to drive any other logic. If other devices need a clock source, the D0/CLKOUT pin is available for this function. When using an external clock generator, supply the clock signal to XTAL1/CLKIN and leave XTAL2 floating. Make sure the external clock generator supplies a clean clock waveform. Overshoot and glitches on the clock will degrade overall performance. 23 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 CALIBRATION where α and β vary with data rate settings shown in Table 18 along with the ideal values (assumes perfect analog performance) for OFC and FSC. OFC is a Binary Two’s Complement number that can range from −8,388,608 to 8,388,607, while FSC is unipolar ranging from 0 to 16,777,215. Offset and gain errors can be minimized using the ADS1255/6 onboard calibration circuitry. Figure 23 shows the calibration block diagram. Offset errors are corrected with the Offset Calibration (OFC) register and, likewise, full-scale errors are corrected with the Full-Scale Calibration (FSC) register. Each of these registers is 24-bits and can be read from or written to. The ADS1255/6 supports both self-calibration and system calibration for any PGA setting using a set of five commands: SELFOCAL, SELFGCAL, SELFCAL, SYSOCAL, and SYSGCAL. Calibration can be done at any time, though in many applications the ADS1255/6 drift performance is low enough that a single calibration is all that is needed. DRDY goes high when calibration begins and remains so until settled data is ready afterwards. There is no need to discard data after a calibration. It is strongly recommended to issue a self-calibration command after power-up when the reference has stabilized. After a reset, the ADS1255/6 performs self-calibration. Calibration must be performed whenever the data rate changes and should be performed when the buffer configuration or PGA changes. VREFP VREFN AINP Analog Modulator PGA AINN Digital Filter Σ X OFC Register FSC Register Output Figure 23. Calibration Block Diagram The output of the ADS1255/6 after calibration is shown in Equation 3. Output + ǒPGA2V · V REF IN Ǔ * OFC a FSC ·b (3) Table 18. Calibration Values for Different Data Rate Settings 24 DATA RATE (SPS) α β IDEAL OFC IDEAL FSC 30,000 400000H 1.8639 000000H 44AC08H 15,000 400000H 1.8639 000000H 44AC08H 7500 400000H 1.8639 000000H 44AC08H 3750 400000H 1.8639 000000H 44AC08H 2000 3C0000H 1.7474 000000H 494008H 1000 3C0000H 1.7474 000000H 494008H 500 3C0000H 1.7474 000000H 494008H 100 4B0000H 2.1843 000000H 3A99A0H 60 3E8000H 1.8202 000000H 4651F3H 50 4B0000H 2.1843 000000H 3A99A0H 30 3E8000H 1.8202 000000H 4651F3H 25 4B0000H 2.1843 000000H 3A99A0H 15 3E8000H 1.8202 000000H 4651F3H 10 5DC000H 2.7304 000000H 2EE14CH 5 5DC000H 2.7304 000000H 2EE14CH 2.5 5DC000H 2.7304 000000H 2EE14CH ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Self-Calibration Table 20. Self Gain Calibration Timing Self-calibration corrects internal offset and gain errors. During self-calibration, the appropriate calibration signals are applied internally to the analog inputs. SELFOCAL performs a self offset calibration. The analog inputs AINP and AINN are disconnected from the signal source and connected to AVDD/2. See Table 19 for the time required for self offset calibration for the different data rate settings. As with most of the ADS1255/6 timings, the calibration time scales directly with fCLKIN. Self offset calibration updates the OFC register. Table 19. Self Offset and System Offset Calibration Timing DATA RATE (SPS) SELF OFFSET CALIBRATION AND SYSTEM OFFSET CALIBRATION TIME 30,000 387μs 15,000 453μs 7500 587μs 3750 853μs 2000 1.3ms 1000 2.3ms 500 4.3ms 100 20.3ms 60 33.7ms 50 40.3ms 30 67.0ms 25 80.3ms 15 133.7ms 10 200.3ms 5 400.3ms 2.5 800.3ms NOTE: For fCLKIN = 7.68MHz. SELFGCAL performs a self gain calibration. The analog inputs AINP and AINN are disconnected from the signal source and AINP is connected internally to VREFP while AINN is connected to VREFN. Self gain calibration can be used with any PGA setting, and the ADS1255/6 has excellent gain calibration even for the higher PGA settings, as shown in the Typical Characteristics section. Using the buffer will limit the common-mode range of the reference inputs during self gain calibration since they will be connected to the buffer inputs and must be within the specified analog input range. When the voltage on VREFP or VREFN exceeds the buffer analog input range (AVDD – 2.0V), the buffer must be turned off during self gain calibration. Otherwise, use system gain calibration or write the gain coefficients directly to the FSC register. Table 20 shows the time required for self gain calibration for the different data rate and PGA settings. Self gain calibration updates the FSC register. PGA SETTING 4 8 DATA RATE (SPS) 1 2 30,000 417μs 417μs 451μs 517μs 651μs 15,000 484μs 484μs 484μs 551μs 551μs 7500 617μs 617μs 617μs 617μs 751μs 3750 884 2000 1.4ms 1000 2.4ms 500 4.5ms 100 21.0ms 60 34.1ms 50 41.7ms 30 67.8ms 25 83.0ms 15 135.3ms 10 207.0ms 5 413.7ms 2.5 827.0ms 16, 32, 64 NOTE: For fCLKIN = 7.68MHz. SELFCAL performs first a self offset and then a self gain calibration. The analog inputs are disconnected from the from the signal source during self-calibration. When using the input buffer with self-calibration, make sure to observe the common-mode range of the reference inputs as described above. Table 21 shows the time required for self-calibration for the different data rate settings. Self-calibration updates both the OFC and FSC registers. Table 21. Self-Calibration Timing PGA SETTING 4 8 DATA RATE (SPS) 1 2 30,000 596μs 596μs 692μs 696μs 15,000 696μs 696μs 696μs 762μs 896μs 7500 896μs 896μs 896μs 896μs 1029μs 3750 1.3ms 2000 2.0ms 1000 3.6ms 500 6.6ms 100 31.2ms 60 50.9ms 50 61.8ms 30 101.3ms 25 123.2ms 15 202.1ms 10 307.2ms 5 613.8ms 2.5 1227.2ms 16, 32, 64 892μs NOTE: For fCLKIN = 7.68MHz. 25 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 System Calibration System calibration corrects both internal and external offset and gain errors using the SYSOCAL and SYSGCAL commands. During system calibration, the appropriate calibration signals must be applied by the user to the inputs. SYSOCAL performs a system offset calibration. The user must supply a zero input differential signal. The ADS1255/6 then computes a value that will nullify the offset in the system. Table 22 shows the time required for system offset calibration for the different data rate settings. Note this timing is the same for the self offset calibration. System offset calibration updates the OFC register. SYSGCAL performs a system gain calibration. The user must supply a full-scale input signal to the ADS1255/6. The ADS1255/6 then computes a value to nullify the gain error in the system. System gain calibration can correct inputs that are 80% of the full-scale input voltage and larger. Make sure not to exceed the full-scale input voltage when using system gain calibration. Table 22 shows the time required for system gain calibration for the different data rate settings. System gain calibration updates the FSC register. Table 22. System Gain Calibration Timing DATA RATE (SPS) 30,000 SYSTEM GAIN CALIBRATION TIME 417μs 15,000 484μs 7500 617μs 3750 884μs 2000 1.4ms 1000 2.4ms 500 4.4ms 100 20.4ms 60 33.7ms 50 40.4ms 30 67.0ms 25 80.4ms 15 133.7ms 10 200.4ms 5 400.4ms 2.5 800.4ms NOTE: For fCLKIN = 7.68MHz. Auto-Calibration Auto-calibration can be enabled (ACAL bit in STATUS register) to have the ADS1255/6 automatically initiate a self-calibration at the completion of a write command (WREG) that changes the data rate, PGA setting, or Buffer status. 26 SERIAL INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT, and allows a controller to communicate with the ADS1255/6. The programmable functions are controlled using a set of on-chip registers. Data is written to and read from these registers via the serial interface The DRDY output line is used as a status signal to indicate when a conversion has been completed. DRDY goes low when new data is available. The Timing Specification shows the timing diagram for interfacing to the ADS1255/6. CHIP SELECT (CS) The chip select (CS) input allows individual selection of a ADS1255/6 device when multiple devices share the serial bus. CS must remain low for the duration of the serial communication. When CS is taken high, the serial interface is reset and DOUT enters a high impedance state. CS may be permanently tied low. SERIAL CLOCK (SCLK) The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and DOUT pins into and out of the ADS1255/6. Even though the input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. If SCLK is held low for 32 DRDY periods, the serial interface will reset and the next SCLK pulse will start a new communication cycle. This timeout feature can be used to recover communication when a serial interface transmission is interrupted. A special pattern on SCLK will reset the chip; see the RESET section for more details on this procedure. When the serial interface is idle, hold SCLK low. DATA INPUT (DIN) AND DATA OUTPUT (DOUT) The data input pin (DIN) is used along with SCLK to send data to the ADS1255/6. The data output pin (DOUT) along with SCLK is used to read data from the ADS1255/6. Data on DIN is shifted into the part on the falling edge of SCLK while data is shifted out on DOUT on the rising edge of SCLK. DOUT is high impedance when not in use to allow DIN and DOUT to be connected together and be driven by a bi-directional bus. Note: the RDATAC command must not be issued while DIN and DOUT are connected together. ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DATA READY (DRDY) STANDBY MODE The DRDY output is used as a status signal to indicate when conversion data is ready to be read. DRDY goes low when new conversion data is available. It is reset high when all 24 bits have been read back using Read Data (RDATA) or Read Data Continuous (RDATAC) command. It also goes high when the new conversion data is being updated. Do not retrieve during this update period as the data is invalid. If data is not retrieved, DRDY will only be high during the update time as shown in Figure 24. The standby mode shuts down all of the analog circuitry and most of the digital features. The oscillator continues to run to allow for fast wakeup. If enabled, clock output D0/CLKOUT will also continue to run during during Standby mode. To enter Standby mode, issue the STANDBY command. To exit Standby mode, issue the WAKEUP command. DRDY will stay high after exiting Standby mode until valid data is ready. Standby mode can be used to perform one-shot conversions; see Settling Time Using One-Shot Mode section for more details. Data Updating DRDY Figure 24. DRDY with No Data Retreival After changing the PGA, data rate, buffer status, writing to the OFC or FSC registers, and enabling or disabling the sensor detect circuitry, perform a synchronization operation to force DRDY high. It will stay high until valid data is ready. If auto-calibration is enabled (by setting the ACAL bit in the STATUS register), DRDY will go low after the self-calibration is complete and new data are valid. Exiting from Reset, Synchronization, Standby or Power-Down mode will also force DRDY high. DRDY will go low as soon as valid data are ready. SYNCHRONIZATION Synchronization of the ADS1255/6 is available to coordinate the A/D conversion with an external event and also to speed settling after an instantaneous change on the analog inputs (see Conversion Time using Synchronization section). Synchronization can be achieved either using the SYNC/PDWN pin or with the SYNC command. To use the SYNC/PDWN pin, take it low and then high, making sure to meet timing specification t16 and t16B. Synchronization occurs after SYNC/PDWN is taken high. No communication is possible on the serial interface while SYNC/PDWN is low. If the SYNC/PDWN pin is held low for 20 DRDY periods the ADS1255/6 will enter Power-Down mode. To synchronize using the SYNC command, first shift in all eight bits of the SYNC command. This stops the operation of the ADS1255/6. When ready to synchronize, issue the WAKEUP command. Synchronization occurs on the first rising edge of the master clock after the first SCLK used to shift in the WAKEUP command. After a synchronization operation, either with the SYNC/PDWN pin or the SYNC command, DRDY stays high until valid data is ready. POWER-DOWN MODE Holding the SYNC/PDWN pin low for 20 DRDY cycles activates the Power-Down mode. During Power-Down mode, all circuitry is disabled including the oscillator and the clock output. To exit Power-Down mode, take the SYNC/PDWN pin high. Upon exiting from Power-Down mode, the ADS1255/6 crystal oscillator typically requires 30ms to wake up. If using an external clock source, 8192 CLKIN cycles are needed before conversions begin. RESET There are three methods to reset the ADS1255/6: the RESET input pin, RESET command, and a special SCLK reset pattern. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect after all eight bits have been shifted into DIN. Afterwards, the reset releases automatically. The ADS1255/6 can also be reset with a special pattern on SCLK (see Figure 2). Reset occurs on the falling edge of the last SCLK edge in the pattern. After performing the operation, the reset releases automatically. On reset, the configuration registers are initialized to their default state except for the CLK0 and CLK1 bits in the ADCON register that control the D0/CLKOUT pin. These bits are only initialized to the default state when RESET is performed using the RESET pin. After releasing from RESET, self-calibration is performed, regardless of the reset method or the state of the ACAL bit before RESET. POWER-UP All of the configuration registers are initialized to their default state at power-up. A self-calibration is then performed automatically. For the best performance, it is strongly recommended to perform an additional self-calibration by issuing the SELFCAL command after the power supplies and voltage reference have had time to settle to their final values. 27 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 APPLICATIONS INFORMATION GENERAL RECOMMENDATIONS The ADS1255 and ADS1256 are very high-resolution A/D converters. Getting the optimal performance from them requires careful attention to their support circuitry and printed circuit board (PCB) design. Figure 25 shows the basic connections for the ADS1255. It is recommended to use a single ground plane for both the analog and digital supplies. This ground plane should be shared with the bypass capacitors and analog conditioning circuits. However, avoid using this ground plane for noisy digital components such as microprocessors. If a split ground plane is used with the ADS1255/6, make sure the analog and digital planes are tied together. There should not be a voltage difference between the ADS1255/6 analog and digital ground pins (AGND and DGND). As with any precision circuit, use good supply bypassing techniques. A smaller value ceramic capacitor in parallel with a larger value tantalum or a larger value low-voltage ceramic capacitor works well. Place the capacitors, in particular the ceramic ones, close to the supply pins. Run the digital logic off as low of voltage as possible. This helps reduce coupling back to the analog inputs. Avoid ringing on the digital inputs. Small resistors (≈100Ω) in series with the digital pins can help by controlling the trace impedance. When not using the RESET or SYNC/PDWN inputs, tie directly to the ADS1255/6 DVDD pin. +5V 10μF 47μF 0.1μF 1 AVDD D1 20 2 AGND D0/CLKOUT 19 3 VREFN SCLK 18 100pF 4 VREFP DIN 17 49.9Ω 5 AINCOM DOUT 16 6 AIN0 DRDY 15 100pF 7 AIN1 CS 14 301Ω VINP VINN 0.1μF 301Ω +3.3V 10μF Often times, only a simple RC filter (as shown in Figure 25) is needed on the inputs. This circuit limits the high-frequency noise near the modulator frequency; see the Frequency Response section. Avoid low-grade dielectrics for the capacitors to minimize temperature variations and leakage. Keep the input traces as short as possible and place the components close to the input pins. When using the ADS1256, make sure to filter all the input channels being used. ADS1255 0.1μF 49.9Ω 2.5V(1) Pay special attention to the reference and analog inputs. These are the most critical circuits. On the voltage reference inputs, bypass with low equivalent series resistance (ESR) capacitors. Make these capacitors as large as possible to maximize the filtering on the reference. With the outstanding performance of the ADS1255/6, it is easy for the voltage reference to limit overall performance if not carefully selected. When using a stand-alone reference, make sure it is very low noise, very low drift, and capable of driving the ADS1255/6 reference inputs. For voltage references not suited for driving the ADS1255/6 directly (for example, high output impedance references or resistive voltage dividers), use the recommended buffer circuit shown in Figure 26. Ratiometric measurements, where the input signal and reference track each other, are somewhat less sensitive, but verify the reference signal is clean. 8 SYNC/PDWN 9 RESET XTAL2 12 10 DVDD DGND 11 100Ω 100Ω XTAL1/CLKIN 13 0.1μF NOTE: (1) See Figure 26 for the recommended voltage reference buffer. Figure 25. ADS1255 Basic Connections 28 100Ω 18pF 7.68MHz 18pF ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 +5V 0.1μF OPA350 10kΩ 2.5V Input 47μF 0.1μF 100μF To VREFP Pin 4 of the ADS1255/6 1μF Figure 26. Recommended Voltage Reference Buffer Circuit DIGITAL INTERFACE CONNECTIONS The ADS1255/6 5V tolerant SPI-, QSPI™, and MICROWIRE™-compatible interface easily connects to a wide variety of microcontrollers. Figure 27 shows the basic connection to TI’s MSP430 family of low-power microcontrollers. Figure 28 shows the connection to microcontrollers with an SPI interface like TI’s MSC12xx family or the 68HC11 family. Note that the MSC12xx includes a high-resolution A/D converter; the ADS1255/6 can be used to add additional channels of measurement or provide higher-speed conversions. Finally, Figure 29 shows how to connect the ADS1255/6 to an 8xC51 UART in serial mode 0 in a 2-wire configuration. Avoid using the continuous read mode (RDATAC) when DIN and DOUT are connected together. ADS1255 ADS1256 ADS1255 ADS1256 MSC12xx or 68HC11 DIN MOSI DOUT MISO DRDY INT SCLK SCK CS(1) IO (1) CS may be tied low. Figure 28. Connection to Microcontrollers with an SPI Interface MSP430 DIN P1.3 DOUT P1.2 DRDY P1.0 SCLK P1.6 CS(1) P1.4 (1) CS may be tied low. Figure 27. Connection to MSP430 Microcontroller ADS1255 ADS1256 8xC51 DIN P3.0/RXD DOUT DRDY SCLK P3.1xTXD CS DGND Figure 29. Connection to 8xC51 Microcontroller UART with a 2-Wire Interface 29 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 REGISTER MAP The operation of the ADS1255/6 is controlled through a set of registers. Collectively, the registers contain all the information needed to configure the part, such as data rate, multiplexer settings, PGA setting, calibration, etc., and are listed in Table 23. Table 23. Register Map ADDRESS REGISTER RESET VALUE 00h STATUS x1H ID3 ID2 01h MUX 01H PSEL3 PSEL2 02h ADCON 20H 0 CLK1 03h DRATE F0H DR7 DR6 04h IO E0H DIR3 05h OFC0 xxH 06h OFC1 xxH 07h OFC2 08h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 ID1 ID0 PSEL1 PSEL0 CLK0 DR5 DIR2 OFC07 OFC15 xxH FSC0 09h 0Ah BIT 0 ORDER ACAL BUFEN DRDY NSEL3 NSEL2 NSEL1 NSEL0 SDCS1 SDCS0 PGA2 PGA1 PGA0 DR4 DR3 DR2 DR1 DR0 DIR1 DIR0 DIO3 DIO2 DIO1 DIO0 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 xxH FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 FSC1 xxH FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 FSC2 xxH FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 STATUS : STATUS REGISTER (ADDRESS 00h) Reset Value = x1h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID ID ID ID ORDER ACAL BUFEN DRDY Bits 7-4 ID3, ID2, ID1, ID0 Factory Programmed Identification Bits (Read Only) Bit 3 ORDER: Data Output Bit Order 0 = Most Significant Bit First (default) 1 = Least Significant Bit First Input data is always shifted in most significant byte and bit first. Output data is always shifted out most significant byte first. The ORDER bit only controls the bit order of the output data within the byte. Bit 2 ACAL: Auto-Calibration 0 = Auto-Calibration Disabled (default) 1 = Auto-Calibration Enabled When Auto-Calibration is enabled, self-calibration begins at the completion of the WREG command that changes the PGA (bits 0-2 of ADCON register), DR (bits 7-0 in the DRATE register) or BUFEN (bit 1 in the STATUS register) values. Bit 1 BUFEN: Analog Input Buffer Enable 0 = Buffer Disabled (default) 1 = Buffer Enabled Bit 0 DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin. 30 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 MUX : Input Multiplexer Control Register (Address 01h) Reset Value = 01h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 Bits 7-4 PSEL3, PSEL2, PSEL1, PSEL0: Positive Input Channel (AINP) Select 0000 = AIN0 (default) 0001 = AIN1 0010 = AIN2 (ADS1256 only) 0011 = AIN3 (ADS1256 only) 0100 = AIN4 (ADS1256 only) 0101 = AIN5 (ADS1256 only) 0110 = AIN6 (ADS1256 only) 0111 = AIN7 (ADS1256 only) 1xxx = AINCOM (when PSEL3 = 1, PSEL2, PSEL1, PSEL0 are “don’t care”) NOTE: When using an ADS1255 make sure to only select the available inputs. Bits 3-0 NSEL3, NSEL2, NSEL1, NSEL0: Negative Input Channel (AINN)Select 0000 = AIN0 0001 = AIN1 (default) 0010 = AIN2 (ADS1256 only) 0011 = AIN3 (ADS1256 only) 0100 = AIN4 (ADS1256 only) 0101 = AIN5 (ADS1256 only) 0110 = AIN6 (ADS1256 only) 0111 = AIN7 (ADS1256 only) 1xxx = AINCOM (when NSEL3 = 1, NSEL2, NSEL1, NSEL0 are “don’t care”) NOTE: When using an ADS1255 make sure to only select the available inputs. ADCON: A/D Control Register (Address 02h) Reset Value = 20h Bit 7 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 CLK1 CLK0 SDCS1 SDCS0 PGA2 PGA1 PGA0 Reserved, always 0 (Read Only) Bits 6-5 CLK1, CLK0: D0/CLKOUT Clock Out Rate Setting 00 = Clock Out OFF 01 = Clock Out Frequency = fCLKIN (default) 10 = Clock Out Frequency = fCLKIN/2 11 = Clock Out Frequency = fCLKIN/4 When not using CLKOUT, it is recommended that it be turned off. These bits can only be reset using the RESET pin. Bits 4-2 SDCS1, SCDS0: Sensor Detect Current Sources 00 = Sensor Detect OFF (default) 01 = Sensor Detect Current = 0.5μA 10 = Sensor Detect Current = 2μA 11 = Sensor Detect Current = 10μA The Sensor Detect Current Sources can be activated to verify the integrity of an external sensor supplying a signal to the ADS1255/6. A shorted sensor produces a very small signal while an open-circuit sensor produces a very large signal. Bits 2-0 PGA2, PGA1, PGA0: Programmable Gain Amplifier Setting 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 64 31 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DRATE: A/D Data Rate (Address 03h) Reset Value = F0h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 The 16 valid Data Rate settings are shown below. Make sure to select a valid setting as the invalid settings may produce unpredictable results. Bits 7-0 DR[7: 0]: Data Rate Setting(1) 11110000 = 30,000SPS (default) 11100000 = 15,000SPS 11010000 = 7,500SPS 11000000 = 3,750SPS 10110000 = 2,000SPS 10100001 = 1,000SPS 10010010 = 500SPS 10000010 = 100SPS 01110010 = 60SPS 01100011 = 50SPS 01010011 = 30SPS 01000011 = 25SPS 00110011 = 15SPS 00100011 = 10SPS 00010011 = 5SPS 00000011 = 2.5SPS (1) for fCLKIN = 7.68MHz. Data rates scale linearly with fCLKIN. I/O: GPIO Control Register (Address 04H) Reset Value = E0h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DIR3 DIR2 DIR1 DIR0 DIO3 DIO2 DIO1 DIO0 The states of these bits control the operation of the general-purpose digital I/O pins. The ADS1256 has 4 I/O pins: D3, D2, D1, and D0/CLKOUT. The ADS1255 has two digital I/O pins: D1 and D0/CLKOUT. When using an ADS1255, the register bits DIR3, DIR2, DIO3, and DIO2 can be read from and written to but have no effect. Bit 7 DIR3, Digital I/O Direction for Digital I/O Pin D3 (used on ADS1256 only) 0 = D3 is an output 1 = D3 is an input (default) Bit 6 DIR2, Digital I/O Direction for Digital I/O Pin D2 (used on ADS1256 only) 0 = D2 is an output 1 = D2 is an input (default) Bit 5 DIR1, Digital I/O Direction for Digital I/O Pin D1 0 = D1 is an output 1 = D1 is an input (default) Bit 4 DIR0, Digital I/O Direction for Digital I/O Pin D0/CLKOUT 0 = D0/CLKOUT is an output (default) 1 = D0/CLKOUT is an input Bits 3-0 DI0[3:0]: Status of Digital I/O Pins D3, D2, D1, D0/CLKOUT Reading these bits will show the state of the corresponding digital I/O pin, whether if the pin is configured as an input or output by DIR3-DIR0. When the digital I/O pin is configured as an output by the DIR bit, writing to the corresponding DIO bit will set the output state. When the digital I/O pin is configured as an input by the DIR bit, writing to the corresponding DIO bit will have no effect. When DO/CLKOUT is configured as an output and CLKOUT is enabled (using CLK1, CLK0 bits in the ADCON register), writing to DIO0 will have no effect. 32 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 OFC0: Offset Calibration Byte 0, least significant byte (Address 05h) Reset value depends on calibration results. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 OFC1: Offset Calibration Byte 1 (Address 06h) Reset value depends on calibration results. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 OFC2: Offset Calibration Byte 2, most significant byte (Address 07h) Reset value depends on calibration results. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 FSC0: Full−scale Calibration Byte 0, least significant byte (Address 08h) Reset value depends on calibration results. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 FSC1: Full−scale Calibration Byte 1 (Address 09h) Reset value depends on calibration results. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 FSC2: Full−scale Calibration Byte 2, most significant byte (Address 0Ah) Reset value depends on calibration results. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 33 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 COMMAND DEFINITIONS The commands summarized in Table 24 control the operation of the ADS1255/6. All of the commands are stand-alone except for the register reads and writes (RREG, WREG) which require a second command byte plus data. Additional command and data bytes may be shifted in without delay after the first command byte. The ORDER bit in the STATUS register sets the order of the bits within the output data. CS must stay low during the entire command sequence. Table 24. Command Definitions COMMAND DESCRIPTION WAKEUP Completes SYNC and Exits Standby Mode 1ST COMMAND BYTE 0000 0000 (00h) (01h) RDATA Read Data 0000 0001 RDATAC Read Data Continuously 0000 0011 (03h) SDATAC Stop Read Data Continuously 0000 1111 (0Fh) 2ND COMMAND BYTE RREG Read from REG rrr 0001 rrrr (1xh) 0000 nnnn WREG Write to REG rrr 0101 rrrr (5xh) 0000 nnnn SELFCAL Offset and Gain Self-Calibration 1111 0000 (F0h) SELFOCAL Offset Self-Calibration 1111 0001 (F1h) SELFGCAL Gain Self-Calibration 1111 0010 (F2h) SYSOCAL System Offset Calibration 1111 0011 (F3h) SYSGCAL System Gain Calibration 1111 0100 (F4h) SYNC Synchronize the A/D Conversion 1111 1100 (FCh) STANDBY Begin Standby Mode 1111 1101 (FDh) RESET Reset to Power-Up Values 1111 1110 (FEh) WAKEUP Completes SYNC and Exits Standby Mode 1111 1111 (FFh) NOTE: n = number of registers to be read/written − 1. For example, to read/write three registers, set nnnn = 2 (0010). r = starting register address for read/write commands. RDATA: Read Data Description: Issue this command after DRDY goes low to read a single conversion result. After all 24 bits have been shifted out on DOUT, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new data is being updated. See the Timing Characteristics for the required delay between the end of the RDATA command and the beginning of shifting data on DOUT: t6. DRDY DIN 0000 0001 DOUT MSB Mid−Byte t6 SCLK • •• • •• Figure 30. RDATA Command Sequence 34 LSB ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 RDATAC: Read Data Continuous Description: Issue command after DRDY goes low to enter the Read Data Continuous mode. This mode enables the continuous output of new data on each DRDY without the need to issue subsequent read commands. After all 24 bits have been read, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new data is being updated. This mode may be terminated by the Stop Read Data Continuous command (SDATAC). Because DIN is constantly being monitored during the Read Data Continuous mode for the SDATAC or RESET command, do not use this mode if DIN and DOUT are connected together. See the Timing Characteristics for the required delay between the end of the RDATAC command and the beginning of shifting data on DOUT: t6. DRDY DIN 0000 0011 t6 DOUT 24 Bits 24 Bits Figure 31. RDATAC Command Sequence On the following DRDY, shift out data by applying SCLKs. The Read Data Continuous mode terminates if input_data equals the SDATAC or RESET command in any of the three bytes on DIN. DRDY DIN DOUT input_data input_data input_data MSB Mid−Byte LSB Figure 32. DIN and DOUT Command Sequence During Read Continuous Mode SDATAC: Stop Read Data Continuous Description: Ends the continuous data output mode. (see RDATAC). The command must be issued after DRDY goes low and completed before DRDY goes high. DRDY DIN 000 1111 Figure 33. SDATAC Command Sequence 35 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 RREG: Read from Registers Description: Output the data from up to 11 registers starting with the register address specified as part of the command. The number of registers read will be one plus the second byte of the command. If the count exceeds the remaining registers, the addresses will wrap back to the beginning. 1st Command Byte: 0001 rrrr where rrrr is the address of the first register to read. 2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to read – 1. See the Timing Characteristics for the required delay between the end of the RREG command and the beginning of shifting data on DOUT: t6. DIN 0001 0001 0000 0001 1st Command 2nd Command Byte Byte t6 DOUT MUX ADCON Data Byte Data Byte Figure 34. RREG Command Example: Read Two Registers Starting from Register 01h (multiplexer) WREG: Write to Register Description: Write to the registers starting with the register specified as part of the command. The number of registers that will be written is one plus the value of the second byte in the command. 1st Command Byte: 0101 rrrr where rrrr is the address to the first register to be written. 2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to be written – 1. Data Byte(s): data to be written to the registers. DIN 0101 0011 0000 0001 DRATE Data 1st Command Byte 2nd Command Byte Data Byte IO Data Data Byte Figure 35. WREG Command Example: Write Two Registers Starting from 03h (DRATE) SELFCAL: Self Offset and Gain Calibration Description: Performs a self offset and self gain calibration. The Offset Calibration Register (OFC) and Full-Scale Calibration Register (FSC) are updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete. SELFOCAL: Self Offset Calibration Description: Performs a self offset calibration. The Offset Calibration Register (OFC) is updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete. SELFGCAL: Self Gain Calibration Description: Performs a self gain calibration. The Full-Scale Calibration Register (FSC) is updated with new values after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete. 36 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 SYSOCAL: System Offset Calibration Description: Performs a system offset calibration. The Offset Calibration Register (OFC) is updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete. SYSGCAL: System Gain Calibration Description: Performs a system gain calibration. The Full-Scale Calibration Register (FSC) is updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete. SYNC: Synchronize the A/D Conversion Description: This command synchronizes the A/D conversion. To use, first shift in the command. Then shift in the WAKEUP command. Synchronization occurs on the first CLKIN rising edge after the first SCLK used to shift in the WAKEUP command. DIN 1111 1100 (SYNC) SCLK ••• 0000 0000 (WAKEUP) ••• ••• CLKIN ••• Synchronization Occurs Here Figure 36. SYNC Command Sequence STANDBY: Standby Mode / One-Shot Mode Description: This command puts the ADS1255/6 into a low-power Standby mode. After issuing the STANDBY command, make sure there is no more activity on SCLK while CS is low, as this will interrupt Standby mode. If CS is high, SCLK activity is allowed during Standby mode. To exit Standby mode, issue the WAKEUP command. This command can also be used to perform single conversions (see One-Shot Mode section) . DIN 1111 1101 (STANDBY) 0000 0000 (WAKEUP) SCLK Normal Mode Standby Mode Normal Mode Figure 37. STANDBY Command Sequence WAKEUP: Complete Synchronization or Exit Standby Mode Description: Used in conjunction with the SYNC and STANDBY commands. Two values (all zeros or all ones) are available for this command. RESET: Reset Registers to Default Values Description: Returns all registers except the CLK0 and CLK1 bits in the ADCON register to their default values. This command will also stop the Read Continuous mode: in this case, issue the RESET command after DRDY goes low. 37 ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Revision History DATE REV PAGE SECTION 09/12/13 K 20 Settling Time 09/12/13 K 22 09/12/13 K 22 09/12/13 K 26 Auto−Calibration Changed ADCON to STATUS 09/12/13 K 27 Data Ready Changed ADCON to STATUS 09/12/13 K 35 RDATAC: Read Data Continuous Changed STOPC to SDATAC. 8/08/08 J 7 Timing 8/08/08 J 28 Synchronization 11/01/06 I 23 Clock Generation 11/01/06 I 23 Sample Crystals Table Settling Time Using One One−Shot Shot Mode DESCRIPTION Added note to Table 13 Added new text, (causing text to shift in the 2 column format) and updated t18 settling time. Changed Figure 20 t18 settling time. Added SYNC/PWDN to CLK timing specification (t16B of Figure 3). Updated second paragraph: changed second and third sentences. Changed first paragraph: changed fourth sentence and added fifth sentence. Changed table title. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 38 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS1255IDBR ACTIVE SSOP DB 20 1000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1255IDB ADS1255IDBT ACTIVE SSOP DB 20 250 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1255IDB ADS1255IDBTG4 ACTIVE SSOP DB 20 250 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1255IDB ADS1256IDBR ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1256IDB ADS1256IDBRG4 ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1256IDB ADS1256IDBT ACTIVE SSOP DB 28 250 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1256IDB ADS1256IDBTG4 ACTIVE SSOP DB 28 250 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1256IDB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of