ADS1259BIPW

ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Industrial, 14kSPS, 24-Bit Analog-to-Digital Converter with Low-Drift Reference Check for Samples: ADS1259 FEATURES DESCRIPTION • • • The ADS1259 is a high-linearity, low-drift, 24-bit, analog-to-digital converter (ADC) designed for the needs of industrial process control, precision instrumentation, and other exacting applications. Combined with a signal amplifier (such as the PGA280), a high-resolution, high-accuracy measurement system is formed that is capable of digitizing a wide range of signals. 1 23 • • • • • • • • • 24 Bits, No Missing Codes Output Data Rates From 10 To 14kSPS High Performance: – INL: 0.4ppm – Reference Drift: 2ppm/°C – Gain Drift: 0.5ppm/°C – Offset Drift: 0.05μV/°C – Noise: 0.7μVRMS at 60SPS Simultaneous 50/60Hz Rejection at 10SPS Single-Cycle Settling Internal Oscillator Out-of-Range Detection Readback Data Integrity by Checksum and Redundant Data Read Capability SPI™-Compatible Interface Analog Supply: +5V or ±2.5V Digital Supply: +2.7V to +5V Low Power: 13mW APPLICATIONS • • • AINP VREFP VREFN REFOUT DS Modulator AINN SYNCOUT 2.5V Reference fCLK/8 Programmable Digital Filter Calibration Engine DVDD Clock Generator XTAL2 Dissipating only 13mW in operation, the ADS1259 can be powered down, dissipating less than 25μW. The ADS1259 is offered in a TSSOP-20 package and is fully specified from –40°C to +105°C. START SCLK DIN CS DGND RELATED PRODUCTS DRDY DOUT ADS1259 AVSS XTAL1/CLKIN RESET/PWDN Control and Serial Interface Out-of-Range Detection The ADS1259 also provides an integrated low-noise, very low drift 2.5V reference. The on-chip oscillator, an external crystal, or an external clock can by used as the ADC clock source. Data and control communication are handled over a 4MHz, SPI-compatible interface capable of operating with a minimum of three wires. Data integrity is augmented by data bytes checksum and redundant data read capability. Conversions are synchronized either by command or by pin. Industrial Process Control Scientific Instrumentation Test and Measurement AVDD The converter uses a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator that provides outstanding noise and linearity performance. The data rates are programmable up to 14kSPS including 10SPS, 50SPS, and 60SPS that provide excellent normal mode line-cycle rejection. The digital filter can be programmed for a fast settling mode where the conversions settle in a single cycle, or programmed for a high line-cycle rejection mode. A fast responding input over-range detector flags the conversion data if an input over-range should occur. FEATURES PRODUCT 24-bit ADC with integrated PGA ADS1256 Wide-range PGA PGA280 High-precision PGA; G = 1, 10, 100, 1000 PGA204 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS1259 MIN MAX UNIT AVDD to AVSS –0.3 +5.5 V AVSS to DGND –2.8 +0.3 V DVDD to DGND –0.3 +5.5 V Input current, momentary –100 +100 mA Input current, continuous –10 +10 mA V Analog input voltage to DGND AVSS – 0.3 AVDD + 0.3 Digital input voltage to DGND –0.3 DVDD + 0.3 V +150 °C Maximum junction temperature Operating temperature range –40 +125 °C Storage temperature range –60 +150 °C (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS Minimum/maximum specifications are at TA = –40°C to +105°C. Typical specifications are at TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 7.3728MHz, VREF = 2.5V, and fDATA = 60SPS, unless otherwise noted. ADS1259 PARAMETER TEST CONDITIONS MIN TYP ADS1259B MAX MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage range (FSR) VIN = (AINP – AINN) Absolute input voltage (AINP, AINN to DGND) ±VREF AVSS – 0.1 ±VREF AVDD + 0.1 AVSS – 0.1 V AVDD + 0.1 V Differential input impedance 120 120 kΩ Common-mode input impedance 500 500 kΩ SYSTEM PERFORMANCE Resolution No missing codes Data rate (fDATA) 24 24 10 14400 Bits 10 14400 SPS (1) ±0.0003 ±0.001 ±0.00004 (2) ±0.0003 %FSR Offset error ±40 ±250 ±40 ±250 μV Offset error after calibration (3) ±1 0.05 0.25 μV/°C ±0.05 ±0.5 % 2.5 ppm/°C Integral nonlinearity Offset drift (4) Best fit method TA = –40°C to +105°C Gain error (5) Gain error after calibration (3) Gain drift (4) Common-mode rejection Noise 0.05 0.25 ±0.05 ±0.5 ±0.0002 TA = –40°C to +105°C Normal mode rejection ±1 0.5 μV ±0.0002 2.5 0.5 % See Figure 42 60Hz, ac (6) 100 See Table 1 120 100 0.7 120 dB 0.7 μV AVDD, AVSS power-supply rejection 60Hz, ac (6) 85 95 85 95 dB DVDD power-supply rejection 60Hz, ac (6) 85 110 85 110 dB OUT-OF-RANGE DETECTION Threshold (7) Level ±105 ±105 %FSR Accuracy ±0.5 ±0.5 %FSR VOLTAGE REFERENCE INPUTS Reference input range (VREF) VREF = (VREFP – VREFN) 0.5 2.5 AVDD – AVSS + 200mV 0.5 2.5 AVDD – AVSS + 200mV V Negative reference absolute input (VREFN to DGND) AVSS – 100mV VREFP – 0.5 AVSS – 100mV VREFP – 0.5 V Positive reference absolute input (VREFP to DGND) VREFN + 0.5 AVDD + 100mV VREFN + 0.5 AVDD + 100mV V 200nA + 60nA/V 200nA + 60nA/V Internal or external clock 0.2 0.2 nA/°C VREFOUT = (REFOUT – AVSS) 2.5 2.5 V Average reference input current (8) Average reference input current drift INTERNAL VOLTAGE REFERENCE Reference output voltage Accuracy Temperature drift ±0.4 TA = +25°C (4) TA = –40°C to +105°C 10 40 4 TA = 0°C to +85°C 2 –10 Drive current sink and source Load regulation 10 –10 ±0.2 % 12 ppm/°C 5 ppm/°C 10 mA (9) μV/mA 10 10 Turn-on settling time (10) ±0.001% settling 1 1 s Long-term stability 0 to 1000 hours 70 70 ppm/1000hr 30 30 ppm Thermal hysteresis (11) (1) (2) (3) (4) (5) (6) SPS = samples per second. Shaded cells indicate improved specifications of the ADS1259B. Calibration accuracy is on the level of noise (signal and ADC), reduced by the effect of 16 reading averaging. Reference drift specified by design and final production test. Drift calculated over the specified temperature range using box method. Excludes internal reference error. fDATA = 14.4kSPS. Placing a notch of the digital filter at 60Hz (setting fDATA = 10SPS or 60SPS) further improves the common-mode rejection and power-supply rejection of this input frequency. (7) Absolute input voltage range for out-of-range specification: AVSS + 150mV ≤ AINP or AINN ≤ AVDD – 150mV. (8) Over the range: AVSS ≤ VREFP or VREFN ≤ AVDD. For reference voltage exceeding AVDD or AVSS, input current = 150nA/10mV. (9) Limit the reference output current to ±10mA. (10) CREFOUT = 1μF, CREFIN = 1μF. (11) See the Thermal Hysteresis section. Copyright © 2009–2011, Texas Instruments Incorporated 3 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications are at TA = –40°C to +105°C. Typical specifications are at TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 7.3728MHz, VREF = 2.5V, and fDATA = 60SPS, unless otherwise noted. ADS1259 PARAMETER TEST CONDITIONS MIN TYP ADS1259B MAX MIN TYP MAX UNIT CLOCK SOURCE (fCLK) Nominal frequency 7.3728 Accuracy ±0.2 ±2 2 7.3728 8 Frequency range 0.1 7.3728 Duty cycle 40 Internal oscillator Frequency range Crystal oscillator Start-up time (12) 7.3728 MHz ±0.2 ±2 % 2 7.3728 8 MHz 8 0.1 7.3728 8 MHz 60 40 60 % 20 20 ms External clock DIGITAL INPUT/OUTPUT (DVDD = 2.7V to 5.25V) VIH 0.8 DVDD DVDD 0.8 DVDD DVDD V VIL DGND 0.2 DVDD DGND 0.2 DVDD V VOH VOL IOH = 1mA 0.8 DVDD IOH = 8mA 0.75 DVDD IOL = 1mA V 0.75 DVDD 0.2 DVDD IOL = 8mA Input hysteresis Input leakage 0.8 DVDD 0.2 DVDD 0.2 DVDD 0.1 0.1 0 < VDIGITAL INPUT < DVDD V 0.2 DVDD ±10 V V V ±10 μA POWER SUPPLY AVSS –2.6 0 –2.6 0 V AVDD AVSS + 4.75 AVSS + 5.25 AVSS + 4.75 AVSS + 5.25 V DVDD 2.7 5.25 2.7 5.25 V 3.8 |mA| AVDD, AVSS current DVDD current (13) Operating (reference enabled) 2.3 Sleep mode (reference enabled) 200 Sleep mode (reference disabled) 1 3.8 2.3 200 40 1 |μA| 40 |μA| Power-Down mode 1 40 1 40 |μA| Operating 500 700 500 700 μA Sleep mode 160 300 160 300 μA Power-Down mode (14) 1 10 1 10 μA Operating 13 22 13 22 mW Sleep mode (reference enabled) 1.5 Sleep mode (reference disabled) 0.5 1.2 0.5 1.2 mW Power-Down mode 10 240 10 240 μW 1.5 mW Power dissipation TEMPERATURE RANGE Specified temperature range –40 +105 –40 +105 °C Operating temperature range –40 +125 –40 +125 °C Storage temperature range –60 +150 –60 +150 °C (12) Crystal operation using 18pF load capacitors. (13) Specified with internal oscillator operating (internal oscillator current: 40µA, typ). (14) External CLKIN, SCLK stopped. Digital inputs maintained at VIH or VIL voltage levels. 4 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com PIN CONFIGURATION PW PACKAGE TSSOP-20 (TOP VIEW) AINP 1 20 AVDD AINN 2 19 AVSS RESET/PWDN 3 18 VREFN START 4 17 VREFP SYNCOUT 5 16 REFOUT ADS1259 CS 6 15 DVDD SCLK 7 14 DGND DIN 8 13 BYPASS DOUT 9 12 XTAL2 DRDY 10 11 XTAL1/CLKIN ADS1259 Terminal Functions PIN NAME PIN # FUNCTION DESCRIPTION AINP 1 Analog input Positive analog input AINN 2 Analog input Negative analog input RESET/PWDN 3 Digital input Reset/Power-Down; reset is active low; hold low for power-down START 4 Digital input Start conversions, active high SYNCOUT 5 Digital output Sync clock output (fCLK/8) CS 6 Digital input SPI chip-select, active low SCLK 7 Digital input SPI clock input DIN 8 Digital input SPI data input DOUT 9 Digital output SPI data output DRDY 10 Digital output Data ready output, active low XTAL1/CLKIN 11 Digital input Internal oscillator: DGND External clock: clock input Crystal oscillator: external crystal1 XTAL2 12 Digital External crystal2, otherwise no connection BYPASS 13 Analog Core voltage bypass DGND 14 Digital Digital ground DVDD 15 Digital Digital power supply REFOUT 16 Analog output VREFP 17 Analog input Positive reference input VREFN 18 Analog input Negative reference input AVSS 19 Analog Negative analog power supply and negative reference output AVDD 20 Analog Positive analog power supply Copyright © 2009–2011, Texas Instruments Incorporated Positive reference output 5 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com SPI TIMING CHARACTERISTICS tSPWH tSCLK tCSH CS tCSSC tSPWL SCLK tDIST DIN B7 B6 B5 B4 tDIHD DOUT B7 B3 B2 B1 B0 B3 B2 B1 B0 tDOPD B6 B5 B4 tCSDOD tDOHD tCSDOZ Figure 1. Serial Interface Timing TIMING REQUIREMENTS: SERIAL INTERFACE TIMING At TA = –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted. SYMBOL 6 MIN CS low to first SCLK: setup time (1) 50 tSCLK SCLK period 1.8 tSPWH SCLK pulse width: high 90 tSPWL SCLK pulse width: low (3) tDIST Valid DIN to SCLK falling edge: setup time 35 20 Valid DIN to SCLK falling edge: hold time SCLK rising edge to valid new DOUT: propagation delay (4) tDOHD SCLK rising edge to DOUT invalid: hold time 0 (4) 0 CS low to DOUT driven: propagation delay tCSDOZ CS high to DOUT Hi-Z: propagation delay ns ns tCLK ns ns ns ns 40 20 20 (2) ns 60 CS high pulse UNIT tCLK 216 tDIHD tCSDOD MAX 90 tDOPD tCSH (1) (2) (3) (4) DESCRIPTION tCSSC ns ns tCLK CS can be tied low. tCLK = 1/fCLK. Holding SCLK low longer than 216 × tCLK cycles resets the SPI interface (enabled by SPI register bit). DOUT load = 20pF || 100kΩ to DGND. Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. NOISE DISTRIBUTION HISTOGRAM NOISE DISTRIBUTION HISTOGRAM 200 180 160 160 Data Rate = 10SPS Shorted Input 512 Samples 140 120 Occurrences 140 Occurrences Data Rate = 60SPS Shorted Input 512 Samples 120 100 80 60 100 80 60 40 40 20 20 0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 Reading (mV) Reading (mV) Figure 2. Figure 3. NOISE DISTRIBUTION HISTOGRAM NOISE DISTRIBUTION HISTOGRAM 1600 2800 2400 Data Rate = 400SPS Shorted Input 4096 Samples 1400 1200 Occurrences 2000 Occurrences Data Rate = 14.4kSPS Shorted Input 4096 Samples 1600 1200 800 1000 800 600 400 200 0 0 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 0 -2.5 -5.0 -7.5 -10.0 -12.5 -15.0 -17.5 -20.0 -22.5 -25.0 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 400 Reading (mV) Reading (mV) Figure 4. Figure 5. EFFECTIVE NUMBER OF BITS vs TEMPERATURE EFFECTIVE NUMBER OF BITS HISTOGRAM 25 16 Data Rate = 10SPS 14 24 Data Rate = 60SPS 30 Units Occurrences ENOB (rms) 12 23 Data Rate = 60SPS 22 21 10 8 6 4 20 2 Data Rate = 14.4kSPS 19 Figure 6. Copyright © 2009–2011, Texas Instruments Incorporated 23.5 23.3 23.4 23.1 23.2 23.0 22.8 125 22.9 105 22.7 Temperature (°C) 85 22.5 65 22.6 45 22.3 25 22.4 5 22.2 -15 22.1 -35 22.0 0 -55 ENOB (rms) Figure 7. 7 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. NOISE vs INPUT VOLTAGE NOISE vs INPUT VOLTAGE 7 7 Data Rate = 60SPS 6 5 5 Noise (mVrms) Noise (mVrms) Data Rate = 10SPS 6 4 3 Ratiometric Configuration Internal Reference CREFIN = 1mF 2 Internal Reference CREFIN = 1mF 4 2 REF5025 1 REF5025 1 0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0 -2.5 -2.0 -1.5 -1.0 -0.5 2.5 Figure 8. Figure 9. 8 REF5025 Noise (mVrms) Noise (mVrms) 1.5 2.0 2.5 Shorted Input 9 8 1.0 NOISE vs REFERENCE VOLTAGE 10 Internal Reference CREFIN = 1mF 6 Ratiometric Configuration 4 2 Data Rate = 14.4kSPS 7 6 5 Data Rate = 14.4kSPS 4 3 Data Rate = 10SPS Data Rate = 400SPS Data Rate = 16.6SPS 2 Data Rate = 14.4kSPS 0 -2.5 -2.0 -1.5 -1.0 -0.5 1 0 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VIN (V) Reference Voltage (V) Figure 10. Figure 11. LINEARITY DEVIATION vs INPUT LEVEL 4.0 4.5 5.0 5.5 INTEGRAL NONLINEARITY vs TEMPERATURE 3 3.0 5 Units T = +125°C T = +85°C T = +25°C T = -40°C 2.5 1 2.0 INL (ppm) Linearity Deviation (ppm) 0.5 VIN (V) NOISE vs INPUT VOLTAGE 0 1.5 -1 1.0 -2 0.5 -3 -2.5 -2.0 -1.5 -1.0 -0.5 8 0 VIN (V) 10 2 Ratiometric Configuration 3 0 0 0.5 1.0 1.5 2.0 2.5 -55 -35 -15 5 25 45 Input Signal (V) Temperature (°C) Figure 12. Figure 13. 65 85 105 125 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. OFFSET vs TEMPERATURE GAIN vs TEMPERATURE 100 500 5 Units 400 75 5 Units 300 Gain Error (ppm) 25 0 -25 200 100 0 -100 -200 -300 -50 -400 -75 -500 -55 -35 -15 5 25 45 65 85 105 125 -55 -35 5 -15 Figure 14. 45 65 85 105 125 Figure 15. OFFSET DRIFT DISTRIBUTION HISTOGRAM GAIN DRIFT DISTRIBUTION HISTOGRAM 30 20 60 Units From Two Production Lots 60 Units From Two Production Lots 25 16 2.6 2.2 2.4 2.0 1.8 1.6 1.2 1.4 0 0.26 0.22 0.24 0.18 0.20 0.14 0.16 0.12 0.08 0.10 0 0.06 0 0.04 4 0 5 0.8 8 0.4 10 12 0.6 15 0.2 Occurrences 20 0.02 Occurrences 25 Temperature (°C) Temperature (°C) 1.0 Offset (mV) 50 Gain Drift (ppm/°C) Offset Drift (mV/°C) Figure 16. Figure 17. INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE GAIN ERROR AND OFFSET vs REFERENCE VOLTAGE 50 3.0 150 40 2.5 1.5 1.0 20 50 10 0 0 -10 -50 -20 -30 0.5 Offset (mV) Gain Error (ppm) 2.0 INL (ppm) 100 30 -100 -40 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Reference Voltage (V) Figure 18. Copyright © 2009–2011, Texas Instruments Incorporated 4.5 5.0 5.5 -50 -150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Reference Voltage (V) Figure 19. 9 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. POWER-SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY 140 CMR 3.5 DVDD DVDD 100 Power-Supply Current (mA) 120 PSR and CMR (dB) POWER-SUPPLY CURRENT vs TEMPERATURE 4.0 CMR AVDD, AVSS 80 AVDD 60 AVSS 40 20 3.0 AVDD, AVSS (Internal Reference On) 2.5 2.0 1.5 1.0 0.5 0 DVDD 0 10 100 1k 10k 100k 1M -55 -35 -15 5 Power-Supply and Common-Mode Frequency (Hz) 25 Figure 20. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 105 125 INTERNAL REFERENCE VOLTAGE vs TEMPERATURE ADS1259 Internal Reference Voltage (V) Internal Reference Voltage (V) 85 2.504 ADS1259B 2.500 2.499 2.498 2.497 2.496 2.502 2.500 2.498 2.496 2.494 -50 -25 0 25 50 75 100 125 -55 -35 -15 5 Temperature (°C) 25 45 65 85 105 125 Temperature (°C) Figure 22. Figure 23. OUT-OF-RANGE THRESHOLD DISTRIBUTION HISTOGRAM OUT-OF-RANGE THRESHOLD vs TEMPERATURE 2.0 18 Relative to ±105% 30 Units 1.6 5 Units 1.2 Threshold Error (%) 14 12 10 8 6 0.8 0.4 0 -0.4 -0.8 4 -1.2 2 -1.6 0 -2.0 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Occurrences 65 Figure 21. 2.501 16 45 Temperature (°C) -55 -35 -15 5 25 45 65 85 105 125 Temperature (°C) Threshold Error (%) Figure 24. 10 Figure 25. Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. REFERENCE INPUT CURRENT vs TEMPERATURE REFERENCE INPUT CURRENT vs REFERENCE VOLTAGE 250 VREFP, VREFN Input Current (nA) VREFP, VREFN Input Current (nA) 0 -25 -50 VREFP Input Current -75 -100 -125 VREFN Input Current -150 -175 -200 -225 200 150 100 50 -50 -100 -150 -55 -35 5 -15 25 45 65 85 105 125 VREFP Input Current (VREFN = AVSS) -200 -250 -250 VREFN Input Current (VREFP = AVDD) 0 0.5 1.0 1.5 2.0 Figure 26. DIFFERENTIAL INPUT IMPEDANCE vs TEMPERATURE 3.5 4.0 4.5 5.0 INTERNAL REFERENCE SETTLING TIME 0.010 CREFIN = 1mF X7R 0.008 128 Settling (% of Final Value) Differential Input Impedance (kW) 3.0 Figure 27. 130 Internal Oscillator 126 External Crystal 124 122 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 120 -55 -35 -15 5 25 45 65 85 105 -0.010 125 0 1 2 3 4 5 6 Time (s) Temperature (°C) Figure 28. Figure 29. INTERNAL OSCILLATOR vs TEMPERATURE INTERNAL REFERENCE LONG-TERM STABILITY 0 Reference Voltage Stability (ppm) 7.50 7.45 Internal Oscillator (MHz) 2.5 VREF (V) Temperature (°C) 7.40 7.35 7.30 7.25 −20 −30 −40 −50 −60 −70 −80 −90 −100 7.20 -55 -35 -15 5 25 45 65 Temperature (°C) Figure 30. Copyright © 2009–2011, Texas Instruments Incorporated 85 105 125 48 units −10 0 100 200 300 400 500 600 700 800 900 1000 Hours G001 Figure 31. 11 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com OVERVIEW The ADS1259 is a high-linearity, low drift analog-to-digital converter (ADC) designed for the needs of industrial process control, precision instrumentation, and similar applications. The converter provides high-resolution, 24-bit output data at sample rates ranging from 10SPS to 14.4kSPS. Figure 32 shows a block diagram of the ADS1259. The device allows unipolar or bipolar analog power-supply configuration (AVDD – AVSS = 5V total). The analog supplies may be set to single +5V to accept unipolar (or offset-bipolar) signals or the supplies can be set to ±2.5V to accept true bipolar signals. The operating range of the digital power supply (DVDD) is 2.7V to 5V. An internal low dropout regulator (LDO) powers the digital core from the DVDD supply while the device I/O operates directly from DVDD. BYPASS is the LDO output and requires a 0.1μF or larger capacitor to ground. The inherently stable, fourth-order, ΔΣ modulator measures the differential input signal [VIN = (AINP – AINN)] against the differential reference [VREF = (VREFP – VREFN)]. A fast responding out-of-range detector flags the output data if the input should over-range while converting. The digital filter receives the modulator signal and provides the digital output. The filter consists of a fifth-order sinc filter followed by a programmable averager, selectable as either a sinc1 or sinc2. In sinc1 mode, the filter settles in a single conversion. The programmable averaging yields output data rates from 10SPS to 14.4kSPS. The ADS1259 integrates a low-drift, low-noise +2.5V reference. The internal reference can drive loads up to ±10mA. The ADS1259 also operates from an external reference if desired. The reference input is buffered to reduce loading of external circuits. An onboard oscillator is provided as the clock source for the device. Optionally, an external crystal can be used. As a third clock option, the device can be driven by an external clock source. SYNCOUT is an output that provides a 1/8 rate clock intended to drive the chopping clock input of the PGA280. Gain and offset registers scale the digital filter output to produce the final code value. On-command calibration corrects for system offset and gain errors. An SPI-compatible serial interface provides the control and configuration as well as the data interface to the ADS1259. Onboard registers combined with commands are used to control and configure the device. The RESET/PWDN pin is dual function. A momentary low resets the device and, if the pin is held low, powers down the device. The START pin, as well as commands, controls the conversions. AVDD VREFP +1.8V (Digital Core) 2.5V Reference REFOUT AINP DS Modulator AINN BYPASS DVDD VREFN Out-of-Range Detection Programmable Digital Filter LDO SYNCOUT fCLK/8 Clock Generator XTAL2 RESET/PWDN Calibration Engine FLAG XTAL1/CLKIN START Control and Serial Interface DRDY SCLK DIN DOUT CS ADS1259 AVSS DGND Figure 32. ADS1259 Block Diagram 12 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com NOISE PERFORMANCE MODULATOR The ADS1259 offers excellent noise performance that can be optimized by adjusting the data rate and by selection of the digital filter mode. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Additionally, because the sinc2 digital filter provides more filtering than the sinc1 digital filter, sinc2 provides lower noise conversions. Table 1 shows the noise as a function of data rate and filter mode. The high-performance modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as shown in Figure 33. It shifts the quantization noise to a higher frequency (out of the passband) where digital filtering can easily remove it. Table 1 expresses typical noise data in several ways: RMS noise, effective number of bits (ENOB), and noise-free bits. ENOB is calculated from Equation 1: ln fMOD = fCLK/8 2nd-Order DS 1st-Stage Analog Input (VIN) To Digital Filter 2nd-Order DS 2nd-Stage FSR RMS Noise ENOB = 4th-Order Modulator ln(2) Figure 33. Fourth-Order Modulator Where: FSR = 2VREF (1) The calculation of noise-free bits uses the same formula as Equation 1, except that the peak-to-peak noise value is used instead of RMS noise. ADC The analog-to-digital converter (ADC) section of the ADS1259 is composed of two blocks: a high accuracy modulator and a programmable digital filter. The modulator first stage converts the analog input voltage into a pulse-code modulated (PCM) stream. When the level of differential analog input (AINP – AINN) is near the level of the reference voltage (VREFP – VREFN), the 1s density of the PCM data stream is at its highest. When the level of the differential analog input is near zero, the PCM 0s and 1s densities are nearly equal. At the two extremes of the analog input levels (+FS and –FS), the 1s density of the PCM streams are approximately +90% and +10%, respectively. The modulator second stage produces a 1s density data stream designed to cancel the quantization noise of the first stage. The data streams of the two stages are then combined in the digital filter stage. Table 1. Typical Noise Data vs Data Rate and Digital Filter (1) (1) (2) (3) SINC1 DIGITAL FILTER DATA RATE (SPS) SAMPLE SIZE (2) SINC2 DIGITAL FILTER NOISE (μVRMS) NOISE (μVPP) ENOB (RMS) NOISEFREE BITS NOISE (μVRMS) NOISE (μVPP) ENOB (RMS) NOISEFREE BITS 10 128 0.5 1.8 23.3 21.4 0.45 1.6 23.4 21.6 16.6 256 0.55 2.4 23.1 21.0 0.5 2 23.3 21.3 50 512 0.65 3.5 22.9 20.4 0.6 3 23.0 20.7 60 512 0.7 4 22.8 20.3 0.65 3.5 22.9 20.4 400 4096 1.4 9.5 21.8 19.0 1.2 8.3 22.0 19.2 1200 8192 2.3 17 21.1 18.2 2 14 21.3 18.4 3600 8192 3.9 32 20.3 17.3 3.4 27 20.5 17.5 14400 8192 6.2 50 19.6 16.6 (3) (3) (3) (3) Noise data taken with shorted analog inputs and internal 2.5V reference using the circuit of Figure 64. Data sample sizes used for analysis. Same as sinc1 mode. Copyright © 2009–2011, Texas Instruments Incorporated 13 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 The ADS1259 modulator is inherently stable and therefore has predictable recovery behavior resulting from an input overdrive condition. The modulator does not exhibit the self-resetting behavior of other modulator types, which often results in unstable output conversion results when overdriven. The ADS1259 modulator outputs a 1s density data stream at 90% duty cycle with the positive full-scale input signal applied (10% duty cycle with the negative full-scale signal). If the input is overdriven past 90% modulation, but below 100% modulation (10% and 0% for negative overdrive, respectively), the modulator remains stable and continues to output the 1s density data stream. The digital filter may or may not clip the output codes to +FS or –FS, depending on the duration of the overdrive. When the input is returned to the normal range from a long duration overdrive (worst case), the modulator returns immediately to the normal range, but the group delay of the digital filter delays the return of the conversion result to within the linear range (one reading for the sinc1 filter and two readings for completely settled data). If the inputs are sufficiently overdriven to drive the modulator to full duty cycle (that is, all 1s or all 0s), the modulator enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on the duration. A small duration overdrive may not always clip the output code. When the input returns to the normal range, the modulator requires up to 12 modulator clock cycles (fMOD) to exit saturation and return to the linear region. The digital filter requires two additional conversions (sinc1, more for sinc2) for fully settled data. In the extreme case of over-range, either input is overdriven exceeding that either analog supply voltage plus an internal ESD diode drop. The internal ESD diodes begin to conduct and the signal on the input is clipped. If the differential input signal range is not exceeded, the modulator remains in linear operation. If the differential input signal range is exceeded, the modulator is saturated but stable, and outputs all 1s or 0s. When the input overdrive is removed, the diodes recovery quickly and the 14 ADS1259 recovers as normal. Note that the linear input range is ±100mV beyond the analog supply voltages; with input levels greater than this range, use care to limit the input current to 100mA peak transient (10mA continuous). INPUT OUT-OF-RANGE DETECTION (FLAG) The ADS1259 has a fast-responding out-of-range circuit that triggers when the differential input exceeds +105% or –105% of FSR (±1.05 VREF). The out-of-range circuit latches the result of the comparator output and appends the result as either the LSB of conversion data or as bit 7 of the data checksum byte. After the conversion data are read, or after a new conversion is started, the comparator latch is reset. Figure 34 and Figure 35 show the detection block diagram and the detection operation, respectively. See the Data Checksum Byte and FLAG Bit section for more detail. AINP å IABSI 1.05 VREF AINN J Q fMOD/2 Data Read Reset FLAG K Figure 34. Input Out-Of-Range Detect Block Diagram AINP - AINN (% VREF) MODULATOR OVERLOAD BEHAVIOR www.ti.com +105 (Conversions) 0 -105 FLAG Bit 1 0 Figure 35. Input Out-Of-Range Detect Operation Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ANALOG INPUTS (AINP, AINN) ESD diodes protect the analog inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 300mV, and likewise do not exceed AVDD by more than 300mV. The ADS1259 measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN) using internal capacitors that are continuously charged and discharged. Figure 37 shows the simplified schematic of the ADC input circuitry; the right side of the figure illustrates the input circuitry with the capacitors and switches replaced by an equivalent circuit. Figure 36 demonstrates the ON/OFF timings for the switches of Figure 37. AVSS – 300mV < (AINP or AINN) < AVDD + 300mV. Note that the valid input range is: AVSS – 100mV < (AINP or AINN) < AVDD + 100mV tSAMPLE = 1/fMOD ON In Figure 37, S1 switches close during the input sampling phase. With switch S1 closed, CA1 charges to AINP, CA2 charges to AINN, and CB charges to (AINP – AINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately to AVSS + 2.5V and CB discharges to 0V. This two-phase sample/discharge cycle repeats with a period of tSAMPLE = 1/fMOD. fMOD is the operating frequency of the modulator, where fMOD = fCLK/8. S1 OFF ON S2 OFF Figure 36. S1 and S2 Switch Timing for Figure 37 Although optimized for differential signals, the ADS1259 inputs may be driven with a single-ended signal by fixing one input to AVSS or mid-supply. Full dynamic range is achieved when the inputs are differentially driven ±VREF. The charging of the input sampling capacitors draws a transient current from the source driving the ADS1259 ADC inputs. The average value of this current can be used to calculate an effective impedance (REFF) where REFF = VIN/IAVERAGE. These impedances scale inversely with fMOD. For example, if fMOD is reduced by a factor of two, the impedances double. Note that the sampling capacitors can vary ±15% over production lots and typically vary 1% with temperature. The variations of the sampling capacitors have a corresponding effect on the analog input impedance. AVDD As a result of the switched-capacitor input structure of the ADS1259, a buffer is recommended to drive the analog inputs. An input filter comprised of 20Ω to 50Ω resistors and 10nF capacitors should be used between the buffer and the ADS1259 inputs. (fMOD = 0.9216MHz) AVSS + 2.5V AVSS + 2.5V S2 AINP REFF A = 500kW CA1 = 2pF ESD Diodes Equivalent Circuit S1 AINP REFF B = 130kW CB = 8pF S1 AINN AINN REFF A = 500kW CA2 = 2pF ESD Diodes S2 AVSS AVSS + 2.5V REFF = 1 fMOD ´ CX and fMOD = fCLK/8 AVSS + 2.5V RDIFF = REFF B || 2REFF A = 120kW RCOM = REFF A = 500kW Figure 37. Simplified ADC Input Structure Copyright © 2009–2011, Texas Instruments Incorporated 15 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com REFERENCE the ADC reference input pins, VREFP and VREFN. (Note that these device pins are not intended to drive external circuits.) An external 1μF capacitor, connected from VREFP to VREFN, is recommended for noise reduction. The capacitor can be increased for increased noise filtering, but the settling time of the reference may also increase. The settling time should be considered upon activating the internal reference. The ADS1259 includes an onboard voltage reference with a low temperature coefficient. The reference voltage is 2.5V with the capability of sinking and sourcing 10mA via the REFOUT pin. The ADS1259 can also operate from an external reference. The external reference is the default selection. Refer to Figure 38 for a reference block diagram. Internal Reference See Figure 29 for typical reference settling CREFIN = 1µF. The capacitor dielectric absorption results in increased settling time for RC filter circuits. The reference output is provided between pins REFOUT and AVSS. Because the reference output return shares the same pin as AVSS, route the reference return trace and the AVSS trace independently as Kelvin-connected printed circuit board (PCB) traces. For stability reasons, connect a 1μF capacitor between REFOUT and AVSS. To activate the internal reference, set the register bit RBIAS = 1. This enables the reference bias. Once biased, the internal reference can then be selected as the ADC reference by the register bit EXTREF. EXTREF = 0 closes the internal switches. An internal switch connects the internal reference to AVDD REFOUT (+) + Reference Output (-) Reference Bias RBIAS Register Bit (1 = Bias On) 2.5V Reference 1 mF (CREFOUT) AVSS Reference Select EXTREF Register Bit (1 = Switch Open for External Reference) 2kW (+) Reference Input (-) VREFP (+) + 1mF (CREFIN) ADC Reference Input (-) VREFN Figure 38. Reference Block Diagram Table 2. Reference Selection for Figure 38 ADS1259 REFERENCE RBIAS REGISTER BIT EXTREF REGISTER BIT Internal 1 0 External (1) 16 See (1) 1 If the reference output is not required, set RBIAS = 0. If the reference output is enabled (RBIAS = 1), an external 1µF capacitor must be used between REFOUT and AVSS. Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Reference Drift External Reference The ADS1259 internal reference is designed for minimal drift error, which is defined as the change in reference voltage over temperature. The drift is calculated using the box method, as described by Equation 2. VREFMAX - VREFMIN Drift = x 106 (ppm) VREFNOM ´ Temp Range To select the ADS1259 for external reference operation, set the EXTREF register bit = 1 (default). If desired, the internal reference can continue to provide a +2.5V reference output via the REFOUT and AVSS pins. In this case, set the RBIAS register bit = 1 to power the internal reference. If the internal reference is activated, an external 1μF capacitor from REFOUT to AVSS is required. Where: VREFMAX, VREFMIN, and VREFNOM are the maximum, minimum, and nominal reference output voltages, respectively, over the specified temperature range. (2) For external reference applications, place a 1μF (minimum) capacitor close to the VREFP and VREFN pins. The ADS1259 internal reference features a maximum drift coefficient of 5ppm/°C over 0°C to +85°C operating range and 12ppm/°C over –40°C to +105°C operating range. Thermal Hysteresis Thermal hysteresis of the internal reference is defined as the change in voltage after operating the device at +25°C, cycling the device through the specified temperature range, and returning to +25°C. It can be expressed as Equation 3. VHYST = |VPRE - VPOST| VNOM ´ 106(ppm) Because the ADS1259 measures the signal inputs (AINP and AINN) against the reference inputs (VREFP and VREFN), reference noise and drift may degrade overall system performance. In ratiometric measurement applications, reference noise and drift have a cancelling effect. In absolute measurement applications, reference noise and drift directly effect the conversion results. Voltage Reference Inputs (VREFP, VREFN) ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AVSS by more than 300mV, and likewise do not exceed AVDD by more than 300mV. The absolute maximum reference input range is: AVSS – 300mV < (VREFP or VREFN) < AVDD + 300mV(4) Where: VHYST = thermal hysteresis (in units of ppm). VNOM = nominal reference voltage (+2.5V). VPRE = reference voltage measured at +25°C pretemperature cycling. VPOST = reference voltage measured after the device has been cycled from +25°C through the temperature range of 0°C and +85°C and returned to +25°C. (3) Copyright © 2009–2011, Texas Instruments Incorporated Note that the valid operating range of the reference inputs are shown in the Electrical Characteristics table. 17 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com DIGITAL FILTER The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rate. The filter consists of two sections: a fixed decimation sinc5 filter followed by a variable decimation filter, configurable as sinc1 or sinc2, as illustrated in Figure 39. The sinc5 filter has fixed decimation of 64 and reduces the data rate of the modulator from fCLK/8 to fCLK/512. The second filter stage receives the data from the sinc5 filter. The second filter stage has programmable averaging (or decimation) and can be configured in either sinc1 or sinc2 mode. The decimation ratio of this stage sets the final output data rate. As detailed in Table 3, the DR[2:0] register bits program the decimation ratio and the final output data rate. The output data rates are identical for both sinc1 and sinc2 filters. Table 3. Decimation Ratio of Final Filter Stage DR[2:0] REGISTER BITS DECIMATION RATIO (R) DATA RATE (SPS) 111 1 14400 110 4 3600 101 12 1200 100 36 400 011 240 60 010 288 50 001 864 16.6 000 1440 10 Modulator Rate = fCLK/8 The SINC2 register bit selects either the sinc1 or sinc2 filter. The sinc1 filter settles in one conversion cycle while the sinc2 filter settles in two conversion cycles. However, the sinc2 filter has the benefit of wider frequency notches which improve line cycle rejection. FREQUENCY RESPONSE The low-pass digital filter sets the overall frequency response of the ADS1259. The filter response is the product of the fixed and programmable filter sections, and is given by Equation 5: ½H(f)½ = ½Hsinc5(f)½ ´ ½HsincN(f)½ = 5 512p ´ f sin fCLK 64 ´ sin 8p ´ f fCLK N sin ´ 512p ´ R ´ f fCLK R ´ sin 512p ´ f fCLK where: N = 1 (sinc1) N = 2 (sinc2) R = Decimation ratio (refer to Table 3) (5) The digital filter attenuates noise on the modulator output, including noise from within the ADS1259 and external noise present within the ADS1259 input signal. Adjusting the filtering by changing the decimation ratio used in the programmable filter changes the filter bandwidth. With a higher number of decimation, the bandwidth is reduced and more noise is attenuated. fCLK/512 1 sinc Filter Analog Modulator 5 Output Data Rate = fCLK/(R ´ 512) sinc Filter (decimate by 64) 2 sinc Filter SINC2 Register Bit DR[2:0] Register Bits (Program Decimation) 1 (0 = sinc ) Figure 39. Block Diagram of Digital Filter 18 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com The sinc5 filter produces wide notches at fCLK/512 and multiples thereof. At these frequencies the filter has zero gain. Figure 40 shows the response data rate = 14.4kSPS. -20 Magnitude (dB) With decimation of the second stage, the wide notches produced by the sinc5 filter remain, but a number of narrow notches are superimposed in the response. The first of the notches occur at the data rate. The number of superimposed notches is determined by the decimation ratio, minus 1. 0 sinc2 10 4.3 3.1 16.6(3) 16.6 7.3 5.2 50 50 22 16 60 60 27 19 400 400 177 127 1200 1200 525 380 3600 3600 1440 1100 14400 14400 2930 See (4) 10 fCLK = 7.3728MHz. Notch at 50Hz and 60Hz. Notch at 50Hz. Same as sinc1. 10 20 30 40 50 60 Frequency (kHz) Figure 40. Frequency Response for Data Rate = 14.4kSPS 0 sinc 2 -20 sinc 1 -40 -60 -80 -100 -120 –3dB BANDWIDTH (Hz) sinc1 (2) (1) (2) (3) (4) FIRST NOTCH (Hz) -100 0 -140 0 10 20 30 40 50 60 Frequency (kHz) Figure 41. Frequency Response (Data Rate = 3600SPS, R = 4) 0 -10 -20 Magnitude (dB) DATA RATE (SPS) -80 -140 Magnitude (dB) Table 4. First Notch Frequency and –3dB Filter Bandwidth(1) -60 -120 The second stage filter has notches (or zeroes) at the data rate and multiples thereof. Figure 41 shows the response of the second stage filter combined with the sinc5 stage. Decimation of 4 produces three equally-spaced notches between each main notch of the sinc5 filter. The frequency response of the other data rates (higher decimation ratios) produces a similar pattern, but with more equally-spaced notches between the main sinc5 notches. Table 4 lists the first notch frequency and the –3dB bandwidth. Figure 42 illustrates the detail of the magnitude response with data rate = 60SPS. Note that input frequencies within the ±1% 60Hz bandwidth are attenuated 40dB by the sinc1 filter and 80dB by the sinc2 filter. -40 -30 sinc -40 -50 sinc -60 1 2 -70 -80 -90 -100 55 56 57 58 59 60 61 62 63 64 65 Frequency (Hz) Figure 42. Magnitude Response for Data Rate = 60SPS Copyright © 2009–2011, Texas Instruments Incorporated 19 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ALIASING CLOCK SOURCE The low-pass characteristic of the digital filter repeats at multiples of the modulator rate (fMOD = fCLK/8). Figure 43 shows the responses plotted out to 7.3728MHz at the data rate of 14.4kSPS. Notice how the responses near dc, 0.9216MHz, 1.8432MHz, 2.7698MHz, etc, are the same as given by f = NfMOD ± fDATA where N = 0, 1, 2, etc. The digital filter attenuates high-frequency noise on the ADS1259 inputs up to the frequency where the response repeats. However, noise or frequency components existing in the signal where the response repeats alias into the passband. Often, a simple RC antialias filter is sufficient to reject these input frequencies. There are three ways to provide the ADS1259 clock: the internal oscillator, an external clock, or an external crystal/ceramic resonator. The ADS1259 selects the clock source automatically. Figure 44 shows the clock select block. If either external clock sources are present, the internal oscillator is disabled and the external clock source is selected. If no external clock is present, the internal oscillator is selected. The ADS1259 continuously monitors the clock source. The clock source can be polled by the EXTCLK bit (bit 6 of register CONFIG2), 0 = internal oscillator, 1 = external clock. 0 Magnitude (dB) -20 The data rate and corresponding filter notches scale by the accuracy of clock frequency. Consideration should be given to the clock accuracy and the corresponding effect to the notch frequency locations. -40 -60 Clock Detect XTAL1/CLKIN -80 -100 Internal Oscillator XTAL2 S0 -120 ENB S1 SEL MUX -140 0 0.9 1.8 2.8 3.7 4.6 5.5 6.5 System Clock 7.4 Frequency (MHz) Figure 43. Frequency Response to 7.3728MHz (Data Rate = 14400SPS) Figure 44. Equivalent Circuitry of the Clock Source Internal Oscillator Figure 45 shows the internal oscillator connection. XTAL1/CLKIN is grounded and XTAL2 is not connected (floating). The internal oscillator draws approximately 40μA from the DVDD supply. Note that the internal oscillator has ±2% accuracy over temperature. The oscillator accuracy has a corresponding effect on line-cycle notch frequency locations. XTAL1/CLKIN XTAL2 Figure 45. Internal Oscillator Connection 20 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com External Clock SYNCOUT Figure 46 shows the external clock connection. The clock is applied to XTAL1/CLKIN and XTAL2 floats. Make sure a clean clock input is applied to the ADS1259, free of overshoot and glitches. A series resistor often helps to reduce overshoot and should be placed close to the driving end of the clock source. SYNCOUT is a digital output pin intended to synchronize the chopping frequency of the PGA280 to the sampling frequency of the ADS1259. Synchronizing the PGA280 to the ADS1259 places the PGA280 chopped 1/f noise at an exact null in the ADS1259 frequency response, where the PGA280 1/f noise is rejected. External Clock 50W XTAL1/CLKIN XTAL2 Figure 46. External Clock Connection Crystal Oscillator Figure 47 shows the crystal oscillator connection. The crystal connects to XTAL1/CLKIN and XTAL2 and the capacitors connect to ground. The crystal and capacitors should be placed close to the device pins with short, direct traces. Neither the XTAL1/CLKIN nor the XTAL2 pins can be used to drive any other logic. Table 5 lists the recommended crystal for the ADS1259. If using other crystals, verify the oscillator start-up behavior. XTAL1/CLKIN Crystal (7.3728MHz) C1 XTAL2 C2 C1, C2: 5pF to 20pF Figure 47. Crystal Connection Table 5. Recommended Crystal MANUFACTURER FREQUENCY PART NUMBER ECS 7.3728MHz ECS-73-18-10 SYNCOUT frequency is equal to the ADS1259 clock rate divided by 8 (fSYNCOUT = fCLK/8). The output clock is enabled by the register bit SYNCOUT. Disabling the output stops the clock but the output remains actively driven low. In power-down mode, the SYNCOUT output becomes an input. As with all digital inputs, the pin must not be allowed to float. An external 1MΩ pull-down resistor is recommended to ground the input in power-down mode. The SYNCOUT clock is reset when START is received and whenever registers CONFIG[2:0] are changed. Connect SYNCOUT to the PGA280 SYNCIN pin through a 4.7kΩ series resistor. Place the resistor as close as possible to the ADS1259 SYNCOUT pin. SLEEP MODE SLEEP mode is started by sending the SLEEP command. In SLEEP mode, the device enters a reduced power state and only a minimum of circuitry is kept active. The WAKEUP command exits the SLEEP mode and after which 512 fCLK cycles are counted before the ADS1259 is ready for communication. The register settings are unaffected in SLEEP. SLEEP does not change the RBIAS register bit. For quick conversions after WAKEUP, keep the internal reference bias on before entering SLEEP. Otherwise, after exiting SLEEP mode, allow time for the reference to settle. Alternatively, to minimize power consumption during SLEEP, set the internal reference bias off prior to engaging SLEEP. Note that in SLEEP mode the SPI timeout function is disabled. BYPASS The digital core of the ADS1259 is powered by an internal low dropout regulator (LDO). The DVDD supply is the LDO input and the BYPASS pin is the LDO output. A 1μF capacitor must be connected from the LDO output to DGND. No other load current should be drawn from the BYPASS pin. Copyright © 2009–2011, Texas Instruments Incorporated 21 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com RESET/PWDN RESET The RESET/PWDN pin has two functions: device power-down and device reset. Momentarily holding the pin low resets the device and holding the pin low for 216 fCLK cycles activates the Power-Down mode. There are three methods to reset the ADS1259: cycle the power supplies, take RESET/PWDN low, or send the RESET opcode command. When using the RESET/PWDN pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. POWER-DOWN MODE In power-down mode, internal circuit blocks are disabled (including the oscillator, reference, and SPI) and the device enters a micro-power state. To engage power-down mode, hold the RESET/PWDN pin low for 216 fCLK cycles. Note that the register contents are not saved because they are reset when RESET/PWDN goes high. The RESET command takes effect on the eighth falling SCLK edge of the opcode command. On reset, the configuration registers are initialized to the default states and the conversion cycle restarts. After reset, allow eight fCLK cycles before communicating to the ADS1259. Note that when using the reset command, the SPI interface itself may require reset before accepting the command. See the SPI Timing Characteristics section for details. Keep the digital inputs at defined VIH or VINL logic levels (do not 3-state). To minimize power-supply leakage current, disable the external clock. Note that the ADS1259 digital outputs remain active in power-down. The analog signal inputs may float. POWER-ON SEQUENCE To exit power-down, take RESET/PWDN high. Wait 216 fCLK cycles before communicating to the ADS1259, as shown in Figure 48. The ADS1259 has three power supplies: AVDD, AVSS, and DVDD. The supplies can be sequenced in any order but be sure that at any time the analog inputs do not exceed AVDD or AVSS and the digital inputs do not exceed DVDD. After the last power supply has crossed the respective power-on threshold, 216 fCLK cycles are counted before releasing the internal reset. After the internal reset is released, the ADS1259 is ready for operation. Figure 49 shows the power-on sequence of the ADS1259. tLOW RESET/PWDN tRHSC SCLK Figure 48. RESET/PWDN Timing Table 6. Timing Characteristics for Figure 48 SYMBOL DESCRIPTION MIN UNIT tLOW Pulse width low for reset 4 tCLK 16 tCLK tLOW Pulse width low for power-down tRHSC Reset high to SPI communication start 8 tCLK tRHSC Exit power-down to SPI communication start 216 tCLK AVDD - AVSS DVDD 2 3.5V nom 1V nom CLK 2 Internal Reset 16 ´ tCLK ADS1259 Operational Figure 49. Power-On Sequence 22 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com START START is a digital input that controls the ADS1259 conversions. Conversions are started when START is taken high and are stopped when START is taken low. If START is toggled during a conversion, the conversion is restarted. DRDY goes high when START is taken high. Figure 50 andTable 7 show the START timing. Note that reasserting START within 22 tCLK cycles of the DRDY falling edge causes DRDY to fall soon after. This conversion result should be discarded. The next DRDY falling edge, as given in Table 9, is the valid conversion data. tSDSU DRDY tPWH tSTDR Gate Control Mode (PULSE Bit = 0, Default) Conversions begin when either the START pin is taken high or when the START command is sent. Conversions continue indefinitely until the START pin is taken low or the STOP command is transmitted. As seen in Figure 51, DRDY is forced high when the conversion starts and falls low when data are ready. When stopped, the conversion in process completes and further conversions are halted. Figure 50 and Table 7 show the timing of DRDY and START. tDSHD START START Pin tPWL or Command When using commands to control conversions, hold the START pin low. The ADS1259 features two modes to control conversions: Gate Control mode and Pulse Control mode. The mode is selected by the PULSE register bit. (1) START STOP STOP or START Command(1) (1) START and STOP commands take effect on the seventh SCLK falling edge. or STOP START Halted Converting Halted Figure 50. START to DRDY Timing DRDY CONVERSION CONTROL The conversions of the ADS1259 are controlled by either the START pin or by the START command. (1) START and STOP opcode commands take effect on the seventh SCLK falling edge. Figure 51. Gate Control Mode Table 7. START Timing (See Figure 50) SYMBOL DESCRIPTION MIN tSDSU START pin low or STOP opcode to DRDY setup time to halt further conversions 16 tCLK tDSHD START pin low or STOP opcode hold time to complete current conversion (gate mode) 16 tCLK tPWH, START pin pulse width high, low 4 L tSTDR START pin rising edge to DRDY rising edge Copyright © 2009–2011, Texas Instruments Incorporated MAX UNIT tCLK 4 tCLK 23 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Pulse Control Mode (PULSE Bit = 1) Settling Time Using START In the Pulse Control mode, the ADS1259 performs a single conversion when either the START pin is taken high or when the START command is sent. As seen in Figure 52, DRDY goes high when the conversion is started. When the conversion is complete, DRDY goes low and further conversions are halted. To start a new conversion, transition the START pin back to high, or transmit the START opcode again. When START goes high (via pin or command) a delay may be programmed before the conversion filter cycle begins. The programmable delay may be useful to provide time for external circuits (such as after an external signal mux change), before the reading is started. Register bits DELAY[2:0] set the initial delay time as shown in Table 8. Table 8. Initial START Delay START Pin OR OR START Halted START Single Conversion Halted Single Conversion DRDY (1) START opcode command takes effect on the seventh SCLK falling edge. Figure 52. Pulse Control Mode CONVERSION SETTLING TIME The ADS1259 features a digital filter architecture in which settling time can be traded for wide filter notches, resulting in improved line-cycle rejection. This trade-off is determined by the selection of the sinc1 or sinc2 filter. The sinc1 filter settles in a single cycle while the sinc2 filter provides wide-width filter notches. The settling time of the ADS1259 is different if START is used to begin conversions or if the ADS1259 is free-running the conversions. These modes are explained in the Settling Time Using START and Settling Time While Continuously Converting sections. VIN = AINP - AINN Settled VIN START Pin or 7th Falling SCLK Edge of Opcode START Command DELAY[2:0] tDELAY (tCLK) tDELAY (µs)(1) 000 0 0 001 64 8.68 010 128 17.4 011 256 34.7 100 512 69.4 101 1024 139 110 2048 278 111 4096 556 (1) fCLK = 7.3728MHz. After the programmable delay, the digital filter is reset and a new conversion is started. DRDY goes low when data are ready. There is no need to ignore or discard data; the data are completely settled. The total time to perform the first conversion is the sum of the programmable delay time and the settling of the digital filter. That is, the value of Table 8 and Table 9 combined. Figure 53 shows the timing and Table 9 shows the settling time with programmable delay equal to '0'. Table 9. Settling Time Using START DATA RATE (SPS) SETTLING TIME (tSET) (ms)(1) sinc1 sinc2 10 100 200 16.6 60.3 120 50 20.3 40.4 60 17.0 33.7 5.42 400 2.85 1200 1.18 2.10 3600 0.632 0.980 14,400 0.424 0.563 (1) fCLK = 7.3728MHz, DELAY[2:0] = 000. DRDY DOUT tSET(1) Settled Data (1) tSET = initial start delay plus the new conversion cycle time. Figure 53. Data Retrieval Time After START 24 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Settling Time While Continuously Converting OFFSET AND GAIN If there is a step change on the input signal while continuously converting, the next data represent a combination of the previous and current input signal and should therefore be discarded; see Figure 54 for this step change. Table 10 shows the number of conversion cycles for completely settled data while continuously converting. The ADS1259 features low offset (40μV, typ) and low gain errors (0.05%, typ). The offset and gain errors can be corrected by sending calibration commands to the ADS1259; see the Calibration section. Table 10. Settling Time While Continuously Converting DRDY Periods(1) DATA RATE (SPS) SETTLING TIME (tSET) (Conversions) sinc1 sinc2 10 2 3 16.6 2 3 50 2 3 60 2 3 400 2 3 1200 2 3 3600 3 4 14,400 6 7 The ADS1259 also features very low offset drift (0.05μV/°C, typ) and very low gain drift (0.5ppm/°C, typ). The offset and gain drift are calculated using the box method, as described by Equation 6 and Equation 7: VOFFMAX - VOFFMIN Offset Drift = Temp Range (6) Gain Drift = GainErrorMAX - GainErrorMIN Temp Range where: VOFFMAX, VOFFMIN, GainErrorMAX, and GainErrorMIN are the maximum and minimum offset and gain error readings recorded over the Temp Range (–40°C to +105°C) (7) (1) Settling time is defined as the number of DRDY periods after the input signal has settled following an input step change. For best data throughput in multiplexed applications, issue a START condition (START pin or Start command) after the input has settled following a multiplexer change; see the Setling Time Using START section. New VIN VIN = AINP - AINN Old VIN DRDY DOUT Old VIN Data tSET Mix of Old and New VIN Data Fully Settled New VIN Data Settled Data Figure 54. Step Change on VIN while Continuously Converting Copyright © 2009–2011, Texas Instruments Incorporated 25 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Table 11. Offset Calibration Values OFFSET AND FULL-SCALE CALIBRATION REGISTERS The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 55, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC). Equation 8 shows the scaling: FSC[2:0] Final Output Data = (Input - OFC[2:0]) ´ 400000h (8) The values of the offset and full-scale registers are set by writing to them directly, or they are set by calibration commands. OFC[2:0] Registers The offset calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 13. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from the conversion data. A register value of 00000h has no offset correction (default value). Note that while the offset calibration register value can correct offsets ranging from –FS to +FS (as Table 11 shows), to avoid input overload, the analog inputs cannot exceed 105% full-scale. AINP Modulator AINN Digital Filter OFC REGISTER FINAL OUTPUT CODE(1) 7FFFFFh 800001h 000001h FFFFFFh 000000h 000000h FFFFFFh 000001h 800001h 7FFFFFh (1) Ideal output code excluding noise and inherent offset error. FSC[2:0] Registers The full-scale calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 14. The full-scale calibration value is 24-bit, straight binary, normalized to 1.0 at code 400000h. Table 12 summarizes the scaling of the full-scale register. A register value of 400000h (default value) has no gain correction (gain = 1). Note that while the gain calibration register value corrects gain errors above 1 (gain correction < 1), the full-scale range of the analog inputs cannot exceed 105% full-scale to avoid input overload. Table 12. Full-Scale Calibration Register Values FSC REGISTER GAIN FACTOR 800000h 2.0 400000h 1.0 200000h 0.5 000000h 0 + Output Data Clipped to 24 Bits S ´ OFC Register FSC Register 400000h - Final Output Figure 55. Calibration Block Diagram Table 13. Offset Calibration Word REGISTER BYTE OFC0 LSB B7 B6 B5 B4 BIT ORDER B3 B2 B1 B0 (LSB) OFC1 MID B15 B14 B13 B12 B11 B10 B9 B8 OFC2 MSB B23 (MSB) B22 B21 B20 B19 B18 B17 B16 Table 14. Full-Scale Calibration Word REGISTER BYTE FSC0 LSB B7 B6 B5 B4 B3 B2 B1 B0 (LSB) FSC1 MID B15 B14 B13 B12 B11 B10 B9 B8 FSC2 MSB B23 (MSB) B22 B21 B20 B19 B18 B17 B16 26 BIT ORDER Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com CALIBRATION The ADS1259 has commands to correct for system offset and gain errors. Calibration can be performed at any time the ADS1259 and associated circuitry (such as the input amplifier, external reference, power supplies, etc) have stabilized. Options include calibrating after power-up, after temperature changes, or calibration at regular intervals. To calibrate: • Set the gate control mode (PULSE bit = 0) • Start the ADS1259 conversions • Apply the appropriate input to the ADS1259 (zero or full-scale) • Allow time for the input to completely settle • Send the OFSCAL (offset calibration) or GANCAL (full-scale calibration) command, as appropriate • Wait for calibration to complete as given by the time listed in Table 15. DRDY goes low when calibration is complete. The conversion result at this time uses the new offset or full-scale calibration words. Figure 56 shows the calibration calibration, do not send commands. timing. During The internal full-scale calibration word is bypassed during offset calibration. Do not exceed +105% of full-scale range for gain calibration. Note that the out-of-range threshold is unaffected by gain calibration. Table 15. Calibration Timing tCAL CALIBRATION TIME (ms) DATA RATE (SPS) sinc1 sinc2 14400 1.89 2.19 3600 5.43 6.15 1200 14.9 16.7 400 43.2 48.4 60 284 318 50 341 380 16.6 1020 1140 10 1700 1900 1. fCLK = 7.3728MHz. DRDY (DOUT with CS = 0) tCAL Calibration complete and first data ready. Perform offset calibration prior to the gain calibration. DIN CAL Command Figure 56. Calibration Timing Copyright © 2009–2011, Texas Instruments Incorporated 27 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com SERIAL INTERFACE DATA INPUT (DIN) The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT or three signals, in which case CS may be tied low. The interface is used to read conversion data, configure registers, and control the ADS1259 operation. DIN is the input data pin and is used with SCLK to send data to the ADS1259 (opcode commands and register data). The device latches input data on the falling edge of SCLK. DATA OUTPUT (DOUT) SERIAL COMMUNICATION The ADS1259 communications occur by clocking commands into the device (on DIN) and reading register and conversion data (on DOUT). The SCLK input is used to clock the data into and out of the device. CS disables the ADS1259 serial port but otherwise does not affect the ADC operation. The communication protocol to the ADS1259 is half-duplex. That is, data are transmitted to and from the device one direction at a time. Communications to and from the ADS1259 occurs on 8-bit boundaries. If an unintentional SCLK transition should occur (such as from a possible noise spike), the ADS1259 serial port may not respond properly. The port can be reset by one of the following ways: 1. Take CS high and then low to reset the interface 2. Hold SCLK low for 216 fCLK cycles to reset the interface 3. Take RESET/PWDN low and back high to overall reset the device 4. Cycle the power supplies to overall reset the device CHIP SELECT (CS) The chip select (CS) selects the ADS1259 for SPI communication. To select the device, pull CS low. CS must remain low for the duration of the serial communication. When CS is taken high, the serial interface is reset, input commands are ignored, and DOUT enters a high-impedance state. If the ADS1259 does not share the serial bus with another device, CS may be tied low. Note that DRDY remains active when CS is high. DOUT is the output data pin and is used with SCLK to read conversion and register data from the ADS1259. In addition to providing data output, in RDATAC mode DOUT indicates when data are ready. Data are ready when DOUT transitions low. In this manner, DOUT functions the same as DRDY (with CS = 0), as shown in Figure 57. When reading data, the data are shifted out on the rising edge of SCLK. DOUT is in a 3-state condition when CS is high. DATA READY (DRDY) DRDY is an output that indicates when conversion data are available for reading (falling edge active). DRDY is asserted on an output pin and also a register bit. To poll the DRDY register bit, set the stop read data continuous mode and then read the CONFIG2 register. When the DRDY bit is low, data can be read. The data read operation must complete within 20 fCLK cycles of the next DRDY falling edge. After power-on or after reset, DRDY defaults high. When reading data in Gate Control mode, DRDY is reset high on the first SCLK rising edge. If data are not retrieved, DRDY pulses high during the new data update time, as shown in Figure 57. Do not retrieve data during this time as the data are invalid. In Pulse Control mode, DRDY remains low until a new conversion is started. The previous conversion data may be read 20 tCLK prior to the DRDY falling edge. 20 tCLK DRDY Pin Data Updating (1)(2) SERIAL CLOCK (SCLK) The serial clock (SCLK) is a Schmitt-triggered input used to clock data into and out of the ADS1259. Even though the input is relatively noise immune, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. If SCLK is held low for 216 fCLK periods, the serial interface resets. After reset the next communication cycle can be started. The timeout can be used to recover communication when the serial interface is interrupted. The SPI timeout is enabled by register bit SPI. When the serial interface is idle, hold SCLK low. 28 (1) DOUT functions in the same manner as the DRDY pin if CS is low and in the RDATAC mode. (2) The DRDY bit functions in the same manner as the DRDY pin (SDATAC mode only). Figure 57. DRDY and DOUT With No Data Retrieval Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com DATA FORMAT DATA CHECKSUM BYTE AND FLAG BIT The ADS1259 outputs 24 bits of conversion data in binary twos complement format, MSB first. The data LSB has a weight of VREF/(223 – 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 16 summarizes the ideal output codes for different input signals. An optional checksum byte can be appended to the conversion data bytes. The checksum makes the data word length four bytes in length instead of three. The checksum byte is enabled by the register bit CHKSUM. The checksum itself is the least significant byte sum of the three conversion data bytes, offset by 9Bh. Note that the checksum byte option only applies to the readback conversion data, not to register data. The checksum is either seven bits or eight bits, depending if the FLAG register bit is enabled. If the FLAG bit is enabled the checksum is seven bits, with bit 7 replaced by the out-of-range flag. Figure 58 and Table 17 describe the combinations of the FLAG and CHKSUM register bits. Table 16. Ideal Output Code versus Input Signal DIFFERENTIAL INPUT SIGNAL VIN (AINP – AINN) IDEAL OUTPUT CODE(1) ≥ VREF +VREF (223 - 1) 0 7FFFFFh 000001h Checksum = MSB data byte + Mid data byte + LSB data byte + 9Bh. 000000h 32-Bit Conversion Data (CHKSUM = 1) -VREF (223 - 1) FFFFFFh 24-Bit Conversion Data (CHKSUM = 0) MSB £ -VREF 2 MID LSB CHECKSUM 23 23 800000h Flag = 1; Bit 0 of LSB Conversion Data 2 -1 (1) Excludes effects of noise, linearity, offset, and gain errors. DATA INTEGRITY Data readback integrity is augmented by a checksum byte and redundant data read capability. The checksum byte is the sum of three data conversion bytes, offset by 9Bh. Additionally, the data conversion bytes may be read multiple times by continuing to shift data past the initial read of 24 bits (32 bits if checksum is enabled). Copyright © 2009–2011, Texas Instruments Incorporated or Bit 7 of Checksum Figure 58. Checksum Byte and Out-of-Range Flag Table 17. Checksum Byte and Over-Range Flag FLAG REGISTER BIT CHKSUM REGISTER BIT 0 0 No checksum byte, no out-of-range flag 0 1 8-bit checksum byte, no out-of-range flag 1 0 No checksum byte, out-of-range flag replaces LSB (bit 0) of conversion data 1 1 7-bit checksum byte, out-of-range replaces MSB (bit 7) of checksum byte. DESCRIPTION 29 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com DATA RETRIEVAL New conversion data are available when DRDY goes low. Read the data within 20 fCLK cycles of the next DRDY falling edge or the data are incorrect. Do not read data during this interval. The conversion data may be read in two ways: Data Read in Continuous mode and Data Read in Stop Continuous mode. Data Read Operation in Continuous Mode The Read Data Continuous mode is cancelled by sending the Stop Read Data Continuous command (SDATAC). This operation occurs simultaneously with ADC conversion data on DOUT which can be ignored. Once the SDATAC command is sent, other commands may be sent to the ADS1259. Observe the SCLK and DRDY timing requirements, when reading data in this mode, as shown in Figure 59 and Table 18. In Read Data Continuous mode the conversion data may be shifted out directly without the need of the data read command. When DRDY (and DOUT, if CS is low) assert low, the conversion data are ready. The data are shifted out on DOUT on the rising edges of SCLK, with the most significant bit (MSB) clocked out first. In Gate Convert Mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Convert mode, DRDY remains low until a new conversion starts. As shown in Figure 60, the conversion data consist of three or four bytes (data MSB first), depending on whether the checksum byte is included. The data may be read multiple times by continuing to shift the data. The data read operation must be completed with 20 fCLK cycles of next DRDY falling edge. tDRSC DRDY SCLK tSCDR Figure 59. SCLK to DRDY Timing Table 18. SCLK and DRDY Timing Characteristics for Figure 57 SYMBOL tSCDR (1) tDRSC (1) DESCRIPTION MIN UNIT SCLK low before DRDY low(1) 20 tCLK DRDY falling edge to SCLK rising edge(1) 40 ns (1) These requirements apply only to reading conversion data in RDATAC mode. Data Ready DRDY Next Data Ready (1) CS (2) 1 SCLK DOUT DIN 9 17 25 33 (4) tUPDATE (3) Hi-Z (5) DATA MSB DATA MID DATA LSB CHECKSUM (6) (7) DATA MSB (8) (1) In Gate Convert Conversion mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Convert mode, DRDY remains low until the next conversion is started. (2) CS may be held low. If CS is low, DOUT asserts low with DRDY. (3) Data are updated on the rising edge of SCLK. DOUT is low until the first rising edge of SCLK. (4) tUPDATE = 20/fCLK. Do not read data during this time. (5) During this interval, DOUT follows DRDY. (6) Optional data checksum byte. (7) Optional repeat of previous conversion data. (8) Hold DIN low, except for transmission of the SDATAC (STOP Read Data Continuous command). Figure 60. Data Read Operation in Continuous Mode 30 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Data Read Operation in Stop Continuous Mode As shown in Figure 61, after sending the RDATA command the data are shifted out on DOUT on the rising edges of SCLK. The MSB is clocked out on the first rising edge of SCLK. In Gate Control mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Control mode, DRDY remains low until a new conversion is started. In Stop Read Data Continuous mode, a read data command (RDATA) must be sent for each new data read operation. New conversion data are ready when DRDY falls low or the DRDY register bit transitions low. The data read operation may then occur. The read data command must be sent at least 20 fCLK cycles before the DRDY falling edge or the data are incorrect. Do not the read data command during this time. The conversion data consist of three or four bytes (MSB first), depending on whether the checksum byte is included. The data may be read multiple times by continuing to shift the data. Data Ready DRDY Next Data Ready (1) (3) tUPDATE CS (2) 1 9 17 25 33 41 SCLK DOUT DIN (7) Hi-Z (4) 012h DATA MSB DATA MID DATA LSB CHECKSUM (5) (6) DATA MSB (8) (1) In Gate Control mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Control mode, DRDY remains low until the next conversion is started. The DRDY pin or DRDY register bit can also be polled to determine when data are ready. (2) CS may be held low. (3) tUPDATE = 20/fCLK. Do not issue the Read Data opcode during this time. (4) During this interval, DOUT does not follow DRDY (stop continuous mode). (5) Optional conversion data checksum. (6) Optional repeat of previous conversion data. (7) DIN data are latched on the falling edge of SCLK. Data are output on the rising edges of SCLK. (8) Read Data command = 012h. Figure 61. Data Read Operation in STOP Continuous Mode Copyright © 2009–2011, Texas Instruments Incorporated 31 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com COMMAND DEFINITIONS The commands summarized in Table 19 control and configure the operation of the ADS1259. The commands are stand-alone, except for the register read and register write operations which require a second command byte plus data. CS can be taken high or held low between opcode commands but must stay low for the entire command operation. Note that the Read Data Continuous mode must be cancelled by the Stop Read Data Continuous mode opcode (SDATAC) before sending further commands. Table 19. Command Definitions (1) COMMAND TYPE DESCRIPTION FIRST OPCODE BYTE WAKEUP Control Wake up from SLEEP mode 0000 001x (02h or 03h) (2) SLEEP Control Begin SLEEP mode 0000 010x (04h or 05h) (2) RESET Control Reset to power-up values 0000 011x (06h or 07h) (2) START Control START conversion 0000 100x (08h or 09h) (2) STOP Control STOP conversion 0000 101x (0Ah or 0Bh) (2) RDATAC Control Set Read Data Continuous mode 0001 0000 (10h) SDATAC Control Stop Read Data Continuous mode 0001 0001 (11h) RDATA Data Read data by opcode 0001 001x (12h or 13h) (2) (1) (2) SECOND OPCODE BYTE RREG Register Read nnnn register at address rrrr 0010 rrrr (20h + 0000 rrrr) 0000 nnnn (00h + nnnn) WREG Register Write nnnn register at address rrrr 0100 rrrr (40h + 0000 rrrr) 0000 nnnn (00h + nnnn) OFSCAL Calibration Offset calibration 0001 1000 (18h) GANCAL Calibration Gain calibration 0001 1001 (19h) nnnn = number of registers to be read/written – 1. For example, to read/write 3 registers, set nnnn = 2 (0010). rrrr = starting register address for read/write opcodes. These commands are decoded on the seventh bit of the opcode. The eighth bit is a don't care bit. All other commands are decoded on the eighth bit. WAKEUP: Exit SLEEP Mode Description: This command exits the low-power SLEEP mode; see the SLEEP Mode section. SLEEP: Enter SLEEP Mode Description: This command enters the low-power SLEEP mode. See the SLEEP Mode section. RESET: Reset Registers to Default Values Description: This command resets the digital filter cycle and returns all register settings to the default values. START: Start Conversions Description: This command starts data conversions. If PULSE bit = 1, then a single conversion is performed. If PULSE bit = 0, then conversions continue until the STOP command is sent. Tie the START pin low to control conversions by command. STOP: Stop Conversions Description: This command stops conversions. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. See the Conversion Control section. Tie the START pin low to control conversions by command. RDATAC: Read Data Continuous Description: This command enables the Read Data Continuous mode (default). See the Read Data Continuous Mode section for details. Disable this mode with the SDATAC command before sending other commands. SDATAC: Stop Read Data Continuous Description: This command cancels the Read Data Continuous mode. 32 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com RDATA: Read Data Description: Issue this command opcode after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). See the Read Data Mode section for more details. RREG: Read from Registers Description: These opcode bytes read register data. The Register Read command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1. First opcode byte: 0010 rrrr, where rrrr is the starting register address. Second opcode byte: 0000 nnnn, where nnnn is the number of registers to read. The 17th SCLK rising edge of the operation clocks out the MSB of the first register. (1) CS 1 9 17 25 SCLK DIN OPCODE 1 DOUT OPCODE 2 REG DATA REG DATA + 1 (1) CS may be tied low. Figure 62. RREG Command Example: Read Two Registers Starting from Register 00h (CONFIG0) (OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001) Copyright © 2009–2011, Texas Instruments Incorporated 33 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com WREG: Write to Register Description: These two opcode bytes write register data. The Register Write command is a two-byte opcode followed by the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to write – 1. First opcode byte: 0100 rrrr, where rrrr is the starting register address. Second opcode byte: 0000 nnnn, where nnnn is the number of registers to write After the opcode bytes, the register data follows (in MSB-first format). (1) CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2 DOUT (1) CS may be tied low. Figure 63. WREG Command Example: Write Two Registers Starting from 00h (CONFIG0) (OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001) OFSCAL: Offset Calibration Description: This command performs an offset calibration. Apply a zero signal and allow the input to stabilize before sending the command; see the Calibration section for more details. GANCAL: Gain Calibration Description: This command performs a gain calibration. Apply a full-scale signal and allow the input to stabilize before sending the command; see the Calibration section for more details. 34 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com REGISTER MAP The operation of the ADS1259 is controlled through a set of registers. Collectively, the registers contain all the information needed to configure the part, such as data rate, calibration, etc. Table 20 shows the register map. Table 20. Register Map ADDRESS REGISTER RESET VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 0h CONFIG0 10XX0101b 1 0 ID1 ID0 0 RBIAS 0 SPI 1h CONFIG1 00001000b FLAG CHKSUM 0 SINC2 EXTREF DELAY2 DELAY1 DELAY0 2h CONFIG2 XX000000b DRDY EXTCLK SYNCOUT PULSE 0 DR2 DR1 DR0 3h OFC0 00000000b OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 4h OFC1 00000000b OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 5h OFC2 00000000b OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 6h FSC0 00000000b FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 7h FSC1 00000000b FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 8h FSC2 01000000b FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 BIT 0 CONFIG0: CONFIGURATION REGISTER 0 (Address = 0h) 7 6 5 4 3 2 1 0 1 0 ID1 ID0 0 RBIAS 0 SPI Reset value = 10XX0101b. Bit 7 Reserved (read-only) Always returns '1'. Bit 6 Reserved (read-only) Always returns '0'. Bits 5-4 ID[1:0]: Factory-programmed identification bits (read-only) (Note that these bits may change without notification.) Bit 3 Reserved Always write '0'. Bit 2 RBIAS: Internal reference bias 0 = Internal reference bias disabled 1 = Internal reference bias enabled (default) Bit 1 Reserved Always write '0'. Bit 0 SPI: SCLK timeout of SPI interface 0 = SPI timeout disabled 1 = SPI timeout enabled (default), when SCLK is held low for 216 clock cycles Copyright © 2009–2011, Texas Instruments Incorporated 35 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com CONFIG1: CONFIGURATION REGISTER 1 (Address = 1h) 7 6 5 4 3 2 1 0 FLAG CHKSUM 0 SINC2 EXTREF DELAY2 DELAY1 DELAY0 Reset value = 00001000b. Bit 7 FLAG: Out-of-range flag 0 = Disabled (default) 1 = Enabled: replaces bit 24 (LSB) of the conversion data with the out-of-range bit; if the CHKSUM byte is enabled, bit 7 of the checksum byte Bit 6 CHKSUM: Checksum 0 = Disabled (default) 1 = Conversion data checksum byte included in readback Bit 5 Reserved Always write '0'. Bit 4 SINC2: Digital filter mode 0 = sinc1 filter (default) 1 = sinc2 filter Bit 3 EXTREF: Reference select 0 = Internal 1 = External (default) Bits 2-0 DELAY[2:0]: START conversion delay 000 001 010 011 100 101 110 111 36 = = = = = = = = No delay (default) 64 tCLK 128 tCLK 256 tCLK 512 tCLK 1024 tCLK 2048 tCLK 4096 tCLK Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com CONFIG2: CONFIGURATION REGISTER 2 (Address = 2h) 7 6 5 4 3 2 1 0 DRDY EXTCLK SYNCOUT PULSE 0 DR2 DR1 DR0 Reset value = XX000000b. Bit 7 DRDY: Data ready (read-only) This bit duplicates the state of the DRDY pin. Poll this bit to indicate that data are ready. When DRDY is low, data are ready. Bit 6 EXTCLK: Clock source (read-only) 0 = Device clock source is internal oscillator 1 = Device clock source is external clock Note that the ADS1259 selects the clock source automatically. Bit 5 SYNCOUT: SYNCOUT clock enable 0 = SYNCOUT disabled (default) 1 = SYNCOUT enabled Note that if disabled, the output is driven low. Bit 4 PULSE: Conversion Control mode select 0 = Gate Control mode (default) 1 = Pulse Control mode Bit 3 Reserved Always write '0' Bits 2-0 DR[2:0] Data rate setting 000 = 10SPS (default) 001 = 16.6SPS 010 = 50SPS 011 = 60SPS 100 = 400SPS 101 = 1200SPS 110 = 3600SPS 111 = 14400SPS NOTE: fCLK = 7.3728MHz Copyright © 2009–2011, Texas Instruments Incorporated 37 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com OFC0: OFFSET CALIBRATION BYTE 0, LEAST SIGNIFICANT BYTE (Address = 3h) 7 6 5 4 3 2 1 0 OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 Reset value = 00000000b. OFC1: OFFSET CALIBRATION BYTE 1 (Address = 4h) 7 6 5 4 3 2 1 0 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 Reset value = 00000000b. OFC2: OFFSET CALIBRATION BYTE 2, MOST SIGNIFICANT BYTE (Address = 5h) 7 6 5 4 3 2 1 0 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 Reset value = 00000000b. FSC0: FULL-SCALE CALIBRATION BYTE 0, LEAST SIGNIFICANT BYTE (Address = 6h) 7 6 5 4 3 2 1 0 FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 Reset value = 00000000b. FSC1: FULL-SCALE CALIBRATION BYTE 1 (Address = 7h) 7 6 5 4 3 2 1 0 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 Reset value = 00000000b. FSC2: FULL-SCALE CALIBRATION BYTE 2, MOST SIGNIFICANT BYTE (Address = 8h) 7 6 5 4 3 2 1 0 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 Reset value = 01000000b. 38 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com BASIC CONNECTION The ADS1259 basic connections are shown in Figure 64. The diagram shows the ADS1259 operating with an internal oscillator and with internal reference. Dual ±2.5V analog power supplies are also shown. Pins 6-9 are the SPI port connection. The remaining digital I/O pins connect to the controller I/O. Note that the minimum configuration of the digital I/O may include only SCLK, DIN, and DOUT. +2.5V (1) (+) 20W to 50W 1 10nF Signal Input (-) (2) 2 AINN 3 20W to 50W Controller I/O 4 4.7kW 5 Drives the PGA280 SYNCIN Pin ADS1259 AINP VREFN START VREFP SYNCOUT CS 7 Controller SPI Port 8 9 Controller I/O AVSS RESET/PWDN 6 1MW AVDD SCLK DIN REFOUT DVDD DGND BYPASS DOUT XTAL2 DRDY XTAL1/CLKIN 10 1mF 20 -2.5V 19 1 mF 18 17 + 1mF + 1mF + 16 15 +3.3V 1mF 14 13 2.5V Reference Output + 1mF 12 11 1MW (1) It is recommended to buffer the ADS1259 inputs. The output isolation resistors may be incorporated within the amplifier feedback loop. (2) Low distortion C0G or film capacitor recommended. Figure 64. ADS1259 Basic Connection Diagram LAYOUT Place the input buffer and input decoupling capacitors close to the ADS1259 inputs. The bypass capacitors for power-supply and reference decoupling should also be placed close to the device. In some cases, it may be necessary to use a split ground plane in which digital return currents of external components are routed away from the ADS1259. In this case, connect the grounds at the power supply. CONFIGURATION GUIDE Configuration of the ADS1259 involves configuring the device hardware (power supply, I/O pins, etc) and device register settings. The registers are configured by commands sent via the device SPI port. Power Supplies The ADS1259 analog section operates either with a single +5V or dual ±2.5V supplies. The digital section operates from +2.7V to +5V. The digital and analog power supplies may be tied together (+5V only). Reference Select either the internal reference or an external reference for the ADS1259 (see the Reference section). The default is external reference. Figure 64 depicts the internal reference connection. Clock Choose the desired clock source (see the Clock Source section). Figure 64 depicts the internal clock operation. Copyright © 2009–2011, Texas Instruments Incorporated 39 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com SYNCOUT Pin Connect the SYNCOUT pin to the SYNCIN pin of the PGA280, using a 4.7kΩ series resistor (placed close to the ADS1259). The 1MΩ pull-down resistor is required when the ADS1259 is in power-down mode. RESET/PWDN Pin This pin must be high in normal operation. If it is desired to completely power down the device, or to have a hardware reset control, then connect this pin to a controller. If these functions are not needed, tie the pin high. (Note that the device can both be reset and SLEEP mode engaged by commands.) START Pin If it is desired to control conversions by pin, connect this line to the controller. Otherwise, this line can be tied high to free-run conversions. The conversions can also be controlled by software commands. In this case, tie the START pin low. DRDY Pin DRDY is an output that indicates when data are ready for readback. Note that the DOUT pin (and also the DRDY register bit) indicates when data are ready as well, so DRDY connection to a controller is optional. CS Pin If the ADS1259 is a single device connected to the SPI bus, then CS can be tied low. Otherwise, for applications where the ADS1259 shares the bus with another device, CS must be connected. DOUT Pin When the ADS1259 SPI is deselected (CS = 1), the DOUT pin is in 3-state mode. A pull-down resistor may be necessary to prevent floating the controller input pin. Miscellaneous Digital I/O Avoid ringing on the digital inputs and outputs. Resistors in series with the trace driving end helps to reduce ringing by controlling impedances. SOFTWARE GUIDE After the power supplies have fully established, allow a minimum of 216 system clocks before beginning communication to the device. The registers can then be configured by commands via the SPI port. The following steps detail a suggested procedure to initialize the ADS1259. 1. Send the SDATAC command . This command cancels the RDATAC mode. RDATAC mode must be cancelled before the register write commands. 2. Send the register write command. The following example shows the register write as a block of nine bytes, starting at register 0 (CONFIG0). BYTES DATA OPERATION 1, 2 01000000, 00001000 Write register opcode bytes, starting at address 0, 9-byte block 3 00000101 CONFIG0; register data, bias the reference, SPI timeout 4 01010000 CONFIG1; checksum enabled, sinc2 filter selection, internal reference 5 00000011 CONFIG2; Gate Convert mode, 60SPS 6, 7, 8 00000000, 00000000, 00000000 OFC[2:0]; 3 bytes for offset, no offset correction 9, 10, 11 00000000, 00000000, 01000000 FSC[2:0]; 3 bytes for gain, no full-scale correction 40 Copyright © 2009–2011, Texas Instruments Incorporated ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com 3. Optional readback verification of the register data READ register command: , The nine bytes of readback data that follow represent the nine register bytes. 4. Take the START pin high or send the START command to start conversions. 5. Optionally, send the RDATAC command . This permits reading of conversion data without the need of the read data command. Otherwise, the read data opcode must be sent to read each conversion result. 6. When the DRDY pin or the DRDY bit goes low, or when DOUT transitions low, read the data. PGA280 APPLICATION Figure 65 shows the ADS1259 connected to the PGA280. The PGA280 is a programmable gain, fully-differential instrumentation amplifier that is ideally suited to drive the ADS1259. The amplifier features ±5V to ±18V supply input section that accepts wide ranging signal levels and features a +5V output section that matches the ADS1259 low-voltage inputs. The ADS1259 +2.5V REFOUT drives the PGA280 VOCM pin to level shift the signal. The ADS1259 provides a clock output (SYNCOUT) that drives the PGA280 (GPIO6) chopping clock input. An optional extended CS (ECS) function feature of the PGA280 (GPIO0) allows use of one CS to alternately select each device for SPI communication. Additionally, the optional BUFA trigger output of the PGA280 (GPIO5) starts the ADS1259 conversions. The trigger can be delayed to occur after an input multiplexer change. The delay allows settling of the PGA280 before the ADC conversion begins. VSN (1) 1mF VSOP 9 VOP INP1 2 50W 10 INN1 7 MUX PGA VOCM 3 VON 1 INP2 8 1 10nF (3) 1mF 50W INN2 16 GPIO5 PGA280 GPIO0 17 14 16 24 13 18 AVDD VREFP VREFN RESET/PWDN 5 DRDY 8 DIN DOUT SYNCOUT START SCLK ADS1259 100kW 9 7 SPI 6 1MW (1) Controller 10 REFOUT CS +3.3V 5 3 AINP AINN 4 19 VSON SCLK SDO SDI 15 DVDD DGND CS 12 4.7kW 18 17 2 (2) GPIO6 20 1mF 19 15 14 BYPASS VSP 4 XTAL2 11 1 mF + XTAL1 6 +5V (1) DGND -15V DVDD (1) AVSS +15V 11 12 13 1mF (1) Refer to the PGA280 product data sheet for power-supply bypassing recommendations. (2) Locate this resistor as close as possible to pin 5 of the ADS1259. (3) C0G or film capacitor. Figure 65. PGA280 Driving the ADS1259 Copyright © 2009–2011, Texas Instruments Incorporated 41 ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2010) to Revision D Page • Added Internal Voltage Reference, Long-term stability parameter to Electrical Characteristics table ................................. 3 • Added Internal Voltage Reference, Thermal hysteresis parameter and footnote 11 to Electrical Characteristics table ...... 3 • Added Figure 31 ................................................................................................................................................................. 11 • Added Thermal Hysteresis subsection to Reference section ............................................................................................. 17 Changes from Revision B (January 2010) to Revision C Page • Changed ADS1259B and ADS1259 Internal Voltage Reference, Accuracy parameter in the Electrical Characteristics ...................................................................................................................................................................... 3 • Changed ADS1259 Internal Voltage Reference, Temperature drift parameter in the Electrical Characteristics ................. 3 • Added Figure 23, ADS1259 internal reference voltage versus temperature graph ............................................................ 10 • Added PGA280 Application section .................................................................................................................................... 41 42 Copyright © 2009–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1259BIPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 ADS1259B ADS1259BIPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 ADS1259B ADS1259IPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 ADS1259 ADS1259IPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 ADS1259 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of