ADS1262IPWR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 ADS126x 32-Bit, Precision, 38-kSPS, Analog-to-Digital Converter (ADC) with Programmable Gain Amplifier (PGA) and Voltage Reference 1 Features • • • • • • 1 • • • • • • • 3 Description The ADS1262 and ADS1263 are low-noise, low-drift, 38.4-kSPS, delta-sigma (ΔΣ) ADCs with an integrated PGA, reference, and internal fault monitors. The ADS1263 integrates an auxiliary, 24-bit, ΔΣ ADC intended for background measurements. The sensorready ADCs provide complete, high-accuracy, onechip measurement solutions for the most-demanding sensor applications, including weigh scales, straingauge sensors, thermocouples, and resistance temperature devices (RTD). Precision, 32-bit, ΔΣ ADC Auxiliary 24-Bit, ΔΣ ADC (ADS1263) Data Rates: 2.5 SPS to 38400 SPS Differential Input, CMOS PGA 11 Multifunction Analog Inputs High-Accuracy Architecture – Offset Drift: 1 nV/°C – Gain Drift: 0.5 ppm/°C – Noise: 7 nVRMS (2.5 SPS, Gain = 32) – Linearity: 3 ppm 2.5-V Internal Voltage Reference – Temperature Drift: 2 ppm/°C 50-Hz and 60-Hz Rejection Single-Cycle Settled Conversions Dual Sensor Excitation Current Sources Internal Fault Monitors Internal ADC Test Signal 8 General-Purpose Input/Outputs The ADCs are comprised of a low-noise, CMOS PGA (gains 1 to 32), a ΔΣ modulator, followed by a programmable digital filter. The flexible analog frontend (AFE) incorporates two sensor-excitation current sources suitable for direct RTD measurement. A single-cycle settling digital filter maximizes multipleinput conversion throughput, while providing 130-dB rejection of 50-Hz and 60-Hz line cycle interference. The ADS1262 and ADS1263 are pin and functional compatible. These devices are available in a 28-pin TSSOP package and are fully specified over the –40°C to +125°C temperature range. 2 Applications • • • • • Device Information(1) PART NUMBER High-Resolution PLCs Temperature, Pressure Measurement Weigh Scales and Strain-Gauge Digitizers Panel Meters, Chart Recorders Analytical Instrumentation TSSOP (28) ADS1263 0.25 +3.3 V Input Range = r78 mV 0.2 Data Rate = 20 SPS 0.15 Noise = 0.16 PVP-P DVDD 2.5-V Ref ADS1262 ADS1263 Ref Mux AIN0 +Sig AIN1 ±Sig AIN2 ±Sen AIN3 Bridge Dual Sensor Excitation Sensor Test Ref Alarm Buf START RESET/PWDN AIN4 AIN5 ±Exc AIN6 AIN7 PGA AIN8 Pt 100 Input Mux AIN9 32-Bit ûADC Digital Filter Serial Interface and Control DIN DOUT/DRDY SCLK Signal Alarm AINCOM CS DRDY GPIO PGA Level Shift Temp Sensor 24-Bit ûADC ADS1263 Only Test V AVSS Digital Filter Internal Oscillator Clock Mux DGND ADC Output (PV) +Exc +Sen 9.70 mm × 4.40 mm ADC Conversion Noise +5 V AVDD BODY SIZE (NOM) (1) For all available packages, see the package option addendum at the end of the data sheet. Temperature Compensated Bridge Measurement REFOUT PACKAGE ADS1262 0.1 0.05 0 -0.05 -0.1 -0.15 XTAL2 XTAL1/CLKIN -0.2 -0.25 0 1 2 3 4 5 6 Time (s) 7 8 9 10 D017 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison ............................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 4 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 8 Timing Requirements: Serial Interface.................... 11 Switching Characteristics: Serial Interface.............. 12 Typical Characteristics ............................................ 13 Parameter Measurement Information ................ 24 8.1 8.2 8.3 8.4 8.5 8.6 Offset Temperature Drift Measurement .................. 24 Gain Temperature Drift Measurement .................... 24 Common-Mode Rejection Ratio Measurement....... 24 Power-Supply Rejection Ratio Measurement ......... 24 Crosstalk Measurement (ADS1263) ....................... 25 Reference-Voltage Temperature-Drift Measurement ........................................................... 25 8.7 Reference-Voltage Thermal-Hysteresis Measurement ........................................................... 25 8.8 Noise Performance ................................................. 26 9 9.1 9.2 9.3 9.4 9.5 9.6 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes....................................... Programming.......................................................... Register Maps ......................................................... 30 31 32 61 85 88 10 Application and Implementation...................... 106 10.1 10.2 10.3 10.4 Application Information........................................ Typical Applications ............................................ Dos and Don'ts.................................................... Initialization Setup ............................................... 107 114 119 120 11 Power-Supply Recommendations ................... 122 11.1 Power-Supply Decoupling................................... 122 11.2 Analog Power-Supply Clamp .............................. 123 11.3 Power-Supply Sequencing.................................. 123 12 Layout................................................................. 124 12.1 Layout Guidelines ............................................... 124 12.2 Layout Example .................................................. 125 13 Device and Documentation Support ............... 126 13.1 13.2 13.3 13.4 13.5 Related Links ...................................................... Community Resources........................................ Trademarks ......................................................... Electrostatic Discharge Caution .......................... Glossary .............................................................. 126 126 126 126 126 14 Mechanical, Packaging, and Orderable Information ......................................................... 126 Detailed Description ............................................ 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2015) to Revision B Page • Changed ADS1263 from product preview to production data, and added text and specifications throughout data sheet to include the ADS1263 and ADC2 .............................................................................................................................. 1 • Changed text throughout data sheet for clarity ...................................................................................................................... 1 • Added condition line to Absolute Maximum Ratings table ..................................................................................................... 6 • Added Crosstalk section to Electrical Characteristics table ................................................................................................... 9 • Added Figure 32 ................................................................................................................................................................... 17 • Added Figure 36 ................................................................................................................................................................... 18 • Changed legend in Figure 45 ............................................................................................................................................... 19 • Added missing gain term in FSR definition of Equation 8 .................................................................................................... 26 • Changed text in fourth paragraph of Noise Performance section to clarify conditions to achieve maximum ENOB ........... 26 • Changed bit names from PGAH and PGAL to PGAH_ALM and PGAL_ALM, respectively, in PGA Absolute OutputVoltage Monitor section ........................................................................................................................................................ 40 • Changed Figure 77 to show correct name of bit 4 ............................................................................................................... 41 • Changed RMUX to RMUXP in second paragraph of ADC Reference Voltage section ....................................................... 41 • Changed text in last paragraph of ADC Reference Voltage section to show correct name of bit 4 .................................... 41 • Changed text in External Reference section to clarify external reference inputs, polarity reversal switch, reference input current, and external reference buffer ......................................................................................................................... 42 • Changed text in Power-Supply Reference section to clarify use of power-supply reference in critical applications ........... 42 2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Revision History (continued) • Changed text in last paragraph of Sensor-Excitation Current Sources (IDAC1 and IDAC2) section to clarify settling time in IDAC rotation mode .................................................................................................................................................. 44 • Added ADC1 Modulator section ........................................................................................................................................... 45 • Changed text in General-Purpose Input/Output (GPIO) section regarding GPIO data readback when programmed as an output.......................................................................................................................................................................... 52 • Changed Figure 92............................................................................................................................................................... 52 • Changed TSIGP and TSIGN to TDACP and TDACN, respectively, in the last paragraph of the Test DAC (TDAC) section .................................................................................................................................................................................. 54 • Changed text in Test DAC (TDAC) section allowing for any common-mode value instead of 0 V...................................... 54 • Added note (1) to Figure 95 ................................................................................................................................................ 57 • Changed th(DRSP) value of 16 from max to min...................................................................................................................... 61 • Added stop-start sequence text to restart conversions in Continuous Conversion Mode section ....................................... 61 • Deleted software polling text from Data Ready (DRDY) section.......................................................................................... 67 • Added Conversion Data Software Polling section................................................................................................................ 67 • Added text to clarify data reset at conversion restart ........................................................................................................... 68 • Added text to Read Data Direct (ADC1) section to clarify conversion restart...................................................................... 68 • Changed Figure 108 to show complete list of CRC bit settings ........................................................................................... 68 • Changed text in Read Data by Command section to clarify software polling ...................................................................... 69 • Changed Figure 109 to show complete list of CRC bit settings ........................................................................................... 69 • Added text to Offset Calibration Registers section regarding offset calibration register disabled in chop mode................. 76 • Added new step 1 to Calibration Command Procedure section........................................................................................... 79 • Added text to WREG Command section regarding conversion restart ................................................................................ 87 • Changed text in 2nd paragraph of Register Map section..................................................................................................... 88 • Changed Group Update column of Table 38 ...................................................................................................................... 88 • Added software polling to Figure 159................................................................................................................................. 120 Changes from Original (February 2015) to Revision A • Page Changed ADS1262 from product preview to production data ................................................................................................ 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 3 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 5 Device Comparison PRODUCT INPUTS ADS1262 11 AUXILIARY 24-BIT ADC No ADS1263 11 Yes 6 Pin Configuration and Functions PW Package 28-Pin TSSOP Top View (Not To Scale) 4 AIN8 1 28 AIN7 AIN9 2 27 AIN6 AINCOM 3 26 AIN5 CAPP 4 25 AIN4 CAPN 5 24 AIN3 AVDD 6 23 AIN2 AVSS 7 22 AIN1 REFOUT 8 21 AIN0 START 9 20 RESET/PWDN CS 10 19 DVDD SCLK 11 18 DGND DIN 12 17 BYPASS DOUT/DRDY 13 16 XTAL2 DRDY 14 15 XTAL1/CLKIN Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Pin Functions PIN I/O DESCRIPTION NO. NAME 1 AIN8 Analog input/output Analog input 8, IDAC1, IDAC2, GPIO5 2 AIN9 Analog input/output Analog input 9, IDAC1, IDAC2, GPIO6 3 AINCOM Analog input/output Analog input common, IDAC1, IDAC2, GPIO7, VBIAS 4 CAPP Analog output PGA output P: connect a 4.7-nF C0G dielectric capacitor from CAPP to CAPN 5 CAPN Analog output PGA output N: connect a 4.7-nF C0G dielectric capacitor from CAPP to CAPN 6 AVDD Analog Positive analog power supply Negative analog power supply 7 AVSS Analog 8 REFOUT Analog Output 9 START Digital Input Start conversion control 10 CS Digital Input Serial interface chip select (active low) 11 SCLK Digital Input Serial interface shift clock 12 DIN Digital Input Serial interface data input 13 DOUT/DRDY Digital output Serial interface data output and data ready indicator (active low) 14 DRDY Digital output Data ready indicator (active low) 15 XTAL1/CLKIN Digital Input 1) Internal oscillator: Connect to DGND 2) External clock: Connect clock input 3) Crystal oscillator: Connect to crystal and crystal load capacitor 16 XTAL2 Digital Input 1) Internal oscillator: No connection (float) 2) External clock: No connection (float) 3) Crystal oscillator: Connect to crystal and crystal load capacitor 17 BYPASS Analog Output 18 DGND Digital Digital ground 19 DVDD Digital Digital power supply 20 RESET/PWDN Digital input 21 AIN0 Analog input/output Analog input 0, REFP1, IDAC1, IDAC2 22 AIN1 Analog input/output Analog input 1, REFN1, IDAC1, IDAC2 23 AIN2 Analog input/output Analog input 2 ,REFP2, IDAC1, IDAC2 24 AIN3 Analog input/output Analog input 3, REFN2, IDAC1, IDAC2, GPIO0 25 AIN4 Analog input/output Analog input 4, REFP3, IDAC1, IDAC2, GPIO1 26 AIN5 Analog input/output Analog input 5, REFN3, IDAC1, IDAC2, GPIO2 27 AIN6 Analog input/output Analog input 6, IDAC1, IDAC2, GPIO3, TDACP 28 AIN7 Analog input/output Analog input 7, IDAC1, IDAC2, GPIO4, TDACN Internal reference voltage output, connect 1-µF capacitor to AVSS 2-V sub-regulator external bypass; connect 1-µF capacitor to DGND Reset (active low); hold low to power down the ADC Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 5 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.3 7 V AVSS to DGND –3 0.3 V DVDD to DGND –0.3 7 V Analog input VAVSS – 0.3 VAVDD + 0.3 V Digital input VDGND – 0.3 VDVDD + 0.3 AVDD to AVSS Voltage Current Temperature (1) (2) V Input current (2) –10 10 mA Junction, TJ –50 150 °C Storage, Tstg -60 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds VAVDD + 0.3 V or is below VAVSS – 0.3 V, or if the digital input voltage exceeds VDVDD + 0.3 V or is below VDGND – 0.3 V. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT VAVDD to VAVSS 4.75 5 5.25 V VAVSS to VDGND –2.6 0 V VDVDD to VDGND 2.7 5.25 V –VREF / Gain VREF / Gain V POWER SUPPLY Analog power supply Digital power supply ADC1 ANALOG INPUTS FSR VINP,VINN Full-scale differential input voltage range (1) PGA enabled Absolute input voltage (2) PGA bypassed See Equation 12 V VAVSS – 0.1 VAVDD + 0.1 V –VREF / Gain VREF / Gain V VAVSS – 0.1 VAVDD + 0.1 V ADC2 ANALOG INPUTS (ADS1263) Full-scale differential input voltage range Gain = 1, 2 and 4 Absolute input voltage Gain = 8 to 128 See Equation 15 V VOLTAGE REFERENCE INPUTS VREF Differential reference voltage VREFN Negative reference voltage VREFP Positive reference voltage VAVDD – VAVSS + 0.2 V VAVSS – 0.1 VREFP – 0.9 V VREFN + 0.9 VAVDD + 0.1 V VREF = VREFP – VREFN 0.9 CLOCK INPUT fCLK External clock frequency 1 External clock duty cycle 30% External crystal frequency 1 7.3728 8 MHz 70% 7.3728 8 MHz GENERAL-PURPOSE INPUT/OUTPUT (GPIO) Input voltage VAVSS VAVDD V VDGND VDVDD V –40 125 °C DIGITAL INPUTS (other than GPIO) Input voltage TEMPERATURE TA (1) (2) Operating ambient temperature FSR is the ideal full-scale differential input voltage range, excluding noise, offset and gain errors. For ADC1, the maximum FSR is achieved with VREF = 5 V and the PGA bypassed. If the PGA is enabled and VREF = 5 V, the FSR is limited by the PGA input range. For ADC2, if VREF = 5 V and gains = 8 to 128 then FSR is limited by the PGA input range. VINP, VINN = Absolute Input Voltage. VIN = Differential Input Voltage = VINP – VINN. 7.4 Thermal Information ADS126x THERMAL METRIC (1) PW (TSSOP) UNIT 28 PINS RθJA Junction-to-ambient thermal resistance 65.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 13.6 °C/W RθJB Junction-to-board thermal resistance 23.6 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 23.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 7 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 7.5 Electrical Characteristics Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC1 ANALOG INPUTS Absolute input current Differential input current Differential input impedance Channel-to-channel crosstalk Gain = 32 2 nA PGA bypassed 150 nA Gain = 32 0.1 nA PGA bypassed, VIN = 5 V 150 nA 1 GΩ PGA enabled PGA bypassed 40 MΩ DC, VAVSS ≤ VINX ≤ VAVDD 0.5 µV/V ADC1 PERFORMANCE PGA gain DR 1, 2, 4, 8, 16, 32 Resolution 32 Data rate 2.5 Noise performance INL Integral nonlinearity VOS Offset voltage GE Gain error Gain drift NMRR Normal-mode rejection ratio (2) CMRR Common-mode rejection ratio (3) PSRR Power-supply rejection ratio (4) 38400 SPS ppm See Table 1 Gain = 1 to 32, PGA bypassed TA = 25°C 3 12 Chop mode off 350 / Gain 800 / Gain µV Chop mode on ±0.1 / Gain ±0.5 / Gain µV After calibration (1) Offset voltage drift V/V Bits Noise / 4 Chop mode off 30 / Gain + 10 100 / Gain + 50 Chop mode on TA = 25°C, gain = 1 to 32 After calibration (1) 1 5 ±50 ±300 nV/°C nV/°C ppm Noise / 4 Gain = 1 to 32, and PGA bypassed 0.5 4 ppm/°C See Table 11 fIN = 60 Hz, data rate = 20 SPS 130 dB 100 120 dB AVDD and AVSS 80 90 dB DVDD 80 120 dB fIN = 60 Hz, data rate = 400 SPS ADC2 ANALOG INPUTS (ADS1263) Absolute input current Gain = 16 2 nA Differential input current Gain = 16 0.5 nA ADC2 PERFORMANCE (ADS1263) DR Gain 1, 2, 4, 8, 16, 32, 64, 128 V/V Resolution 24 Bits Data rate 10, 100, 400, 800 Noise performance Gain = 1 to 64 4 20 ppm Gain = 128 7 30 ppm ±150 ±500 µV 30 200 nV/°C ±500 ±3000 1 5 INL Integral nonlinearity VOS Offset voltage TA = 25°C, gain = 1 to 128 Offset voltage drift Gain = 1 to 128 Gain error TA = 25°C, gain = 1 to 128 Gain drift Gain = 1 to 128 GE NMRR Normal-mode rejection ratio CMRR Common-mode rejection ratio PSRR Power-supply rejection ratio (1) (2) (3) (4) 8 SPS See Table 3 ppm ppm/°C See Table 15 fIN = 60 Hz, DR = 10 SPS 110 dB fIN = 60 Hz, DR = 400 SPS, gain = 8 75 90 dB AVDD and AVSS 75 90 dB Offset and gain calibration accuracy on the order of ADC conversion noise/4. Conversion noise depends on data rate and PGA gain. Normal-mode rejection ratio depends on the digital filter setting. Common-mode rejection ratio is specified at date rate 20 SPS and 400 SPS. Power-supply rejection ratio is specified at dc. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Electrical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CROSSTALK Crosstalk ADC1 to ADC2 20 µV/V ADC2 to ADC1 1 µV/V EXTERNAL VOLTAGE REFERENCE INPUTS Reference input current (5) ADC1 150 ADC2 1 nA nA Input current vs voltage VREF = 2 V to 4.8 V, ADC1 10 nA/V Input current drift ADC1 0.1 nA/°C Input impedance Differential, ADC1 50 Low reference monitor Threshold, ADC1 0.4 MΩ 0.6 V INTERNAL VOLTAGE REFERENCE Reference voltage Initial accuracy 2.5 TA = 25°C V ±0.1% ±0.2% TA = 0°C to +85°C 2 6 ppm/°C TA = –40°C to +105°C 4 12 ppm/°C Reference voltage long term drift TA = 85°C, 1st 1000 hr 50 Thermal hysteresis First 0°C to 85°C cycle 50 Reference voltage temperature drift Output current ppm -10 10 Load regulation Start-up time ppm Settling time to ±0.001% final value mA 40 µV/mA 50 ms TEMPERATURE SENSOR Voltage TA = 25°C 122.4 Temperature coefficient mV 420 µV/°C CURRENT SOURCES (IDAC1, IDAC2) 50, 100, 250, 500, 750, 1000, 1500, 2000, 2500, 3000 Currents Compliance range All currents Absolute error All currents ±0.7% ±4% IDAC1 current = IDAC2 current ±0.1% ±1% IDAC1 current ≠ IDAC2 current ±1% Match error Temperature drift VAVSS µA VAVDD – 1.1 Absolute 50 Match 5 V ppm/°C 20 ppm/°C LEVEL-SHIFT VOLTAGE Voltage (VAVDD + VAVSS) / 2 Output impedance V Ω 100 SENSOR BIAS Currents ±0.5, ±2, ±10, ±50, ±200 µA 10 MΩ Pull-up/pull-down resistor TEST DAC (TDAC) DAC reference voltage VAVDD – VAVSS 18 binary weighted settings –4 4 V Absolute output voltage To VAVSS 0.5 4.5 V Accuracy ±0.1% Output impedance (5) V Differential output voltage ±1.5% See Table 12 Specified with VAVSS ≤ VREFN and VREFP ≤ VAVDD. For reference input voltage exceeding VAVDD or VAVSS, the ADC1 reference input current = 10 nA/ mV. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 9 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PGA OVER-RANGE MONITOR Differential alarm Threshold ±105% Differential alarm accuracy Absolute alarm thresholds ±1% FSR ±3% Low threshold VAVSS + 0.2 V High threshold VAVDD – 0.2 V ADC CLOCK fCLK Internal oscillator frequency 7.3728 Internal oscillator accuracy ±0.5% External crystal startup time See Table 25 for recommended crystals MHz ±2% 20 ms GENERAL-PURPOSE INPUT/OUTPUTS (GPIO) (6) VOH High-level output voltage IOH = 1 mA VOL Low-level output voltage IOL = –1 mA VIH High-level input voltage VIL Low-level input voltage 0.8 · VAVDD V 0.2 · VAVDD V 0.7 · VAVDD VAVDD V VAVSS 0.3 · VAVDD V Input hysteresis 0.5 V DIGITAL INPUT/OUTPUT (Other Than GPIO) IOH = 1 mA 0.8 · VDVDD V VOH High-level output voltage VOL Low-level output voltage VIH High-level input voltage 0.7 · VDVDD VDVDD V VIL Low-level input voltage VDGND 0.3 · VDVDD V ±10 µA IOH = 8 mA 0.75 · VDVDD IOL = –1 mA V 0.2 · VDVDD IOL = –8 mA 0.2 · VDVDD Input hysteresis V 0.1 Input leakage V V POWER SUPPLY IAVDD IAVSS Analog supply current Active mode, ADS1262 voltage reference off 4 Active mode, ADS1262 voltage reference on 4.2 6.5 mA Active mode, ADS1263 voltage reference on 4.3 6.5 mA 2 15 µA 1 1.25 mA Power-down mode IDVDD Digital supply current Active mode Power-down mode PD (6) (7) 10 Power dissipation ADS1262 ADS1263 (7) mA 25 50 µA Active mode, ADS1262 voltage reference on 24 37 mW Active mode, ADS1263 voltage reference on 25 37 mW Power-down mode 90 240 µW GPIO input and output voltages are referenced to VAVSS. External CLK input stopped. All other digital inputs maintained at VDVDD or VDGND. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 7.6 Timing Requirements: Serial Interface MIN MAX UNIT td(CSSC) CS↓ before first SCLK↑: delay time (1) td(DRSC) DRDY↓ or DRDY/DOUT↓before first SCLK↑: delay time tsu(DI) Valid DIN to SCLK↓: setup time th(DI) SCLK↓to valid DIN: hold time tc(SC) SCLK period (2) tw(SCH),tw(SCL) SCLK high pulse width or SCLK low pulse width 40 ns td(SCCS) Last SCLK↓ to CS↑: delay time 40 ns tw(CSH) CS high pulse width 30 ns (1) (2) 50 ns 0 ns 35 ns 25 ns 106 125 ns CS can be tied low. If serial interface time-out mode enabled, minimum SCLK frequency = 1 kHz. If serial interface time-out mode disabled (default), there is no minimum SCLK frequency. DRDY td(DRSC) tw(CSH) CS td(CSSC) tc(SC) td(SCCS) tw(SCH) SCLK tsu(DI) th(DI) tw(SCL) DIN Figure 1. Serial Interface Timing Requirements Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 11 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 7.7 Switching Characteristics: Serial Interface over operating the ambient temperature range and DVDD = 2.7 V to 5.25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tw(DRH) DRDY high pulse width tp(CSDO) CS↓ to DOUT/DRDY driven: propagation delay time DOUT/DRDY load: 20 pF || 100 kΩ to DGND tp(SCDO) SCLK↑ to valid DOUT/DRDY: propagation delay time DOUT/DRDY load: 20 pF || 100 kΩ to DGND th(SCDO) SCLK↑ to invalid DOUT/DRDY: hold time DOUT/DRDY load: 20 pF || 100 kΩ to DGND tp(CSDOZ) CS↑ to DOUT/DRDY high impedance: propagation delay time DOUT/DRDY load: 20 pF || 100 kΩ to DGND TYP MAX 16 0 UNIT 1/fCLK 40 ns 60 ns 0 ns 40 ns tw(DRH) DRDY CS SCLK tp(CSDOZ) tp(SCDO) (A) DOUT/DRDY MSB tp(CSDO) th(SCDO) (A): If new ADC data is ready since the last operation, DOUT/DRDY is logic low during this interval. Otherwise, DOUT/DRDY can be logic high or low depending on the previous state of the pin. Figure 2. Serial Interface Switching Characteristics VDVDD ½ V DVDD 50% VDGND td, th, tp, tw,tc Figure 3. Timing Reference 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 7.8 Typical Characteristics at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 4 0.5 3 0.4 0.3 Offset Voltage (PV) Offset Voltage (PV) 2 1 0 -1 -2 PGA Bypass Gain = 1 Gain = 2 Gain = 4 -3 -4 -50 -25 Gain = 8 Gain = 16 Gain = 32 0 25 50 Temperature (qC) 0.2 0.1 0 -0.1 -0.2 PGA Bypass Gain = 1 Gain = 2 Gain = 4 -0.3 -0.4 75 100 -0.5 -50 125 -25 Gain = 8 Gain = 16 Gain = 32 0 25 50 Temperature (qC) D028 After offset calibration, shorted inputs 75 100 125 D029 Chop mode on, after offset calibration, shorted inputs Figure 4. ADC1 Offset Voltage vs Temperature Figure 5. ADC1 Offset Voltage vs Temperature 100 80 Gain = 1 Gain = 32 70 Gain = 1 Gain = 32 90 80 70 Population (%) Population (%) 60 50 40 30 60 50 40 30 20 Input Referred Offset Voltage Drift (nV/qC) 2 1.8 1.6 1.4 1.2 1 50 20 SPS, Gain = 1 20 SPS, Gain = 32 400 SPS, Gain = 1 7200 SPS, Gain = 1 38400 SPS, Gain = 1 25 Gain Error (ppm) Offset Voltage (PV) 0.8 Figure 7. ADC1 Offset Voltage vs Temperature Distribution 400 100 0 -100 0 -25 PGA Bypass Gain = 1 Gain = 2 Gain = 4 -200 -300 0.5 D072 Chop mode on, shorted inputs, 30 units Figure 6. ADC1 Offset Voltage vs Temperature Distribution 200 0.6 Input Referred Offset Voltage Drift (nV/qC) D064 Shorted inputs, 30 units 300 0.4 0 100 90 80 70 60 50 40 30 20 0 10 0 0 10 0.2 20 10 1 1.5 2 2.5 3 3.5 Reference Voltage (V) 4 4.5 5 -50 -50 -25 D054 Shorted inputs 0 25 50 Temperature (qC) 75 Gain = 8 Gain = 16 Gain = 32 100 125 D030 After gain calibration Figure 8. ADC1 Offset Voltage vs Reference Voltage Figure 9. ADC1 Gain Error vs Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 13 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 100 60 Gain = 1 Gain = 32 20 SPS, Gain = 1 20 SPS, Gain = 32 400 SPS, Gain = 1 7200 SPS, Gain = 1 38400 SPS, Gain = 1 80 Gain Error (ppm) Population (%) 40 60 40 20 0 20 0 0 0.5 1 1.5 2 2.5 3 3.5 Gain Drift (ppm/qC) 4 4.5 -20 0.5 5 1 1.5 2 2.5 3 3.5 Reference Voltage (V) D037 4 4.5 5 D053 30 units Figure 10. ADC1 Gain vs Temperature Distribution Figure 11. ADC1 Gain Error vs Reference Voltage 8 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 0.4 0.3 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 7 Input Referred Noise (uVRMS) Input Referred Noise (uVRMS) 0.5 0.2 0.1 6 5 4 3 2 1 -25 0 25 50 Temperature (qC) 75 100 0 -50 125 -25 0 20 SPS, sinc4 200 100 50 70 7200 SPS, Gain = 1 38400 SPS, Gain = 1 2 1 0.5 0.2 0.1 0.05 D027 50 40 30 20 10 2.1 1.8 1.5 1.2 0.9 0.6 0 0.3 5 -0.3 4.5 -0.6 4 -1.2 2 2.5 3 3.5 Reference Voltage (V) -1.5 1.5 -1.8 0 1 D070 20 SPS, 400 SPS, 7200 SPS = sinc4, 38400 SPS = sinc5 Figure 14. ADC1 Noise vs Reference Voltage 14 125 60 -2.1 0.02 0.01 0.5 100 Figure 13. ADC1 Noise vs Temperature 80 Number of Occurrences Input Referred Noise (PVRMS) Figure 12. ADC1 Noise vs Temperature 20 SPS, Gain = 1 20 SPS, Gain = 32 400 SPS, Gain = 1 75 7200 SPS, sinc4 500 20 10 5 25 50 Temperature (qC) D026 -0.9 0 -50 D055 Output Voltage (PV) 20 SPS, FIR filter, gain = 1, after offset calibration, 256 samples Figure 15. ADC1 Output Reading Distribution Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 3000 120 2700 Number of Occurrences Number of Occurrences 100 80 60 40 2400 2100 1800 1500 1200 900 600 20 300 28 24 20 16 8 12 4 0 -4 -8 -12 -16 -20 -28 0.21 0.18 0.15 0.12 0.09 0.06 0 0.03 -0.03 -0.06 -0.09 -0.12 -0.15 -0.18 -0.21 Input Referred Voltage (PV) D056 Input Referred Voltage (PV) D057 7200 SPS, sinc4 filter, Gain = 1, after offset calibration, 8192 samples 20 SPS, FIR filter, gain = 32, after offset calibration, 256 samples Figure 16. ADC1 Output Reading Distribution Figure 17. ADC1 Output Reading Distribution 0 2100 -20 1800 -40 1500 Amplitude (dB) Number of Occurrences -24 0 0 1200 900 -60 -80 -100 -120 600 -140 300 -160 -180 1.6 1.4 1.2 1 0.8 0.6 0.4 0 0.2 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 0 0 1 2 3 D058 Input Referred Voltage (PV) 4 5 6 Frequency (Hz) 7 8 9 10 D059 20 SPS, Gain = 1, 256 points 7200 SPS, sinc4 filter, Gain = 32, after offset calibration, 8192 samples Figure 19. ADC1 Output Spectrum Figure 18. ADC1 Output Reading Distribution 0 8 Gain = 1 Gain = 32 -20 6 4 -60 INL (ppm) Amplitude (dB) -40 -80 -100 -120 2 0 -2 -4 -140 Gain = 1 Gain = 4 Gain = 16 Gain = 32 -6 -160 -180 0 2 4 6 8 10 12 Frequency (kHz) 14 16 18 20 -8 -100 -80 -60 D060 -40 -20 0 20 VIN (% of FSR) 40 60 80 100 D024 38400 SPS, 8192 points Figure 20. ADC1 Output Spectrum Figure 21. ADC1 INL vs VIN Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 15 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 6 60 Gain = 1 Gain = 4 Gain = 16 Gain = 32 5 50 40 Population (%) INL (ppm) 4 3 2 30 20 1 10 0 -50 0 -25 0 25 50 Temperature (qC) 75 100 125 0 1 2 D033 3 4 5 6 INL (ppm) 7 8 9 10 D001 D034 Gain = 32, 30 units Figure 22. ADC1 INL vs Temperature Figure 23. ADC1 INL Distribution 180 10 20 SPS, Gain = 1 20 SPS, Gain = 32 20 SPS, Gain = 1 7200 SPS, Gain = 1 38400 SPS, Gain = 1 Differential Input Current (nA) INL (ppm) 8 150 6 4 2 120 90 60 30 0 -30 -60 -90 T = -40qC T = 25qC T = 85qC T = 125qC -120 -150 0 0.5 1 1.5 2 2.5 3 3.5 Reference Voltage (V) 4 4.5 5 -180 -5 -4 -3 D052 -2 -1 0 1 2 Differential Input Voltage (V) 3 4 5 D040 PGA bypassed Figure 24. ADC1 INL vs Reference Voltage Figure 25. ADC1 Differential Input Current 250 8 Gain = 1, T = -40qC Gain = 1, T = 25qC Gain = 1, T = 85qC Gain = 1, T = 125qC 200 Absolute Input Current (nA) Absolute Input Current (nA) 7 150 100 T = -40qC T = 25qC T = 85qC T = 125qC 50 6 5 4 3 2 1 0 0 0 0.5 1 1.5 2 2.5 3 3.5 Absolute Input Voltage (V) 4 4.5 5 0 0.5 1 D041 PGA bypassed 1.5 2 2.5 3 3.5 Absolute Input Voltage (V) 4 4.5 5 D042 Gain = 1, 4 Figure 26. ADC1 Absolute Input Current 16 Gain = 4, T = -40qC Gain = 4, T = 25qC Gain = 4, T = 85qC Gain = 4, T = 125qC Figure 27. ADC1 Absolute Input Current Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 3 8 Absolute Input Current (nA) 7 6 Gain = 32, T = -40qC Gain = 32, T = 25qC Gain = 32, T = 85qC Gain = 32, T = 125qC Differential Input Current (nA) Gain = 16, T = -40qC Gain = 16, T = 25qC Gain = 16, T = 85qC Gain = 16, T = 125qC 5 4 3 2 1 0.5 1 1.5 2 2.5 3 3.5 Absolute Input Voltage (V) 4 4.5 5 0 -1 -2 -80 -60 -40 -20 0 20 40 60 Differential Input Voltage (% FSR) D043 Gain = 16, 32 Figure 28. ADC1 Absolute Input Current 100 D044 Figure 29. ADC1 Differential Input Current 2.502 PGA = 16, T = -40qC PGA = 16, T = 25qC PGA = 16, T = 85qC PGA = 16, T = 125qC 2 PGA = 32, T = -40qC PGA = 32, T = 25qC PGA = 32, T = 85qC PGA = 32, T = 125qC 2.501 Reference Voltage (V) Differential Input Current (nA) 80 Gain = 1, 4 3 1 0 -1 2.5 2.499 2.498 -2 -3 -100 -80 -60 -40 -20 0 20 40 60 Differential Input Voltage (% FSR) 80 2.497 -50 100 -25 0 25 50 Temperature (qC) D045 Gain = 16, 32 75 100 125 D035 D030 30 units Figure 30. ADC1 Differential Input Current Figure 31. Voltage Reference vs Temperature 80 0.01 Reference Voltage (% final value) Reference Voltage Stability (ppm) PGA = 4, T = -40qC PGA = 4, T = 25qC PGA = 4, T = 85qC PGA = 4, T = 125qC 1 -3 -100 0 0 PGA = 1, T = -40qC PGA = 1, T = 25qC PGA = 1, T = 85qC PGA = 1, T = 125qC 2 60 40 20 0 -20 -40 -60 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.01 0 100 200 300 400 500 600 Time (hr) 700 800 900 1000 0 0.5 D086 1 1.5 2 2.5 3 Time (s) 3.5 4 4.5 5 D025 TA = 85°C, 30 units Figure 32. Voltage Reference Long term Drift Figure 33. Voltage Reference Start-Up Time Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 17 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 140 200 120 150 100 125 CMRR (dB) Reference Input Current (nA) 175 100 75 50 25 80 60 40 IREFP, T = -40qC IREFP, T = 25qC IREFP, T = 85qC IREFP, T = 125qC 0 -25 -50 0.5 1 1.5 IREFN, T = -40qC IREFN, T = 25qC IREFN, T = 85qC IREFN, T = 125qC 2 2.5 3 3.5 Reference Voltage (V) 20 4 4.5 0 0.001 5 0.01 0.1 D031 1 10 Frequency (kHz) 100 1000 D065 IREFP measured with VREFN = VAVSS, IREFN measured with VREFP = VAVDD Figure 35. ADC1 CMRR vs Frequency 140 140 120 120 100 100 CMRR,PSRR (dB) PSRR (dB) Figure 34. ADC1 Reference Input Current 80 60 40 20 0.01 0.1 1 10 Frequency (kHz) 100 60 40 CMRR PSRR (Analog) PSRR (Digital) 20 Analog Supply Digital Supply 0 0.001 80 0 -50 1000 Figure 36. ADC1 PSRR vs Frequency 0 75 100 125 D069 0.25 0 Absolute IDAC Error (%) T = -40qC T = 25qC T = 85qC T = 125qC -0.25 -0.5 -0.75 -1 0 -0.25 -0.5 T = -40qC T = 25qC T = 85qC T = 125qC -0.75 -1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 IDAC Compliance Voltage (VAVDD - VAINX) 5 D046 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 IDAC Compliance Voltage (VAVDD - VAINx) IIDAC = 250 µA 5 D047 IIDAC = 1000 µA Figure 38. IDAC Error vs Compliance Voltage 18 25 50 Temperature (qC) Figure 37. ADC1 CMRR, PSRR vs Temperature 0.25 Absolute IDAC Error (%) -25 D075 Figure 39. IDAC Error vs Compliance Voltage Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 0.1 T = -40qC T = 25qC T = 85qC T = 125qC 0 IDAC Match Error (%) -0.25 -0.5 T = -40qC T = 25qC T = 85qC T = 125qC -0.75 0 -0.1 -0.2 -0.3 -1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 IDAC Compliance Voltage (VAVDD - VAINX) 0 5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 IDAC Compliance Voltage (VAVDD - VAINX) D048 IIDAC = 3000 µA Figure 40. IDAC Error vs Compliance Voltage D049 Figure 41. IDAC Current Error vs Compliance Voltage 170 50 160 40 150 Population (%) 140 130 120 30 20 110 10 100 D038 124.2 125 123.8 100 123.4 75 123 25 50 Temperature (qC) 122.6 0 122.2 0 -25 121.4 90 -50 121 Temperature Sensor Voltage (mV) 5 IIDAC1= IIDAC2 = 250 µA 121.8 Absolute IDAC Error (%) 0.25 D039 Temperature Sensor Voltage (mV) 30 units TA = 25°C, 30 units Figure 43. Temperature Sensor Voltage Distribution Figure 42. Temperature Sensor Voltage vs Temperature 6 2 IAVDD,IAVSS IDVDD, 20 SPS IDVDD, 38400 SPS 5 1 Active Current (mA) Internal Oscillator Error (%) 1.5 0.5 0 -0.5 4 3 2 -1 1 -1.5 -2 -50 -25 0 25 50 Temperature (qC) 75 100 125 0 -50 -25 D036 0 25 50 Temperature (qC) 75 100 125 D032 30 units Figure 44. Internal Oscillator Frequency vs Temperature Figure 45. ADS1262 Active Current vs Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 19 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 0.25 0.24 Low Alarm Threshold Voltage (V) Differential Alarm Threshold (r% of FSR) 110 108 106 104 102 100 -50 -25 0 25 50 Temperature (qC) 75 100 0.23 0.22 0.21 0.2 0.19 0.18 0.17 0.16 0.15 -50 125 -25 0 D001 30 units 75 100 125 D061 30 units Figure 46. ADC1 Differential Over-range Alarm Threshold vs Temperature Figure 47. ADC1 Absolute Low Alarm Threshold vs Temperature 4.85 0.14 4.84 TDAC Voltage Absolute Error (%) High Alarm Threshold Voltage (V) 25 50 Temperature (qC) 4.83 4.82 4.81 4.8 4.79 4.78 4.77 4.76 4.75 -50 -25 0 25 50 Temperature (qC) 75 100 0.5 V 2.25 V 2.484375 V 0.12 2.5 V 2.515625 V 2.75 V 4.5 V 0.1 0.08 0.06 0.04 0.02 0 -50 125 -25 0 D062 25 50 Temperature (qC) 75 100 125 D067 30 units Figure 48. ADC1 Absolute High Alarm Threshold vs Temperature Figure 49. TDAC Error vs Temperature 10 60 8 55 50 45 4 Population (%) 2 0 -2 -4 30 25 20 15 Gain = 1 Gain = 4 Gain = 16 Gain = 64 10 5 D080 20 90 100 Input Referred Offset Voltage Drift (nV/°C) After offset calibration, shorted input Figure 50. ADC2 Offset Voltage vs Temperature 80 125 70 100 60 75 50 25 50 Temperature (qC) 40 0 30 0 -25 20 -10 -50 35 10 -8 40 0 Offset Voltage (PV) 6 -6 Gain = 1 Gain = 64 D081 Inputs shorted, 30 units Figure 51. ADC2 Offset Voltage vs Temperature Distribution Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 100 100 75 80 Population (%) 50 Gain Error (ppm) Gain = 1 Gain = 64 Gain = 1 Gain = 4 Gain = 16 Gain = 64 25 0 -25 60 40 -50 20 -75 0 -100 -50 -25 0 25 50 Temperature (qC) 75 100 0 125 0.5 1 1.5 D078 After gain calibration 2 2.5 3 3.5 Gain drift (ppm/qC) 4 4.5 5 D079 30 units Figure 52. ADC2 Gain vs Temperature Figure 53. ADC2 Gain vs Temperature Distribution 35 50 Number of Occurrences Number of Occurrences 30 25 20 15 10 40 30 20 10 5 0 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 Input Referred Voltage (PV) -0.5 28 24 20 16 8 12 4 0 -4 -8 -12 -16 -20 -24 -28 0 D091 D092 D056 Input Referred Voltage (PV) Gain = 1, 10 SPS, after offset calibration, 128 samples Gain = 128, 10 SPS, after offset calibration, 128 samples Figure 55. ADC2 Output Reading Distribution Figure 54. ADC2 Output Reading Distribution 6 10 Gain = 1 Gain = 4 Gain = 16 Gain = 64 4 Gain = 1 Gain = 4 Gain = 16 Gain = 64 8 INL (ppm) INL (ppm) 2 0 6 4 -2 2 -4 -6 -100 -80 -60 -40 -20 0 20 VIN (% of FSR) 40 60 80 100 0 -50 -25 D076 Figure 56. ADC2 INL vs VIN 0 25 50 Temperature (qC) 75 100 125 D077 Figure 57. ADC2 INL vs Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 21 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 1000 500 Gain = 1 Gain = 4 Gain = 16 Gain = 64 50 30 20 Input Referred Noise (PVRMS) Input Referred Noise (uVRMS) 100 10 5 3 2 1 0.5 0.3 0.2 0.1 -50 -25 0 25 50 Temperature (qC) 75 100 10 SPS, Gain = 1 10 SPS, Gain = 4 10 SPS, Gain = 8 200 100 50 20 10 5 2 1 0.5 0.2 0.1 0.5 125 10 SPS, Gain = 16 800 SPS, Gain = 8 1 1.5 D090 2 2.5 3 3.5 Reference Voltage (V) 4 4.5 5 D074 10 SPS Figure 58. ADC2 Noise vs Temperature Figure 59. ADC2 Noise vs Reference Voltage 8 Gain = 1, T = -40qC Gain = 1, T = 25qC Gain = 1, T = 85qC Gain = 1, T = 125qC 16 Gain = 4, T = -40qC Gain = 4, T = 25qC Gain = 4, T = 85qC Gain = 4, T = 125qC Gain = 16, T = -40qC Gain = 16, T = 25qC Gain = 16, T = 85qC Gain = 16, T = 125qC 7 Absolute Input Current (nA) Absolute Input Current (nA) 20 12 8 4 6 Gain = 64, T = -40qC Gain = 64, T = 25qC Gain = 64, T = 85qC Gain = 64, T = 125qC 5 4 3 2 1 0 0 0 0.5 1 1.5 2 2.5 3 3.5 Absolute Input Voltage (V) 4 4.5 0 5 0.5 1 D082 Gain = 1, 4 20 4 15 10 5 0 -5 -10 -20 -25 -100 -80 5 D043 PGA = 4, T = -40qC PGA = 4, T = 25qC PGA = 4, T = 85qC PGA = 4, T = 125qC -60 -40 -20 0 20 40 60 Differential Input Voltage (% FSR) 80 3 2 1 0 -1 -2 -3 -4 100 D084 -5 -100 PGA = 16, T = -40qC PGA = 16, T = 25qC PGA = 16, T = 85qC PGA = 16, T = 125qC -80 PGA = 64, T = -40qC PGA = 64, T = 25qC PGA = 64, T = 85qC PGA = 64, T = 125qC -60 -40 -20 0 20 40 60 Differential Input Voltage (% FSR) Gain = 1, 4 80 100 D085 Gain = 16, 64 Figure 62. ADC2 Differential Input Current 22 4.5 Figure 61. ADC2 Absolute Input Current 5 Differential Input Current (nA) Differential Input Current (nA) Figure 60. ADC2 Absolute Input Current PGA = 1, T = -40qC PGA = 1, T = 25qC PGA = 1, T = 85qC PGA = 1, T = 125qC 4 Gain = 16, 64 25 -15 1.5 2 2.5 3 3.5 Absolute Input Voltage (V) Figure 63. ADC2 Differential Input Current Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Typical Characteristics (continued) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1 16 120 14 Reference Input Current (nA) 100 CMRR (dB) 80 60 40 20 12 10 IREFP, T = -40qC IREFP, T = 25qC IREFP, T = 85qC IREFP, T = 125qC IREFN, T = -40qC IREFN, T = 25qC IREFN, T = 85qC IREFN, T = 125qC 8 6 4 2 0 -2 -4 0 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1000 -6 0.5 1 D073 1.5 2 2.5 3 3.5 Reference Voltage (V) 4 4.5 5 D031 IREFP measured with VREFN = VAVSS, IREFN measured with VREFP = VAVDD Figure 64. ADC2 CMRR vs Frequency Figure 65. ADC2 Reference Input Current Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 23 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 8 Parameter Measurement Information 8.1 Offset Temperature Drift Measurement Offset temperature drift is defined as the maximum change of offset voltage measured over the specified temperature range. The offset voltage drift is input referred and is calculated using the box method, as described by Equation 1: Offset Voltage Drift = (VOSMAX – VOSMIN) / (TMAX – TMIN) where • • VOSMAX and VOSMIN are the maximum and minimum offset voltages, respectively TMAX and TMIN are the maximum and minimum temperatures, respectively, over the specified temperature range (1) 8.2 Gain Temperature Drift Measurement Gain temperature drift is defined as the maximum change of gain error measured over the specified temperature range. The gain error drift is calculated using the box method, as described by Equation 2: Gain Error Drift = (GEMAX – GEMIN) / (TMAX – TMIN) where • • GEMAX and GEMIN are the maximum and minimum gain errors, respectively TMAX and TMIN are the maximum and minimum temperatures, respectively, over the specified temperature range (2) 8.3 Common-Mode Rejection Ratio Measurement Common-mode rejection ratio (CMRR) is defined as the rejection of the ADC output to an applied common-mode input voltage. The common-mode input is 60 Hz with a peak-to-peak amplitude equal to the specified absolute input voltage range. The standard deviation (RMS) value of the ADC output is calculated and scaled to volts. In order to measure CMRR, record two ADC readings. The first reading (VA) is with no common-mode input signal. The first reading represents the baseline ADC noise. The second reading (VB) is with the common-mode input applied. The second reading represents the combination of the ADC baseline noise plus the increased RMS noise caused by the common-mode input. The ADC baseline noise is extracted from the combined noise to yield the noise induced by the common-mode input voltage. The CMRR measurement is described by Equation 3: CMRR = 20 · Log (VIC / VOC) where • • • • VIC = RMS value of the input common-mode voltage = 1.56 VRMS VOC = Calculated RMS value of output voltage = (VB2 – VA2 )0.5 VA = RMS output voltage with no common-mode input VB = RMS output voltage with common-mode input (3) For gains > 1, add 6 dB of compensation value for each binary increase of gain. 8.4 Power-Supply Rejection Ratio Measurement Power-supply rejection ratio (PSRR) is defined as the rejection of the ADC output to the DC change of the power supply voltage referred to the input range. PSRR is calculated using two ADC mean-value readings with inputs shorted, scaled to volts. The first ADC reading (VOA) is acquired at one power-supply voltage, and the second ADC reading (VOB) is acquired after changing the power-supply voltage by 0.5 V. The PSRR calculation is described by Equation 4: PSRR = 20 · Log |(VPSA– VPSB )/ (VOA – VOB)| – 20 dB where • • • VPSA– VPSB = power-supply DC voltage change = 0.5 V VOA – VOB = ADC DC output voltage change (V) Range compensation factor = 20 · log (0.5 V / 5 V) = –20 dB for gain = 1 (4) For gains > 1, add an additional 6 dB of compensation value for each binary increase of gain. 24 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 8.5 Crosstalk Measurement (ADS1263) Crosstalk is defined as the unintended coupling of signals between ADC1 and ADC2. Measure crosstalk by changing the dc input voltage of one ADC and measuring the rejection of the other ADC. The dc input voltage change is 0.3 V, and the gain of the affected ADC is 16. Acquire two mean-value readings of the affected ADC with inputs shorted. Take the first ADC reading (VOA) with VIN = 0 V, and take the second ADC reading (VOB) after changing the input voltage by 0.3 V. The crosstalk calculation is described by Equation 5: Crosstalk = |(VOA – VOB) / (VINA – VINB)| · 106 (µV/V) where • • VOA – VOB = DC output voltage change of the affected ADC VINA – VINB = DC input voltage change of the driven ADC = 0.3 V (5) 8.6 Reference-Voltage Temperature-Drift Measurement Internal reference-voltage temperature drift is defined as the maximum change in reference voltage measured over the specified temperature range. The reference voltage drift is calculated using the box method, as described by Equation 6: Reference Drift = (VREFMAX – VREFMIN) / (VREFNOM · (TMAX – TMIN) ) · 106 (ppm) where • • VREFMAX, VREFMIN and VREFNOM are the maximum, minimum and nominal (TA = 25°C) reference voltages, respectively TMAX and TMIN are the maximum and minimum temperatures, respectively, over the specified temperature range (6) 8.7 Reference-Voltage Thermal-Hysteresis Measurement Internal reference-voltage thermal hysteresis is defined as the change in reference voltage after operating the device at TA = 25°C, cycling the device through the TA = 0°C to 85°C temperature range for ten minutes at each temperature and returning to TA = 25°C. The internal reference thermal hysteresis is defined in Equation 7: Reference Thermal Hysteresis = |VREFPRE – VREFPOST| / VREFPRE · 106 (ppm) where • VREFPRE and VREFPOST are the reference voltages before and after the temperature cycle, respectively Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 (7) 25 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 8.8 Noise Performance The ADC noise performance depends on the following ADC settings: PGA gain, data rate, digital filter mode, and chop mode. Generally, the lowest input-referred noise is achieved using the highest gain possible, consistent with the input signal range. Do not set the gain too high or the result is ADC overrange. Noise also depends on the output data rate and mode of the digital filter. As the data rate reduces, the ADC bandwidth correspondingly reduces. As the order of the digital filter mode increases, the ADC bandwidth also reduces. This reduction in total bandwidth results in lower overall noise. The ADC noise is reduced by a factor of 1.4 with chop mode enabled. Table 1 shows ADC1 noise performance in units of µVRMS (RMS = root mean square) under the conditions shown. The values in parenthesis are peak-to-peak values. Table 2 shows the noise performance in effective number of bits (ENOB) with an external 5-V reference voltage. The values shown in parenthesis are noise-free bits. The definition of noise-free bits is the resolution of the ADC with no code flicker. The noise-free bits data are based on the µVPP values. Note that for data rate = 38400 SPS, noise scales with increased reference voltage. For all other data rates, noise does not scale with reference voltage. Table 3 shows the noise performance of ADC2 (ADS1263) in units of µVRMS and (µVP–P). The values in parenthesis are peak-to-peak values. Table 4 shows the ENOB and noise-free bits of ADC2. The ENOB and noise-free bits shown in the tables are calculated using Equation 8: ENOB = ln (FSR / VNRMS) / ln (2) where • • FSR = full scale range = 2 · VREF/Gain VNRMS = Input referred noise voltage (8) Achieve maximum ENOB with maximum FSR. For ADC1, achieve maximum FSR with VREF = 5 V and the PGA bypassed. If the PGA is enabled, the FSR is limited by the PGA input range (see the Electrical Characteristics table.) For ADC2, achieve maximum FSR with VREF = 5 V and gains = 1, 2, or 4. If gain = 8 to 128, then FSR is limited by the PGA input range (see the Electrical Characteristics table). For ADC1 operation, if the reference voltage is equal to 5 V and the PGA is enabled, the available FSR is restricted because of the limited PGA range specification. For ADC2 operation, if the reference voltage is equal to 5 V, The FSR is reduced for ADC2 gains equal to or greater than eight because of the limited PGA range. The data shown in the noise performance tables represent typical ADC performance at TA = 25°C. The noiseperformance data are the standard deviation and peak-to-peak computations of the ADC data. Because of the statistical nature of noise, repeated noise measurements may yield higher or lower noise results. The noise data are acquired with inputs shorted, from consecutive ADC readings for a period of ten seconds or 8192 data points, whichever occurs first. Table 1. ADC1 Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V DATA RATE GAIN FILTER MODE 1 2 4 8 16 32 2.5 SPS FIR 0.145 (0.637) 0.071 (0.279) 0.038 (0.149) 0.023 (0.089) 0.014 (0.064) 0.011 (0.051) 2.5 SPS Sinc1 0.121 (0.510) 0.058 (0.249) 0.033 (0.143) 0.018 (0.073) 0.012 (0.054) 0.008 (0.037) 2.5 SPS Sinc2 0.101 (0.437) 0.055 (0.225) 0.025 (0.104) 0.015 (0.064) 0.010 (0.043) 0.007 (0.031) 2.5 SPS Sinc3 0.080 (0.307) 0.046 (0.195) 0.026 (0.116) 0.013 (0.052) 0.008 (0.034) 0.006 (0.023) 2.5 SPS Sinc4 0.080 (0.308) 0.043 (0.180) 0.020 (0.078) 0.013 (0.049) 0.008 (0.031) 0.007 (0.027) 5 SPS FIR 0.206 (1.007) 0.098 (0.448) 0.054 (0.252) 0.028 (0.123) 0.020 (0.098) 0.015 (0.073) 5 SPS Sinc1 0.161 (0.726) 0.090 (0.432) 0.047 (0.246) 0.026 (0.120) 0.017 (0.083) 0.012 (0.057) 5 SPS Sinc2 0.146 (0.661) 0.069 (0.308) 0.038 (0.195) 0.021 (0.100) 0.013 (0.061) 0.011 (0.050) 5 SPS Sinc3 0.128 (0.611) 0.067 (0.325) 0.033 (0.153) 0.019 (0.095) 0.012 (0.054) 0.010 (0.046) 5 SPS Sinc4 0.122 (0.587) 0.063 (0.269) 0.030 (0.144) 0.017 (0.076) 0.011 (0.048) 0.008 (0.039) 10 SPS FIR 0.284 (1.418) 0.142 (0.753) 0.077 (0.379) 0.041 (0.197) 0.027 (0.156) 0.023 (0.118) 10 SPS Sinc1 0.229 (1.220) 0.123 (0.662) 0.060 (0.322) 0.035 (0.177) 0.023 (0.118) 0.018 (0.103) 10 SPS Sinc2 0.193 (1.019) 0.093 (0.488) 0.048 (0.254) 0.028 (0.149) 0.019 (0.099) 0.016 (0.079) 10 SPS Sinc3 0.176 (0.896) 0.088 (0.452) 0.043 (0.217) 0.028 (0.137) 0.018 (0.091) 0.014 (0.067) 10 SPS Sinc4 0.164 (0.788) 0.076 (0.389) 0.040 (0.200) 0.024 (0.119) 0.016 (0.081) 0.013 (0.065) 26 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Noise Performance (continued) Table 1. ADC1 Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V (continued) DATA RATE FILTER MODE GAIN 1 2 4 8 16 32 16.6 SPS Sinc1 0.306 (1.708) 0.147 (0.810) 0.077 (0.436) 0.044 (0.250) 0.030 (0.176) 0.024 (0.138) 16.6 SPS Sinc2 0.248 (1.401) 0.122 (0.729) 0.068 (0.403) 0.037 (0.213) 0.024 (0.136) 0.020 (0.111) 16.6 SPS Sinc3 0.216 (1.221) 0.120 (0.667) 0.060 (0.332) 0.033 (0.197) 0.022 (0.130) 0.017 (0.095) 16.6 SPS Sinc4 0.214 (1.169) 0.101 (0.544) 0.054 (0.302) 0.031 (0.175) 0.022 (0.129) 0.016 (0.092) 20 SPS FIR 0.393 (2.467) 0.191 (1.102) 0.104 (0.603) 0.057 (0.353) 0.039 (0.222) 0.030 (0.167) 20 SPS Sinc1 0.336 (1.861) 0.167 (0.964) 0.085 (0.486) 0.049 (0.266) 0.033 (0.191) 0.026 (0.138) 20 SPS Sinc2 0.270 (1.560) 0.136 (0.745) 0.070 (0.376) 0.039 (0.231) 0.028 (0.149) 0.021 (0.111) 20 SPS Sinc3 0.237 (1.415) 0.124 (0.701) 0.067 (0.399) 0.035 (0.192) 0.024 (0.130) 0.020 (0.109) 20 SPS Sinc4 0.229 (1.285) 0.113 (0.612) 0.060 (0.325) 0.034 (0.193) 0.022 (0.123) 0.017 (0.098) 50 SPS Sinc1 0.514 (2.925) 0.255 (1.584) 0.140 (0.940) 0.077 (0.457) 0.051 (0.315) 0.042 (0.264) 50 SPS Sinc2 0.426 (2.400) 0.209 (1.217) 0.108 (0.666) 0.064 (0.381) 0.042 (0.265) 0.033 (0.200) 50 SPS Sinc3 0.389 (2.324) 0.196 (1.185) 0.104 (0.624) 0.057 (0.367) 0.038 (0.228) 0.030 (0.179) 50 SPS Sinc4 0.358 (2.319) 0.175 (1.023) 0.096 (0.597) 0.055 (0.319) 0.036 (0.217) 0.028 (0.176) 60 SPS Sinc1 0.558 (3.574) 0.285 (1.703) 0.151 (0.913) 0.085 (0.515) 0.055 (0.335) 0.045 (0.271) 60 SPS Sinc2 0.465 (2.753) 0.235 (1.424) 0.121 (0.760) 0.068 (0.417) 0.046 (0.276) 0.036 (0.208) 60 SPS Sinc3 0.414 (2.704) 0.208 (1.187) 0.112 (0.655) 0.064 (0.396) 0.042 (0.276) 0.034 (0.197) 60 SPS Sinc4 0.383 (2.288) 0.195 (1.174) 0.105 (0.623) 0.059 (0.347) 0.040 (0.242) 0.031 (0.188) 100 SPS Sinc1 0.734 (4.715) 0.361 (2.276) 0.192 (1.209) 0.108 (0.679) 0.071 (0.473) 0.058 (0.362) 100 SPS Sinc2 0.604 (3.662) 0.305 (1.934) 0.156 (1.072) 0.088 (0.579) 0.059 (0.371) 0.048 (0.321) 100 SPS Sinc3 0.531 (3.431) 0.277 (1.780) 0.143 (0.935) 0.081 (0.545) 0.054 (0.343) 0.043 (0.288) 100 SPS Sinc4 0.511 (3.340) 0.255 (1.632) 0.134 (0.861) 0.076 (0.479) 0.050 (0.322) 0.041 (0.271) 400 SPS Sinc1 1.438 (10.374) 0.734 (5.410) 0.380 (2.657) 0.215 (1.469) 0.143 (1.066) 0.116 (0.843) 400 SPS Sinc2 1.186 (8.523) 0.607 (4.333) 0.313 (2.280) 0.178 (1.313) 0.119 (0.884) 0.095 (0.676) 400 SPS Sinc3 1.072 (7.923) 0.550 (3.999) 0.285 (1.991) 0.161 (1.132) 0.107 (0.781) 0.087 (0.630) 400 SPS Sinc4 0.995 (7.107) 0.508 (3.664) 0.266 (1.947) 0.151 (1.061) 0.101 (0.708) 0.081 (0.583) 1200 SPS Sinc1 2.451 (17.755) 1.254 (9.305) 0.651 (5.044) 0.368 (2.807) 0.244 (1.846) 0.197 (1.519) 1200 SPS Sinc2 2.038 (15.480) 1.037 (8.128) 0.545 (4.107) 0.309 (2.315) 0.205 (1.586) 0.165 (1.283) 1200 SPS Sinc3 1.858 (14.005) 0.960 (7.223) 0.494 (3.833) 0.281 (2.145) 0.186 (1.374) 0.148 (1.094) 1200 SPS Sinc4 1.743 (13.428) 0.890 (6.585) 0.459 (3.405) 0.261 (2.018) 0.174 (1.337) 0.139 (1.032) 2400 SPS Sinc1 3.411 (26.095) 1.724 (13.528) 0.903 (6.609) 0.510 (3.920) 0.335 (2.626) 0.270 (2.107) 2400 SPS Sinc2 2.870 (21.677) 1.468 (11.032) 0.770 (5.932) 0.435 (3.379) 0.286 (2.123) 0.230 (1.758) 2400 SPS Sinc3 2.656 (20.100) 1.337 (9.936) 0.705 (5.355) 0.395 (3.035) 0.262 (1.951) 0.211 (1.533) 2400 SPS Sinc4 2.475 (19.447) 1.262 (9.452) 0.657 (4.966) 0.371 (2.869) 0.245 (1.885) 0.198 (1.576) 4800 SPS Sinc1 4.590 (34.155) 2.329 (17.298) 1.221 (8.943) 0.682 (5.252) 0.446 (3.239) 0.361 (2.957) 4800 SPS Sinc2 4.091 (30.903) 2.070 (15.168) 1.077 (8.141) 0.606 (4.777) 0.398 (2.986) 0.321 (2.397) 4800 SPS Sinc3 3.720 (28.423) 1.894 (14.842) 0.998 (7.626) 0.560 (4.176) 0.367 (2.890) 0.297 (2.211) 4800 SPS Sinc4 3.535 (27.437) 1.784 (13.760) 0.926 (7.273) 0.527 (4.004) 0.349 (2.626) 0.277 (2.184) 7200 SPS Sinc1 5.326 (42.076) 2.709 (19.749) 1.407 (11.126) 0.792 (5.784) 0.516 (3.881) 0.409 (3.189) 7200 SPS Sinc2 4.867 (36.820) 2.467 (18.627) 1.280 (9.874) 0.726 (5.612) 0.472 (3.531) 0.379 (2.792) 7200 SPS Sinc3 4.567 (35.194) 2.310 (17.516) 1.209 (9.036) 0.682 (5.181) 0.445 (3.590) 0.359 (2.666) 7200 SPS Sinc4 4.365 (34.008) 2.211 (17.432) 1.143 (8.804) 0.642 (5.075) 0.426 (3.261) 0.341 (2.467) 14400 SPS Sinc5 6.377 (48.242) 3.235 (25.178) 1.675 (12.508) 0.929 (7.280) 0.596 (4.430) 0.466 (3.524) 19200 SPS Sinc5 8.720 (65.389) 4.432 (32.931) 2.285 (17.055) 1.227 (9.870) 0.747 (5.725) 0.555 (4.058) 38400 SPS Sinc5 103.55 (759.91) 51.76 (371.46) 25.95 (192.20) 13.02 (99.09) 6.493 (46.060) 3.276 (24.435) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 27 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Table 2. ADC1 ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V DATA RATE FILTER MODE GAIN 1 (BYPASS) 2 4 8 16 32 2.5 SPS FIR 26.0 (23.9) 25.9 (23.9) 25.8 (23.8) 25.5 (23.6) 25.4 (23.0) 24.6 (22.4) 2.5 SPS Sinc1 26.3 (24.2) 26.2 (24.1) 26.0 (23.9) 25.9 (23.8) 25.6 (23.3) 25.0 (22.8) 2.5 SPS Sinc2 26.6 (24.4) 26.3 (24.2) 26.4 (24.3) 26.1 (24.0) 25.8 (23.6) 25.2 (23.1) 2.5 SPS Sinc3 26.9 (25.0) 26.5 (24.4) 26.3 (24.2) 26.3 (24.3) 26.1 (23.9) 25.6 (23.5) 2.5 SPS Sinc4 26.9 (25.0) 26.6 (24.5) 26.7 (24.7) 26.3 (24.4) 26.2 (24.1) 25.2 (23.3) 5 SPS FIR 25.5 (23.2) 25.4 (23.2) 25.3 (23.1) 25.2 (23.1) 24.8 (22.4) 24.1 (21.9) 5 SPS Sinc1 25.9 (23.7) 25.5 (23.3) 25.5 (23.1) 25.4 (23.1) 25.0 (22.7) 24.4 (22.2) 5 SPS Sinc2 26.0 (23.9) 25.9 (23.8) 25.8 (23.4) 25.7 (23.4) 25.4 (23.1) 24.6 (22.4) 5 SPS Sinc3 26.2 (24.0) 26.0 (23.7) 26.0 (23.8) 25.8 (23.5) 25.6 (23.3) 24.7 (22.5) 5 SPS Sinc4 26.3 (24.0) 26.1 (24.0) 26.1 (23.9) 25.9 (23.8) 25.7 (23.5) 25.0 (22.8) 10 SPS FIR 25.1 (22.7) 24.9 (22.5) 24.8 (22.5) 24.7 (22.4) 24.4 (21.8) 23.5 (21.2) 10 SPS Sinc1 25.4 (23.0) 25.1 (22.7) 25.1 (22.7) 24.9 (22.6) 24.6 (22.2) 23.8 (21.4) 10 SPS Sinc2 25.6 (23.2) 25.5 (23.1) 25.4 (23.0) 25.2 (22.8) 24.9 (22.4) 24.1 (21.7) 10 SPS Sinc3 25.8 (23.4) 25.6 (23.2) 25.6 (23.3) 25.2 (22.9) 25.0 (22.5) 24.2 (22.0) 10 SPS Sinc4 25.9 (23.6) 25.8 (23.4) 25.7 (23.4) 25.5 (23.1) 25.1 (22.7) 24.4 (22.0) 16.6 SPS Sinc1 25.0 (22.5) 24.8 (22.4) 24.8 (22.3) 24.6 (22.1) 24.2 (21.6) 23.5 (20.9) 16.6 SPS Sinc2 25.3 (22.8) 25.1 (22.5) 24.9 (22.4) 24.8 (22.3) 24.6 (21.9) 23.7 (21.2) 16.6 SPS Sinc3 25.5 (23.0) 25.1 (22.7) 25.1 (22.7) 25.0 (22.4) 24.6 (22.0) 23.9 (21.5) 16.6 SPS Sinc4 25.5 (23.0) 25.4 (22.9) 25.3 (22.8) 25.1 (22.6) 24.7 (22.0) 24.0 (21.5) 20 SPS FIR 24.6 (22.0) 24.5 (21.9) 24.3 (21.8) 24.2 (21.6) 23.9 (21.2) 23.1 (20.7) 20 SPS Sinc1 24.8 (22.4) 24.7 (22.1) 24.6 (22.1) 24.4 (22.0) 24.1 (21.5) 23.3 (20.9) 20 SPS Sinc2 25.1 (22.6) 24.9 (22.5) 24.9 (22.5) 24.7 (22.2) 24.3 (21.8) 23.6 (21.2) 20 SPS Sinc3 25.3 (22.8) 25.1 (22.6) 25.0 (22.4) 24.9 (22.4) 24.5 (22.0) 23.7 (21.3) 20 SPS Sinc4 25.4 (22.9) 25.2 (22.8) 25.1 (22.7) 25.0 (22.4) 24.6 (22.1) 23.9 (21.4) 50 SPS Sinc1 24.2 (21.7) 24.0 (21.4) 23.9 (21.2) 23.8 (21.2) 23.5 (20.7) 22.6 (20.0) 50 SPS Sinc2 24.5 (22.0) 24.3 (21.8) 24.3 (21.7) 24.0 (21.5) 23.7 (21.0) 23.0 (20.4) 50 SPS Sinc3 24.6 (22.0) 24.4 (21.8) 24.3 (21.8) 24.2 (21.5) 23.9 (21.2) 23.1 (20.6) 50 SPS Sinc4 24.7 (22.0) 24.6 (22.0) 24.4 (21.8) 24.3 (21.7) 24.0 (21.3) 23.2 (20.6) 60 SPS Sinc1 24.1 (21.4) 23.9 (21.3) 23.8 (21.2) 23.6 (21.0) 23.4 (20.6) 22.5 (20.0) 60 SPS Sinc2 24.4 (21.8) 24.2 (21.6) 24.1 (21.5) 24.0 (21.3) 23.6 (20.9) 22.9 (20.3) 60 SPS Sinc3 24.5 (21.8) 24.3 (21.8) 24.2 (21.7) 24.0 (21.4) 23.7 (20.9) 23.0 (20.4) 60 SPS Sinc4 24.6 (22.1) 24.4 (21.8) 24.3 (21.8) 24.1 (21.6) 23.8 (21.1) 23.1 (20.5) 100 SPS Sinc1 23.7 (21.0) 23.5 (20.9) 23.5 (20.8) 23.3 (20.6) 23.0 (20.1) 22.2 (19.5) 100 SPS Sinc2 24.0 (21.4) 23.8 (21.1) 23.8 (21.0) 23.6 (20.9) 23.2 (20.5) 22.4 (19.7) 100 SPS Sinc3 24.2 (21.5) 23.9 (21.2) 23.9 (21.2) 23.7 (20.9) 23.4 (20.6) 22.6 (19.9) 100 SPS Sinc4 24.2 (21.5) 24.0 (21.4) 24.0 (21.3) 23.8 (21.1) 23.5 (20.7) 22.7 (20.0) 400 SPS Sinc1 22.7 (19.9) 22.5 (19.6) 22.5 (19.7) 22.3 (19.5) 22.0 (19.0) 21.2 (18.3) 400 SPS Sinc2 23.0 (20.2) 22.8 (20.0) 22.7 (19.9) 22.6 (19.7) 22.2 (19.2) 21.5 (18.6) 400 SPS Sinc3 23.2 (20.3) 22.9 (20.1) 22.9 (20.1) 22.7 (19.9) 22.4 (19.4) 21.6 (18.7) 400 SPS Sinc4 23.3 (20.4) 23.0 (20.2) 23.0 (20.1) 22.8 (20.0) 22.5 (19.6) 21.7 (18.8) 1200 SPS Sinc1 22.0 (19.1) 21.7 (18.9) 21.7 (18.7) 21.5 (18.6) 21.2 (18.2) 20.4 (17.5) 1200 SPS Sinc2 22.2 (19.3) 22.0 (19.0) 21.9 (19.0) 21.8 (18.9) 21.5 (18.4) 20.7 (17.7) 1200 SPS Sinc3 22.4 (19.4) 22.1 (19.2) 22.1 (19.1) 21.9 (19.0) 21.6 (18.6) 20.8 (17.9) 1200 SPS Sinc4 22.5 (19.5) 22.2 (19.3) 22.2 (19.3) 22.0 (19.1) 21.7 (18.6) 20.9 (18.0) 28 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Table 2. ADC1 ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V (continued) DATA RATE FILTER MODE GAIN 1 (BYPASS) 2 4 8 16 32 2400 SPS Sinc1 21.5 (18.5) 21.3 (18.3) 21.2 (18.3) 21.0 (18.1) 20.7 (17.7) 20.0 (17.0) 2400 SPS Sinc2 21.7 (18.8) 21.5 (18.6) 21.4 (18.5) 21.3 (18.3) 21.0 (18.0) 20.2 (17.3) 2400 SPS Sinc3 21.8 (18.9) 21.7 (18.8) 21.6 (18.6) 21.4 (18.5) 21.1 (18.1) 20.3 (17.5) 2400 SPS Sinc4 21.9 (19.0) 21.7 (18.8) 21.7 (18.8) 21.5 (18.5) 21.2 (18.2) 20.4 (17.4) 4800 SPS Sinc1 21.1 (18.2) 20.8 (18.0) 20.8 (17.9) 20.6 (17.7) 20.3 (17.4) 19.5 (16.5) 4800 SPS Sinc2 21.2 (18.3) 21.0 (18.1) 21.0 (18.0) 20.8 (17.8) 20.5 (17.5) 19.7 (16.8) 4800 SPS Sinc3 21.4 (18.4) 21.1 (18.2) 21.1 (18.1) 20.9 (18.0) 20.6 (17.5) 19.8 (16.9) 4800 SPS Sinc4 21.4 (18.5) 21.2 (18.3) 21.2 (18.2) 21.0 (18.1) 20.7 (17.7) 19.9 (16.9) 7200 SPS Sinc1 20.8 (17.9) 20.6 (17.8) 20.6 (17.6) 20.4 (17.5) 20.1 (17.1) 19.4 (16.4) 7200 SPS Sinc2 21.0 (18.1) 20.8 (17.8) 20.7 (17.8) 20.5 (17.6) 20.2 (17.2) 19.5 (16.6) 7200 SPS Sinc3 21.1 (18.1) 20.9 (17.9) 20.8 (17.9) 20.6 (17.7) 20.3 (17.2) 19.5 (16.7) 7200 SPS Sinc4 21.1 (18.2) 20.9 (17.9) 20.9 (17.9) 20.7 (17.7) 20.4 (17.4) 19.6 (16.8) 14400 SPS Sinc5 20.6 (17.7) 20.4 (17.4) 20.3 (17.4) 20.2 (17.2) 19.9 (16.9) 19.2 (16.3) 19200 SPS Sinc5 20.1 (17.2) 19.9 (17.0) 19.9 (17.0) 19.8 (16.8) 19.6 (16.6) 18.9 (16.0) 38400 SPS Sinc5 15.6 (12.6) 15.4 (12.6) 15.4 (12.5) 15.3 (12.5) 15.5 (12.6) 15.4 (12.5) Table 3. ADC2 (ADS1263) Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V DATA RATE FILTER GAIN 1 2 4 8 16 32 64 128 10 SPS Sinc1 7.34 (32.6) 3.54 (16.5) 1.52 (7.57) 0.87 (4.22) 0.47 (2.42) 0.28 (1.43) 0.20 (1.08) 0.14 (0.70) 100 SPS Sinc3 10.3 (65.2) 5.58 (36.0) 3.13 (20.4) 1.80 (11.5) 0.96 (6.30) 0.62 (4.03) 0.48 (3.08) 0.32 (2.04) 400 SPS Sinc3 56.8 (827) 29.2 (345) 15.3 (158) 7.88 (76.9) 4.02 (36.2) 2.18 (17.9) 1.32 (9.94) 0.80 (5.56) 800 SPS Sinc3 299 (3195) 151 (1756) 76.8 (875) 38.9 (417) 19.8 (199) 10.0 (90.0) 5.21 (43.6) 2.71 (21.9) Table 4. ADC2 (ADS1263) ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V DATA RATE FILTER 10 SPS 100 SPS GAIN 1 2 4 8 16 32 64 128 Sinc1 21.4 (18.8) 21.3 (18.8) 21.1 (18.6) 20.6 (18.2) 20.6 (18.1) 20.2 (17.8) 19.4 (17.0) 19.1 (16.7) Sinc3 20.3 (17.5) 20.1 (17.3) 19.8 (17.2) 19.4 (16.7) 19.3 (16.5) 18.9 (16.2) 18.2 (15.6) 17.8 (15.0) 400 SPS Sinc3 16.5 (12.5) 16.5 (12.5) 16.4 (12.7) 16.2 (12.8) 16.2 (12.6) 16.2 (13.0) 16.1 (13.0) 15.9 (13.0) 800 SPS Sinc3 14.0 (10.7) 14.0 (10.7) 14.0 (10.4) 13.8 (10.4) 13.8 (10.4) 13.8 (10.4) 13.7 (10.6) 13.7 (10.7) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 29 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 9 Detailed Description 9.1 Overview The ADS1262 and ADS1263 are precision 32-bit, delta-sigma (ΔΣ) ADCs with an integrated analog front end (AFE) to simplify connection to sensors. A 32-bit ADC (ADC1) provides output data rates from 2.5 SPS to 38400 SPS for flexibility in resolution and data rates over a wide range of applications. The ADC low noise and low drift architecture make these devices suitable for precise digitization of low-level transducers, such as load cell bridges and temperature sensors. The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2). The ADS1262 and the ADS1263 incorporate several functions that provide increased utility. The key integrated functions include: • Low-drift voltage reference • Dual, matched, sensor-excitation current sources (IDAC) • Input-level-shift voltage • Eight GPIOs • Dual-sensor, bias current sources • Low-noise, CMOS PGA with integrated signal fault detection • Internal test signal source (TDAC) • Temperature sensor • Internal oscillator • Three sets of buffered external reference inputs with low reference voltage alarm As seen in the Functional Block Diagram, these devices feature 11 analog inputs that are configurable as either ten single-ended inputs, five differential inputs, or any combination, to either ADC1 or ADC2. Many of the analog inputs are multifunction as programmed by the user. The analog inputs can be programmed to the following extended functions: • Three external reference inputs: pins AIN0, AIN1, AIN2, AIN3, AIN4 and AIN5 • Two sensor excitation current source: all analog input pins • Level shift (VBIAS): AINCOM pin • Eight GPIO: pins AIN3, AIN4, AIN5, AIN6, AIN7, AIN8, AIN9, AINCOM • Sensor break current source: all analog input pins • Two test signal output: pins AIN6, AIN7 Following the input multiplexer (mux), ADC1 features a high-impedance, CMOS, programmable gain amplifier (PGA). The PGA provides very low voltage and current noise, enabling direct connection to low-level transducers, and in many cases, eliminating the need for an external amplifier. The PGA gain is programmable from 1 V/V to 32 V/V in binary steps. The PGA can be bypassed to allow the input range to extend below ground. The PGA has voltage overrange monitors to improve the integrity of the conversion result. The PGA overrange alarm is latched during the conversion phase and appended to the conversion data. The programmable sensor bias uses a test current to help detect a failed sensor or sensor connection. An inherently stable delta-sigma modulator measures the ratio of the input voltage to the reference voltage to provide the ADC result. The ADC operates with the internal 2.5-V reference, or with up to three external reference inputs. The external reference inputs are continuously monitored for low (or missing) voltage. The reference alarm status is latched during the conversion phase and appended to the conversion data. The REFOUT pin is the buffered 2.5-V internal voltage reference output. Dual excitation current sources (IDAC) provide bias to resistance sensors (such as 3-wire RTD). The ADC integrates several system monitors for readback, such as temperature sensor and supply monitor. The ADC features an internal test signal voltage (TDAC) that is used to verify the ADC operation across all gains. The TDAC has two outputs to provide test voltages for single-ended and differential input configurations. Eight GPIO ports are available on the analog input pins. The digital filter provides two functional modes, sinc and FIR, allowing optimization of settling time and line-cycle rejection. The sinx/x (sinc) filter is programmable to sinc orders one through four to tradeoff filter settling time and 50-Hz and 60-Hz line-cycle rejection. The finite impulse response (FIR) filter mode provides single-cycle settled data with 50-Hz and 60-Hz line cycle rejection at data rates up to 20 SPS. 30 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Overview (continued) The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2) featuring buffered PGA inputs, gains from 1 V/V to 128 V/V, and data rates up to 800 SPS. All analog inputs and reference inputs are available to ADC2. ADC2 can be used to provide redundant measurements or system measurements such as sensor temperature compensation and thermocouple cold junction compensation (CJC). The ADS1263 is pin and functionally compatible to the ADS1262. The SPI™-compatible serial interface is used to read the conversion data and also to configure and control the ADC. The serial interface consists of four signals: CS, SCLK, DIN and DOUT/DRDY. The conversion data are provided with a CRC code for improved data integrity. The dual function DOUT/DRDY output indicates when conversion data are ready and also provides the data output. The serial interface can be implemented with as little as three connections by tying CS low. The ADC has three clock options: internal oscillator, external crystal, and external clock. The ADC detects the clock mode automatically. The nominal clock frequency is 7.3728 MHz. ADC conversions are started by a control pin or by commands. The ADC can be programmed to free-run mode or perform one-shot conversions. The DRDY and DOUT/DRDY pins are driven low when the conversion data are ready. The RESET/PWDN digital input resets the ADC when momentarily pulsed low, and when held low, enables the ADC power-down mode. The ADC operates with bipolar (± 2.5 V) supplies, or with a single 5-V supply. For single-supply operation, use the internal level-shift voltage to level-shift isolated (floating) sensors The digital power-supply range is 2.7 V to 5.25 V. The BYPASS pin is the subregulator output (2 V) that is used for internal digital supply. 9.2 Functional Block Diagram AVDD AVSS CAPP CAPN 2-V Digital Supply Ref Mux ADC1 2.5 V Ref REFOUT Sensor Bias 8 Level Shift Temp Sensor 32-bit û ADC1 Signal Level Alarm GPIO Sensor Bias PGA DRDY Buf PGA ADS1263 Only Input Mux ADC2 Low Ref Alarm Dual Sensor Excitation Input Mux ADC1 Power Supplies RESET/PWDN Control AIN0 AIN1 AIN2 AIN7 AIN8 AIN9 AINCOM LDO START Ref Mux ADC2 AIN3 AIN4 AIN5 AIN6 DVDD BYPASS Buf 24-bit û ADC2 Digital Filter CS Serial Interface SCLK DOUT/DRDY DIN Internal Oscillator Digital Filter XTAL1 Clock Mux XTAL2/CLKIN Test DAC DGND Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 31 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 9.3 Feature Description 9.3.1 Multifunction Analog Inputs The ADS1262 and ADS1263 have 11 multifunction analog inputs configurable in a variety of extended functions. Figure 66 shows the internal analog signal routing to the circuit blocks. Table 5 summarizes the input pin functions. The devices have two cross-point multiplexers; one multiplexer for ADC1, and one multiplexer for ADC2. The multiplexers select any analog input for the positive PGA input and any input for the negative PGA input. The ADCs are also configurable for a number of internal monitor functions. The internal monitors are temperature sensor, TDAC test voltage, analog power-supply voltage, and digital power-supply voltage. The dual excitation-current sources (IDAC1 and IDAC2) are independently connected to any analog input pin. Eight analog inputs are configurable as GPIO. The GPIOs are programmable as inputs or outputs, and are referenced to the analog power-supply voltages (VAVDD and VAVSS). The level-shift function (VBIAS) is available on AINCOM and is used to provide an input level-shift voltage for isolated sensors. The internal TDAC test voltage is available on output pins AIN6 and AIN7. The ADC has two voltage-reference multiplexers; one reference multiplexer for ADC1, and one reference multiplexer for ADC2. Through the reference multiplexers, select the internal reference, three external reference sources, or the analog power-supply voltage (VAVDD – VAVSS). 6 AIN0-AIN5 INT REF Sensor Excitation AIN0 - AINCOM ADC1 Input Mux Test DAC GPIO[7:0] AIN1 VREFP VREFN Analog Supply 11 AIN0 ADC1 Reference Mux TEMP Sensor 8 VAINP VAINN AIN2 Analog Supply Monitor Digital Supply Monitor AIN3 AIN4 AIN5 AIN6 ADS1263 Only AIN7 AIN0 - AIN5 AIN8 INT REF 2.5 V Reference AIN9 ADC2 Reference Mux VREFP_2 VREFN_2 Analog Supply AINCOM VBIAS Temperature Sensor AIN0 - AINCOM 2 ADC2 Input Mux Test DAC TEMP Sensor Test DAC VAINP_2 VAINN_2 Analog Supply Monitor Digital Supply Monitor Figure 66. Analog Input Routing Overview Table 5. Analog Input Pin Functions (1) 32 PIN ADC1 INPUT ADC2 INPUT ADC2 REF INPUT IDAC1 OUTPUT IDAC2 OUTPUT GPIO TDAC OUTPUT LEVEL SHIFT OUTPUT AIN0 Yes Yes REFP1, REFN1 REFP1 Yes Yes — — — AIN1 Yes Yes REFP1, REFN1 REFN1 Yes Yes — — — AIN2 Yes Yes REFP2, REFN2 REFP2 Yes Yes — — — AIN3 Yes Yes REFP2, REFN2 REFN2 Yes Yes GPIO[0] — — AIN4 Yes Yes REFP3, REFN3 REFP3 Yes Yes GPIO[1] — — AIN5 Yes Yes REFP3, REFN3 REFN3 Yes Yes GPIO[2] — — AIN6 Yes Yes — — Yes Yes GPIO[3] TDACP — AIN7 Yes Yes — — Yes Yes GPIO[4] TDACN — AIN8 Yes Yes — — Yes Yes GPIO[5] — — AIN9 Yes Yes — — Yes Yes GPIO[6] — — AINCOM Yes Yes — — Yes Yes GPIO[7] — Yes ADC1 REF INPUT (1) The reference voltage of ADC1 can be either polarity and reversed by programming. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.2 Analog Input Description As shown in Figure 67, the analog inputs of the device consist of ESD protection diodes, an ADC1 and ADC2 cross-point input multiplexer, the sensor bias circuit, and individual PGAs for each ADC. The ADC has 11 external inputs, four internal monitor signals, and one no-connection (float). Note that in figures throughout this document, italic text shows the associated register and register settings. AVDD ESD Diodes AIN0 AIN0 0000 AIN1 0001 AIN2 0010 AIN3 0011 AIN4 0100 AIN5 0101 AIN6 0110 AIN7 0111 AIN8 1000 AIN9 1001 AINCOM 1010 TEMP Sensor P Analog Supply Mon P 1011 1100 1101 Digital Supply Mon P AIN1 TDAC P AIN2 Float ADC1 Positive Multiplexer MUXP[3:0] bits 7:4 of INPMUX (register address = 06h) ADC2 Positive Multiplexer MUXP2[3:0] bits 7:4 ADC2MUX (register address = 16h) 1110 1111 VAINP1 VAINN1 AIN3 Sensor Bias PGA1 Sensor Bias PGA2 AIN4 AIN5 AIN6 VAINP2 AIN7 AIN8 AIN9 AINCOM ESD Diodes AIN0 0000 AIN1 0001 AIN2 0010 AIN3 0011 AIN4 0100 AIN5 0101 AIN6 0110 AIN7 0111 AIN8 1000 AIN9 1001 AINCOM 1010 TEMP Sensor N Analog Supply Mon N Digital Supply Mon N TDAC N Float VAINN2 (ADS1263) ADC1 Negative Multiplexer MUXN[3:0] bits 3:0 of INPMUX (register address = 06h) ADC2 Negative Multiplexer MUXN2[3:0] bits 3:0 of ADC2MUX (register address = 16h) 1011 1100 1101 1110 1111 AVSS Figure 67. ADC1 and ADC2 Input Block Diagram 9.3.2.1 ESD Diode The analog inputs have internal ESD diodes that are connected to the analog supplies (AVDD and AVSS). The function of the diodes is to protect the ADC inputs from ESD events. If the input signal exceeds VAVDD by more than 0.3 V or goes below VAVSS by more than –0.3 V, the diodes may conduct. When the diodes conduct, input current flows into the analog inputs through the AVDD or AVSS pins. If an input overvoltage is possible, limit the input current to less than |±10 mA|. In many applications, a resistor in series with the input is sufficient to limit the current. Depending on the application requirements, be aware of the thermal noise of the current limit resistor. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 33 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 9.3.2.2 Input Multiplexer Use the dual, cross-point input multiplexers to select from one of the 11 external inputs, one of the four internal monitors, and a floating connection, in any combination, to either ADC. One input is selected by the positive multiplexer, and one input is selected by the negative multiplexer. The ADC1 positive and negative multiplexers are programmed by bits MUXP[3:0] and bits MUXN[3:0] in the INPMUX register (address = 06h). The ADC2 positive and negative multiplexers have identical functionality and are programmed by bits MUXP2[3:0] bits and bits MUXN2[3:0] in the ADC2MUX register (address = 16h). 9.3.3 Sensor Bias The ADC incorporates a sensor bias current source that can be used to apply a small test current to diagnose broken sensor leads or problems existing in the sensor. Figure 68 shows the sensor bias block diagram. The sensor bias circuit consists of programmable current sources and bias resistors. The sensor bias circuit connects to the outputs of either the ADC1 or ADC2 multiplexers. Program the sensor bias to either pull-up or pull-down mode. In pull-up mode, the current flows into the positive input and flows out of the negative input. In pull-down mode, the polarities are reversed. Configure the sensor bias either to a 10-MΩ bias resistor, or to current with magnitudes of ±0.5, ±2, ±10, ±50, or ±200 µA. AVDD AVSS 10 MŸ SBMAG[2:0] bits 2:0 of MODE1 (register address = 04h) 10 MŸ 000 = off 001 = 0.5 uA 010 = 2 uA 011 = 10 uA 100 = 50 uA 101 = 200 uA 110 = 10 0Ÿ(shown) ADC1 INPUT MUX SBPOL bit 3 of MODE1 (register address = 04h) 0 = Pull-up mode (shown) 1 = Pull-down Mode SBADC bit 4 MODE1 (register address = 04h) 0 = ADC1 Connection (shown) 1 = ADC2 Connection VAINP1 VAINN1 PGA1 VAINP2 ADC2 INPUT MUX VAINN2 PGA2 Figure 68. Sensor Bias Block Diagram In pull-up mode, an open sensor results in the positive input pulled to VAVDD, and the negative input pulled to VAVSS. An open sensor in pull-up mode results in a positive full-scale reading. A full-scale reading can also be an indication of sensor overload or that the reference voltage is lower than expected. The sensor bias can remain on while actively converting, or pulsed on periodically to test the sensor. When pulsed on, allow time for settling because external capacitance loads the sensor bias when first enabled. Be aware of offset error as a result of sensor bias current flowing through the multiplexer switch resistance. 34 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.4 Temperature Sensor The ADC incorporates an integrated temperature sensor. The temperature sensor is comprised of two internal diodes with one diode having 16 times the current density of the other, as shown in Figure 69. The difference in current density of the diodes yields a differential output voltage that is proportional to absolute temperature. Measure the temperature sensor voltage with either ADC1 or ADC2. For ADC1 measurement, set the INPMUX register (address 06h) to BBh. For ADC2 measurement, set the ADC2MUX register (address 16h) to BBh. Equation 9 shows how to convert the temperature sensor reading to degrees Celcius (˚C): Temperature (°C) = [(Temperature Reading (µV) – 122,400) / 420 µV/°C] + 25°C where • Temperature reading units are in µV (9) Before temperature sensor measurement, enable the PGA, set gain = 1, disable chop mode, and make sure the internal voltage reference is powered on. As a result of the low package-to-PCB thermal resistance, the internal device temperature closely tracks the PCB temperature. Note that ADC self-heating results in an increase of 0.7°C relative to the temperature of the surrounding PCB. AVDD ADC1 MUX P 1x 2x TEMP Sensor P ADC1 MUX N TEMP Sensor N ADC2 MUX P 1x 8x ADC2 MUX N AVSS Figure 69. Temperature Sensor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 35 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 9.3.5 Power-Supply Monitor To internally monitor the ADC power supplies, use either ADC1 or ADC2. As shown in Figure 70, the power supply voltages are divided by a resistor network to reduce the voltages within the ADC input range. The reduced power-supply voltage is routed to the ADC input multiplexers. The analog (VANLMON) and digital (VDIGMON) power supply readings are scaled by Equation 10 and Equation 11, respectively: VANLMON = (VAVDD – VAVSS) / 4 VDIGMON = (VDVDD – VDGND) / 4 (10) (11) Measure the supply monitor readings using either the internal or an external reference. For an external reference, the minimum reference voltage is 1.5 V. Before measurement, enable the PGA, set gain = 1, and disable chop mode. For analog supply monitor ADC1 measurement, set the INPMUX register (address 06h) to CCh. For digital supply monitor ADC1 measurement, set the INPMUX register to DDh. For analog supply monitor ADC2 measurement, set the ADC2MUX register (address 16h) to CCh. For digital supply monitor ADC2 measurement, set the ADC2MUX register to DDh. AVDD Analog Supply Monitor Digital Supply Monitor DVDD ADC1 MUX P 1.5 R ADC1 MUX P 2.5 R VANLMON_ P VDIGMON_ P ADC1 MUX N R ADC1 MUX N R VANLMON_ N VDIGMON_ N ADC2 MUX P ADC2 MUX P 0.5 R 1.5 R ADC2 MUX N AVSS ADC2 MUX N DGND Figure 70. Power-Supply Monitors 36 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.6 PGA The ADC1 PGA is a low-noise, programmable gain, CMOS differential-input, differential-output amplifier. The PGA extends the ADC dynamic range of sensors with low input-signal levels. The PGA provides gains of 1, 2, 4, 8 ,16, and 32. Bypass the PGA to extend the analog input range to below ground (if the AVSS pin is grounded). Figure 71 shows the PGA block diagram. The PGA consists of two chopper-stabilized amplifiers (A1 and A2), and a resistor network that is programmed to set the PGA gain. The PGA input is equipped with a highfrequency, electromagnetic-interference (EMI) input filter consisting of two 350-Ω input resistors, and several filter capacitors, as shown in the figure. Bypass the PGA to directly connect the inputs to the ADC. The PGA output is monitored by an overrange voltage monitor. The voltage monitor triggers an alarm when the absolute or differential PGA output voltage exceeds the linear range of operation. Pins CAPP and CAPN are the PGA positive and negative outputs, respectively. Connect a 4.7-nF (C0G) capacitor as shown in the figure. The capacitor provides an analog antialias filter, as well as the deglitch filter for the modulator sample pulses. Place the capacitor close to the pins using short, direct traces. Avoid running clock traces or other digital traces close to the pins. BYPASS bit 7 of MODE2 (register address = 05h) 280 Ÿ 350 Ÿ VAINP 0 = PGA active (shown) 1 = PGA bypass CAPP + A1 ± 8 pF 12 pF GAIN[2:0] bits 6:4 of MODE2 (register address = 05h) 000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 PGA1 Over-range Detection 12 pF 12 pF ± A2 + 350 Ÿ VAINN 4.7 nF C0G ADC1 280 Ÿ CAPN 8 pF Figure 71. ADC1 PGA Block Diagram The ADC1 full-scale voltage range is determined by the reference voltage and the PGA gain. Table 6 shows the full-scale voltage range verses gain for reference voltage = 2.5 V. The full-scale voltage range scales with the reference voltage and is increased or decreased by changing the reference voltage. Table 6. ADC1 Full-Scale Voltage Range GAIN[2:0] BITS OF REGISTER MODE2 GAIN (V/V) FULL SCALE RANGE (V) (1) 000 1 ±2.500 V 001 2 ±1.250 V 010 4 ±0.625 V 011 8 ±0.312 V 100 16 ±0.156 V 101 32 ±0.078 V (1) VREF = 2.5 V. The full scale input range is proportional to VREF Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 37 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded. The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA output. The specified minimum and maximum absolute input voltages (VINP and VINN) depend on the PGA gain, the input differential voltage (VIN), and the tolerance of the analog power-supply voltages (VAVDD and VAVSS). The absolute positive and negative input voltages must be within the specified range, as shown in Equation 12: VAVSS + 0.3 + |VIN| · (Gain – 1) / 2 · < VINP and VINN < VAVDD – 0.3 – |VIN| · (Gain – 1) / 2 where • • VINP, VINN = absolute input voltage VIN = differential input voltage = VINP - VINN (12) The relationship between the PGA input to the PGA output is shown graphically in Figure 72. The PGA output voltages (VOUTP, VOUTN) depend on the PGA gain and the input voltage magnitudes. For linear operation, the PGA output voltages must not exceed VAVDD – 0.3 or VAVSS + 0.3. Note the diagram depicts a positive differential input voltage that results in a positive differential output voltage. PGA Input PGA Output VAVDD VAVDD ± 0.3 V VOUTP = VINP + VIN Â(Gain ± 1) / 2 VINP VIN = VINP Â9INN VINN VOUTN = VINN ± VIN Â(Gain ± 1) / 2 VAVSS + 0.3 V VAVSS Figure 72. PGA Input/Output Range If the PGA is bypassed, the ADC absolute input voltage range extends beyond the VAVDD and VAVSS power supplies allowing input voltages at or below ground. The absolute input voltage range when the PGA is bypassed is shown in Equation 13: VAVSS – 0.1 < VINP and VINN < VAVDD + 0.1 (13) 9.3.7 PGA Voltage Overrange Monitors ADC1 incorporates two PGA output-voltage monitors. The monitors trigger an alarm if the PGA output is driven into overrange. The corresponding bits are set (= 1) in the data output status byte when an alarm is triggered. The PGA output voltage is monitored in two ways: 1) Differential: If the PGA differential output voltage exceeds either +105% or –105% FSR. 2) Absolute: If either PGA absolute output voltage is higher than VAVDD – 0.2 V or lower than VAVSS + 0.2 V. The alarms automatically reset when the PGA is no longer in voltage overload. The monitors are fast-responding, analog, voltage-level comparators. Therefore, these monitors detect short-duration voltage overrange events that are not necessarily evident in the output as clipped codes because of averaging of the digital filter that may span one or more conversion cycles. Use the monitor function to detect certain type of faults (such as signal overranges, incorrect gain settings, sensor faults, input miswiring, and so on) without the need to change input configuration or interrupt readings. 38 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.7.1 PGA Differential Output Monitor ADC1 incorporates a differential PGA output voltage monitor. This voltage monitor triggers an alarm when the magnitude of the differential PGA output voltage is more positive than +105% or more negative than –105% of full scale, but only during a conversion cycle. The alarm event, corresponding to the conversion cycle when the alarm occurred, is set in the status byte (PGAD_ALM). For the next conversion, the alarm resets. If the magnitude of differential output voltage is within the range of ±105% of full-scale range, the alarm remains reset. The PGA differential monitor block diagram is shown in Figure 73. Data Bytes VOUTP VOUTN Digital Filter ADC PGA ADC STATUS VREF Comparators +105% VREF DATA 2 DATA 3 DATA 4 CRC/CHK PGAD_ALM Bit 1 of STATUS byte ± + DATA 1 Latch + S Q R Q ± ± PGA Output difference amplifier -105% VREF Conversion Start Reset + Figure 73. PGA Differential Overload Monitor PGA Differential Output (FSR) Figure 74 shows an example of the differential overrange monitor event. + 105% - 105% Alarms latched during conversion cycle Conversions (DRDY) PGAD_ALM bit Figure 74. PGA Differential Alarm Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 39 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 9.3.7.2 PGA Absolute Output-Voltage Monitor ADC1 contains an integrated a PGA absolute output-voltage monitor. If the absolute level of the PGA positive or negative output exceeds VAVDD – 0.2 V, the PGA high alarm triggers (PGAH_ALM). If the absolute level of the PGA positive or negative output voltage is less than VAVSS + 0.2 V, the PGA low alarm triggers (PGAL_ALM). The alarms are set in the status byte corresponding to the conversion cycle when the alarms occurred. For the next conversion cycle, the alarms reset. If the magnitude of PGA output voltages remains within the range (VAVDD – 0.2 V and VAVSS + 0.2 V), the alarms remain reset. The PGA absolute output-voltage monitor block diagram is shown in Figure 75. Data Bytes VOUTP VOUTN Digital Filter ADC PGA ADC VAVDD ± 0.2 V ± STATUS DATA 1 DATA 2 DATA 3 DATA 4 CRC/CHK PGAH_ALM Bit 2 of STATUS byte + S Q R Q Latch ± + ± Supply Rail Comparators PGAL_ALM Bit 3 of STATUS byte + S Q R Q Latch ± + VAVSS + 0.2 V Conversion Start Reset Figure 75. PGA Absolute Output-Voltage Monitor Figure 76 shows an example of the PGA absolute output-voltage monitor overrange event. VOUTP or VOUTN PGA Absolute Output (V) VAVDD - 0.2 VAVSS + 0.2 Alarms latched during conversion cycle Conversions (DRDY) PGAH_ALM bit PGAL_ALM bit Figure 76. PGA Absolute Alarm 40 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.8 ADC Reference Voltage These devices require a reference voltage for operation. Both ADCs default to the same internal reference, however, the reference voltage of ADC1 is independent of the ADC2 reference voltage. The reference voltage is provided internally by the internal 2.5-V reference, or externally, by one of the three external reference inputs. The specified external reference voltage range is 0.9 V to 5 V. The reference voltage is defined as VREF = VREFP – VREFN, where VREFP and VREFN are the absolute positive and absolute negative reference voltages, respectively. The polarity of the reference voltage internal to the ADC must be always positive. The magnitude of the reference voltage together with the PGA gain establishes the ADC full-scale differential input range as defined by VIN = ±VREF / gain. Figure 77 shows the block diagram of the ADC1 reference multiplexer. Use the reference multiplexer to select the internal reference, one of three external reference inputs, or the analog power supply. INTREF bit 0 of POWER (register address = 01h) AVDD REFOUT AIN0 1 PF (1) AIN2 AIN4 +2.5 V Reference 0 = reference off 1 = reference on RMUXP[2:0] bits 5:3 of REFMUX (register address = 0Fh) REFREV bit 7 of MODE0 (register address = 03h) 000 001 REF_MUXP 010 0 = normal 1 = reverse REF_ALM bit of status byte (bit 4) Low Reference Monitor 011 VVREFP + + ± VVREFN ± AIN3 AIN5 S Q R Q 000 AIN1 0 = no alarm 1 = alarm +0.4 V 100 001 Start Conversion Reset 010 011 REF_MUXN 100 ADC1 AVSS RMUXN[2:0] bits 2:0 of REFMUX (register address = 0Fh) (1) The internal reference requires a 1-µF capacitor connected to pins REFOUT and AVSS. Figure 77. ADC1 Reference Multiplexer Block Diagram The ADC1 reference multiplexer consists of a positive multiplexer and a negative multiplexer. The positive and negative multiplexers are programmed by the RMUXP[2:0] and RMUXN[2:0] bits, respectively, of the REFMUX register. The positive reference input is either internal (2.5 V), external (pins AIN0, AIN2, AIN4), or the analog power-supply voltage (VAVDD). The negative reference input is either internal (2.5 V), external (pins AIN1, AIN3, AIN5), or the analog power-supply voltage (VAVSS). A reference polarity-reversal switch changes the reference polarity from negative to positive. The polarity switch allows either positive or negative external reference polarity. Set the reversal switch to the normal position (REFREV = 0) when using the internal reference or analog power supplies. The ADC also contains and integrated low-reference voltage monitor. This monitor provides continuous detection of a low or missing reference during the conversion cycle. The low reference alarm is appended to the data output status byte (REF_ALM, bit 4 of the status byte). Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 41 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 9.3.8.1 Internal Reference The ADC incorporates an integrated, precision, 2.5-V reference featuring very low drift. The internal reference is enabled by setting INTREF equal to 1 (default is on). To select the internal reference for use with ADC1, set the RMUXP and RMUXN bits of register REFMUX to 0h. The REFOUT pin provides a buffered reference output voltage. The negative reference (return) is the AVSS pin, as shown in Figure 77. Be careful when laying out the REFOUT return to the AVSS pin. Connect a 1-uF capacitor from the REFOUT pin to the AVSS pin. The capacitor is not required if the internal reference is not used. The internal reference must be powered if using the IDACs or the internal temperature sensor. After internal reference start-up, the reference requires start-up time before beginning the first conversion; see Figure 33. 9.3.8.2 External Reference The ADC provides three external reference inputs. The reference inputs are differential with independent positive and negative inputs. The reference inputs are the analog pins, AIN0 to AIN5. Typically, the positive reference is applied to pin AIN0, AIN2, or AIN4, and the negative reference is applied to pin AIN1, AIN2, or AIN3. The reference polarity can be negative, but the ADC requires a positive voltage reference. In this case, reverse the polarity using the internal polarity-reversal switch (ADC1 reference only). The reference polarity-reversal switch changes the reference polarity from negative to positive, and is controlled by REFREV (bit 7 of MODE0). The reference inputs are high impedance. A reference input current flowing through a reference-voltage source impedance leads to possible loading errors (see Figure 34). To reduce the input current, use an external reference buffer; however, in most applications, an external reference buffer is not necessary. Connect a 100-nF bypass capacitor across the external reference input pins. Follow the specified absolute and differential reference voltage requirements. 9.3.8.3 Power-Supply Reference A third option for ADC reference is the internal analog power supply. However, an increase of linearity error results with this connection, and therefore, use this option only for less-critical applications, such as ADC selfdiagnostics. For critical applications, do not not use power-supply reference option. For applications that use the powersupply voitage as the reference voltage, connect the power-supply voltage to the external reference inputs, and select the appropriate external reference bits in the REFMUX register. For example, to measure a 6-wire loadcell, connect the bridge excitation voltages to the external reference inputs, and select the appropriate REFMUX bits. 9.3.8.4 Low-Reference Monitor ADC1 incorporates a low-reference monitor to detect a low or missing reference. If the differential reference voltage (VREF = VREFP – VREFN) falls below 0.4 V (typical), the low reference alarm triggers (REF_ALM). The lowreference monitor sets the corresponding alarm bit in the conversion data status byte. The alarm resets at the start of each new conversion. Use the low-reference monitor to detect a missing or failed reference voltage connection. Connect a 100-kΩ resistor across the reference inputs to provide the necessary bias. If either reference input is missing or unconnected, this external resistor biases the reference inputs to each other. The low-reference monitor is a fast-responding analog comparator; therefore, transients in the reference voltage may trigger the alarm. 42 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.8.5 Sensor-Excitation Current Sources (IDAC1 and IDAC2) The ADS1262 and ADS1263 incorporate two, integrated, matched current sources (IDAC1, IDAC2). The current sources provide excitation current to resistive temperature devices (RTDs), thermistors, diodes, and other sensors that require constant current biasing. These devices also contain an internal IDAC multiplexer that provides connection of IDAC1 or IDAC2 to one of the 11 analog pins (AIN0 to AINCOM). The IDACs can be programmed over these current ranges: 50 µA, 100 µA, 250 µA, 500 µA, 750 µA, 1000 µA, 1500 µA, 2000 µA, and 3000 µA. Figure 78 details the IDAC connection. The IDAC switches shown in the diagram are used in the IDAC rotation mode. MUX1[3:0] bits 3:0 of IDACMUX (register address = 0Dh) IDAC Modes CHOP[1:0] bits 5:4 of register MODE0 (register address = 03h) AIN0 AIN0 0000 AIN1 0001 AIN2 0010 AIN3 0011 AIN4 0100 AIN5 0101 AIN6 0110 AIN7 AIN8 0111 1000 AIN9 1001 AINCOM 1010 No Connection 1011 AIN0 0000 AIN1 0001 AIN2 0010 AIN3 0011 VAVDD IDAC1 MUX 00: Normal (shown) 01: Chop on (see Chop section) 10: IDAC rotation (automated) 11: Chop on and IDAC rotation MAG1[3:0] bits 3:0 of IDACMAG (register address = 0Eh) IDAC1 0000: off 0001: 50 µA 0010: 100 µA 0011: 250 µA 0100: 500 µA 0101: 750 µA 0110: 1000 µA 0111: 1500 µA 1000: 2000 µA 1001: 3000 µA AIN1 AIN2 AIN4 ` AIN3 AIN5 AIN6 AIN7 AIN8 AIN9 AINCOM AIN4 0100 AIN5 0101 AIN6 0110 AIN7 0111 AIN8 1000 AIN9 1001 AINCOM No Connection VAVDD IDAC2 MUX 1010 1011 MAG2[3:0] bits 7:4 of IDACMAG (register address = 0Eh) IDAC2 0000: off 0001: 50 µA 0010: 100 µA 0011: 250 µA 0100: 500 µA 0101: 750 µA 0110: 1000 µA 0111: 1500 µA 1000: 2000 µA 1001: 3000 µA MUX2[3:0] bits 7:4 of IDACMUX (register address = 0Dh) Figure 78. IDAC Block Diagram The internal reference must be enabled for IDAC operation. Take care not to exceed the compliance voltage of the IDACs. In other words, the voltage on the input pin must not exceed VAVDD – 1.1 V; otherwise, the specified accuracy of the IDAC current is not met. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 43 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com The IDAC currents track the internal reference voltage. As a result of using the same reference voltage for IDAC1 and IDAC2, the current sources are matched. Matched performance is important for applications such as hardware compensated, 3-wire RTDs. IDAC to IDAC mismatch can be improved further by use of the IDAC rotation mode. The rotation mode automatically swaps the IDAC1 and IDAC2 connections of alternate conversions. The ADC averages the alternate conversions to eliminate IDAC mismatch. IDAC rotation can be performed manually by the user (by alternating the IDAC pin connections) or by the IDAC automatic rotation mode. The IDAC rotation sequence is shown as follows: • Conversion 1: IDAC1, IDAC2 normal → first output result withheld • Conversion 2: IDAC1, IDAC2 rotated positions → Output result 1 = (Conversion 1 + Conversion 2) / 2 • Conversion 3: IDAC1, IDAC2 normal → Output result 2 = (Conversion 3 + Conversion 2) / 2 • Conversion 4: IDAC1, IDAC2 rotated positions → Output result 3 = (Conversion 4 + Conversion 3) / 2 The sequence repeats for all succeeding conversions. In rotation mode, the ADC provides a time delay to allow for settling after the IDAC pin connections are alternated. Note IDAC switching transients may interact with external components that may require additional time to settle. Additional settling time are provided by bits DELAY[3:0] in the MODE0 register. The total delay time results in a reduction of the nominal data rate (See Conversion Latency). Nevertheless, the existing frequency response nulls provided by the digital filter remain unchanged. 9.3.8.6 Level-Shift Voltage The ADC integrates an optional level-shift voltage on the AINCOM pin. As shown in Figure 79, the level-shift voltage is the midvoltage of the analog power supply. The level-shift voltage shifts floating sensors (that is, sensors isolated from the ADC ground) to within the ADC specified input range. Thermocouple and 4-mA to 20mA transmitters (isolated supply) are examples of floating signals. AVDD INPUT MUX AINCOM R 100 Ÿ VBIAS = (VAVDD + VAVSS) /2 R VBIAS bit 1 of POWER (register address = 01h) 0 = off 1 = on AVSS Figure 79. Level-Shift Voltage Diagram When operating the ADC with ±2.5-V analog supplies, either ground the AINCOM pin or use the level-shift voltage. Level shift other inputs by connecting the input pins to the REFOUT pin (2.5 V). The turn-on time of the level-shift voltage depends on the pin load capacitance. The total capacitance includes those connected to AVDD, AVSS and ground. Table 7 lists the level-shift voltage settling times for various external load capacitances. Be certain the level-shift voltage is fully settled before starting a conversion. Table 7. Level-Shift Enable Time 44 LOAD CAPACITANCE LEVEL-SHIFT VOLTAGE SETTLING TIME 0.1 µF 0.22 ms 1 µF 2.2 ms 10 µF 22 ms Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.9 ADC1 Modulator The ADC1 modulator is an inherently stable, fourth-order, 2 + 2 pipelined ΔΣ modulator. The modulator samples the analog input voltage at a high sample rate (fMOD = fCLK / 8 = 921.6 kHz) and converts the analog input to a ones density bit stream. The digital filter receives the ones density bit stream output, and then filters and decimates the data to yield the final conversion result. 9.3.10 Digital Filter The digital filter of ADC1 receives the modulator output data and produces a high-resolution conversion result. The digital filter low-pass filters and decimates the modulator data (rate reduction), yielding the final data output. By adjusting the type of filtering, tradeoffs are made between resolution, data rate, line cycle rejection, and conversion latency. The digital filter has two selectable modes: sin (x) / x (sinc) mode and finite impulse response (FIR) mode (see Figure 80). The sinc mode provides data rates of 2.5 SPS though 38400 SPS with selectable sinc orders of 1 through 5. The FIR filter provides simultaneous rejection of 50-Hz and 60-Hz power-line frequencies with data rates 2.5 SPS through 20 SPS with single-cycle settled conversions. fCLK: 7.3728 MHz 38400 SPS 19200 SPS 14400 SPS fCLK/8 fMOD: 921.6 kHz Modulator 921.6 kHz 1st Stage Sinc5 Filter 14400 SPS Decimation A (24, 48, 64) 2.5 SPS...7200 SPS 2nd Stage SincN Filter Filter Output FIR Filter Section Decimation B (2...5760) 20 SPS 600 SPS FIR DR[3:0] bits 3:0 of MODE2 (register address = 05h) 0000 = 2.5 SPS 0001 = 5 SPS 0010 = 10 SPS 0011 = 16.6 SPS 0100 = 20 SPS 0101 = 50 SPS 0110 = 60 SPS 0111 = 100 SPS 1000 = 400 SPS 1001 = 1200 SPS 1010 = 2400 SPS 1011 = 4800 SPS 1100 = 7200 SPS 1101 = 14400 SPS 1110 = 19200 SPS 1111 = 38400 SPS FILTER[2:0] bits 7:5 of MODE1 (register address = 04h) Decimation (30) Averager Average (2,4,8) 10 SPS 5 SPS 2.5 SPS 000 = sinc1 001 = sinc2 010 = sinc3 011 = sinc4 100 = FIR Figure 80. Digital Filter Block Diagram 9.3.10.1 Sinc Filter Mode The sinc filter consists of two stages: a variable-decimation, fixed-order sinc5 filter, followed by a variabledecimation, variable-order sinc filter. The first-stage filter is sinc5. The sinc5 stage filters and down-samples the modulator data (fCLK / 8 = 921.6 kHz) to 38400 SPS, 19200 SPS, and 14400 SPS by decimating to 24, 48, and 64, respectively. These data rates bypass the second filter stage and as a result have a sinc5 frequency response profile. The second filter stage receives the data from the first stage at 14400 SPS. The second stage reduces the data rate to produce output data of 7200 SPS to 2.5 SPS. The second stage is a variable-order sinc filter that is programmable. The combined decimation ratio of the first and second stages determine the output data rate as follows: data rate = 921.6 kHz / (A · B). The filter order of the second stage affects the 50-Hz and 60-Hz rejection together with conversion latency. The high-order sinc filter yields the widest 50-Hz and 60-Hz response null widths, but correspondingly increases the conversion latency. The sinc order is programmed by the FILTER[2:0] bits of register MODE1. Table 8 lists the decimation ratio corresponding to the first and second filter stages (A and B, respectively) for each data rate. The data rate is programmed by the DR[3:0] bits of register MODE2. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 45 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Table 8. Sinc Filter Mode Data Rates and Decimation Ratio DATA RATE (SPS) (1) DR[3:0] BITS OF REGISTER MODE2 FIRST-STAGE DECIMATION RATIO A SECOND-STAGE DECIMATION RATIO B 2.5 0000 64 5760 (1) 5 0001 64 2880 10 0010 64 1440 16.6 0011 64 864 20 0100 64 720 50 0101 64 288 60 0110 64 240 100 0111 64 144 400 1000 64 36 1200 1001 64 12 2400 1010 64 6 4800 1011 64 3 7200 1100 64 2 14400 1101 64 1 19200 1110 48 1 38400 1111 24 1 fCLK = 7.3728 MHz. Data rate scales with fCLK 9.3.10.1.1 Sinc Filter Frequency Response The low-pass filtering effect of the sinc filter sets the overall frequency response of the ADC. The frequency response of data rates 14400 SPS, 19200 SPS and 38400 SPS is that of the first filter stage. The frequency response of data rates 2.5 SPS ranging to 7200 SPS is the product of the first and second stage individual frequency responses. The overall filter response is given in Equation 14: 5 H sinc5  f  u H sincN  f  H f  ª 512ŒI B º ª 8ŒIA º sin « sin « » » f CLK ¼ ¬ ¬ f CLK ¼ u ª 512ŒI º ª 8Œf º A u sin « B u sin « » » ¬ f CLK ¼ ¬ f CLK ¼ N where • • • • • f = signal frequency fCLK = ADC clock frequency A = First-stage decimation ratio (see Table 8) B = Second-stage decimation ratio (see Table 8) N = Second-stage filter order where N = 1 (sinc1), 2 (sinc2), 3 (sinc3), or 4 (sinc4) (14) The digital filter attenuates out-of-band noise that is present in the signal, and noise within the PGA and ADC modulator. Adjusting the filter by changing the decimation ratio and sinc order changes the filter bandwidth. Tradeoffs are made between signal bandwidth, noise, and filter latency. 46 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) As shown in Figure 81 and Figure 82, the first-stage sinc5 filter has frequency response nulls occurring at the data rate (fMOD / A) and at data rate multiples. At the null frequencies, the filter has zero gain. -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 10 20 30 40 50 60 70 80 Frequency (kHz) 0 90 100 110 120 10 20 30 40 D001 Figure 81. Sinc Frequency Response (38400 SPS) 50 60 70 80 Frequency (kHz) 90 100 110 120 D002 Figure 82. Sinc Frequency Response (14400 SPS) The second stage superimposes new nulls in the frequency response over the nulls produced by the first stage. The first of the superimposed frequency response nulls occur at the output data rate, followed by nulls occurring at data rate multiples. Figure 83 illustrates the frequency response of data rate 2400 SPS produced by the combined filter stages. This data rate has five equally-spaced nulls between the larger nulls produced by the first stage. The frequency response is also characteristic of data rates 2.5 SPS to 7200 SPS that are also produced by the second-stage filter. Figure 84 shows the frequency response nulls for 10 SPS. 0 0 sinc1 sinc2 sinc3 sinc4 -20 -40 Amplitude (dB) Amplitude (dB) -40 sinc1 sinc2 sinc3 sinc4 -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 5 10 15 20 25 30 Frequency (kHz) 35 40 45 0 10 20 D003 Figure 83. Sinc Frequency Response (2400 SPS) 30 40 50 60 70 80 Frequency (Hz) 90 100 110 120 D004 Figure 84. Sinc Frequency Response (10 SPS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 47 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Figure 85 and Figure 86 illustrate the frequency response of data rates 50 SPS and 60 SPS. The frequency response is plotted out to the 50-Hz 12th harmonic (10th harmonic for 60 Hz). The 50-Hz or 60-Hz fundamental frequency and harmonics are suppressed by increasing the second-stage filter order, as shown in the figures. 0 0 sinc1 sinc2 sinc3 sinc4 -20 -40 Amplitude (dB) Amplitude (dB) -40 sinc1 sinc2 sinc3 sinc4 -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 200 250 300 350 400 450 500 550 600 Frequency (Hz) D005 0 Figure 85. Sinc Frequency Response (50 SPS) 60 120 180 240 300 360 Frequency (Hz) 420 480 540 600 D006 Figure 86. Sinc Frequency Response (60 SPS) Figure 87 and Figure 88 plot the detailed frequency response of 50-SPS and 60-SPS data rates of different sincfilter orders. Note that the high-order sinc filter increases the width of the null and improves line cycle rejection. The high-order filter decreases the sensitivity of the ratio tolerance between the ADC clock frequency and the line frequency that can otherwise degrade line cycle rejection. As shown in the plots, the best 50-Hz or 60-Hz rejection is provided by the sinc4 order, but has longer filter latency compared to the sinc1 order. 0 0 sinc1 sinc2 sinc3 sinc4 -20 -40 Ampliude (dB) Amplitude (dB) -40 -60 -80 -100 -80 -100 -120 -140 -140 46 47 48 49 50 51 Frequency (Hz) 52 53 54 55 -160 55 56 D009 Figure 87. Sinc Frequency Response Zoom (50 SPS) 48 -60 -120 -160 45 sinc1 sinc2 sinc3 sinc4 -20 57 58 59 60 61 Frequency (Hz) 62 63 64 65 D010 Figure 88. Sinc Frequency Response Zoom (60 SPS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 The overall sinc filter frequency has a low-pass response that rolls off high-frequency components in the signal. The signal bandwidth depends on the output data rate and the order of the sinc filter. Note the overall system bandwidth is the combination of the digital filter, the antialias filter, and external filter components. Table 9 lists the –3-dB filter bandwidth of the sinc filter. Note the bandwidth reduction of the higher-order sinc filters. Table 9. Sinc Filter Bandwidth -3-dB BANDWIDTH (Hz) DATA RATE (SPS) SINC1 SINC2 SINC3 SINC4 SINC5 2.5 1.10 0.80 0.65 0.58 — 5 2.23 1.60 1.33 1.15 — 10 4.43 3.20 2.62 2.28 — 16.6 7.38 5.33 4.37 3.80 — 20 8.85 6.38 5.25 4.63 — 50 22.1 16.0 13.1 11.4 — 60 26.6 19.1 15.7 13.7 — 100 44.3 31.9 26.2 22.8 — 400 177 128 105 91.0 — 1200 525 381 314 273 — 2400 1015 751 623 544 — 4800 1798 1421 1214 1077 — 7200 2310 1972 1750 1590 — 14400 — — — — 2940 19200 — — — — 3920 38400 — — — — 7740 9.3.10.2 FIR Filter The finite impulse response (FIR) filter of ADC1 is a coefficient based filter that provides simultaneous rejection of 50-Hz and 60-Hz line cycle frequencies and harmonics. The FIR filter data rates are 2.5, 5, 10 and 20 SPS. All of the FIR data rates settle within a single conversion cycle. As shown in Figure 80, the FIR filter section receives data from the second-stage sinc filter at 600 Hz. The FIR filter section decimates by 30 to yield the output data rate of 20 SPS. A first-order averager (sinc1) with variable decimation provides the data rates of 10 SPS, 5 SPS, and 2.5 SPS. 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) As shown in Figure 89 and Figure 90, the FIR filter frequency response has a series of response nulls close to 50 Hz and 60 Hz. The response nulls repeat close to the 50-Hz and 60-Hz harmonics. The FIR frequency response superimposes with the response of the 600-SPS pre-stage filter. -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 0 30 60 90 120 150 180 Frequency (Hz) 210 240 270 300 -160 40 45 D011 Figure 89. FIR Frequency Response (20 SPS) 50 55 60 Frequency (Hz) 65 70 D012 Figure 90. FIR Frequency Response Detail (20 SPS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 49 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Figure 91 is the FIR filter response at 10 SPS. As a result of the sinc1 averager in the FIR filter block, new frequency-response nulls are superimposed to the response shown in Figure 89. The first of the added response nulls occur at 10 Hz. Additional nulls occur at folded frequencies around 20-Hz multiples. These additional nulls are seen at 10 Hz and 30 Hz. 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 0 30 60 90 120 150 180 Frequency (Hz) 210 240 270 300 D013 Figure 91. FIR Frequency Response (10 SPS) Similar to the response of the sinc filter, the overall FIR filter frequency has a low-pass response that rolls off high frequencies of the signal. The response is such that the FIR filter limits the bandwidth of the input signal. The FIR filter signal bandwidth depends on the output data rate. Table 10 lists the –3-dB filter bandwidth of the FIR filter. The total system bandwidth is the combined individual responses of the digital filter, the ADC antialias filter, and external filter components. Table 10. FIR Filter Bandwidth 50 DATA RATE (SPS) –3-dB BANDWIDTH (Hz) 2.5 1.2 5 2.4 10 4.7 20 13 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.10.3 50-Hz and 60-Hz Line Cycle Rejection If the ADC connection leads are in close proximity to industrial motors and conductors, coupling of 50-Hz and 60Hz power line frequencies can occur. The coupled noise interferes with the signal voltage, and may lead to inaccurate or unstable conversions. The digital filter provides enhanced rejection of power-line coupled noise for data rates of 60 SPS and less. Program the filter to tradeoff data rate and conversion latency versus the desired level of line cycle rejection. Table 11 summarizes the ADC1 50-Hz and 60-Hz line-cycle rejection based on 2% and 6% ratio tolerance of power-line to ADC clock frequency. Best possible power line rejection is provided by the high-order sinc filter and by using an accurate ADC clock. Table 11. 50-Hz and 60-Hz Line Cycle Rejection DIGITAL FILTER Response (dB) DATA RATE (SPS) FILTER TYPE 50 Hz ±2% 60 Hz ±2% 50 Hz ±6% 60 Hz ±6% 2.5 FIR –113 –99 –88 –80 2.5 Sinc1 –36 –37 –40 –37 2.5 Sinc2 –72 –74 –80 –74 2.5 Sinc3 –108 –111 –120 –111 2.5 Sinc4 –144 –148 –160 –148 5 FIR –111 –95 –77 –76 5 Sinc1 –34 –34 –30 –30 5 Sinc2 –68 –68 –60 –60 5 Sinc3 –102 –102 –90 –90 5 Sinc4 –136 –136 –120 –120 10 FIR –111 –94 –73 –68 10 Sinc1 –34 –34 –25 –25 10 Sinc2 –68 –68 –50 –50 10 Sinc3 –102 –102 –75 –75 10 Sinc4 –136 –136 –100 –100 16.6 Sinc1 –34 –21 –24 –21 16.6 Sinc2 –68 –42 –48 –42 16.6 Sinc3 –102 –63 –72 –63 16.6 Sinc4 –136 –84 –96 –84 20 FIR –95 –94 –66 –66 20 Sinc1 –18 –34 –18 –24 20 Sinc2 –36 –68 –36 –48 20 Sinc3 –54 –102 –54 –72 20 Sinc4 –72 –136 –72 –96 50 Sinc1 –34 –15 –24 –15 50 Sinc2 –68 –30 –48 –30 50 Sinc3 –102 –45 –72 –45 50 Sinc4 –136 –60 –96 –60 60 Sinc1 –13 –34 –12 –24 60 Sinc2 –27 –68 –24 –48 60 Sinc3 –40 –102 –36 –72 60 Sinc4 –53 –136 –48 –96 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 51 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 9.3.11 General-Purpose Input/Output (GPIO) Eight analog inputs can be programmed as GPIO functions (GPIO[0] through GPIO[7]). The GPIO function is a digital input/output with a logic value that is read and written by the GPIODAT data register. The GPIO voltage levels are referenced to the ADC analog power supply voltages, VAVDD and VAVSS. The GPIO input voltage threshold for logic 1 is (VAVDD + VAVSS) / 2. As shown in Figure 92, analog inputs, AIN3 through AINCOM, can be programmed for GPIO function. Register GPIOCON programs the GPIO connection for each pin (1 = connect). Register GPIODIR programs the direction of each pin, either as input or output (0 = output). Register GPIODAT is the GPIO data value register. Note if a GPIO pin is programmed as an output, the readback data value of the corresponding GPIODAT register bit is zero. AVDD CON[7:0] bits 7:0 of GPIOCON 0 = no connect (register address = 12h) 1 = connect DAT[7:0] bits 7:0 of GPIODAT (register address = 14h) AIN3 AIN4 0 = VGPIO < (VAVDD+ VAVSS) /2 1 = VGPIO > (VAVDD+ VAVSS) /2 GPIO[0] GPIO[1] GPIO 1 of 8 Write Read GPIO[2] AIN5 0 0 GPIO[3] AIN6 AIN7 AIN8 AIN9 AINCOM 1 GPIO[4] GPIO[5] + GPIO[6] ± GPIO[7] VAVDD + VAVSS 2 GPIO Read Select DIR[7:0] bits 7:0 of GPIODIR (register address = 13h) 0 = Output 1 = Input AVSS Figure 92. GPIO Block Diagram 52 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 9.3.12 Test DAC (TDAC) The ADC includes a test voltage digital-to-analog converter (TDAC) intended for ADC self-testing and verification. The TDAC is capable of providing single-ended, differential and common mode test voltages. The voltages are suitable to test the ADCs under all gains and input configurations. As shown in Figure 93, the TDAC consists of two independent DACs, TDACP, and TDACN. The DACs have independent control registers to program the output voltage. TDACP is programmed by register TDACP and TDACN is programmed by register TDACN. The TDACP output connects to the ADC1 and ADC2 positive input multiplexer input and TDACN connects to the ADC1 and ADC2 negative input multiplexer. The OUT1 and OUT2 bits can be programmed to connect the TDAC outputs to pins AIN6 and AIN7. The TDAC outputs are unbuffered and should not be loaded. The TDAC reference voltage is the analog supply (VAVDD – VAVSS); therefore, the output levels refer to, and scale with, the analog power supply. Note that chop mode must be disabled to test the ADC with the TDAC. AVDD MAGP[4:0] bits 4:0 of TDACP (register address = 10h) AVSS TDACP ADC VTDACP ADC1 Input MUX MAGN[4:0] bits 4:0 of TDACN (register address = 11h) TDACN ADC VTDACN >0000h: > Mid-supply 00000: = Mid-supply VAVSS – 0.3 V under the expected minimum and maximum input conditions, respectively. The input range requirement of ADC2 is verified in the same way as ADC1. See Equation 15 for the ADC2 input range requirements. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 109 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Application Information (continued) 10.1.5 Input Filtering Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process; and second, to reduce external noise that affects the measurement. 10.1.5.1 Aliasing As with all ADCs, out-of-band input signals can fold back or alias if not band-limited. Aliasing describes the effect of input frequencies greater than ½ the sample rate folding back to the bandwidth of interest. An antialias filter placed at the ADC inputs reduces the magnitude of the aliased frequencies. The ADS1262 and ADS1263 incorporate analog and digital antialiasing filters to attenuate the aliased frequencies. There are two ranges of aliased frequencies: frequencies greater than ½ of the down-sampled output data rate (Nyquist frequency) and frequencies occurring at multiples of the modulator sample rate. Aliasing can occur at frequencies greater than ½ the ADC output data rate. For example, at data rate of 50 SPS, aliasing occurs at frequencies greater than 25 Hz. The ADC digital filter rejects the aliased frequencies as input frequency increases. The amount of aliased frequency rejection is given by the filter type and order. Figure 150 shows the frequency response of the sinc filter. Note the sinc4 filter provides the best rejection of aliased frequencies. 0 sinc1 sinc2 sinc3 sinc4 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 0 50 100 150 200 250 300 350 400 450 500 550 600 Frequency (Hz) D005 Figure 150. Frequency Response (50 SPS) 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) The second band of aliased frequencies occur at the ADC modulator sample rate multiples (fMOD = fCLK / 8 = 921.6 kHz, multiples = 1843.2 kHz and so on). Figure 151 shows the 38400 SPS frequency response plotted to 1.2 MHz. The response near dc is the signal bandwidth of interest. Observe how the digital filter response repeats on the sides of the modulator sample rate (921.6 kHz). Figure 152 shows the repeated response at the modulator frequency multiples = N · fMOD ± fDR, where N = multiples of fMOD starting at 1, and fDR = data rate frequency. The digital filter attenuates signal or noise up to where the response repeats. However, signal or noise occurring at the modulator sample rate is not attenuated by the digital filter and therefore, is aliased to the passband. -60 -80 -100 -80 -100 -120 -120 -140 -140 -160 -160 0 200 400 600 800 Frequency (kHz) 1000 1200 0 1 D014 Figure 151. Frequency Response to 1.2 MHz (38400 SPS) 110 -60 2 3 4 5 Frequency (MHz) 6 7 8 D015 Figure 152. Frequency Response to 8 MHz (38400 SPS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Application Information (continued) Figure 153 illustrates how the frequencies alias near the modulator sample rate frequency. The final figure shows the aliased frequency rejection provided by an antialias filter. The ADC incorporates an analog antialias filter with a cutoff frequency of 60 kHz that rejects the aliased frequencies. Magnitude Sensor Signal Unwanted Signals Unwanted Signals Output Data Rate fMOD / 2 fMOD Frequency fMOD Frequency fMOD Frequency Magnitude Digital Filter Aliasing of Unwanted Signals Output Data Rate fMOD / 2 Magnitude External Antialiasing Filter Roll-Off Output Data Rate fMOD / 2 Figure 153. Alias Effect Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of change. In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However, any noise picked up along the sensor wiring or the application circuitry can potentially alias into the pass band. Power line-cycle frequency and harmonics are one common noise source. External noise is also generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 111 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Application Information (continued) cellular phones. Another noise source exists on the printed circuit board (PCB) in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result. The ADC incorporates an low-pass, antialias filter with a corner frequency of 60 kHz to reduce the aliased frequencies. The filter consists of the external 4.7-nF PGA output capacitor (CAPP and CAPN pins) and internal 280-Ω resistors. Use an input filter to provide increased rejection of aliased noise frequencies and further attenuate possible strong high-frequency interference signals. For best performance, filter strong interference frequencies at the ADC inputs. Ideally, select a low-pass corner frequency that allows frequencies within the desired bandwidth and attenuates those frequencies outside the desired bandwidth. As a result of the stable and linear dielectric characteristics, use C0G-type MLCC capacitors in analog signal filters. In applications where high energy transients can be generated, such as caused by inductive load switching, transient voltage suppressor (TVS) diodes or external ESD diodes should be used to protect the ADC inputs. 10.1.6 Input Overload Follow the input overvoltage precautions as outlined in the ESD Diode section. Despite external current limit provided for the input pins, if an overvoltage condition occurs on an unused channel, the overvoltage channel may crosstalk to the measurement channel. One solution is to externally clamp the inputs with low-forward voltage diodes as shown in Figure 154. The external diodes shunt the overvoltage fault current around the ADC inputs. Be aware of the reverse leakage current in the external clamp diodes in the application. IFAULT Schottky Diode RI-LIM +5 V AVDD AINx ADC VIN-FAULT > VAVDD + 0.3 V VIN-FAULT < VAVSS + 0.3 V Schottky Diode AVSS IFAULT Figure 154. External Diode Voltage Clamp 10.1.7 Unused Inputs and Outputs To minimize input leakage of the measurement channel, tie the unused input channels to midsupply (VAVDD + VAVSS) / 2. Use the 2.5-V reference output voltage for this purpose if operating with single 5-V supply. Do not float unused digital inputs. Tie all unused digital inputs to the appropriate levels, VDVDD or VDGND, including when in power-down mode. Do not float (3-state) the digital inputs to the ADC or excessive power-supply leakage current can result. If the DRDY output is unused, leave the pin unconnected or connect to an external circuit. 10.1.8 Voltage Reference For nonratiometric (absolute) measurements where the input signal is not derived from the voltage reference, either use the internal precision voltage reference, or use an external precision reference. Examples of these types of measurements come from sensors such as thermocouples, 20-mA transmitters, and accelerometers. For ratiometric measurements, where the input signal is derived from the voltage reference, reference noise and drift are cancelled by the same ratio of noise and drift within the signal. Ratiometric operation is common with many types of bridge and RTD measurements. For best noise performance, match the reference filter and input filter time constants (see the 3-Wire RTD Measurement with Lead-Wire Compensation section for more information). In general, achieve the best ADC signal-to-noise ratio by using large amplitude signals, a large reference voltage, and the highest gain setting possible. 112 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Application Information (continued) 10.1.9 Serial Interface Connections After power up, take the CS input high to reset the ADC serial interface. CS high resets the serial interface in the event an unintentional SCLK glitch has occurred during power-on initialization. If CS is tied low, glitches at SCLK power on can interrupt synchronization to the serial interface and must be avoided. In this case, reset the ADC using the PWDN/RESET input. The SCLK input is edge sensitive, and therefore must be free of noise, glitches, and overshoot. Use a terminating resistor located at the SCLK buffer to smooth the edges and reduce overshoot. Most microcontroller SPI peripherals can operate with the ADC. The interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are updated or changed on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol employed by the device is found in the Timing Requirements: Serial Interface table. Place a 47-Ω resistor in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, and DRDY). The resistors match the characteristic impedance of the PCB trace by source termination, helping reduce overshoot and ringing. 1 AIN8 AIN7 28 2 AIN9 AIN6 27 3 AINCOM AIN5 26 4 CAPP AIN4 25 5 CAPN AIN3 24 6 AVDD AIN2 23 7 AVSS AIN1 22 8 REFOUT AIN0 21 9 START RESET/PWDN 20 10 CS DVDD 19 11 SCLK DGND 18 12 DIN BYPASS 17 13 DOUT/DRDY XTAL2 16 14 DRDY XTAL1/CLKIN 15 4.7 nF 5V 1 F 0.1 F 3.3 V Device 1 F 10 k 47 GPIO GPIO 3.3 V 47 GPIO 0.1 F Microcontroller with SPI 47 SCLK 1 F 47 MOSI 47 MISO 1 F 47 GPIO/IRQ 3.3 V DVDD 0.1 F DGND Figure 155. Serial Interface Connections Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 113 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 10.2 Typical Applications 10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation Figure 156 is a fault-protected, filtered, 3-wire RTD application circuit with hardware-based, lead-wire compensation. Two IDAC current sources provide the lead-wire compensation. One IDAC current source (IDAC1) provides excitation to the RTD element. The ADC reference voltage input (pins AIN2 and AIN3) is derived from the same current by resistor RREF, providing ratiometric cancellation of current-source drift. The other current source (IDAC2) has the same current setting, providing cancellation of lead-wire resistance by generating a voltage drop across lead-wire resistance RLEAD2 equal to the voltage drop of RLEAD1. Because the RRTD voltage is measured differentially at ADC pins AIN4 and AIN5, the voltages across the lead wire resistance cancel. Resister RBIAS level-shifts the RTD signal to within the ADC specified input range. The current sources are provided by two additional pins (AIN1 and AIN6) that connect to the RTD through blocking diodes. The additional pins are used to route the RTD excitation currents around the input resistors, avoiding the voltage drop otherwise caused by the filter resistors RF1 and RF4. The diodes protect the ADC inputs in the event of a miswired connection. The input filter resistors limit the input fault currents flowing into the ADC. 5V 3.3 V 0.1 PF 0.1 PF IIDAC1 IDAC1 AIN1 (IDAC1) AVDD AVDD DVDD Device 500 A CCM4 RF4 AIN2 (REFP) RREF Reference Mux CDIF2 RF3 Internal Reference REFOUT AIN3 (REFN) CCM3 Ref Alarm Buf 3-Wire RTD RLEAD1 CCM2 RF2 AIN4 (AINP) CDIF1 RRTD RLEAD2 RF1 Input MUX 32-bit ûADC PGA AIN5 Digital Filter Serial Interface and Control Internal Oscillator Clock Mux (AINN) CCM1 IIDAC2 IDAC2 AIN6 (IDAC2) Signal Alarm AVDD 500 A AVSS RLEAD3 START RESET/PWDN CS DIN DOUT/DRDY SCLK DRDY XTAL2 XTAL1 DGND IIDAC1 + IIDAC2 RBIAS Figure 156. 3-Wire RTD Application 10.2.1.1 Design Requirements Table 60 shows the design requirements of the 3-wire RTD application. Table 60. Design Requirements DESIGN PARAMETER VALUE ADC supply voltage 4.75 V (minimum) RTD sensor type 3-wire Pt100 RTD resistance range 20 Ω to 400 Ω RTD lead resistance range 0 Ω to 10 Ω RTD self heating Accuracy (1) 114 (1) 1 mW ±0.02 Ω TA = 25°C. After offset and full-scale calibration. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 10.2.1.2 Detailed Design Procedure The key considerations In the design of a 3-wire RTD circuit are the accuracy, the lead wire compensation, and the sensor self-heating. As the design values of Table 61 illustrate, several values of excitation currents are available. The resolution is expressed in units of noise-free bits (NFR). Noise-free resolution is resolution with no code flicker. The selection of excitation currents trades off resolution against sensor self-heating. In general, measurement resolution improves with increasing excitation current. Increasing the excitation current beyond 1000 µA results in no further improvement in resolution. The design procedure is based on 500-µA excitation current, because this level of current results in very low sensor self-heating (0.4 mW). Table 61. RTD Circuit Design Parameters Gain (V/V) VREFMIN (3) (V) VREF (4) (V) 0.02 32 0.64 0.04 32 1.28 0.025 0.10 16 19.1 0.100 0.20 750 18.9 0.225 1000 19.3 1500 2000 IIDAC (µA) RREF (5) (kΩ) VINNLIM (6) (V) VINPLIM (7) (V) RBIAS (8) (kΩ) VRTDN (9) (V) VRTDP (10) (V) VIDAC1 (11) (V) 0.90 18 0.6 4.1 7.10 0.7 0.7 1.9 1.41 14.1 0.9 3.8 5.10 1.0 1.1 2.8 1.60 1.76 7.04 1.1 3.7 2.30 1.2 1.3 3.3 8 1.60 1.76 3.52 1.0 3.8 1.10 1.1 1.3 3.4 0.30 4 1.20 1.32 1.76 0.8 4.0 0.57 0.9 1.2 2.8 0.400 0.40 4 1.60 1.76 1.76 0.9 3.9 0.50 1.0 1.4 3.5 19.1 0.900 0.60 2 1.20 1.32 0.88 0.6 4.2 0.23 0.7 1.3 3.0 18.3 1.600 0.80 1 0.80 0..90 0.45 0.3 4.5 0.10 0.4 1.2 2.4 NFR (bits) PRTD (mW) 50 16.8 0.001 100 17.8 0.004 250 18.8 500 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (1) VRTD (V) (2) VRTD is the RTD input voltage. Gain is the ADC gain VREFMIN is the minimum reference voltage required by the design. VREF is the design target reference voltage allowing for 10 % over-range or the minimum 0.9 V reference voltage requirement. RREF is the resistor that senses the IDAC current to generate VREF. VINNLIM is the absolute minimum input voltage required by the ADC. VINPLIM is the absolute maximum input voltage required by the ADC. RBIAS establishes the level-shift voltage. VRTDN is the design target negative input voltage. VRTDP is the design target positive input voltage. VIDAC1 is the design target IDAC1 loop voltage. Initially, RLEAD1 and RLEAD2 are considered to be 0 Ω. Route the IDAC1 current through the external reference resistor, RREF. IDAC1 generates the ADC reference voltage, VREF, across the reference resistor. This voltage is defined by Equation 24: VREF = IIDAC1 · RREF (24) Route the second current (IDAC2) to the second RTD lead. Program both IDAC1 and IDAC2 to the same value by using the IDACMAG register; however, only the IDAC1 current flows through the reference resistor and RTD. The IDAC1 current excites the RTD to produce a voltage proportional to the RTD resistance. The RTD voltage is defined by Equation 25: VRTD = RRTD · IIDAC1 (25) The ADC amplifies the RTD signal voltage (VRTD) and measures the resulting voltage against the reference voltage to produce a proportional digital output code, as shown in Equation 26 through Equation 28. Code ∝ VRTD · Gain / VREF Code ∝ (RRTD · IIDAC1) · Gain / (IIDAC1 · RREF) Code ∝ (RRTD · Gain) / RREF (26) (27) (28) As shown in Equation 28, the RTD measurement depends on the value of the RTD, the PGA gain, and the reference resistor RREF, but not on the IDAC1 value. Therefore, the absolute accuracy and temperature drift of the excitation current does not matter. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 115 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com The second excitation current (IDAC2) provides a second voltage drop across the second RTD lead resistance, RLEAD2. The second voltage drop compensates the voltage drop caused by IDAC1 and RLEAD1. The leads of a 3wire RTD typically have the same length; therefore, the lead resistance is typically identical. Taking the lead resistance into account (RLEADx ≠ 0), the differential voltage (VIN) across ADC inputs AIN4 and AIN5 is shown in Equation 29: VIN = IIDAC1 · (RRTD + RLEAD1) – IIDAC2 · RLEAD2 (29) If RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2, the expression for VIN reduces to Equation 30: VIN = IIDAC1 · RRTD (30) In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated, as long as the lead resistance values and the IDAC values are matched. Using Equation 25, the value of RTD resistance (400 Ω, maximum) and the excitation current (500 µA) yields an RTD voltage of VRTD = 500 µA · 400 Ω = 0.2 V. Use the maximum gain of 8 V/V in order to limit the reference voltage requirement as well as the corresponding loop voltage of IDAC1. The total loop voltage must not exceed the maximum IDAC voltage compliance specification. Gain = 8 requires a minimum reference voltage VREFMIN = 0.2 V · 4 = 1.6 V. To provide a margin for the ADC operating range, increase the target reference voltage by 10% (VREF = 1.6 V · 1.1 = 1.76 V). Calculate the value of the reference resistor, as shown in Equation 31: RREF = VREF / IIDAC1 = 1.76 V / 500 µA = 3.52 kΩ (31) For best results, use a precision reference resistor RREF with a low temperature drift (< 10 ppm/°C). The next step in the design is determining the value of the RBIAS resistor, in order to level shift the RTD voltage to meet the ADC absolute input-voltage specification. The required level-shift voltage is determined by calculating the minimum absolute voltage (VINNLIM) as shown in Equation 32: VAVSS + 0.3 + VRTD · (Gain – 1) / 2 ≤ VINNLIM where • • • VRTD = maximum differential RTD voltage = 0.2 V Gain = 8 VAVSS = 0 V (32) The result of the equation requires a minimum absolute input voltage (VRTDN) > 1.0 V. Therefore, the RTD voltage must be level shifted a minimum of 1.0 V. To meet this requirement, a target level-shift value of 1.1 V is chosen to provide 0.1 V margin. Calculate the value of RBIAS as shown in Equation 33: RBIAS= VINN / (IIDAC1+ IIDAC2) = 1.1 V / ( 2 · 500 µA) = 1.1 kΩ. (33) After the level-shift voltage is determined, verify that the positive RTD voltage (VRTDP) is less than the maximum absolute input voltage (VINPLIM), as shown in Equation 34: VINPLIM ≤ VAVDD – 0.3 – VRTD · (Gain – 1) / 2 where • • • VRTD = maximum differential RTD voltage = 0.2 V Gain = 8 VAVDD = 4.75 V (minimum) (34) Solving Equation 34 results in a required VRTDP of less than 3.8 V. Calculate the VRTDP input voltage by Equation 35: VINP = VRTDN + IIDAC1 · ( RRTD + RLEAD1) = 1.1 V + 500 µA · (400 Ω + 10 Ω) = 1.3 V (35) Because 1.3 V is less than the 3.8-V maximum input voltage limit, the absolute positive and negative RTD voltages are within the ADC specified input range. 116 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 The next step in the design is to verify that the loop voltage of the excitation current is less than the specified IDAC compliance voltage. The IDAC compliance voltage is the maximum voltage drop developed across each IDAC current path to AVSS. In this circuit, IDAC1 has the largest voltage drop developed across its current path. The IDAC1 calculation is sufficient to satisfy IDAC2 because the IDAC2 voltage drop is always less than IDAC1 voltage drop. The sum of voltages in the IDAC1 loop is shown in Equation 36: VIDAC1 = [(IIDAC1 + IIDAC2) · (RLEAD3 + RBIAS)] + [IIDAC1 · (RRTD + RLEAD1 + RREF)] + VD where • VD = external blocking diode voltage. (36) The equation results in a loop voltage of VIDAC1= 3.4 V. The worst-case current source compliance voltage is: (VAVDD – 1.1 V) = (4.75 V – 1.1 V) = 3.64 V. The VIDAC1 loop voltage is less than the specified current source compliance voltage (3.4 V < 3.64 V). Many applications benefit from using an analog filter at the inputs to remove noise and interference from the signal. Filter components are placed on the ADC inputs (RF1, RF2, CDIF1, CCM1, and CCM2), as well as on the reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The filters remove both differential and common-mode noise. The application shows a differential input noise filter formed by RF1, RF2 and CDIF, with additional differential mode capacitance provided by the common-mode filter capacitors, CM1 and CM2. Calculate the differential cutoff frequency as shown in Equation 37: fDIF = 1 / [2π · (RF1 + RF2) · (CDIF1 + CM1|| CM2)] (37) The common-mode noise filter is formed by components RF1, RF2, CM1 and CM2. Calculate the common-mode signal cutoff frequency as shown in Equation 38: fCM = 1 / (2π · RF1 · CM1) = 1 / (2π · RF2 · CM2) (38) Mismatches in the common-mode filter components convert common-mode noise into differential noise. To reduce the effect of mismatch, use a differential mode filter with a corner frequency that is 10 times lower than the common-mode filter corner frequency. The low-frequency differential filter removes the common-mode converted noise. The filter resistors (RFx) also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AINx) of the device to safe levels when an overvoltage occurs on the inputs. Filter resistors lead to an offset voltage error due to the dc input current leakage flowing into and out of the device. Remove this voltage error by system offset calibration. Resistor values that are too large generate excess thermal noise and degrade the overall noise performance. The recommended range of the filter resistor values is 2 kΩ to 10 kΩ. The properties of the capacitors are important because the capacitors are connected to the signal; use high-quality C0G ceramics or film-type capacitors. For consistent noise performance across the full range of RTD measurements, match the corner frequencies of the input and reference filter. Detailed information on matching the input and reference filter is found in Application Report SBAA201, RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 117 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 10.2.1.3 Application Curve Figure 157 shows the resistance measurement results. The measurements are taken at TA = 25°C. A system offset calibration is performed using shorted inputs. A system gain calibration is performed using a 390-Ω precision resistor. The data are taken using a precision resistor simulator with a 3-wire connection in place of a 3-wire RTD. Note that the measurement data are in ohms and do not include the error of the RTD sensor itself. The measured resistance error is < ±0.02 Ω over the 20-Ω to 400-Ω range. Measurement Error (:) 0.1 0.05 0 -0.05 -0.1 0 50 100 150 200 250 300 350 400 RTD Value (:) Figure 157. Resistance Measurement Error 118 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 10.3 Dos and Don'ts • • • • • • • • • • • Do partition the analog, digital, and power supply circuitry into separate sections on the PCB. Do use a single ground plane for analog and digital grounds. Do place the analog components close to the ADC pins using short, direct connections. Do keep the SCLK pin free of glitches and noise. Do verify that the analog input voltages are within the specified PGA input voltage range under all input conditions. Do tie unused analog input pins to midsupply to minimize input leakage current. Do provide current limiting to the analog inputs in case overvoltage faults occur. Do use an LDO regulator to reduce ripple voltage generated by switch-mode power supplies. Don't route digital clock traces in the vicinity of the CAPP and CAPN pins. Don't cross digital signals over analog signals. Don't allow the analog and digital power supply voltages to exceed 7 V under all conditions, including during power-up and power-down. Figure 158 shows Do's and Don'ts of ADC circuit connections. CORRECT INCORRECT 5V 5V AVDD AVDD Device Device AINP AINP 32-bit ûADC PGA AINN AVSS 0V 32-bit ûADC PGA AINN AVSS 0V 0V 0V Single-ended input, PGA enabled Single-ended input, PGA bypassed CORRECT CORRECT 2.5 V 5V AVDD AVDD Device Device AINP AINP 32-bit ûADC PGA 2.5 V AINN PGA AVSS -2.5 V 0V Single-ended input, PGA enabled INCORRECT AVDD 32-bit ûADC AVSS 0V Single-ended input, PGA enabled 5V PGA enabled AINN 3.3 V 5V INCORRECT 3.3 V DVDD AVDD PGA 32-bit ûADC PGA 32-bit ûADC AVSS DGND AVSS DGND Device Inductive supply or ground connections 5V CORRECT AVDD 3.3 V Device DVDD AGND/DGND isolation 2.5 V CORRECT 3.3 V DVDD AVDD PGA 32-bit ûADC PGA 32-bit ûADC AVSS DGND AVSS DGND Device Device DVDD -2.5 V Low impedance AGND/DGND connection Low impedance AGND/DGND connection Figure 158. Dos and Don'ts Circuit Connections Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 119 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 10.4 Initialization Setup Figure 159 is a general procedure that shows a typical ADS1262 configuration and measurement sequence. Apply Power Set RESET/PWDN High /* This pin must be high for operation Y /* ADC automatically detects external clock (external clock can be applied at power-on) External clock? Apply clock to XTAL1 N Wait 216 clock cycles /* The ADC is internally held in reset for 216 clocks after power-on Y /* If START pin is high, conversions are free-running If START pin is low, conversions are stopped START High? DRDY pulses at 20 Hz N Set START low or STOP1 command /* For simplicity, stop conversions before register configuration DRDY not pulsing Issue Write Register command to configure the ADC /* Readings are suspended until Write Register command completes (If conversions are active, changes to certain registers result in ADC restart) Issue Read Register command to verify registers /* Readings are suspended until Read Register command completes Wait for reference voltage to settle /* The internal reference require time to settle after power-on Set START pin high or START1 command /* Start or restart new ADC conversion N Read Data using RDATA1 command Hardware DRDY? /* Read data at a rate faster than the data rate to avoid dropping data Y N N ADC1 Status bit = 1 ? DRDY low ? Y Y /* By Direct or Command method Read Data N New ADC1 data Change ADC Settings ? Y Figure 159. ADS1262 Configuration and Measurement Procedure 120 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 Initialization Setup (continued) Figure 160 illustrates a general procedure to read concurrent ADC1 and ADC2 data of the ADS1263. The conversion time of ADC1 can be faster or slower than ADC2. If the conversion time of ADC1 is less than or equal to that of ADC2, and if the ADC2 status bit is equal to 1, then when ADC1 data are ready, ADC2 data are also ready. The ADC2 data can then be read by the RDATA2 command. Similarly, if the conversion time of ADC2 is less than that of ADC1, and if the ADC1 status bit is equal to 1, then when ADC2 data are ready. ADC1 data are also ready, The ADC1 data can then be read by the RDATA1 command. It is important to note an exception to the conversion time related to the data rate: the time of the first conversion is not always the same as (1 / data rate) because of digital filter latency. Therefore, it is possible that although the data rate of ADC1 can be faster than ADC2, the time required for the first conversion of ADC1 can be greater than ADC2 depending on the digital filter setting and chop mode. When checking the ADC2 status by reading ADC1 data, use the RDATA1 command. Begin Stop Conversions ADC1: START pin low; or STOP1 command ADC2: STOP2 command /* For simplicity, stop conversions before ADC configuration Configure ADC1 Configure ADC2 /* Configure the ADCs Start Conversions ADC1: START pin high; or START1 command ADC2: START2 command /* Start conversions /* Read data at a rate faster than the data rate to avoid dropping data N ADC1 conversion WLPH”$'&2 ? Read ADC2 data using RDATA2 command Y N N ADC2 Status bit = 1 ? Read ADC1 data using RDATA1 command Hardware DRDY? Y Y New ADC2 data N ADC1 Status bit = 1 ? N DRDY low ? Y N Y ADC1 Status bit =1 ? New ADC1 data Read ADC1 data using RDATA1 command Y Read ADC1 data using RDATA1 command N ADC2 Status bit =1 ? Y Read ADC2 data using RDATA2 command N Change ADC configuration ? Y Figure 160. ADS1263 Concurrent Read of ADC1 and ADC2 Data Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 121 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 11 Power-Supply Recommendations The ADS1262 and ADS1263 require an analog power supply (VAVDD, VAVSS) and digital power supply (VDVDD). The analog power supply can be bipolar (for example, VAVDD = +2.5 V, VAVSS = –2.5 V) or unipolar (for example, VAVDD = 5 V, VAVSS = 0 V). The digital supply (VDVDD) range is 2.7 V to 5.25 V. The digital supply voltage determines the digital I/O logic levels. Keep in mind that the GPIO logic levels (AIN3-AINCOM) are referenced to the analog supply voltage and may be different from the digital I/O logic level. The analog and digital sections of the ADC are not internally isolated and the grounds for analog and digital must be connected together. Output voltage ripple produced by switch-mode power supplies may interfere with the ADC resulting in reduced performance. Use low-dropout regulators (LDOs) to reduce the power-supply ripple voltage produced by switchmode power supplies. 11.1 Power-Supply Decoupling Good power-supply decoupling is important in order to achieve optimum performance. Power supplies VAVDD, VAVSS and VDVDD must be decoupled to a common ground potential. For proper power-supply decoupling, place a 0.1-µF capacitor as close as possible to the supply with an additional 1-µF bulk capacitor placed nearby. Figure 161 shows decoupling for bipolar-supply (left figure) and single-supply (right figure) operation. When using bipolar supplies, bypass both AVDD and AVSS to ground separately, and include a bypass capacitor between AVDD and AVSS. Use a multilayer ceramic chip capacitors (MLCCs) that offers low equivalent series resistance (ESR) and equivalent series inductance (ESL) characteristics for power-supply decoupling purposes. The BYPASS pin is the bypass output of an internal 2-V regulator. The 2-V regulator powers the digital circuitry. Connect a ceramic or tantalum 1-µF capacitor from this pin to DGND. Do not load this voltage by external circuits. 1 AIN8 AIN7 28 1 AIN8 AIN7 28 2 AIN9 AIN6 27 2 AIN9 AIN6 27 3 AINCOM AIN5 26 3 AINCOM AIN5 26 4 CAPP AIN4 25 4 CAPP AIN4 25 5 CAPN AIN3 24 6 AVDD AIN2 23 7 AVSS AIN1 22 AIN0 21 RESET/PWDN 20 4.7 nF 4.7 nF 5 CAPN AIN3 24 6 AVDD AIN2 23 5V +2.5 V 1 PF 0.1 PF 1 PF 1 PF 1 PF 7 ±2.5 V ±2.5 V AVSS AIN1 0.1 PF 22 ADS1262 ADS1263 8 REFOUT 9 START 10 CS AIN0 21 RESET/PWDN 20 DVDD 19 SCLK 12 DIN 13 DOUT/DRDY 14 DRDY 8 REFOUT 9 START 10 CS DVDD 19 DGND 18 BYPASS 17 XTAL2 16 XTAL1/CLKIN 15 3.3 V 0.1 PF 11 ADS1262 ADS1263 1 PF 0.1 PF 1 PF DGND 18 11 SCLK BYPASS 17 12 DIN XTAL2 16 13 DOUT/DRDY XTAL1/CLKIN 15 14 DRDY 1 PF 3.3 V 1 PF 1 PF Figure 161. Power-Supply Decoupling for Bipolar (left) and Single-Supply (right) Operation 122 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 11.2 Analog Power-Supply Clamp It is important to evaluate circumstances when an input signal is present while the ADC is powered and unpowered. When the input signal exceeds the power-supply voltage, it is possible to back drive the analog power-supply voltage with the input signal through a conduction path of the internal ESD diodes. Back driving the ADC power supply can also occur when the power-supply voltage is on. The back-drive, fault-current path is illustrated in the Figure 162. Depending on the external power-supply components, it is possible that the maximum rating of the ADC power-supply voltage can be exceeded if back-driven. ADC power supply overvoltage must be prevented in all cases. One solution is to clamp the AVDD to AVSS voltage with an external 6-V Zener diode. ADC supply On or Off IFAULT +V +5 V Reg AVDD RLIMIT AINx Input Voltage + ± ESD Diode ADC Optional 6-V Zener Diode AINx ESD Diode IFAULT IFAULT AVSS Figure 162. Analog Power-Supply Clamp 11.3 Power-Supply Sequencing Sequence the power supplies in any order, but never allow and analog or digital inputs to exceed the respective analog or digital power-supplies without limiting the input fault current. The ADC remains in reset until both analog and digital power supplies exceed the respective power-on reset (POR) thresholds. Figure 117 shows the power-on reset sequence. After the power supplies have crossed the reset levels (including the internal 2-V LDO), the ADC resets (POR) and is ready for communication 65536 clock periods later (nominally 9 ms). Delay communication for 50 ms after the power supplies have stabilized within the specified range to make sure the ADC is operational. In addition to POR, make sure that the reference voltage has fully settled before starting the conversions. When using a 1-µF reference capacitor allow a minimum of 50 ms for the internal reference to settle. External references may require additional settling time. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 123 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 12 Layout Good layout practices are crucial to realize the full-performance of the ADS1262 and ADS1263. Poor grounding can quickly degrade the noise performance of the main 32-bit ADC and auxiliary 24-bit ADC. The following layout recommendations are given to help provide best results. 12.1 Layout Guidelines Ground must be a low impedance connection for return currents to flow undisturbed back to their respective sources. Keep connections to the ground plane as short and direct as possible. When using vias to connect to the ground layer, use multiple vias in parallel to reduce impedance to ground. A mixed-signal layout sometimes incorporates separate analog and digital ground planes that are tied together at one location; however, separating the ground planes is not necessary when analog, digital, and power supply components are properly placed. Proper placement of components partitions the analog, digital, and power supply circuitry into different PCB regions to prevent digital return currents from coupling into sensitive analog circuitry. For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific form factors, single ground planes may not be possible. If ground plane separation is necessary, then make the connection at the ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. A single plane for analog and digital ground avoids ground loops. If isolation is required in the application, isolate the digital signals between the ADC and controller, or provide the isolation from the controller to the remaining system. if an external crystal is used to provide the ADC clock, place the crystal and load capacitors directly to the ADC pins using short direct traces. See the Crystal Oscillator section for more details. Supply pins must be bypassed with a low-ESR ceramic capacitor. Place the bypass capacitors as close as possible to the supply pins using short, direct traces. For optimum performance, use low-impedance connections on the the ground-side connections of the bypass capacitors. Flow the supply current through the bypass capacitor pin first and then to the supply pin to make the bypassing most effective (also known as a Kelvin connection). If multiple ADCs are on the same PCB, use wide power supply traces or dedicated power-supply planes to minimize the potential of crosstalk between ADCs. If external filtering is used for the analog inputs, use C0G-type ceramic capacitors when possible. C0G capacitors have stable properties and low-noise characteristics. Ideally, route the differential signals as pairs in order to minimize the loop area between the traces. For the ADC CAPP and CAPN pins, place the 4.7-nF C0G capacitor close to the pins using short direct traces. Route digital circuit traces (such as clock signals) away from all analog pins. Note the internal reference output return shares the same pin as the AVSS power supply. To minimize coupling between the power-supply trace and reference-return trace, route the two traces separately; ideally, as a star connection at the AVSS pin. It is important the SCLK input of the serial interface is free from noise and glitches. Even with relatively slow SCLK frequencies, short digital-signal rise and fall times may cause excessive ringing and noise. For best performance, keep the digital signal traces short, use termination resistors as needed, and ensure all digital signals are routed directly above the ground plane with minimal use of vias. Signal Conditioning (RC filters and amplifiers) Supply Generation Interface Tranceiver Microcontroller Optional: Split Ground Cut Device Ground Fill or Ground Plane Ground Fill or Ground Plane Optional: Split Ground Cut Ground Fill or Ground Plane Connector or Antenna Ground Fill or Ground Plane Figure 163. System Component Placement 124 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 ADS1262, ADS1263 www.ti.com SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 12.2 Layout Example Figure 164 is an example layout of the ADS1262 and ADS1263, requiring a minimum of three PCB layers. The example circuit is shown for a single analog supply (5 V) connection and an external crystal oscillator. In this example, an inner layer is dedicated to the ground plane and the outer layers are used for signal and power traces. If a four-layer PCB is used, dedicate the additional inner layers to route power traces. The ADC orientation is shown left to right to minimize crossover of the analog and digital signal traces. The PCB is partitioned with analog signals routed from the left, digital signals routed to the lower-right, and power routed from the upper-right. Analog supply bypass capacitors are placed opposite to the ADC on the bottom layer to allow the reference and PGA output capacitors to be placed closer to the ADC. Internal plane connected to GND (DGND = AVSS) IN1 RTD input IN2 6V Zener Diode (OPTIONAL) AVDD IN6 DVDD Differential input External Crystal (OPTIONAL) IN7 15: XTAL1 16: XTAL2 17: BYPASS 18: DGND 19: DVDD 20: /RST/PD 21: AIN0 22: AIN1 23: AIN2 24: AIN3 25: AIN4 26: AIN5 Differential input 27: AIN6 28: AIN7 IN6 (TO XTAL1) (TO XTAL2) ADS126x IN7 COM /RESET/PWDN START /CS 14: /DRDY 13: DOUT 12: DIN 11: SCLK 10: /CS 9: START 8: REFOUT 7: AVSS 6: AVDD 5: CAPN 4: CAPP 2: AIN9 1: AIN8 IN9 3: AINCOM /DRDY Thermocouple/single-ended input DOUT DIN SCLK (REFP OUT) (REFN OUT) Tie unused inputs to REFOUT for lowest leakage current Figure 164. PCB Layout Example Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 125 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com 13 Device and Documentation Support 13.1 Related Links Table 62 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 62. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS1262 Click here Click here Click here Click here Click here ADS1263 Click here Click here Click here Click here Click here 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 126 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS1262IPW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1262 ADS1262IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1262 ADS1263IPW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1263 ADS1263IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1263 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2017 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1262IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS1263IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1262IPWR TSSOP PW 28 2000 367.0 367.0 38.0 ADS1263IPWR TSSOP PW 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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