User's Guide
SBAU197A – February 2012 – Revised January 2016
ADS1x7xEVM-PDK
ADS1x7xEVM-PDK
This user's guide describes the characteristics, operation, and use of the ADS1x7xEVM-PDK. These
evaluation module kits (EVM-PDK) are an evaluation system for the ADS1278, a 24-bit, 8 channel, deltasigma analog-to-digital converter (ADC), the ADS1178, a 16-bit version of the ADS1278 and the ADS1274
and ADS1174, which are 4 channel versions of the ADS1278 and ADS1178, respectively. The EVM-PDK
allows evaluation of all aspects of the ADS1x7x devices.
This document includes an EVM QuickStart, hardware and software details, bill of materials, and
schematic.
The following related documents are available through the Texas Instruments web site at
http://www.ti.com.
Table 1. EVM-Compatible Device Data Sheets
Device
Literature Number
Device
Literature Number
ADS1278
ADS1274
SBAS367
OPA1632
SBOS286
SBAS367
SN74LVC2G157
SCES207
ADS1178
SBAS373
TPS73018
SBVS054
ADS1174
SBAS373
TPS65131
SLVS493
REF5025
SBOS410
PCA9535
SCPS129
OPA2350
SBOS099
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2
3
4
5
6
Contents
EVM Overview ............................................................................................................... 3
Quick Start .................................................................................................................... 4
Quick Reference ............................................................................................................. 6
Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro ................................................. 7
ADS1278EVM Hardware Details ......................................................................................... 11
Schematic and Bill of Materials ........................................................................................... 16
1
ADS1x7xEVM Default Jumper Locations................................................................................. 4
2
Channel Enable .............................................................................................................. 8
3
Clock Settings and Mode ................................................................................................... 9
List of Figures
List of Tables
1
EVM-Compatible Device Data Sheets .................................................................................... 1
2
Default Jumper/Switch Configuration ..................................................................................... 4
3
Critical Connections ......................................................................................................... 6
4
Operating Modes: Clock Frequency ..................................................................................... 10
5
Jumper and Switch Descriptions ......................................................................................... 11
6
J3: Primary Analog Interface Pinout ..................................................................................... 13
7
J1: Secondary Analog Interface Pinout
8
9
10
11
.................................................................................
J4, Serial Interface Header ...............................................................................................
J2, DOUTx Header .........................................................................................................
J5 Configuration: Power-Supply Input ...................................................................................
ADS1x7xEVM Bill of Materials ...........................................................................................
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14
15
15
16
Trademarks
ADCPro is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors, Inc.
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EVM Overview
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EVM Overview
The ADS1x7xEVM-PDK is an evaluation module kit that includes an EVM, MMB0 motherboard and
software. As a standalone PCB, the ADS1x7xEVM is useful for prototyping designs and firmware. It can
be connected to any modular EVM system interface card.
1.1
Features
ADS1x7xEVM Features:
• Contains all support circuitry needed for the ADS1178/ADS1278/ADS1174/ADS1274
• Voltage reference options: external or onboard
• Clock options: External clock source (PLL or DSP supplied) or 27MHz onboard crystal oscillator
• GPIO access
• Compatible with the TI Modular EVM System
ADS1x7xEVM-PDK includes the ADS1x7xEVM board with the DSP-based MMB0 motherboard, that can
be used with ADCPro™ to quickly evaluate the device.
This manual covers the operation of the ADS1x7xEVM-PDK. Throughout this document, the abbreviation
EVM and the term evaluation module are synonymous with the
ADS1178EVM/ADS1278EVM/ADS1174EVM/ADS1274EVM. For clarity of reading, this manual will refer
only to the ADS1278EVM or ADS1x7xEVM-PDK, but operation of the EVM and kit for the
ADS1178/ADS1274/ASD1174 is identical, unless otherwise noted.
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Quick Start
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Quick Start
This section provides a QuickStart guide to quickly begin evaluating the ADS1x7xEVM with ADCPro.
2.1
Default Jumper/Switch Configuration
Figure 1 shows the jumpers found on the EVM and the respective factory default conditions for each.
Figure 1. ADS1x7xEVM Default Jumper Locations
Table 2 lists the jumpers and switches and the factory default conditions.
Table 2. Default Jumper/Switch Configuration
4
Switch
Default Position
S1
All OFF (Down)
Power-down channel DIP switches (Hardware control)
S2
All OFF (Down)
Mode, Format, and CLKDIV DIP switches (Hardware
control)
S3
INT (Right)
S4
Header connected to converter (Left)
Channel 4 header connected to converter (not
buffered)
S5
Header connected to converter (Left)
Channel 3 header connected to converter (not
buffered)
S6
[1-2], [4-5], [7-8], [10-11]
S7
Header connected to converter (Left)
ADS1x7xEVM-PDK
Switch Description
On-board voltage reference selected
Jumpers installed to select FS serial interface format
Channel 2 header connected to converter (not
buffered)
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Table 2. Default Jumper/Switch Configuration (continued)
Switch
Default Position
Switch Description
S8
Header connected to converter (Left)
Channel 1 header connected to converter (not
buffered)
Jumper
2.2
JP1
Open
FSX NOT connected to SYNC/DRDY
JP2
Short
FSR connected to SYNC/DRDY
JP3
Short
Input buffer op-amps are powered-down
JP4
Short
Clock source selection using software control
JP5
Short
External clock source selected (invalid since using
software control)
ADS1x7xEVM-PDK Operation
To prepare to evaluate the ADS1278 with the ADS1x7xEVM-PDK, complete the following steps:
1. Verify the jumpers on the ADS1x7xEVM are as shown in Figure 1 (note that these settings are the
factory-configured settings for the EVM).
2. Using ADCPro HW/SW Installation Manual, verify the MMB0 jumpers are in the default position and
install ADCPro and ADS1278EVM plug-in software. Complete hardware connection and driver
installation as part of ADCPro HW/SW Installation Manual using the below settings.
• MMB0 J13A → Open
• MMB0 J13B → Short
• No additional power connections are required
3. Plug the ADS1278EVM onto the MMB0 (if not already connected). The female portion of J3, J4 and J5
on the EVM align with male connectors J10, J4, and J5 respectively on the MMB0.
4. Connect power to the MMB0 board. If power is supplied from an AC adapter (not included), ensure that
it satisfies the following requirements:
• Output voltage: 5.5 VDC to 15 VDC
• Maximum output current: ≥ 500 mA
• Output connector: barrel plug (positive center), 2.5-mm I.D. x 5.5-mm O.D. (9-mm insertion depth)
• Complies with applicable regional safety standards
CAUTION
Do not misalign the pins when plugging the ADS1278EVM into the MMB0.
Check the pin alignment of J3, J4, and J5 carefully before applying power to
the PDK.
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Quick Reference
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Quick Reference
Table 3 provides a quick summary of the connections required for operation of the EVM as a standalone
Table 3. Critical Connections
Function
Pin Name
J4.3
CLKX
Description
SCLK
DIN
J4.11
DX
Data In
DOUT
J4.13
DR
Data Out
Interrupt
J4.15
INT
DRDY/FSYNC
1.8V
J5.7
+1.8VD
Digital supply
3.3V
J5.9
+3.3VD
Digital supply
5.0V
J5.3
+5VA
Analog supply
Channels 1-4
J3.1-8
Analog Inputs
Channels 5-8
J1.3-10
Analog Inputs (ADS1178 and
ADS1278 only)
Interface
Power
Analog Inputs
Header/Pin
SCLK
CAUTION
When using the EVM as part of the ADS1278EVM-PDK, the DIP switches S1
and S2 must all be switched so that they are down, toward the center of the
board. Failure to do so may damage the EVM.
3.1
Analog Inputs
The analog inputs for the ADS1278EVM are connected to J1 and J3. Channels 1-4 connect to J3 and
provisions are provided to buffer these signals before being connected to the converter. Switches S4, S5,
S7, and S8 control whether the buffered or unbuffered signal is connected to the ADS1278. Channels 5-8
connect to J1 and have an RC filter available to filter the input before connecting to the converter.
Channels 5-8 do not have provisions for buffering the signal.
3.2
Digital Control
The digital control signals can be applied directly to J4 (top or bottom side).
3.3
Power Supply
The ADS1278EVM requires power rails as follows:
• 5.0V analog supply - supplied by MMB0 motherboard via J13B
• 3.3V digital supply - supplied by MMB0 motherboard
• 1.8V digital supply - supplied by MMB0 motherboard
3.4
Voltage Reference
The ADS1278EVM has two options for the reference voltage. Switch S3 selects the reference voltage
from either the buffered REF5025 or a external reference voltage that is connected to the reference pins
of J3 (J3.18 = REFN and J3.20 = REFP).
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Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro
The ADS1278EVM-PDK plug-in for ADCPro provides complete control over all settings of the ADS1278. It
consists of a tabbed interface (see Figure 2) with different functions available on different tabs. The tabs
are:
• Channel Enable
• Settings
• About
The user can adjust the ADS1178EVM/ADS1278EVM settings when not acquiring data. During
acquisition, all controls are disabled and settings may not be changed. When a setting is changed on the
ADS1178EVM/ADS1278EVM plug-in, the setting immediately updates on the board.
Settings on the ADS1178EVM/ADS1278EVM correspond to settings described in the ADS1278 product
data sheet product data sheet.
4.1
Top Level Controls
You can adjust the ADS1278EVM settings when you are not acquiring data. During acquisition, all
controls are disabled and settings may not be changed.
The effective data rate of the ADS1278 depends upon settings of the Clock Freq and Operating Mode.
The Data Rate indicator in the upper right corner of the plug-in interface (see Figure 2) is always visible
and updates whenever a setting changes that affects the data rate.
4.2
Channel Enable Tab
The ADS1278 can acquire data from one to eight channels simultaneously. The Channel Enable tab (as
shown in Figure 2) provides the control to power on or off each channel.
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Figure 2. Channel Enable
The Master (All) Enable control allows for the selection of channels to convert. Manual Control allows
channel enable control via CH1 through CH8 selector switches. All Channels Enabled and All Channels
Disabled turn all the selector switches either ON or OFF.
4.3
Settings Tab
The Settings tab allows for the selection of the various clock frequencies, operating mode, data format,
and other settings.
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Figure 3. Clock Settings and Mode
The Clock Source control selects the input clock source for the ADS1278. The clock can be selected
from the MMB0 PLL, an External source, or use the On-board oscillator.
The Modulator Frequency indicator shows the ADS1278 modulator frequency based on the clock
source.
The Clock Frequency control allows the user to input the desired clock frequency when the PLL clock
source is selected. Once the frequency is entered, the software finds the closest frequency for the PLL to
synthesize (and which is within the maximum allowable frequency for the mode selected). This clock
frequency is configured in the PLL and overwrites the user entered value in the Clock Frequency
indicator.
The Operating Mode control allows selection of the converter operating mode: High-Speed, HighResolution, Low-Power, or Low-Speed.
The CLKDIV control can be set to 0 or 1.
The Data Output Format allows selection of the data output formats. For the ADS1278EVM software, the
formats are limited to the Frame-Sync, TDM Format. The available options select whether the software
collects data for all channels Fixed Mode or only channels that are powered up Dynamic Mode.
The Vref control allows the user to input the current Vref value being used by the data converter. This
control does not change the actual reference voltage, but is required for the software to process the data
correctly for display.
The maximum clock frequency is shown for the different converter options in Table 4.
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Table 4. Operating Modes: Clock Frequency
4.4
Operating Mode
CLKDIV
Frequency (MHz)
High-Speed
1
32.768
High-Resolution
1
27
Low-Power
1
27
Low-Power
0
13.5
Low-Speed
1
27
Low-Speed
0
5.4
About Tab
The About tab provides information on the EVM hardware and software versions.
Plug-in Version is software version of ADCPro plug-in.
Firmware Version is firmware version loaded and running on the processor.
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5
ADS1278EVM Hardware Details
The ADS1278EVM is designed to easily interface with multiple control platforms. Dual-row, header/socket
combinations at J3, J4, and J5 allow connection to external circuitry for evaluation and debug.
5.1
Jumpers and Switches
Jumpers and Switches function shown in table below
Table 5. Jumper and Switch Descriptions
Jumper/Switch
Functions
Descriptions
JP1
FSYNC/DRDY Source
Short to select FSR as the source (1)
JP2
FSYNC/DRDY Source
Short to select FSX as the source (1)
JP3
Analog Input Buffers Power-down
Short - input buffers powered-down
Open - input buffers powered-up
JP4
Hardware/Software Control of Clock Source
Short - Software control
Open - Hardware control
JP5
Internal/External Clock Select (Hardware
control)
Short - External clock source selected
Open - Internal clock source selected
Power down Channel 1
Hardware control for PWDN1 (set to OFF position for use with
software)
Power down Channel 2
Hardware control for PWDN2 (set to OFF position for use with
software)
Power down Channel 3
Hardware control for PWDN3 (set to OFF position for use with
software)
Power down Channel 4
Hardware control for PWDN4 (set to OFF position for use with
software)
Power down Channel 5 (2)
Hardware control for PWDN5 (set to OFF position for use with
software)
Power down Channel 6 (2)
Hardware control for PWDN6 (set to OFF position for use with
software)
Power down Channel 7 (2)
Hardware control for PWDN7 (set to OFF position for use with
software)
Power down Channel 8 (2)
Hardware control for PWDN8 (set to OFF position for use with
software)
GPIO2
Hardware control for GPIO2 (set to OFF position for use with
software)
GPIO3
Hardware control for GPIO3 (set to OFF position for use with
software)
GPIO4
Hardware control for GPIO4 (set to OFF position for use with
software)
CLKDIV
Hardware control for CLKDIV (set to OFF position for use with
software)
GPIO0
Hardware control for GPIO0 (set to OFF position for use with
software)
GPIO1
Hardware control for GPIO1 (set to OFF position for use with
software)
S3
Converter voltage reference source selector
Selects source for reference voltage - buffered on-board
reference or header (external)
S4
Channel 4 input source selector
Selects Channel 4 input source - header or input buffer
Left - header
Right - input buffer
S5
Channel 3 input source selector
Selects Channel 3 input source - header or input buffer
Left - header
Right - input buffer
S1
S2
(1)
(2)
Only one of FSYNC/DRDY signals should be connected at a time (JP1 or JP2).
Channels 4-8 only available for ADS1278 and ADS1178.
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Table 5. Jumper and Switch Descriptions (continued)
Jumper/Switch
(3)
5.2
Functions
Descriptions
S6
Serial Interface format
FS - Frame Sync format. [1-2], [4-5], [7-8], [10-11] installed. (3)
SPI - SPI-compatible mode. [2-3], [5-6], [8-9], [11-12] installed. (3)
S7
Channel 2 input source selector
Selects Channel 2 input source - header or input buffer
Left - header
Right - input buffer
S8
Channel 1 input source selector
Selects Channel 1 input source - header or input buffer
Left - header
Right - input buffer
Refer to Section 5.5.1 for more details.
Power-Down, MODE, and FORMAT Control
The ADS1278 has several pins to control the power-down of individual channels, and select the mode and
format for the digital interface.
For users of the ADS1278EVM as a standalone module, these pins may be pulled high or low through DIP
switches S1 and S2 (see Table 5). Refer to the ADS1278 product data sheet for complete details on these
pins and which state sets which options.
For use in the ADS1x7xEVM-PDK, the state of these pins is controlled by software, using the I2C port
expanders (U7 and U8) on the EVM. When using the EVM with the EVM-PDK, the DIP switches S1 and
S2 must all be switched down (toward the center of the board). The ADS1278EVM-PDK software checks
at startup to verify that these switches are set correctly, and generates an error message for incorrect
settings. The software cannot detect if the switches are changed after startup.
CAUTION
When using the ADS1x7xEVM-PDK, the DIP switches S1 and S2 must all be
switched down (toward the center of the board). Failure to do so may damage
the EVM.
5.3
Clock Source
The ADS1278 clock can come from one of several sources: the onboard 27MHz crystal oscillator, a clock
supplied by a processor on the TOUT pin (J4.17), or an external clock source connected between J4.17
(TOUT) and J4.18 (DGND).
If the onboard 27MHz oscillator is selected, the device can be run in high-speed mode, high-resolution
mode, low-power mode, or low-speed modes with CLKDIV set to 1.
If the performance of the device must be explored with CLKDIV set to 0 in the low-power and low-speed
modes, an external clock must be provided to the board, either using the TOUT connection or having an
external clock source connected to J4.17. The same condition is true if frequencies other than the 27MHz
provided by the onboard oscillator must be investigated.
5.4
Analog Headers, J1 and J3
For maximum flexibility, the ADS1278EVM is designed for easy interfacing to multiple analog sources.
These headers/socket provide access to the analog input pins of the ADS1278.
Four of the analog input sources (Channels 1–4) connect directly to J3 (top or bottom side) or through
signal-conditioning modules available for the modular EVM system. These inputs have provisions to buffer
the inputs using THS4521 before connecting to the converter. Switches S4, S5, S7, and S8 provide the
capability to connect either the header directly or through a buffer. When the buffers are not selected, the
op-amps used for buffering can be powered down by shorting JP3.
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Analog input sources (Channels 5-8) are connected directly to J1. These inputs can be filtered by
installing passive components in the option filter circuitry. By default, the resistors are populated with 0-Ω
resistors and the capacitors are not installed. No circuitry is provided to buffer these signals before
connecting to the converter.
Table 6. J3: Primary Analog Interface Pinout
Description
Signal
Pin Number
Signal
Description
Analog Input Channel 4 Negative
AINN4
J3.1 (1)
J3.2
AINP4
Analog Input Channel
4 Positive
Analog Input Channel 3 Negative
AINN3
J3.3
J3.4
AINP3
Analog Input Channel
3 Positive
Analog Input Channel 2 Negative
AINN2
J3.5
J3.6
AINP2
Analog Input Channel
2 Positive
Analog Input Channel 1 Negative
AINN1
J3.7
J3.8
AINP1
Analog Input Channel
1 Positive
Analog Ground
AGND
J3.9
J3.10
Not Connected
Not used for this
design
Analog Ground
AGND
J3.11
J3.12
Analog Ground
AGND
Analog Ground
AGND
J3.13
J3.14
Not Connected
Not used for this
design
Not used for this design
Not Connected
J3.15
J3.16
Not Connected
Not used for this
design
Analog Ground
AGND
J3.17
J3.18
EXTREFN
External Reference
negative input
Analog Ground
AGND
J3.19
J3.20
EXTREFP
External Reference
positive input
(1)
Pin 1 is top left-hand corner, located next to reference designator.
Table 7. J1: Secondary Analog Interface Pinout
Description
Signal
Pin Number
Signal
Description
Not used for this design
Not Connected
J1.1 (1)
J1.2
Not Connected
Not used for this
design
Analog Input Channel 8 Negative
AINN8
J1.3
J1.4
AINP8
Analog Input Channel
8 Positive
Analog Input Channel 7 Negative
AINN7
J1.5
J1.6
AINP7
Analog Input Channel
7 Positive
Analog Input Channel 6 Negative
AINN6
J1.7
J1.8
AINP6
Analog Input Channel
6 Positive
Analog Input Channel 5 Negative
AINN5
J1.9
J1.10
AINP5
Analog Input Channel
5 Positive
(1)
5.5
Pin 1 is top right-hand corner, located next to reference designator.
Digital Interface
The digital signals are controlled via DSP interface or I2C ICs on the EVM. Some of the digital control pins
allow control via hardware or software methods. See Section 5.2 for details on these pins and their
operation. The digital control signals can be applied directly to the EVM or by connecting the EVM to a
DSP or micro controller interface board, such as the MMB0 if purchased as part of the ADS1278EVMPDK, the 5-6K Interface or HPA-MCUInterface boards which are available from Texas Instruments. For a
list of compatible interface and/or accessory boards for the EVM or the ADS1278, see the relevant product
folder on the TI web site.
5.5.1
Digital Format Control
The ADS1278 allows the serial interface to be used in two different formats: an SPI-compatible mode and
a frame-sync format. Switch S6 is populated with jumpers to select between these two formats:
• SPI format configures the signals as follows:
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– The SCLK input of the converter is driven by the serial port signal CLKX, pin J4.3.
– The signal from the selected source for the clock (see Section 5.3, Clock Source) is connected to
the CLKR pin (J4.5) allowing the serial port of a processor to be synchronized to the converters
master clock.
– The signal from the selected clock source is routed to the CLK input of the converter.
– Port P10 of the I2C port expander U8 is connected to a logic high level, so that the position of
switch S12 can be read back by software.
FS format configures the signals as follows:
– The SCLK input of the converter is driven by the serial port signal CLKR, pin J4.5.
– The signal from the selected clock source is connected to the CLKX pin (J4.3), allowing the serial
port of a processor to be synchronized to the converter's master clock.
– The CLK input of the converter is driven by the CLKR signal (J4.5). This ensures that the CLK and
SCLK signals have the same phase and the correct ratio as outlined in the data sheet of the
device.
– Port P10 of the I2C port expander U8 is connected to a logic low level, so that the position of S6
can be read back by software.
•
For use in the ADS1278EVM-PDK, the jumpers on S6 must be installed in the FS positions, which is the
factory default setting. See Figure 1.
Switching to SPI format will allow users to connect the EVM to any SPI-compatible processor not
supporting the frame-sync mode. If this format is selected, keep in mind that the high-speed mode will not
operate at full speed (32.768MHz) because of the limitations outlined in the device product data sheet.
5.5.2
Serial Data Interface, J4
This header/socket provides access to the digital control and serial data pins of the ADC.
All logic levels on J4 are 3.3V CMOS, except for the I2C™ pins. These pins conform to 3.3V I2C rules.
Table 8 describes the J4 serial interface pins.
Table 8. J4, Serial Interface Header
Pin
Number
(J4)
Signal Name
Function
1 (1)
2
MODE0
Select bit 0 of converter
MODE
SPI clock SCLK
3
4
DGND
Digital ground
SCLK clock CLKR
5
6
MODE1
Select bit 1 of converter
MODE
DRDY/FSYNC source 1 DRDY/FSYNC
7
8
FORMAT0
Select bit 0 of FORMAT
to select Frame-Sync/SPI
Protocol
DRDY/FSYNC source 2 DRDY/FSYNC
9
10
DGND
Digital ground
11
12
FORMAT1
Select bit 1 of FORMAT
to select Frame-Sync/SPI
Protocol
ADS1278 data out DOUT1 (2)
13
14
FORMAT2
Select bit 2 of FORMAT
to select Frame-Sync/SPI
Protocol
DRDY/FSYNC to DSP DRDY/FSYNC
(interrupt)
15
16
SCL
I2C clock
17
18
DGND
Digital ground
19
20
SDA
I2C data
Signal Name
Synchronize channels input SYNC
ADS1278 SPI data in DIN
Can be used to provide a clock CLK
from a processor
Clock source select (SW CLK Select
mode)
(1)
(2)
14
Pin 1 is top left-hand corner, located next to reference designator.
DOUT1 buffered through a D flip-flop. See Section 5.5.3.1 below.
ADS1x7xEVM-PDK
SBAU197A – February 2012 – Revised January 2016
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ADS1278EVM Hardware Details
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Some pins on J5 have weak pull-up/down resistors. These resistors provide default settings for many of
the control pins. Many pins on J5 correspond directly to ADS1278 pins. See the ADS1278 product data
sheet for complete details on these pins.
5.5.3
Data Output Signals
5.5.3.1
DOUT on Digital Interface J4
In TDM mode, the data from all eight channels can be observed on the DOUT1 pin of the converter. The
DOUT1 signal is used by the ADS1x7xEVM-PDK to read back and display all the channels. The digital
data output pin on the digital interface header J4 is connected to DOUT1 signal via a D flip-flop. The D
flip-flop provides a half cycle delay in order to align the data correctly to reach the higher speeds of the
device. Otherwise, the propagation delay from the MSB in Frame Sync mode may result in missing the
MSB out of the data word.
5.5.3.2
DOUTx Header, J2
All the data output signals (DOUT1 to DOUT8) can be monitored on J2. Table 9 illustrates the pinout for
J2.
Table 9. J2, DOUTx Header
Data Out Line
(1)
5.6
Pin Number
Data Out Line
DOUT1
1 (1)
2
DOUT2
DOUT3
3
4
DOUT4
DOUT5
5
6
DOUT6
DOUT7
7
8
DOUT8
Pin 1 is top right-hand corner, located next to reference designator.
Power Supply Header, J5
J5 is the power-supply input connector. Table 10 lists the configuration details for J5. Supplies of 1.8V,
3.3V, and 5.0V are required for operation of the EVM. When using the EVM as part of the EVM-PDK,
these voltages are generated by the MMB0 and no external supplies are required. For operation as a
stand-alone EVM, the power supplies should be connected as shown below.
Table 10. J5 Configuration: Power-Supply Input
Function
Pin Name
Not used for this design
Not used
+5V analog supply
Digital ground
Pin Number
(J5)
Pin Name
Function
1 (1)
2
Not used
Not used for this design
+5VA
3
4
Not used
Not used for this design
DGND
5
6
AGND
Analog ground input
1.8V digital supply
+1.8VD
7
8
Not used
Not used for this design
3.3V digital supply
+3.3VD
9
10
N/A
Do not use
(1)
Pin 1 is bottom left-hand corner, located next to reference designator.
NOTE: For monitoring the current from each supply, CM1, CM2, and CM3 (0Ω resistors) can be
removed and replaced with sense resistors or ammeters.
The ADS1278 digital supplies are connected as follows:
• IOVDD supply is connected to the +1.8VD pin of the J3 header.
• DVDD supply is connected to the +3.3VD pin of the J3 header.
The ADS1278 analog supply, AVDD, is connected to the +5VA pin of the J5 header.
SBAU197A – February 2012 – Revised January 2016
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ADS1x7xEVM-PDK
15
Schematic and Bill of Materials
6
www.ti.com
Schematic and Bill of Materials
A complete schematic for the ADS1x7xEVM is appended to this user's guide. The bill of materials is
provided in Table 11. Gerber files are available on request. Please e-mail support@ti.com or E2E
Community Forums and ask for details on how to receive the files.
6.1
Bill of Materials
NOTE: All components should be compliant with the European Union Restriction on Use of
Hazardous Substances (RoHS) Directive. Some part numbers may be either leaded or
RoHS. Verify that purchased components are RoHS-compliant. (For more information about
TI's position on RoHS compliance, see the http://www.ti.com.)
Table 11. ADS1x7xEVM Bill of Materials
Item No.
Qty
Value
Ref Des
1
1
100u
C1
Capacitor, Ceramic, X5R, 10V
Taiyo Yuden
LMK325BJ107MM-T
2
1
150n
C2
Capacitor, Ceramic, X7R, 25V
TDK
C1608X7R1E154K
3
25
0.1u
C3, C11, C13,
C17, C20, C21,
C22, C27, C28,
C29, C38, C39,
C40, C41, C42,
C44, C45, C46,
C49, C50, C51,
C54, C55, C56,
C58
Capacitor, Ceramic, X7R, 25V
TDK
C1608X7R1E104K
4
3
1.0u
C4, C6, C43
Capacitor, Ceramic, X7R, 25V
TDK
C1608X7R1E105K
5
4
10u
C5 C7 C26 C57
Capacitor, Ceramic, X5R, 10V
TDK
C1608X5R1A106M
6
4 (1)
2.2n
C8-10 C12
Capacitor, Ceramic, C0G, 50V
TDK
C1608COG1H222/*J
4
2.2n
C16 C18 C23 C25
8
1.5n
C14-15 C19 C24
C47-48 C52-53
Capacitor, Ceramic, X7R, 25V
TDK
C1608X7R1E152M
7
(1)
16
Description
Manufacturer
Part Number
8 (1)
1.5n
C30-37
8
3
0
CM1-3
Resistor, Chip, 1/4W
Vishay Dale
CRCW06030000Z0EAHP
9
1 (1)
J1 (Top)
Header, SMT Vert. 5x2 pin, 100mil spacing
Samtec
TSM-105-01-T-DV-P
10
1
J5 (Top)
Header, SMT Vert. 5x2 pin, 100mil spacing
Samtec
TSM-105-01-T-DV-P
11
1
J5 (Bottom)
Header, SMT Vert. 5x2 pin, 100mil spacing
Samtec
SSW-105-22-F-D-VS-K
12
1
J2
Header, SMT Vert. 4x2 pin, 100mil spacing
Samtec
TSW-104-07-L-S
13
2
J3 J4
Header, SMT Vert. 10x2 pin, 100mil spacing
Samtec
TSM-110-01-T-DV-P
14
2
J3 J4 (Bottom)
Header, SMT Vert. 10x2 pin, 100mil spacing
Samtec
SSW-110-22-F-D-VS-K
15
5
JP1-JP5
Header, Male 2-pin, 100mil spacing
Samtec
TSW-102-07-L-S
16
1
2k
R1
Resistor, Chip, 1/10W, 5%
Rohm
MCR03EZPJ202
17
18
1k
R2 R17-18 R20-22 Resistor, Chip, 1/10W, 5%
R24 R26-27 R3840 R42-43 R45-48
Rohm
MCR03EZPJ102
18
6
47
R3 R12-13 R16
R25 R41
Resistor, Chip, 1/10W, 5%
Rohm
MCR03EZPJ470
19
8 (1)
0
R4-11
Resistor, Chip, 1/10W
Rohm
MCR03EZPJ000
20
8
49.9
R14-15 R23 R28
R36-37 R49-50
Resistor, Chip, 1/10W, 1%
Rohm
MCR03EZPJ49R9
21
3
100k
R19 R29 R44
Resistor, Chip, 1/10W, 5%
Rohm
MCR03EZPJ104
22
2
470k
R30-31
Resistor, Chip, 1/10W, 5%
Rohm
MCR03EZPJ474
23
2
100k
R32-33
Resistor Pack, 8x
Panasonic
EXB-2HV104JV
24
1
10k
R34
Resistor, Chip, 1/10W, 5%
Rohm
MCR03EZPJ103
25
1
4.3k
R35
Resistor, Chip, 1/10W, 5%
Rohm
MCR03EZP432
26
2
47k
R51-52
Resistor, Chip, 1/10W, 5%
Rohm
MCR03EZPJ473
27
1
S1
Switch, SMD Low Profile 08 Position
CTS
218-8LPST
These parts are not installed for ADS1274 and ADS1174
ADS1x7xEVM-PDK
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Schematic and Bill of Materials
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Table 11. ADS1x7xEVM Bill of Materials (continued)
(2)
Item No.
Qty
28
1
Value
Ref Des
S2
Switch, 6 POS, SPST, Low Profile, SMT,
0.50 centers
Description
CTS
Manufacturer
218-8LPST
Part Number
29
5
S3-5 S7-8
Switch, Slide DPDT, Low Profile
TE Connectivity
SSB22
30
1
S6
CONN HEADER 12POS DUAL 2MM T/H
Samtec
TMM-106-01-T-D
31
4
TP1 TP4 TP7
TP11
Test Point, Black, Thru Hole Color Keyed
Keystone
5001
32
2
TP6 TP8
Test Point, White, Thru Hole Color Keyed
Keystone
5002
33
5
TP2 TP3 TP5 TP9
TP10
Test Point, Red, Thru Hole Color Keyed
Keystone
5000
34
1
U1
IC, Precision Voltage Reference, 2.5V
TI
REF5025AID
35
1
U2
IC, Op Amp, High-Speed, Single-Supply, RR
TI
OPA2350DGK
36
4
U3 U5 U9 U11
IC, Negative R-R Input, R-R Output, Fully
Differntial Amplifier
TI
THS4521DGK
37
1 (2)
U4
IC, Quad/Octal, Simultaneous Sampling, 24Bit A-D Converter
TI
ADS1278PAP
38
1
U6
Single 2 line To 1Line Data
Selector/Multiplexer
TI
SN74LVC2G157DCT
39
1
U10
IC, Single Inverter
TI
SN74LVC1G04DBV
40
1
U12
IC, single Positive-Edge-Triggered D-Type
Flip-Flop With Clear And Reset
TI
SN74LVC2G74DCU
41
1
U13
IC, Configurable Multiple-Function Gate
TI
SN74LVC1G97DCK
42
1
U14
IC, 256K CMOS Serial EEPROM
Microchip
24AA256-I/ST
43
2
U7-8
IC, Low Voltage 16-BIT I2C and SMBus
Low-Power I/O Expander With Interrupt
Output and Configuration Registers
TI
TCA9535RTW
44
1
Y1
Clock Oscillator, 27MHz
CTS
CB3LV-3I-27M0000
45
1
PCB, 3.31 In x 2.88 In x 0.062 In
Any
6492525
46
4
Shunt, 100-mil, Black
3M
929950-00
47
4
SHUNT JUMPER
Samtec
2SN-BK-G
Installed for ADS1278EVM-PDK. For other EVM-PDKs, the appropriate device will be installed.
SBAU197A – February 2012 – Revised January 2016
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ADS1x7xEVM-PDK
17
Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2012) to A Revision .................................................................................................. Page
•
18
Changed step 4 of Section 2.2 .......................................................................................................... 5
Revision History
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Copyright © 2012–2016, Texas Instruments Incorporated
A
B
C
AGND
1
D
E
F
C41
1
0.1u
DIGITAL
[3]
AVDD_1 [1]
GPIO1
GPIO0
PWDN8
PWDN7
PWDN6
PWDN5
PWDN4
PWDN3
PWDN2
PWDN1
CHAN-P8
CHAN-N8
CHAN-N7
CHAN-P7
ANALOG_IN
[1,2,3]
JP1
MODE1 33
FSYNC_DRDY
53 AVDD
SCLK
54 AGND
CLK
55 VCOM
DVDD
56 VREFP
DGND
57 VREFN
DGND
58 AGND
IOVDD
0.1u
CHAN-P4
DGND
61 AINP4
2
SCL
R16 47
DVDD_26
C43
DGND
22
21
CHAN-N3
64 AINN3
DOUT4 17
IOVDD_22_23
[1]
U10
5
C46
2
8
1 CLK
4
0.1u
C54
PRE 7
2 D
3
Q 5
4
16 DOUT5
15 DOUT6
14 DOUT7
13 DOUT8
12 DIN
11 SYNC
9 TEST1
10 CLKDIV
8 TEST0
7 DGND
DGND
IOVDD
J2
C51
DGND
0.1u
CHAN-N1
CHAN-P1
CHAN-N2
C44
CHAN-P2
U12
IOVDD
.1u
ANALOG_IN
[1,2,3]
0.1u
CLR 6
3 Q
65 PWPD
3
IOVDD
DGND
IOVDD
R51
47k
R52
47k
(see table below)
4 Y
R41
47
AVDD_1 [1]
IOVDD
INT/EXT CLK SOURCE
JP4 = HW/SW CTRL (HW/SW)
JP5 = HW SEL (INT/EXT)
DGND
R40
1k
2
DGND
23
DOUT3 18
AGND
SDA
24
63 AINP3
AGND
R31
470k
1u
DOUT1 20
C11
0.1u
[1]
IOVDD
25
CHAN-P3
U4
1
3
26
DOUT2 19
AGND
GPIO3
GPIO4
R13 47
27
62 AINN4
5
4
6
28
CHAN-N4
TP5
6
60 AVDD
6 AGND
AGND
0.1u
IOVDD
5 AVDD
C45
59 AGND
5
TP8
IOVDD
IN0 3
C56
5 VCC
GND 2
0.1u
6 IN2
IN1 1
1
C42
GPIO4
30
GPIO2
DGND
JP4
JP5
3
2
[1]
31
29
11
10
12
TP6
GPIO3
GPIO1
1
52 AINN5
7
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2
FORMAT2
8
SW_IND
VCC
MODE0 34
/PWDN8 35
/PWDN7 36
/PWDN6 37
/PWDN5 38
51 AINP5
AVDD_1
AVDD
/PWDN4 39
/PWDN3 40
/PWDN2 41
/PWDN1 42
CHAN-P5
2
U2-B
AGND 43
FORMAT1
AGND
7 OUTB
AVDD 44
50 AINN6
CHAN-N5
CM[2]
AINP8 45
CHAN-N6
4 AINN1
REFN
GPIO2
32
SCLK
R44
100k
S6
SW_SSB42
FORMAT0
3 AINP1
AGND
REFN_HDR
SYNC
GPIO0
49 AINP6
2 AINN2
REFN_HDR[2]
J4
IOVDD
GND
CHAN-P6
2
2
JP2
47
REFP
AVDD
1 AINP2
REFP_HDR
AINN8 46
REF_CKT
AINP7 47
AINN7 48
TP2 TP3
(See page -1)
REFP_HDR[2]
1
1
R12
AVDD
DGND
C20
0.1u
U13
DGND
DGND
DGND
DGND
R19
100k
R25
1
2
3
4
5
6
7
8
9
10
IOVDD
47
IOVDD
U6
CLKDIV [3]
CM1 0
AVDD_1 [1]
C26
0.1u
10u
8 VCC
A 1
7 G
B 2
6 B_A
Y 3
5 Y
C27
4
3
Y1
R30
470k
GND 4
C28
1
OUT
EOH
0.1u
2
DGND
AGND
AGND
DGND
CM2 0
DVDD_26
[1]
DGND
IOVDD
CM3 0
IOVDD_22_23
[1]
TP7
TP4
TP11
TP1
JP4 JP5
4
C57
CM1-3 are available for current monitoring
AGND
DGND
10u
Texas Instruments
Setting
OFF ON
Hardware External
OFF OFF
Hardware Internal
ON x
ADS1278EVM
Software Control (GPIO5)
Size
Number
B
C
D
G Hupp
E
Rev
C
Engineer
4
Title
DGND
A
IOVDD
GND
J5
VCC
AGND
AVDD
E
Date
07APR11
Drawn by
Filename
ads1278evm.sch
Sheet
G Hupp
1
F
of
4
2/9/2012
A
B
C
D
E
F
1
1
2
2
S3
R1
2k
C2
150n
AVDD
[1,2]
REFN_HDR
[1,2]
C7
REFP_HDR
[1,2]
10u
[1]
REFN
8
V+
[1]
U2-A
2 VIN
C4
1u
0.1u
C1
DNC 8
NC 7
3 TEMP
VOUT 6
4 GND
TRIM 5
100u
C5
C6
3
C3
V-
4
U1
1 DNC
1
OUTA
3
1k
R3
47
2
R2
REFP
3
10u
1u
AGND
[1,2,3]
Texas Instruments
4
4
Title
ADS1278EVM
Size
Number
C
Engineer
A
B
C
D
G Hupp
E
Rev
E
Date
07APR11
Drawn by
Filename
ads1278evm.sch
Sheet
G Hupp
-1
F
of
4
2/9/2012
A
B
C
D
E
F
ANALOG_IN [1,3]
1
CM
1
R39
R47
1k
C48
1k
C52
1.5n
1.5n
AVDD
PD
7
R29
100k
R45
2
BUF_PDN
[2]
AVDD
1
JP3
VOUT-
R49 49.9
C25
ANN1
R43
ANP1
CHAN-N3
C18
VOUT-
R37
5
VS6
2
VOCM
0.1u
VIN- 1
1k
CHAN-P3
VOUT+ 4
R36 49.9
CM
TP9
AGND
2
VOCM
AVDD
C53
AGND
2.2n
49.9
R42
CHAN-P1
VOUT+ 4
S5
3
VS+
8
VIN+
1k
2.2n
C50
2
5
U9
R50 49.9
0.1u
AGND
PD
7
CHAN-N1
1k
C13
PWRDN BUFFERS
AVDD
S8
VIN- 1
R46
[2]
TP10
3
VS+
8
VIN+
1k
BUF_PDN
U11
AVDD
1.5n
C17
C47
0.1u
1.5n
2
1k
0.1u
R48
AGND
R38
C22
AGND
VS6
ANN3
ANP3
AGND
1k
AGND
R17
AVDD
R22
1k
C14
1k
C19
C39
0.1u
BUF_PDN
1.5n
1.5n
AVDD
[2]
PD
7
R24
3
VS+
R23 49.9
ANP4
2.2n
ANP2
R20
VIN- 1
R21
C24
0.1u
0.1u
1.5n
3
C15
0.1u
1.5n
AGND
J3
2.2n
CHAN-P4
3
R18
1k
AGND
1k
C16
AGND
C49
R27
ANP3
CHAN-N4
VS6
2
VOCM
AVDD
C55
R14 49.9
R15 49.9
CM
AGND
5
VOUT+ 4
VS6
C21
S4
VOUT-
1k
R28 49.9
AGND
3
VS+
8
VIN+
1k
CHAN-P2
VOUT+ 4
1k
2
VOCM
PD
7
ANN4
VIN- 1
R26
5
[2]
C23
ANN2
VOUT-
8
VIN+
1k
ANP2
ANN2
ANP1
ANN1
BUF_PDN
CHAN-N2
AGND
U3
AVDD
S7
U5
ANN3
ANN4
ANP4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ANN4
ANP4
REFN_HDR[1]
REFP_HDR[1]
AGND
BRD_ANLG_IN
Texas Instruments
4
4
Title
ADS1278EVM
Size
Number
C
Engineer
A
B
C
D
G Hupp
E
Rev
E
Date
07APR11
Drawn by
Filename
ads1278evm.sch
Sheet
G Hupp
2
F
of
4
2/9/2012
A
B
C
D
E
F
1
1
Channels 5-8 Analog Connections
C9
C8
C10
C12
2.2n
2.2n
2.2n
2.2n
IOVDD
IOVDD
1
2
3
4
5
S2
1
2
3
4
6
12
11
10
9
7
6
CLKDIV
1 2
5
GPIO1
1 2
4
GPIO0
1 2
8
11
12
13
14
1 2
3
GPIO4
1 2
2
GPIO3
1 2
1
GPIO2
16
14
2
15
8
2
1
3
1
S1
GPIO/Logic Connections
12
AGND
7
AGND
13
AGND
6
AGND
11
AGND
8
AGND
10
AGND
5
AGND
DGND
9
C36
1.5n
7
C37
1.5n
6
C34
1.5n
4
C35
1.5n
5
C32
1.5n
4
C33
1.5n
3
C30
1.5n
2
2
C31
1.5n
15
16
R33-A
100k
5
1 2
8
1 2
7
1 2
1 2
6
5
1 2
4
1 2
3
2
1 2
6
9
10
11
12
13
15
16
ANALOG_IN
[1,2]
1 2
CHAN-N8
CHAN-P8
CHAN-N7
CHAN-P7
CHAN-N6
CHAN-P6
CHAN-N5
CHAN-P5
0
0
0
0
0
0
0
0
R10
R11
R8
R9
R6
R7
R4
R5
1
1
2
3
4
5
6
7
8
9
10
14
R32-A
100k
J1
DGND
R35
4.3k
SCL 19
C40
0.1u
10
11
DGND
12
GPIO1
GPIO0
P01 2
P00 1
PWDN8
PWDN7
PWDN6
PWDN5
PWDN4
PWDN3
PWDN2
SCL
GPIO2
P02 3
SDA
GPIO3
P03 4
A1 23
24
IOVDD
INT 22
P10
VCC 21
P11
SDA 20
P12
SCL 19
IOVDD
C29
0.1u
IOVDD
DGND
U7
DGND
C58
0.1u
U14
DGND
13 P13
U8
A2
P07
8
DGND GND
9
3
25
P06
18 A0
P12
7
17 P17
SDA 20
PWPD
16 P16
P11
R34
10k
C38
15 P15
VCC 21
0.1u
14 P14
INT 22
P10
13 P13
12
24
GND
18 A0
11
A1 23
17 P17
10
P07
16 P16
9
25
A2
15 P15
8
P05 6
IOVDD
P06
14 P14
3
GPIO4
IOVDD
PWPD
7
CLKDIV
[1,3]
P00 1
P01 2
P02 3
P03 4
P04 5
P05 6
IOVDD
P04 5
CLKDIV
SCL
SDA
PWDN1
PWDN2
PWDN3
PWDN5
PWDN4
PWDN6
PWDN7
PWDN8
SW_IND
DIGITAL
[1]
PWDN1
DGND
1 A0
VCC 8
2 A1
WP 7
3 A2
SCL 6
4 VSS
SDA 5
DGND
SDA
SCL
DGND
DGND
DGND
DGND
Texas Instruments
4
4
Title
ADS1278EVM
Size
Number
C
Engineer
A
B
C
D
G Hupp
E
Rev
E
Date
07APR11
Drawn by
Filename
ads1278evm.sch
Sheet
G Hupp
3
F
of
4
2/9/2012
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications
(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you
will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO
ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,
COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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