ADS1278IPAPR

AD S1 274 AD S1 278 www.ti.com ADS1274 ADS1278 SBAS367 – JUNE 2007 Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters 1 FEATURES Simultaneously Measure Four/Eight Channels Up to 128kSPS Data Rate AC Performance: 62kHz Bandwidth 111dB SNR (High-Resolution Mode) –108dB THD DC Accuracy: 0.8μV/°C Offset Drift 1.3ppm/°C Gain Drift Selectable Operating Modes: High-Speed: 128kSPS, 106dB SNR High-Resolution: 52kSPS, 111dB SNR Low-Power: 52kSPS, 31mW/ch Low-Speed: 10kSPS, 7mW/ch Linear Phase Digital Filter SPI™ or Frame-Sync Serial Interface Low Sampling Aperture Error Modulator Output Option (digital filter bypass) Analog Supply: 5V Digital Core: 1.8V I/O Supply: 1.8V to 3.3V • • • 234 DESCRIPTION Based on the single-channel ADS1271, the ADS1274 (quad) and ADS1278 (octal) are 24-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with data rates up to 128k samples per second (SPS), allowing simultaneous sampling of four or eight channels. The devices are offered in identical packages, permitting drop-in expandability. Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for dc measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than respective industrial counterparts. The ADS1274 and ADS1278 combine these types of converters, allowing high-precision industrial measurement with excellent dc and ac specifications. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. These ADCs provide a usable signal bandwidth up to 90% of the Nyquist rate with less than 0.005dB of ripple. Four operating modes allow for optimization of speed, resolution, and power. All operations are controlled directly by pins; there are no registers to program. The devices are fully specified over the extended industrial range (–40°C to +105°C) and are available in an HTQFP-64 PowerPAD™ package. VREFP VREFN AVDD DVDD IOVDD • • • • • • • • • • • • • APPLICATIONS Vibration/Modal Analysis Multi-Channel Data Acquisition Acoustics/Dynamic Strain Gauges Pressure Sensors VREFP VREFN AVDD DVDD IOVDD Input1 Input2 Input3 Input4 DS DS DS DS Four Digital Filters SPI and FrameSync Interface DRDY/FSYNC SCLK DOUT[4:1] DIN TEST[1:0] FORMAT[2:0] CLK SYNC PWDN[4:1] CLKDIV MODE[1:0] Input1 Input2 Input3 Input4 Input5 Input6 Input7 Input8 DS DS DS DS DS DS DS DS AGND Eight Digital Filters SPI and FrameSync Interface DRDY/FSYNC SCLK DOUT[8:1] DIN TEST[1:0] FORMAT[2:0] CLK SYNC PWDN[8:1] CLKDIV MODE[1:0] Control Logic Control Logic AGND DGND DGND ADS1274 1 ADS1278 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Inc. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. Copyright © 2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted (1) ADS1274, ADS1278 AVDD to AGND DVDD, IOVDD to DGND AGND to DGND Input current Analog input to AGND Digital input or output to DGND Maximum junction temperature Operating temperature range Storage temperature range (1) ADS1274 ADS1278 Momentary Continuous –0.3 to +6.0 –0.3 to +3.6 –0.3 to +0.3 100 10 –0.3 to AVDD + 0.3 –0.3 to DVDD + 0.3 +150 –40 to +125 –40 to +105 –60 to +150 UNIT V V V mA mA V V °C °C °C °C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, and all channels active, unless otherwise noted. ADS1274, ADS1278 PARAMETER Analog Inputs Full-scale input voltage (FSR (1)) Absolute input voltage Common-mode input voltage (VCM) High-Speed mode Differential input impedance High-Resolution mode Low-Power mode Low-Speed mode DC Performance Resolution High-Speed mode Data rate (fDATA) High-Resolution mode Low-Power mode Low-Speed mode Integral nonlinearity (INL) (4) Offset error Offset drift Gain error Gain drift High-Speed mode Noise High-Resolution mode Low-Power mode Low-Speed mode Common-mode rejection AVDD Power-supply rejection DVDD IOVDD VCOM output voltage No load fPS = 60Hz Shorted input Shorted input Shorted input Shorted input fCM = 60Hz 90 Differential input, VCM = 2.5V No missing codes fCLK = 32.768MHz (2) fCLK = 27MHz 24 128,000 105,469 52,734 52,734 10,547 ±0.0003 0.25 0.8 0.1 1.3 8.5 5.5 8.5 8.0 108 80 85 105 AVDD/2 16 12 16 16 0.5 ±0.0012 2 Bits SPS SPS (3) SPS SPS SPS % FSR (1) mV μV/°C % FSR ppm/°C μV, rms μV, rms μV, rms μV, rms dB dB dB dB V VIN = (AINP – AINN) AINP or AINN to AGND VCM = (AINP + AINN)/2 AGND – 0.1 2.5 14 14 28 140 ±VREF AVDD + 0.1 V V V kΩ kΩ kΩ kΩ TEST CONDITIONS MIN TYP MAX UNIT (1) (2) (3) (4) FSR = full-scale range = 2VREF. fCLK = 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When fCLK > 27MHz, operation is limited to Frame-Sync mode and VREF ≤ 2.6V. SPS = samples per second. Best fit method. Copyright © 2007, Texas Instruments Incorporated 3 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, and all channels active, unless otherwise noted. ADS1274, ADS1278 PARAMETER AC Performance Crosstalk High-Speed mode Signal-to-noise ratio (SNR) (6) (unweighted) High-Resolution mode Low-Power mode Low-Speed mode Total harmonic distortion (THD) (7) Spurious-free dynamic range Passband ripple Passband –3dB Bandwidth Stop band attenuation High-Resolution mode All other modes High-Resolution mode All other modes High-Resolution mode All other modes High-Resolution mode All other modes Complete settling Complete settling 95 100 0.547 fDATA 0.547 fDATA 39/fDATA 38/fDATA 78/fDATA 76/fDATA 0.5 0.5 AGND – 0.1 VREFN + 0.5 High-Speed mode ADS1274 Reference Input impedance High-Resolution mode Low-Power mode Low-Speed mode High-Speed mode ADS1278 Reference Input impedance High-Resolution mode Low-Power mode Low-Speed mode Digital Input/Output (IOVDD = 1.8V to 3.6V) VIH VIL VOH VOL Input leakage Master clock rate (fCLK) IOH = 4mA IOL = 4mA 0 < VIN DIGITAL < IOVDD High-Speed mode (8) Other modes 0.1 0.1 0.7 IOVDD DGND 0.8 IOVDD DGND IOVDD 0.3 IOVDD IOVDD 0.2 IOVDD ±10 32.768 27 V V V V μA MHz MHz 1.3 1.3 2.6 13 0.65 0.65 1.3 6.5 2.5 2.5 3.1 2.6 AGND + 0.1 AVDD + 0.1 127.453 fDATA 63.453 fDATA Hz Hz s s s s 0.453 fDATA 0.49 fDATA VIN = 1kHz, –0.5dBFS VREF = 2.5V VREF = 3V 101 101 f = 1kHz, –0.5dBFS (5) 101 103 –107 106 110 111 106 107 –108 109 ±0.005 –96 dB dB dB dB dB dB dB dB dB Hz Hz dB TEST CONDITIONS MIN TYP MAX UNIT Stop band Group delay Settling time (latency) Voltage Reference Inputs Reference input voltage (VREF) (VREF = VREFP – VREFN) fCLK = 27MHz fCLK = 32.768MHz (8) V V V V kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ Negative reference input (VREFN) Positive reference input (VREFP) (5) (6) (7) (8) Worst-case channel crosstalk between one or more channels. Minimum SNR is ensured by the limit of the DC noise specification. THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics. fCLK = 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When fCLK > 27MHz, operation is limited to Frame-Sync mode and VREF ≤ 2.6V. 4 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, and all channels active, unless otherwise noted. ADS1274, ADS1278 PARAMETER Power Supply AVDD DVDD IOVDD AVDD Power-down current DVDD IOVDD ADS1274 High-Speed mode ADS1274 AVDD current High-Resolution mode Low-Power mode Low-Speed mode High-Speed mode ADS1274 DVDD current High-Resolution mode Low-Power mode Low-Speed mode High-Speed mode ADS1274 IOVDD current High-Resolution mode Low-Power mode Low-Speed mode High-Speed mode ADS1274 Power dissipation High-Resolution mode Low-Power mode Low-Speed mode ADS1278 High-Speed mode ADS1278 AVDD current High-Resolution mode Low-Power mode Low-Speed mode High-Speed mode ADS1278 DVDD current High-Resolution mode Low-Power mode Low-Speed mode High-Speed mode ADS1278 IOVDD current High-Resolution mode Low-Power mode Low-Speed mode High-Speed mode ADS1278 Power dissipation High-Resolution mode Low-Power mode Low-Speed mode 97 97 44 9 23 16 12 2.5 0.25 0.125 0.125 0.035 530 515 245 50 145 145 64 14 30 20 17 4.5 1 0.5 0.5 0.2 785 765 355 80 mA mA mA mA mA mA mA mA mA mA mA mA mW mW mW mW 50 50 23 5 18 12 10 2.5 0.15 0.075 0.075 0.02 285 275 135 30 75 75 35 9 24 17 15 4.5 0.5 0.3 0.3 0.15 420 410 210 55 mA mA mA mA mA mA mA mA mA mA mA mA mW mW mW mW 4.75 1.65 1.65 1 1 1 5 1.8 5.25 1.95 3.6 10 15 10 V V V μA μA μA TEST CONDITIONS MIN TYP MAX UNIT Copyright © 2007, Texas Instruments Incorporated 5 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com ADS1274/ADS1278 PIN ASSIGNMENTS PAP PACKAGE HTQFP-64 (TOP VIEW) AINN5(1) AINP5(1) AINN6(1) 50 VREFN VREFP VCOM AINP6(1) 49 AINN3 AINN4 AINP3 AINP4 AGND AGND AGND 54 AVDD AVDD 53 64 63 62 61 60 59 58 57 56 55 52 51 AINP2 AINN2 AINP1 AINN1 AVDD AGND DGND TEST0 TEST1 CLKDIV SYNC DIN DOUT8(1) DOUT7(1) DOUT6(1) DOUT5(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (PowerPAD Outline) NOTE: (1) Boldface pin names indicate additional pins for the ADS1278; see pin descriptions. 48 47 46 45 44 43 42 AINN7(1) AINP7(1) AINN8(1) AINP8(1) AVDD AGND PWDN1 PWDN2 PWDN3 PWDN4 PWDN5(1) PWDN6(1) PWDN7(1) PWDN8(1) MODE0 MODE1 ADS1274/ADS1278 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FORMAT1 DOUT1 IOVDD IOVDD DGND DGND DGND DVDD DRDY/FSYNC FORMAT2 DOUT3 DOUT2 ADS1274/ADS1278 PIN DESCRIPTIONS PIN NAME AGND AINP1 AINP2 AINP3 AINP4 AINP5 AINP6 AINP7 AINP8 NO. 6, 43, 54, 58, 59 3 1 63 61 51 49 47 45 FUNCTION Analog ground Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input ADS1274: AINP[8:5] Connected to internal ESD rails. The inputs may float. AINP[4:1] Positive analog input, channels 4 through 1. ADS1278: AINP[8:1] Positive analog input, channels 8 through 1. DESCRIPTION Analog ground; connect to DGND using a single plane. 6 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated FORMAT0 DOUT4 SCLK CLK 32 ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 ADS1274/ADS1278 PIN DESCRIPTIONS (continued) PIN NAME AINN1 AINN2 AINN3 AINN4 AINN5 AINN6 AINN7 AINN8 AVDD VCOM VREFN VREFP CLK CLKDIV DGND DIN DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DRDY/ FSYNC DVDD FORMAT0 FORMAT1 FORMAT2 IOVDD MODE0 MODE1 PWDN1 PWDN2 PWDN3 PWDN4 PWDN5 PWDN6 PWDN7 PWDN8 SCLK SYNC TEST0 TEST1 NO. 4 2 64 62 52 50 48 46 5, 44, 53, 60 55 57 56 27 10 7, 21, 24, 25 12 20 19 18 17 16 15 14 13 29 26 32 31 30 22, 23 34 33 42 41 40 39 38 37 36 35 28 11 8 9 FUNCTION Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog power supply Analog output Analog input Analog input Digital input Digital input Digital ground Digital input Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital input/output Digital power supply Digital input Digital input Digital input Digital power supply Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input/output Digital input Digital input Digital input Serial clock input, Modulator clock output. Synchronize input (all channels). TEST[1:0] Test mode select: 00 = Normal operation 11 = Boundary scan test mode 01 = Do not use 10 = Do not use ADS1274: PWDN[8:5] must = 0V. PWDN[4:1] Power-down control for channels 4 through 1. ADS1278: PWDN[8:1] Power-down control for channels 8 through 1. I/O power supply (+1.65V to +3.6V). MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed mode operation. FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs, fixed/dynamic position TDM data, and modulator mode/normal operating mode. Frame-Sync protocol: frame clock input; SPI protocol: data ready output. Digital core power supply (+1.65V to +1.95V). ADS1274: DOUT[8:5] Internally connected to active circuitry; outputs are driven. DOUT[4:1] Data output for channels 4 through 1. ADS1278: DOUT[8:1] Data output for channels 8 through 1. Analog power supply (4.75V to 5.25V). AVDD/2 Unbuffered voltage output. Negative reference input. Positive reference input. Master clock input. CLK input divider control: Digital ground power supply. Daisy-chain data input. DOUT1 is TDM data output (TDM mode). 1 = 32.768MHz (High-Speed mode only) / 27MHz 0 = 13.5MHz (low-power) / 5.4MHz (low-speed) ADS1274: AINN[8:5] Connected to internal ESD rails. The inputs may float. AINN[4:1] Negative analog input, channels 4 through 1. ADS1278: AINN[8:1] Negative analog input, channels 8 through 1. DESCRIPTION Copyright © 2007, Texas Instruments Incorporated 7 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com TIMING CHARACTERISTICS: SPI FORMAT tCLK CLK tCD DRDY tDS SCLK tMSBPD DOUT Bit 23 (MSB) tSPW Bit 22 tDIST DIN tDIHD tDOHD Bit 21 tDOPD tSD tSCLK tSPW tCPW ··· tCPW tCONV TIMING REQUIREMENTS: SPI FORMAT For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V. SYMBOL tCLK tCPW tCONV tCD (3) tDS (3) tMSBPD tSD (3) PARAMETER CLK period (1/fCLK) (1) MIN 37 15 256 TYP MAX 10,000 2560 UNIT ns ns tCLK ns tCLK CLK positive or negative pulse width Conversion period (1/fDATA) (2) Falling edge of CLK to falling edge of DRDY Falling edge of DRDY to rising edge of first SCLK to retrieve data DRDY falling edge to DOUT MSB valid (propagation delay) Falling edge of SCLK to rising edge of DRDY SCLK period SCLK positive or negative pulse width SCLK falling edge to new DOUT invalid (hold time) SCLK falling edge to new DOUT valid (propagation delay) New DIN valid to falling edge of SCLK (setup time) Old DIN valid to falling edge of SCLK (hold time) (3) 22 1 16 18 1 0.4 10 32 6 6 ns ns tCLK tCLK ns ns ns ns tSCLK (4) tSPW tDOHD (3) (5) tDOPD tDIST tDIHD (5) (1) (2) (3) (4) (5) fCLK = 27MHz maximum. Depends on MODE[1:0] and CLKDIV selection. See Table 6 (fCLK/fDATA). Load on DRDY and DOUT = 20pF. For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns. 8 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 TIMING CHARACTERISTICS: FRAME-SYNC FORMAT tCLK CLK tCS tCPW tFRAME FSYNC tFS SCLK tMSBPD DOUT Bit 23 (MSB) tSPW Bit 22 tDIST DIN tDIHD tDOHD Bit 21 tDOPD tFPW tSCLK tFPW tSPW tSF tCPW TIMING REQUIREMENTS: FRAME-SYNC FORMAT For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V. SYMBOL tCLK tCPW tCS tFRAME tFPW tFS tSF tSCLK tSPW tDOHD (3) (4) PARAMETER CLK period (1/fCLK) CLK positive or negative pulse width Falling edge of CLK to falling edge of SCLK Frame period (1/fDATA) (1) FSYNC positive or negative pulse width Rising edge of FSYNC to rising edge of SCLK Rising edge of SCLK to rising edge of FSYNC SCLK period (2) SCLK positive or negative pulse width SCLK falling edge to old DOUT invalid (hold time) SCLK falling edge to new DOUT valid (propagation delay) FSYNC rising edge to DOUT MSB valid (propagation delay) New DIN valid to falling edge of SCLK (setup time) Old DIN valid to falling edge of SCLK (hold time) All modes High-Speed mode only MIN 37 30.5 12 –0.25 256 1 5 5 1 0.4 10 TYP MAX 10,000 UNIT ns ns ns 0.25 2560 tCLK tCLK tSCLK ns ns tCLK tCLK ns tDOPD (4) tMSBPD tDIST tDIHD (3) (1) (2) (3) (4) 31 31 6 6 ns ns ns ns Depends on MODE[1:0] and CLKDIV selection. See Table 6 (fCLK/fDATA). SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK. tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns. Load on DOUT = 20pF. Copyright © 2007, Texas Instruments Incorporated 9 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. OUTPUT SPECTRUM 0 -20 -40 High-Speed Mode fIN = 1kHz, -0.5dBFS 32,768 Points 0 -20 -40 OUTPUT SPECTRUM High-Speed Mode fIN = 1kHz, -20dBFS 32,768 Points Amplitude (dB) -60 -80 -100 -120 -140 -160 10 100 1k Frequency (Hz) 10k 100k Amplitude (dB) -60 -80 -100 -120 -140 -160 10 100 1k Frequency (Hz) 10k 100k Figure 1. OUTPUT SPECTRUM 0 -20 -40 High-Speed Mode Shorted Input 262,144 Points 25k Figure 2. NOISE HISTOGRAM High-Speed Mode Shorted Input 262,144 Points -60 -80 -100 -120 -140 -160 Number of Occurrences 20k Amplitude (dB) 15k 10k 5k -7 0 7 14 21 28 1 10 100 1k Frequency (Hz) 10k 100k -35 -28 -21 -14 Output (mV) Figure 3. OUTPUT SPECTRUM 0 -20 -40 High-Resolution Mode fIN = 1kHz, -0.5dBFS 32,768 Points 0 -20 -40 Figure 4. OUTPUT SPECTRUM High-Resolution Mode fIN = 1kHz, -20dBFS 32,768 Points Amplitude (dB) -60 -80 -100 -120 -140 -160 10 100 1k Frequency (Hz) 10k 100k Amplitude (dB) -60 -80 -100 -120 -140 -160 10 100 1k Frequency (Hz) 10k 100k Figure 5. Figure 6. 10 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated 35 -180 0 ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. OUTPUT SPECTRUM 0 -20 -40 High-Resolution Mode Shorted Input 262,144 Points 25k NOISE HISTOGRAM High-Resolution Mode Shorted Input 262,144 Points -60 -80 -100 -120 -140 -160 Number of Occurrences 20k Amplitude (dB) 15k 10k 5k -3.5 3.5 10.5 -17.5 -10.5 14.0 17.5 -7.0 0 7.0 -24.5 -21.0 -14.0 21.0 1 10 100 1k Frequency (Hz) 10k 100k Output (mV) Figure 7. OUTPUT SPECTRUM 0 -20 -40 Low-Power Mode fIN = 1kHz, -0.5dBFS 32,768 Points 0 -20 -40 Figure 8. OUTPUT SPECTRUM Low-Power Mode fIN = 1kHz, -20dBFS 32,768 Points Amplitude (dB) -60 -80 -100 -120 -140 -160 10 100 1k Frequency (Hz) 10k 100k Amplitude (dB) -60 -80 -100 -120 -140 -160 10 100 1k Frequency (Hz) 10k 100k Figure 9. OUTPUT SPECTRUM 0 -20 -40 Low-Power Mode Shorted Input 262,144 Points Figure 10. NOISE HISTOGRAM 25k Low-Power Mode Shorted Input 262,144 Points -60 -80 -100 -120 -140 -160 Number of Occurrences 20k Amplitude (dB) 15k 10k 5k -21 -11 11 21 -180 1 10 100 1k Frequency (Hz) 10k 100k 0 -32 32 -5 5 -37 -26 -16 Output (mV) Figure 11. Figure 12. 16 26 37 0 24.5 -180 0 Copyright © 2007, Texas Instruments Incorporated 11 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. OUTPUT SPECTRUM 0 -20 -40 Low-Speed Mode fIN = 100Hz, -0.5dBFS 32,768 Points 0 -20 -40 OUTPUT SPECTRUM Low-Speed Mode fIN = 100Hz, -20dBFS 32,768 Points Amplitude (dB) -60 -80 -100 -120 -140 -160 1 10 100 Frequency (Hz) 1k 10k Amplitude (dB) -60 -80 -100 -120 -140 -160 1 10 100 Frequency (Hz) 1k 10k Figure 13. OUTPUT SPECTRUM 0 -20 -40 Low-Speed Mode Shorted Input 262,144 Points 25k Figure 14. NOISE HISTOGRAM Low-Speed Mode Shorted Input 262,144 Points -60 -80 -100 -120 -140 -160 Number of Occurrences 20k Amplitude (dB) 15k 10k 5k -7 0 7 14 21 28 -20 0.1 1 10 100 Frequency (Hz) 1k 10k -35 -28 -21 -14 Output (mV) Figure 15. TOTAL HARMONIC DISTORTION vs FREQUENCY 0 -20 High-Speed Mode VIN = -0.5dBFS 0 -20 Figure 16. TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE High-Speed Mode fIN = 1kHz THD, THD+N (dB) -40 -60 -80 -100 -120 -140 10 100 1k Frequency (Hz) 10k 100k THD+N THD, THD+N (dB) -40 -60 -80 -100 -120 -140 -120 THD -100 -80 -60 -40 Input Amplitude (dBFS) 0 THD+N THD Figure 17. Figure 18. 12 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated 35 -180 0 ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. TOTAL HARMONIC DISTORTION vs FREQUENCY 0 -20 High-Resolution Mode VIN = -0.5dBFS 0 -20 TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE High-Resolution Mode fIN = 1kHz THD, THD+N (dB) -40 -60 -80 -100 -120 -140 10 100 1k Frequency (Hz) 10k 100k THD+N THD THD, THD+N (dB) -40 -60 -80 -100 -120 -140 -120 THD+N THD -100 -80 -60 -40 Input Amplitude (dBFS) -20 0 Figure 19. TOTAL HARMONIC DISTORTION vs FREQUENCY 0 -20 Low-Power Mode VIN = -0.5dBFS 0 -20 Figure 20. TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE Low-Power Mode fIN = 1kHz THD, THD+N (dB) -40 -60 -80 -100 -120 -140 10 100 1k Frequency (Hz) 10k 100k THD+N THD THD, THD+N (dB) -40 -60 -80 -100 -120 -140 -120 THD+N THD -100 -80 -60 -40 Input Amplitude (dBFS) -20 0 Figure 21. TOTAL HARMONIC DISTORTION vs FREQUENCY 0 -20 Low-Speed Mode VIN = -0.5dBFS 0 -20 Figure 22. TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE Low-Speed Mode THD, THD+N (dB) -40 -60 -80 -100 -120 -140 10 100 Frequency (Hz) 1k 10k THD+N THD THD, THD+N (dB) -40 -60 -80 -100 -120 -140 -120 THD+N THD -100 -80 -60 -40 Input Amplitude (dBFS) -20 0 Figure 23. Figure 24. Copyright © 2007, Texas Instruments Incorporated 13 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. OFFSET DRIFT HISTOGRAM 400 350 Multi-lot data based on 20°C intervals over the range -40°C to +105°C. 900 800 GAIN DRIFT HISTOGRAM 25 units based on 20°C intervals over the range -40°C to +105°C. Number of Occurrences 300 250 200 150 100 50 Number of Occurrences 700 600 500 400 300 200 100 Outliers: T < -20°C -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 Offset Drift (mV/°C) Figure 25. OFFSET WARMUP DRIFT RESPONSE BAND 40 ADS1278 High-Speed and High-Resolution Modes ADS1278 Low-Power Mode 20 10 0 -10 -20 ADS1278 Low-Speed Mode -30 ADS1274 High-Speed and High-Resolution Modes -40 0 50 100 150 200 250 Time (s) 300 350 400 -40 0 50 100 40 30 30 Normalized Gain Error (ppm) Normalized Offset (mV) 20 10 0 -10 -20 ADS1278 Low-Speed Mode -30 150 200 250 Time (s) 300 350 400 Figure 27. OFFSET ERROR HISTOGRAM 40 35 90 High-Speed Mode 25 Units 80 Number of Occurrences Number of Occurrences 30 25 20 15 10 5 70 60 50 40 30 20 10 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 Offset (mV) Figure 29. 14 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 -4000 -3600 -3200 -2800 -2400 -2000 -1600 -1200 -800 -400 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 Gain Error (ppm) 0 0 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Gain Drift (ppm/°C) 0 0 Figure 26. GAIN WARMUP DRIFT RESPONSE BAND ADS1274/78 High-Speed and High-Resolution Modes ADS1278 Low-Power Mode Figure 28. GAIN ERROR HISTOGRAM High-Speed Mode 25 Units Figure 30. Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. CHANNEL GAIN MATCH HISTOGRAM 100 90 Number of Occurrences CHANNEL OFFSET MATCH HISTOGRAM 70 60 Number of Occurrences High-Speed Mode 10 Units High-Speed Mode 10 Units 80 70 60 50 40 30 20 10 -1500 -1400 -1300 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 50 40 30 20 10 - 1500 - 1400 - 1300 - 1200 - 1100 - 1000 - 900 - 800 - 700 - 600 - 500 - 400 - 300 - 200 - 100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 0 0 Channel Gain Match (ppm) Channel Offset Match (mV) Figure 31. OFFSET AND GAIN vs TEMPERATURE 100 50 Offset 300 Figure 32. VCOM VOLTAGE OUTPUT HISTOGRAM 20 18 250 200 150 Gain 100 50 0 -50 -100 120 125 Normalized Gain Error (ppm) AVDD = 5V 25 Units, No Load 0 -50 -100 -150 -200 -250 -300 -40 Number of Occurrences Normalized Offset (mV) 16 14 12 10 8 6 4 2 0 -20 0 20 40 60 Temperature (°C) 80 100 Figure 33. ADS1274/ADS1278 SAMPLING MATCH ERROR HISTOGRAM 40 35 Number of Occurrences Reference Input Impedance (kW) 1.34 1.32 1.30 1.28 1.26 1.24 1.22 -40 High-Speed and High-Resolution Modes Low-Speed Mode 13.4 13.2 13.0 12.8 12.6 12.4 12.2 120 125 30 ADS1278 25 ADS1274 20 15 10 ADS1278 5 50 100 150 200 250 300 350 400 450 500 550 600 650 700 0 -20 0 Sampling Match Error (ps) 20 40 60 Temperature (°C) 80 100 Figure 35. Figure 36. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Reference Input Impedance (kW) 30 units over 3 production lots, inter-channel combinations. 1.36 2.40 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 VCOM Voltage Output (V) Figure 34. ADS1274 REFERENCE INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 13.6 15 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. ADS1278 REFERENCE INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 0.68 Reference Input Impedance (kW) ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 6.8 Reference Input Impedance (kW) Analog Input Impedance (kW) 14.4 14.3 14.2 14.1 14.0 13.9 13.8 13.7 13.6 13.5 13.4 -40 -20 0 20 40 60 Temperature (°C) Low-Power Mode 80 100 High-Speed and High-Resolution Modes 28.8 Analog Input Impedance (kW) 28.6 28.4 28.2 28.0 27.8 27.6 27.4 27.2 27.0 0.67 0.66 0.65 0.64 0.63 0.62 -40 High-Speed and High-Resolution Modes 6.7 6.6 6.5 6.4 6.3 6.2 120 125 Low-Speed Mode -20 0 20 40 60 Temperature (°C) 80 100 26.8 120 125 Figure 37. ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 155 10 Low-Speed Mode 8 150 Figure 38. INTEGRAL NONLINEARITY vs TEMPERATURE Analog Input Impedance (kW) 140 135 130 125 120 115 -40 INL (ppm of FSR) -20 0 20 40 60 Temperature (°C) 80 100 120 125 145 6 4 2 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 Figure 39. LINEARITY ERROR vs INPUT LEVEL 10 8 6 14 12 T = +105°C T = +25°C 10 8 6 4 T = -40°C T = +125°C 2 0 0 0.5 VIN (V) 1.0 1.5 2.0 2.5 0 Linearity Figure 40. LINEARITY AND TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE THD: fIN = 1kHz, VIN = -0.5dBFS -100 -104 -108 -112 -116 -120 -124 See Electrical Characteristics for VREF Operating Range. 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 -128 Linearity Error (ppm) Linearity (ppm) 4 2 0 -2 -4 -6 -8 -10 -2.5 -2.0 -1.5 -1.0 -0.5 Figure 41. Figure 42. 16 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated THD (dB) THD ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. NOISE AND LINEARITY vs INPUT COMMON-MODE VOLTAGE 14 12 RMS Noise (mV) NOISE vs TEMPERATURE 14 12 INL (ppm of FSR) 12 Low-Power Mode 10 High-Speed Mode Low-Speed Mode 6 4 High-Resolution Mode 2 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 RMS Noise (mV) 10 Noise 8 6 Linearity 4 2 0 -0.5 0 10 8 6 4 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Common-Mode Voltage (V) 8 Figure 43. NOISE vs REFERENCE VOLTAGE 12 10 8 Low-Power High-Speed Figure 44. TOTAL HARMONIC DISTORTION AND NOISE vs CLK 0 -20 -40 THD (dB) Low-Speed 14 THD: fIN = fCLK/5120, VIN = -0.5dBFS Noise: Shorted Input All Channels Plotted 12 Noise RMS (mV) 10 8 Noise 6 THD 4 2 0 100M Noise (mV) -60 -80 -100 -120 6 4 High-Resolution 2 See Electrical Characteristics for VREF Operating Range. 0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 -140 10k 100k 1M CLK (Hz) 10M Figure 45. COMMON-MODE REJECTION vs INPUT FREQUENCY 0 0 Figure 46. POWER-SUPPLY REJECTION vs POWER-SUPPLY FREQUENCY Common-Mode Rejection (dB) -40 -60 -80 -100 -120 10 100 1k 10k Input Frequency (Hz) 100k 1M Power-Supply Rejection (dB) -20 -20 -40 -60 AVDD -80 -100 -120 10 100 1k 10k 100k Power-Supply Modulation Frequency (Hz) 1M DVDD IOVDD Figure 47. Figure 48. Copyright © 2007, Texas Instruments Incorporated 17 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. ADS1274 AVDD CURRENT vs TEMPERATURE 70 60 AVDD Current (mA) ADS1274 DVDD CURRENT vs TEMPERATURE 25 50 40 30 Low-Power Mode 20 10 Low-Speed Mode -20 0 20 40 60 Temperature (°C) 80 100 120 125 DVDD Current (mA) High-Speed and High-Resolution Modes 20 High-Speed Mode 15 High-Resolution Mode 10 Low-Power Mode 5 Low-Speed Mode 0 -40 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 Figure 49. ADS1274 IOVDD CURRENT vs TEMPERATURE 0.25 400 350 Power Dissipation (mW) Figure 50. ADS1274 POWER DISSIPATION vs TEMPERATURE 0.20 High-Speed Mode IOVDD Current (mA) 300 250 200 150 100 Low-Speed Mode 50 0 -40 High-Resolution Mode Low-Power Mode 0.15 High-Speed Mode 0.10 High-Resolution Mode 0.05 Low-Power Mode Low-Speed Mode 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 -20 0 20 40 60 Temperature (°C) 80 100 120 125 Figure 51. ADS1278 AVDD CURRENT vs TEMPERATURE 140 120 High-Speed and High-Resolution Modes 30 25 High-Speed Mode Figure 52. ADS1278 DVDD CURRENT vs TEMPERATURE 100 80 60 DVDD Current (mA) AVDD Current (mA) 20 High-Resolution Mode 15 10 5 Low-Power Mode Low-Power Mode 40 20 0 -40 Low-Speed Mode -20 0 20 40 60 Temperature (°C) 80 100 120 125 Low-Speed Mode 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 Figure 53. Figure 54. 18 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. ADS1278 IOVDD CURRENT vs TEMPERATURE 0.5 800 700 ADS1278 POWER DISSIPATION vs TEMPERATURE Power Dissipation (mW) 0.4 IOVDD Current (mA) 600 500 400 300 200 100 0 -40 High-Speed Mode 0.3 High-Speed Mode High-Resolution Mode Low-Power Mode 0.2 Low-Power Mode Low-Speed Mode 0.1 High-Resolution Mode 0 -40 Low-Speed Mode -20 0 20 40 60 Temperature (°C) 80 100 120 125 -20 0 20 40 60 Temperature (°C) 80 100 120 125 Figure 55. Figure 56. Copyright © 2007, Texas Instruments Incorporated 19 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com OVERVIEW The ADS1274 (quad) and ADS1278 (octal) are 24-bit, delta-sigma ADCs based on the single-channel ADS1271. They offer the combination of outstanding dc accuracy and superior ac performance. Figure 57 shows the block diagram. Note that both devices are functionally the same, except that the ADS1274 has four ADCs and the ADS1278 has eight ADCs. The packages are identical, and the ADS1274 pinout is compatible with the ADS1278, permitting true drop-in expandability. The converters are comprised of four (ADS1274) or eight (ADS1278) advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear phase FIR filters. The modulators measure the differential input signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The digital filters receive the modulator signal and provide a low-noise digital output. To allow tradeoffs among speed, resolution, and power, four operating modes are supported: High-Speed, High-Resolution, Low-Power, and Low-Speed. Table 1 summarizes the performance of each mode. In High-Speed mode, the maximum data rate is 128kSPS (when operating at 128kSPS, Frame-Sync format must be used). In High-Resolution mode, the SNR = 111dB (VREF = 3.0V); in Low-Power mode, the power dissipation is 31mW/channel; and in Low-Speed mode, the power dissipation is only 7mW/channel at 10.5kSPS. The digital filters can be bypassed, enabling direct access to the modulator output. The ADS1274/78 is configured by simply setting the appropriate I/O pins—there are no registers to program. Data are retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1274/78 has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in systems requiring more than eight channels. IOVDD Mod 1 Mod 2 VREF AVDD R VCOM R VREFP VREFN DVDD S Modulator Output Mod 8 AINP1 AINN1 S VIN1 DS Modulator1 Digital Filter1 SPI and Frame-Sync Interface DRDY/FSYNC SCLK DOUT[4:1]/[8:1](1) DIN AINP2 AINN2 S VIN2 DS Modulator2 Digital Filter2 TEST[1:0] FORMAT[2:0] CLK Control Logic SYNC PWDN[4:1]/[8:1](1) CLKDIV MODE[1:0] DGND AINP4/8(1) AINN4/8(1) S VIN4/8 DS Modulator4/8(1) Digital Filter4/8(1) AGND NOTE: (1) The ADS1274 has four channels; the ADS1278 has eight channels. Figure 57. ADS1274/ADS1278 Block Diagram Table 1. Operating Mode Performance Summary MODE High-Speed High-Resolution Low-Power Low-Speed MAX DATA RATE (SPS) 128,000 52,734 52,734 10,547 PASSBAND (kHz) 57,984 23,889 23,889 4,798 SNR (dB) 106 110 106 107 NOISE(μVRMS) 8.5 5.5 8.5 8.0 POWER/CHANNEL (mW) 70 64 31 7 20 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 FUNCTIONAL DESCRIPTION The ADS1274/78 is a delta-sigma ADC consisting of four/eight independent converters that digitize four/eight input signals in parallel. The converter is composed of two main functional blocks to perform the ADC conversions: the modulator and the digital filter. The modulator samples the input signal together with sampling the reference voltage to produce a 1's density output stream. The density of the output stream is proportional to the analog input level relative to the reference voltage. The pulse stream is filtered by the internal digital filter where the output conversion result is produced. In operation, the input signal is sampled by the modulator at a high rate (typically 64x higher than the final output data rate). The quantization noise of the modulator is moved to a higher frequency range where the internal digital filter removes it. Oversampling results in very low levels of noise within the signal passband. Since the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal frequency is at the modulator sampling rate. This architecture greatly relaxes the requirement of external antialiasing filters because of the high modulator sampling rate. controlled. Furthermore, the digital filters are synchronized to start the convolution phase at the same modulator clock cycle. This design results in excellent phase match among the ADS1274/78 channels. Figure 35 shows the inter-device channel sample matching for the ADS1274 and ADS1278. The phase match of one 4-channel ADS1274 to that of another ADS1274 (eight or more channels total) may not have the same degree of sampling match. As a result of manufacturing variations, differences in internal propagation delay of the internal CLK signal coupled with differences of the arrival of the external CLK signal to each device may cause larger sampling match errors. Equal length CLK traces or external clock distribution devices can be used to reduce the sampling match error between devices. FREQUENCY RESPONSE The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stop band attenuation. The filter coefficients are identical to the coefficients used in the ADS1271. The oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate, or fMOD/fDATA) is a function of the selected mode, as shown in Table 2. Table 2. Oversampling Ratio versus Mode MODE SELECTION High-Speed High-Resolution Low-Power Low-Speed OVERSAMPLING RATIO (fMOD/fDATA) 64 128 64 64 SAMPLING APERTURE MATCHING The ADS1274/78 converters operate from the same CLK input. The CLK input controls the timing of the modulator sampling instant. The converter is designed such that the sampling skew, or modulator sampling aperture match between channels, is Copyright © 2007, Texas Instruments Incorporated 21 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com High-Speed, Low-Power, and Low-Speed Modes The digital filter configuration is the same in High-Speed, Low-Power, and Low-Speed modes with the oversampling ratio set to 64. Figure 58 shows the frequency response in High-Speed, Low-Power, and Low-Speed modes normalized to fDATA. Figure 59 shows the passband ripple. The transition from passband to stop band is shown in Figure 60. The overall frequency response repeats at 64x multiples of the modulator frequency fMOD, as shown in Figure 61. 0 -20 0 -1 -2 Amplitude (dB) -3 -4 -5 -6 -7 -8 -9 -10 0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/fDATA) Amplitude (dB) -40 -60 -80 -100 -120 Figure 60. Transition Band Response for High-Speed, Low-Power, and Low-Speed Modes 20 0 -20 -40 Gain (dB) -140 0 0.2 0.4 0.6 0.8 1.0 Normalized Input Frequency (fIN/fDATA) -60 -80 -100 Figure 58. Frequency Response for High-Speed, Low-Power, and Low-Speed Modes 0.02 0 -120 -140 -160 0 16 32 Input Frequency (fIN/fDATA) 48 64 Amplitude (dB) -0.02 -0.04 -0.06 -0.08 -0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA) Figure 61. Frequency Response Out to fMOD for High-Speed, Low-Power, and Low-Speed Modes These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. The stop band of the ADS1274/78 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1274/78 inputs is recommended to limit possible high-amplitude, out-of-band signals and noise. Often, a simple RC filter is sufficient. Table 3 lists the image rejection versus external filter order. Table 3. Antialiasing Filter Order Image Rejection ANTIALIASING FILTER ORDER 1 2 3 IMAGE REJECTION (dB) (f–3dB at fDATA) HS, LP, LS 39 75 111 HR 45 87 129 Figure 59. Passband Response for High-Speed, Low-Power, and Low-Speed Modes 22 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 0 -1 -2 High-Resolution Mode The oversampling ratio is 128 in High-Resolution mode. Figure 62 shows the frequency response in High-Resolution mode normalized to fDATA. Figure 63 shows the passband ripple, and the transition from passband to stop band is shown in Figure 64. The overall frequency response repeats at multiples of the modulator frequency fMOD (128 × fDATA), as shown in Figure 65. The stop band of the ADS1274/78 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1274/78 inputs is recommended to limit possible high-amplitude out-of-band signals and noise. Often, a simple RC filter is sufficient. Table 3 lists the image rejection versus external filter order. 0 -20 Amplitude (dB) -3 -4 -5 -6 -7 -8 -9 -10 0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/fDATA) Figure 64. Transition Band Response for High-Resolution mode 20 0 -20 -40 Amplitude (dB) -40 -60 -80 -100 -120 -140 0 0.25 0.50 0.75 1 Normalized Input Frequency (fIN/fDATA) Gain (dB) -60 -80 -100 -120 -140 -160 0 32 64 96 128 Normalized Input Frequency (fIN/fDATA) Figure 62. Frequency Response for High-Resolution Mode 0.02 0 Figure 65. Frequency Response Out to fMOD for High-Resolution Mode Amplitude (dB) -0.02 -0.04 -0.06 -0.08 -0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA) Figure 63. Passband Response for High-Resolution Mode Copyright © 2007, Texas Instruments Incorporated 23 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com PHASE RESPONSE The ADS1274/78 incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (constant group delay). This characteristic means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals. Table 4. Ideal Output Code versus Input Signal INPUT SIGNAL VIN (AINP – AINN) ≥ +VREF IDEAL OUTPUT CODE(1) 7FFFFFh 000001h 000000h FFFFFFh 800000h ) VREF 2 23 * 1 0 * VREF 2 23 * 1 v −VREF 223 2 23 * 1 SETTLING TIME As with frequency and phase response, the digital filter also determines settling time. Figure 66 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X-axis is given in units of conversion. Note that after the step change on the input occurs, the output data change very little prior to 30 conversion periods. The output data are fully settled after 76 conversion periods for High-Speed and Low-Power modes, and 78 conversion periods for High-Resolution mode. (1) Excludes effects of noise, INL, offset, and gain errors. ANALOG INPUTS (AINP, AINN) The ADS1274/78 measures each differential input signal VIN = (AINP – AINN) against the common differential reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF, which produces the most positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is –VREF, which produces the most negative digital output code of 800000h. For optimum performance, the inputs of the ADS1274/78 are intended to be driven differentially. For single-ended applications, one of the inputs (AINP or AINN) can be driven while the other input is fixed (typically to AGND or +2.5V). Fixing the input to 2.5V permits bipolar operation, thereby allowing full use of the entire converter range. While the ADS1274/78 measures the differential input signal, the absolute input voltage is also important. This value is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: –0.1V < (AINN or AINP) < AVDD + 0.1V If either input is taken below –0.4V or above (AVDD + 0.4), ESD protection diodes on the inputs may turn on. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). The ADS1274/78 is a very high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1274/78 inputs. See the Application Information section for several recommended circuits. Final Value 100 Settling (%) Fully Settled Data at 76 Conversions (78 Conversions for High-Resolution mode) Initial Value 0 0 10 20 30 40 50 60 70 80 Conversions (1/fDATA) Figure 66. Step Response DATA FORMAT The ADS1274/78 outputs 24 bits of data in two’s complement format. A positive full-scale input produces an ideal output code of 7FFFFFh, and the negative full-scale input produces an ideal output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 4 summarizes the ideal output codes for different input signals. 24 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 The ADS1274/78 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged. Figure 67 shows a conceptual diagram of these circuits. Switch S2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 68. The sampling time (tSAMPLE) is the inverse of modulator sampling frequency (fMOD) and is a function of the mode, the CLKDIV input, and CLK frequency, as shown in Table 5. AINP Zeff = 14kW ´ (6.75MHz/fMOD) AINN Figure 69. Effective Input Impedances AVDD AGND VOLTAGE REFERENCE INPUTS (VREFP, VREFN) S1 S2 AINP 9pF AINN S1 AGND AVDD ESD Protection Figure 67. Equivalent Analog Input Circuitry tSAMPLE = 1/fMOD The voltage reference for the ADS1274/78 ADC is the differential voltage between VREFP and VREFN: VREF = (VREFP – VREFN). The voltage reference is common to all channels. The reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 70. As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in Figure 71. However, the reference input impedance depends on the number of active (enabled) channels in addition to fMOD. As a result of the change of reference input impedance caused by enabling and disabling channels, the regulation and setting time of the external reference should be noted, so as not to affect the readings. VREFP VREFN S1 S2 ON OFF ON OFF AVDD AGND AGND AVDD ESD Protection Figure 68. S1 and S2 Switch Timing for Figure 67 Table 5. Modulator Frequency (fMOD) Mode Selection MODE SELECTION High-Speed High-Resolution Low-Power Low-Speed CLKDIV 1 1 1 0 1 0 fMOD fCLK/4 fCLK/4 fCLK/8 fCLK/4 fCLK/40 fCLK/8 VREFP VREFN Figure 70. Equivalent Reference Input Circuitry The average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in Figure 69. Note that the effective impedance is a function of fMOD. Zeff = 5.2kW ´ (6.75MHz/fMOD) N N = number of active channels. Figure 71. Effective Reference Impedance Copyright © 2007, Texas Instruments Incorporated 25 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.4V, and likewise do not exceed AVDD by 0.4V. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Note that the valid operating range of the reference inputs is limited to the following parameters: –0.1V ≤ VREFN ≤ +0.1V VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V A high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ADS1274. Noise and drift on the reference degrade overall system performance. See the Application Information section for example reference circuits. Table 6. Clock Input Options MODE SELECTION High-Speed High-Resolution Low-Power MAX fCLK (MHz) 32.768 27 27 13.5 27 5.4 CLKDIV 1 1 1 0 1 0 fCLK/fDATA 256 512 512 256 2,560 512 DATA RATE (SPS) 128,000 52,734 52,734 Low-Speed 10,547 MODE SELECTION (MODE) The ADS1274/78 supports four modes of operation: High-Speed, High-Resolution, Low-Power, and Low-Speed. The modes offer optimization of speed, resolution, and power. Mode selection is determined by the status of the digital input MODE[1:0] pins, as shown in Table 7. The ADS1274/78 continually monitors the status of the MODE pin during operation. Table 7. Mode Selection MODE[1:0] 00 01 10 11 MODE SELECTION High-Speed High-Resolution Low-Power Low-Speed MAX fDATA(1) 128,000 52,734 52,734 10,547 CLOCK INPUT (CLK) The ADS1274/78 requires a clock input for operation. The individual converters of the ADS1274/78 operate from the same clock input. At the maximum data rate, the clock input can be either 27MHz or 13.5MHz for Low-Power mode, or 27MHz or 5.4MHz for Low-Speed mode, determined by the setting of the CLKDIV input. For High-Speed mode, the maximum CLK input frequency is 32.768MHz. For High-Resolution mode, the maximum CLK input frequency is 27MHz. The selection of the external clock frequency (fCLK) does not affect the resolution of the ADS1274/78. Use of a slower fCLK can reduce the power consumption of an external clock buffer. The output data rate scales with clock frequency, down to a minimum clock frequency of fCLK = 100kHz. Table 6 summarizes the ratio of the clock input frequency (fCLK) to data rate (fDATA), maximum data rate and corresponding maximum clock input for the four operating modes. As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible, and using a 50Ω series resistor placed close to the source end, often helps. (1) fCLK = 27MHz max (32.768MHz max in High-Speed mode). When using the SPI protocol, DRDY is held high after a mode change occurs until settled (or valid) data are ready; see Figure 72 and Table 8. In Frame-Sync protocol, the DOUT pins are held low after a mode change occurs until settled data are ready; see Figure 72 and Table 8. Data can be read from the device to detect when DOUT changes to logic 1, indicating that the data are valid. 26 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 MODE[1:0] Pins ADS1274/78 Mode Previous Mode New Mode tNDR-SPI SPI Protocol DRDY New Mode Valid Data Ready tNDR-FS Frame-Sync DOUT Protocol New Mode Valid Data on DOUT Figure 72. Mode Change Timing Table 8. New Data After Mode Change SYMBOL tNDR-SPI tNDR-FS DESCRIPTION Time for new data to be ready (SPI) Time for new data to be ready (Frame-Sync) 127 MIN TYP MAX 129 128 UNITS Conversions (1/fDATA) Conversions (1/fDATA) SYNCHRONIZATION (SYNC) The ADS1274/78 can be synchronized by pulsing the SYNC pin low and then returning the pin high. When the pin goes low, the conversion process stops, and the internal counters used by the digital filter are reset. When the SYNC pin returns high, the conversion process restarts. Synchronization allows the conversion to be aligned with an external event, such as the changing of an external multiplexer on the analog inputs, or by a reference timing pulse. Because the ADS1274/78 converters operate in parallel from the same master clock and use the same SYNC input control, they are always in synchronization with each other. The aperture match among internal channels is typically less than 500ps. However, the synchronization of multiple devices is somewhat different. At device power-on, variations in internal reset thresholds from device to device may result in uncertainty in conversion timing. The SYNC pin can be used to synchronize multiple devices to within the same CLK cycle. Figure 73 illustrates the timing requirement of SYNC and CLK in SPI format. See Figure 74 for the Frame-Sync format timing requirement. After synchronization, indication of valid data depends on whether SPI or Frame-Sync format was used. In the SPI format, DRDY goes high as soon as SYNC is taken low; see Figure 73. After SYNC is returned high, DRDY stays high while the digital filter is settling. Once valid data are ready for retrieval, DRDY goes low. In the Frame-Sync format, DOUT goes low as soon as SYNC is taken low; see Figure 74. After SYNC is returned high, DOUT stays low while the digital filter is settling. Once valid data are ready for retrieval, DOUT begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking SYNC high, and must then remain running. If the clock inputs (CLK, FSYNC or SCLK) are subsequently interrupted or reset, re-assert the SYNC pin. For consistent performance, re-assert SYNC after device power-on when data first appear. Copyright © 2007, Texas Instruments Incorporated 27 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com tCSHD CLK tSCSU SYNC tSYN tNDR DRDY Figure 73. Synchronization Timing (SPI Protocol) Table 9. SPI Protocol SYMBOL tCSHD tSCSU tSYN tNDR DESCRIPTION CLK to SYNC hold time SYNC to CLK setup time Synchronize pulse width Time for new data to be ready tCSHD CLK tSCSU SYNC tSYN MIN 10 5 1 TYP MAX UNITS ns ns CLK periods 129 Conversions (1/fDATA) FSYNC tNDR DOUT Valid Data Figure 74. Synchronization Timing (Frame-Sync Protocol) Table 10. Frame-Sync Protocol SYMBOL tCSHD tSCSU tSYN tNDR DESCRIPTION CLK to SYNC hold time SYNC to CLK setup time Synchronize pulse width Time for new data to be ready MIN 10 5 1 127 128 TYP MAX UNITS ns ns CLK periods Conversions (1/fDATA) 28 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 POWER-DOWN (PWDN) The channels of the ADS1274/78 can be independently powered down by use of the PWDN inputs. To enter the power-down mode, hold the respective PWDN pin low for at least two CLK cycles. To exit power-down, return the corresponding PWDN pin high. Note that when all channels are powered down, the ADS1274/78 enters a microwatt (μW) power state where all internal biasing is disabled. In this state, the TEST[1:0] input pins must be driven; all other input pins can float. The ADS1274/78 outputs remain driven. As shown in Figure 75 and Table 11, a maximum of 130 conversion cycles must elapse for SPI interface, and 129 conversion cycles must elapse for Frame-Sync, before reading data after exiting power-down. Data from channels already running are not affected. The user software can perform the required delay time in any of the following ways: 1. Count the number of data conversions after taking the PWDN pin high. 2. Delay 129/fDATA or 130/fDATA after taking the PWDN pins high, then read data. 3. Detect for non-zero data in the powered-up channel. After powering up one or more channels, the channels are synchronized to each other. It is not necessary to use the SYNC pin to synchronize them. When a channel is powered down in TDM data format, the data for that channel are either forced to zero (fixed-position TDM data mode) or replaced by shifting the data from the next channel into the vacated data position (dynamic-position TDM data mode). In Discrete data format, the data are always forced to zero. When powering-up a channel in dynamic-position TDM data format mode, the channel data remain packed until the data are ready, at which time the data frame is expanded to include the just-powered channel data. See the Data Format section for details. CLK PWDN (1) ··· tPWDN ··· tNDR DRDY/FSYNC DOUT (Discrete Data Output Mode) DOUT1 (TDM Mode, Dynamic Position) DOUT1 (TDM Mode, Fixed Position) Post Power-Up Data Normal Position Data Shifts Position Normal Position Normal Position Data Remains in Position Normal Position NOTE: (1) In SPI protocol, the timing occurs on the falling edge of DRDY/FSYNC. Powering down all channels forces DRDY/FSYNC high. Figure 75. Power-Down Timing Table 11. Power-Down Timing SYMBOL tPWDN tNDR tNDR DESCRIPTION PWDN pulse width to enter Power-Down mode Time for new data ready (SPI) Time for new data ready (Frame-Sync) MIN 2 129 128 130 129 TYP MAX UNITS CLK periods Conversions (1/fDATA) Conversions (1/fDATA) Copyright © 2007, Texas Instruments Incorporated 29 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com FORMAT[2:0] Data can be read from the ADS1274/78 with two interface protocols (SPI or Frame-Sync) and several options of data formats (TDM/Discrete and Fixed/Dynamic data positions). The FORMAT[2:0] inputs are used to select among the options. Table 12 lists the available options. See the DOUT Modes section for details of the DOUT Mode and Data Position. Table 12. Data Output Format FORMAT[2:0] 000 001 010 011 100 101 110 INTERFACE PROTOCOL SPI SPI SPI Frame-Sync Frame-Sync Frame-Sync Modulator Mode DOUT MODE TDM TDM Discrete TDM TDM Discrete — DATA POSITION Dynamic Fixed — Dynamic Fixed — — Even though the SCLK input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation between conversions. Note that one fCLK is required after the falling edge of DRDY until the first rising edge of SCLK. For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section). DRDY/FSYNC (SPI Format) In the SPI format, this pin functions as the DRDY output. It goes low when data are ready for retrieval and then returns high on the falling edge of the first subsequent SCLK. If data are not retrieved (that is, SCLK is held low), DRDY pulses high just before the next conversion data are ready, as shown in Figure 76. The new data are loaded within one CLK cycle before DRDY goes low. All data must be shifted out before this time to avoid being overwritten. 1/fDATA DRDY 1/fCLK SERIAL INTERFACE PROTOCOLS Data are retrieved from the ADS1274/78 using the serial interface. Two protocols are available: SPI and Frame-Sync. The same pins are used for both interfaces: SCLK, DRDY/FSYNC, DOUT[4:1] (DOUT[8:1] for ADS1278), and DIN. The FORMAT[2:0] pins select the desired interface protocol. SCLK Figure 76. DRDY Timing with No Readback DOUT The conversion data are output on DOUT[4:1]/[8:1]. The MSB data are valid on DOUT[4:1]/[8:1] after DRDY goes low. Subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN appear on DOUT after all channel data have been shifted out. When the device is configured for modulator output, DOUT[4:1]/[8:1] becomes the modulator data output for each channel (see the Modulator Output section). DIN This input is used when multiple ADS1274/78s are to be daisy-chained together. The DOUT1 pin of the first device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1274/78, tie DIN low. See the Daisy-Chaining section for more information. SPI SERIAL INTERFACE The SPI-compatible format is a read-only interface. Data ready for retrieval are indicated by the falling DRDY output and are shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the DIN input when using multiple devices. See the Daisy-Chaining section for more information. NOTE: The SPI format is limited to a CLK input frequency of 27MHz, maximum. For CLK input operation above 27MHz (High-Speed mode only), use Frame-Sync format. SCLK The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user normally shifts this data in on the rising edge. 30 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 FRAME-SYNC SERIAL INTERFACE Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data are output MSB first or left-justified on the rising edge of FSYNC. When using Frame-Sync format, the FSYNC and SCLK inputs must be continuously running with the relationships shown in the Frame-Sync Timing Requirements. SCLK The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data readback will be corrupted. The number of SCLKs within a frame period (FSYNC clock) can be any power-of-2 ratio of CLK cycles (1, 1/2, 1/4, etc), as long as the number of cycles is sufficient to shift the data output from all channels within one frame. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section). DRDY/FSYNC (Frame-Sync Format) In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame period, which must be the same as the data rate. The required number of fCLK cycles to each FSYNC period depends on the mode selection and the CLKDIV input. Table 6 indicates the number of CLK cycles to each frame (fCLK/fDATA). If the FSYNC period is not the proper value, data readback will be corrupted. DOUT The conversion data are shifted out on DOUT[4:1]/[8:1]. The MSB data become valid on DOUT[4:1]/[8:1] after FSYNC goes high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN appear on DOUT[4:1]/[8:1] after all channel data have been shifted out. When the device is configured for modulator output, DOUT becomes the modulator data output (see the Modulator Output section). DIN This input is used when multiple ADS1274/78s are to be daisy-chained together. It can be used with either SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1274/78, tie DIN low. See the Daisy-Chaining section for more information. DOUT MODES For both SPI and Frame-Sync interface protocols, the data are shifted out either through individual channel DOUT pins, in a parallel data format (Discrete mode), or the data for all channels are shifted out, in a serial format, through a common pin, DOUT1 (TDM mode). TDM Mode In TDM (time-division multiplexed) data output mode, the data for all channels are shifted out, in sequence, on a single pin (DOUT1). As shown in Figure 77, the data from channel 1 are shifted out first, followed by channel 2 data, etc. After the data from the last channel are shifted out, the data from the DIN input follow. The DIN is used to daisy-chain the data output from an additional ADS1274/78 or other compatible device. Note that when all channels of the ADS1274/78 are disabled, the interface is disabled, rendering the DIN input disabled as well. When one or more channels of the device are powered down, the data format of the TDM mode can be fixed or dynamic. SCLK DOUT1 (ADS1274) DOUT1 (ADS1278) DRDY (SPI) FSYNC (Frame-Sync) 1 2 23 24 25 47 48 49 71 72 73 95 96 97 167 168 169 191 192 193 194 195 CH1 CH2 CH3 CH4 DIN CH1 CH2 CH3 CH4 CH5 CH7 CH8 DIN Figure 77. TDM Mode (All Channels Enabled) Copyright © 2007, Texas Instruments Incorporated 31 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com TDM Mode, Fixed-Position Data In this TDM data output mode, the data position of the channels remain fixed, regardless of whether the channels are powered down. If a channel is powered down, the data are forced to zero but occupy the same position within the data stream. Figure 78 shows the data stream with channel 1 and channel 3 powered down. TDM Mode, Dynamic Position Data In this TDM data output mode, when a channel is powered down, the data from higher channels shift one position in the data stream to fill the vacated data slot. Figure 79 shows the data stream with channel 1 and channel 3 powered down. Discrete Data Output Mode In Discrete data output mode, the channel data are shifted out in parallel using individual channel data output pins DOUT[4:1]/[8:1]. After the 24th SCLK, the channel data are forced to zero. The data are also forced to zero for powered down channels. Figure 80 shows the discrete data output format. SCLK DOUT1 (ADS1274) DOUT1 (ADS1278) DRDY (SPI) FSYNC (Frame-Sync) 1 2 23 24 25 47 48 49 71 72 73 95 96 97 167 168 169 191 192 193 194 195 CH1 CH2 CH3 CH4 DIN CH1 CH2 CH3 CH4 CH5 CH7 CH8 DIN Figure 78. TDM Mode, Fixed-Position Data (Channels 1 and 3 Shown Powered Down) SCLK DOUT1 (ADS1274) DOUT1 (ADS1278) DRDY (SPI) FSYNC (Frame- Sync) 1 2 23 24 25 47 48 49 50 119 120 121 143 144 145 145 146 CH2 CH2 CH4 CH4 DIN CH5 CH7 CH8 DIN Figure 79. TDM Mode, Dynamic Position Data (Channels 1 and 3 Shown Powered Down) 32 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 SCLK DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 ADS1278 Only DOUT7 DOUT8 DRDY (SPI) FSYNC (Frame-Sync) 1 2 22 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 23 24 25 26 Figure 80. Discrete Data Output Mode DAISY-CHAINING Multiple ADS1274/78s can be daisy-chained together to output data on a single pin. The DOUT1 data output pin of one device is connected to the DIN of the next device. As shown in Figure 81, the DOUT1 pin of device 1 provides the output data to a controller, and the DIN of device 2 is grounded. Figure 82 shows the data format when reading back data. The maximum number of channels that may be daisy-chained in this way is limited by the frequency of fSCLK, the mode selection, and the CLKDIV input. The frequency of fSCLK must be high enough to completely shift the data out from all channels within one fDATA period. Table 13 lists the maximum number of daisy-chained channels when fSCLK = fCLK. To increase the number of data channels possible in a chain, a segmented DOUT scheme may be used, producing two data streams. Figure 83 illustrates four ADS1274/78s, with pairs of ADS1274/78s daisy-chained together. The channel data of each daisy-chained pair are shifted out in parallel and received by the processor through independent data channels. Table 13. Maximum Channels in a Daisy-Chain (fSCLK = fCLK) MODE SELECTION High-Speed High-Resolution Low-Power Low-Speed CLKDIV 1 1 1 0 1 0 MAXIMUM NUMBER OF CHANNELS 10 21 21 10 106 21 Whether the interface protocol is SPI or Frame-Sync, it is recommended to synchronize all devices by tying the SYNC inputs together. When synchronized in SPI protocol, it is only necessary to monitor the DRDY output of one ADS1274/78. In Frame-Sync interface protocol, the data from all devices are ready after the rising edge of FSYNC. Since DOUT1 and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT1 creates a setup time on DIN. Minimize the skew in SCLK to avoid timing violations. Copyright © 2007, Texas Instruments Incorporated 33 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com SYNC CLK ADS1274/78 U2 SYNC CLK DIN DOUT1 ADS1274/78 U1 SYNC CLK DIN DOUT1 DOUT from Devices 1 and 2 DRDY DRDY Output from Device 1 SCLK SCLK SCLK Note: The number of chained devices is limited by the SCLK rate and device mode. Figure 81. Daisy-Chaining of Two Devices, SPI Protocol (FORMAT[2:0] = 011 or 100) SCLK 1 2 25 26 49 50 73 74 97 98 193 194 217 218 385 386 DOUT1 DRDY (SPI) FSYNC (Frame-Sync) CH1, U1 CH2, U1 CH3, U1 CH4, U1 CH5, U1 CH1, U2 CH2, U2 DIN2 Figure 82. Daisy-Chain Data Format of Figure 81 (ADS1278 shown) SYNC CLK Serial Data Devices 3 and 4 ADS1274/78 U4 SYNC CLK DIN FSYNC SCLK DOUT1 ADS1274/78 U3 SYNC CLK DIN FSYNC SCLK DOUT1 ADS1274/78 U2 SYNC CLK DIN FSYNC SCLK DOUT1 ADS1274/78 U1 SYNC CLK DIN FSYNC SCLK DOUT1 Serial Data Devices 1 and 2 SCLK FSYNC Note: The number of chained devices is limited by the SCLK rate and device mode. Figure 83. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 000 or 001) 34 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 POWER-UP SEQUENCE The ADS1274/78 has three power supplies: AVDD, DVDD, and IOVDD. AVDD is the analog supply that powers the modulator, DVDD is the digital supply that powers the digital core, and IOVDD is the digital I/O power supply. The IOVDD and DVDD power supplies can be tied together if desired (+1.8V). To achieve rated performance, it is critical that the power supplies are bypassed with 0.1μF and 10μF capacitors placed as close as possible to the supply pins. A single 10μF ceramic capacitor may be substituted in place of the two capacitors. Figure 84 shows the power-up sequence of the ADS1274/78. The power supplies can be sequenced in any order. Each supply has an internal reset circuit whose outputs are summed together to generate a global power-on reset. After the supplies have exceeded the reset thresholds, 218 fCLK cycles are counted before the converter initiates the conversion process. Following the CLK cycles, the data for 129 conversions are suppressed by the ADS1274/78 to allow output of fully-settled data. In SPI protocol, DRDY is held high during this interval. In frame-sync protocol, DOUT is forced to zero. The power supplies should be applied before any analog or digital pin is driven. For consistent performance, assert SYNC after device power-on when data first appear. AVDD DVDD IODVDD Internal Reset CLK 2 fCLK DRDY (SPI Protocol) DOUT (Frame-Sync Protocol) Valid Data (1) The power-supply reset thresholds are approximate. 18 output, tie FORMAT[2:0], as shown in Figure 85. DOUT[4:1]/[8:1] then becomes the modulator data stream outputs for each channel and SCLK becomes the modulator clock output. The DRDY/FSYNC pin becomes an unused output and can be ignored. The normal operation of the Frame-Sync and SPI interfaces is disabled, and the functionality of SCLK changes from an input to an output, as shown in Figure 85. Table 14. Modulator Output Clock Frequencies MODULATOR CLOCK OUTPUT (SCLK) fCLK/4 fCLK/4 fCLK/8 fCLK/4 fCLK/40 fCLK/8 ADS1274 DVDD (mA) 4.5 4.0 2.5 2.5 1.0 0.5 ADS1278 DVDD (mA) 8 7 4 4 1 1 MODE [1:0] 00 01 10 11 CLKDIV 1 1 1 0 1 0 DOUT1 DOUT2 IOVDD DIN FORMAT0 Modulator Data Channel 1 Modulator Data Channel 2 3.0V nom 1V nom 1V nom (1) FORMAT1 DOUT4/8(1) FORMAT2 SCLK Modulator Data Channel 4/8(1) Modulator Clock Output (1) (1) NOTE: (1) ADS1274 has four channels; ADS1278 has eight channels. Figure 85. Modulator Output 129 (max) tDATA In modulator output mode, the frequency of the modulator clock output (SCLK) depends on the mode selection of the ADS1274/78. Table 14 lists the modulator clock output frequency and DVDD current versus device mode. Figure 86 shows the timing relationship of the modulator clock and data outputs. The data output is a modulated 1's density data stream. When VIN = +VREF, the 1's density is approximately 80% and when VIN = –VREF, the 1's density is approximately 20%. Modulator Clock Output Modulator Data Output SCLK Figure 84. Power-Up Sequence MODULATOR OUTPUT The ADS1274/78 incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage digital filter that yields the conversion results. The data stream output of the modulator is available directly, bypassing the internal digital filter. The digital filter is disabled, reducing the DVDD current, as shown in Table 14. In this mode, an external digital filter implemented in an ASIC, FPGA, or similar device is required. To invoke the modulator Copyright © 2007, Texas Instruments Incorporated DOUT (13ns max) Figure 86. Modulator Output Timing 35 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com BOUNDARY SCAN TEST[1:0] INPUTS The Boundary Scan test mode feature of the ADS1274/78 allows continuity testing of the digital I/O pins. In this mode, the normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as shown in Table 15. Note that some of the digital input pins become outputs. Therefore, if using boundary scan tests, the ADS1274/78 digital I/O should connect to a JTAG-compatible device. The analog input, power supply, and ground pins remain connected as normal. The test mode is engaged by the setting the pins TEST[1:0] = 11. For normal converter operation, set TEST[1:0] = 00. Do not use '01' or '10'. Table 15. Test Mode Pin Map (TEST[1:0] = 11) TEST MODE PIN MAP INPUT PINS PWDN1 PWDN2 PWDN3 PWDN4 PWDN5 PWDN6 PWDN7 PWDN8 MODE0 MODE1 FORMAT0 FORMAT1 FORMAT2 OUTPUT PINS DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DIN SYNC CLKDIV FSYNC/DRDY SCLK VCOM OUTPUT The VCOM pin provides a voltage output equal to AVDD/2. The intended use of this output is to set the output common-mode level of the analog input drivers. The drive capability of the output is limited; therefore, the output should only be used to drive high-impedance nodes (> 1MΩ). In some cases, an external buffer may be necessary. A 0.1μF bypass capacitor is recommended to reduce noise pickup. ADS1274/78 OPA350 VCOM » (AVDD/2) 0.1mF Figure 87. VCOM Output 36 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 APPLICATION INFORMATION To obtain the specified performance from the ADS1274, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The allowed range for DVDD is 1.65V to 1.95V; the range of IOVDD is 1.65V to 3.6V; AVDD is restricted to 4.75V to 5.25V. For all supplies, use a 10μF tantalum capacitor, bypassed with a 0.1μF ceramic capacitor, placed close to the device pins. Alternatively, a single 10μF ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power-supply source is used, the voltage ripple should be low (< 2mV) and the switching frequency outside the passband of the converter. The power supplies may be sequenced in any order. 2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter. 3. Digital Inputs: It is recommended to source-terminate the digital inputs to the device with 50Ω series resistors. The resistors should be placed close to the driving end of digital source (oscillator, logic gates, DSP, etc.) This placement helps to reduce ringing on the digital lines (ringing may lead to degraded ADC performance). 4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk. 5. Reference Inputs: It is recommended to use a minimum 10μF tantalum with a 0.1μF ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3μVRMS in-band noise. For references with noise higher than this level, external reference filtering may be necessary. 6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (ac applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. A 1nF to 10nF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground can be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the ac common-mode performance. 7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This layout is particularly important for small-value ceramic capacitors. Larger (bulk) decoupling capacitors can be located farther from the device than the smaller ceramic capacitors. Figure 88 to Figure 90 illustrate basic connections and interfaces that can be used with the ADS1274. Copyright © 2007, Texas Instruments Incorporated 37 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com OPA1632 (1) ADS1274 AINP1 IOVDD +3.3V (2) TMS320VC5509 DVDD (I/O) IN1 2.2nF (3) AINN1 10mF 50W AINP2 IN2 2.2nF (3) CLK DRDY/FSYNC SCLK 50W 50W 50W CLKOUT (27MHz) AINN2 McBSP PORT AINP3 IN3 2.2nF (3) DOUT1 DOUT2 DOUT3 CVDD (CORE) +1.6V AINN3 200MHz AINP4 IN4 +5V 2.2nF + (3) DOUT4 SYNC PWDN1 PWDN2 PWDN3 PWDN4 I/O AINN4 AVDD 10mF (2) +1.8V 1kW 10mF (2) DVDD 20kW See Note (5) 100W + 0.1mF (2) 0.1mF 100W OPA350 + 10mF 0.1mF (2) 1kW REF1004 100mF VREFP VREFN VCOM CLKDIV +3.3V (27MHz clock input selected) 0.1mF Buffered VCOM Output 100W OPA350 (2) JTAG (4) Device TEST0 TEST1 DIN AGND DGND MODE1 MODE0 FORMAT2 FORMAT1 FORMAT0 (High-Speed, Frame-Sync, TDM, and Fixed-Position data selected.) +3.3V NOTES: (1) External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs. See Analog Inputs section. (2) Indicates ceramic capacitors. (3) Indicates COG ceramic capacitors. (4) Optional. For boundary scan test, the ADS1274 digital I/O should connect to a JTAG-compatible device (5) The op amp and input RC components filter the REF1004 noise. Figure 88. ADS1274 Basic Connection Drawing 1kW 1.5nF (2) 1kW 1kW VIN 5.6nF Buffered VCOM Output AINP (2) 249W Buffered VCOM Output VIN VOCM 0.1mF +12V (1) +12V (1) 49.9W OPA1632 49.9W VOCM AINP OPA1632 49.9W AINN -12V (1) (2) 49.9W AINN 0.1mF -12V (1) (2) 1.5nF 5.6nF VO DIFF = 0.25 ´ VIN VO COMM = VREF 1kW 1kW 1kW 249W NOTES: (1) Bypass with 10mF and 0.1mF capacitors. (2) 2.7nF for Low-Power mode; 15nF for Low-Speed mode. NOTES: (1) Bypass with 10mF and 0.1mF capacitors. (2) 10nF for Low-Power mode; 56nF for Low-Speed mode. Figure 89. Basic Differential Input Signal Interface Figure 90. Basic Single-Ended Input Signal Interface Copyright © 2007, Texas Instruments Incorporated 38 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 PowerPAD THERMALLY-ENHANCED PACKAGING The PowerPAD concept is implemented in standard epoxy resin package material. The integrated circuit is attached to the leadframe die pad using thermally conductive epoxy. The package is molded so that the leadframe die pad is exposed at a surface of the package. This design provides an extremely low thermal resistance to the path between the IC junction and the exterior case. The external surface of the leadframe die pad is located on the printed circuit board (PCB) side of the package, allowing the IC Die die pad to be attached to the PCB using standard flow soldering techniques. This configuration allows efficient attachment to the PCB and permits the board structure to be used as a heatsink for the package. Using a thermal pad identical in size to the die pad and vias connected to the PCB ground plane, the board designer can now implement power packaging without additional thermal hardware (for example, external heatsinks) or the need for specialized assembly instructions. Figure 91 illustrates a cross-section view of a PowerPAD package. Mold Compound (Epoxy) Wire Bond Wire Bond Leadframe Die Pad Exposed at Base of Package Die Attach Epoxy (thermally conductive) Leadframe Figure 91. Cross-Section View of a PowerPAD Thermally-Enhanced Package Copyright © 2007, Texas Instruments Incorporated 39 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 ADS1274 ADS1278 SBAS367 – JUNE 2007 www.ti.com PowerPAD PCB Layout Considerations Figure 92 shows the recommended layer structure for thermal management when using a PowerPad package on a 4-layer PCB design. Note that the thermal pad is placed on both the top and bottom sides of the board. The ground plane is used as the heatsink, while the power plane is thermally isolated from the thermal vias. Figure 93 shows the required thermal pad etch pattern for the HTQFP-64 package used for the ADS1274. Nine 13mil (0.33mm) thermal vias plated with 1 ounce of copper are placed within the thermal pad area for the purpose of connecting the pad to the ground plane layer. The ground plane is used as a heatsink in this application. It is very important that the thermal via diameter be no larger than 13mils in order to avoid solder wicking during the reflow process. Solder wicking results in thermal voids that reduce heat dissipation efficiency and hampers heat flow away from the IC die. The via connections to the thermal pad and internal ground plane should be plated completely around the hole, as opposed to the typical web or spoke thermal relief connection. Plating entirely around the thermal via provides the most efficient thermal connection to the ground plane. Additional PowerPAD Package Information Texas Instruments publishes the PowerPAD Thermally Enhanced Package Application Report (TI literature number SLMA002), available for download at www.ti.com, that provides a more detailed discussion of PowerPAD design and layout considerations. Before attempting a board layout with the ADS1274, it is recommended that the hardware engineer and/or layout designer be familiar with the information contained in this document. Package Thermal Pad Component Traces 13mils (0.33mm) Component (top) Side Thermal Via Ground Plane Power Plane Thermal Isolation (power plane only) Solder (bottom) Side Package Thermal Pad (bottom trace) Figure 92. Recommended PCB Structure for a 4-Layer Board 40 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 Copyright © 2007, Texas Instruments Incorporated ADS1274 ADS1278 www.ti.com SBAS367 – JUNE 2007 118mils (3mm) 40mils (1mm) 40mils (1mm) Package Outline Thermal Pad 40mils (1mm) 40mils (1mm) 118mils (3mm) 316mils (8mm) Thermal Via 13mils (0.33mm) 316mils (8mm) Figure 93. Thermal Pad Etch and Via Pattern for the HTQFP-64 Package Copyright © 2007, Texas Instruments Incorporated 41 Submit Documentation Feedback Product Folder Link(s): ADS1274 ADS1278 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2007 PACKAGING INFORMATION Orderable Device ADS1274IPAPR ADS1274IPAPRG4 ADS1274IPAPT ADS1274IPAPTG4 ADS1278IPAPR ADS1278IPAPRG4 ADS1278IPAPT ADS1278IPAPTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type HTQFP HTQFP HTQFP HTQFP HTQFP HTQFP HTQFP HTQFP Package Drawing PAP PAP PAP PAP PAP PAP PAP PAP Pins Package Eco Plan (2) Qty 64 64 64 64 64 64 64 64 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jun-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jun-2007 Device Package Pins Site Reel Diameter (mm) 330 330 330 330 Reel Width (mm) 24 24 24 24 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 16 16 16 16 W Pin1 (mm) Quadrant 24 24 24 24 NONE NONE NONE NONE ADS1274IPAPR ADS1274IPAPT ADS1278IPAPR ADS1278IPAPT PAP PAP PAP PAP 64 64 64 64 TAI TAI TAI TAI 13.0 13.0 13.0 13.0 13.0 13.0 13.0 13.0 1.4 1.4 1.4 1.4 TAPE AND REEL BOX INFORMATION Device ADS1274IPAPR ADS1274IPAPT ADS1278IPAPR ADS1278IPAPT Package PAP PAP PAP PAP Pins 64 64 64 64 Site TAI TAI TAI TAI Length (mm) 0.0 0.0 346.0 0.0 Width (mm) 0.0 0.0 346.0 0.0 Height (mm) 0.0 0.0 41.0 0.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jun-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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