ADS127L11IPWR

ADS127L11 SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 ADS127L11 400-kSPS, Wide-Bandwidth, 24-Bit, Delta-Sigma ADC 1 Features 3 Description • The ADS127L11 is a 24-bit, delta-sigma (ΔΣ), analogto-digital converter (ADC) with data rates up to 400 kSPS using the wideband filter and up to 1067 kSPS using the low-latency filter. The device offers an excellent combination of ac performance and dc precision with low power consumption (18.6 mW in high-speed mode). • • • • • • Programmable data rate: – Up to 400 kSPS (wideband filter) – Up to 1.067 MSPS (low-latency filter) Selectable digital filter: – Wideband or low-latency AC accuracy with dc precision: – Dynamic range: 111.5 dB (200 kSPS) – THD: –120 dB – INL: 0.9 ppm of FS – Offset drift: 50 nV/°C – Gain drift: 0.6 ppm/°C Power-scalable architecture: – High-speed mode: 400 kSPS, 18.6 mW – Low-speed mode: 50 kSPS, 3.3 mW Input and reference precharge buffers Internal or external clock Functional Safety-Capable – Documentation available to aid functional safety system design 2 Applications • • • • • Test and measurement: – Data acquisition (DAQ) – Shock and vibration instruments – Acoustics and dynamic strain gauges Factory automation and control: – Condition monitoring Aerospace and defense: – SONAR Medical: – Electroencephalogram (EEG) Grid Infrastructure: – Power quality analyzer The device integrates input and reference buffers to reduce signal loading. The low-drift modulator achieves excellent dc precision with low in-band noise for outstanding ac performance. The power-scalable architecture provides two speed modes to optimize data rate, resolution, and power consumption. The digital filter is configurable for wideband or lowlatency operation, allowing wideband ac performance or data throughput for dc signals to be optimized, all in one device. The serial interface features daisy-chain capability to reduce the SPI I/O over an isolation barrier. Input and output data and register settings are validated by a cyclic-redundancy check (CRC) feature to enhance operational reliability. The small 3-mm × 3-mm WQFN and 6.5-mm × 4.4mm TSSOP packages are designed for limited space applications. The device is fully specified for operation over the –40°C to +125°C temperature range. Package Information(1) PART NUMBER ADS127L11 (1) ÷2 Modulator AINN RUK (WQFN, 20) 3.00 mm × 3.00 mm PW (TSSOP, 20) 6.50 mm × 4.40 mm IOVDD ADS127L11
AINP BODY SIZE (NOM) For all available packages, see the orderable addendum at the end of the data sheet. AVDD1 REFP REFN AVDD2 VCM PACKAGE Wideband Filter Low-latency Filter Control Logic DRDY START RESET CS SPI Interface SCLK SDI SDO/DRDY Osc AVSS Mux CLK DGND Simplified Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)......... 10 6.7 Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)... 10 6.8 Timing Requirements (2 V < IOVDD ≤ 5.5 V)............11 6.9 Switching Characteristics (2 V < IOVDD ≤ 5.5 V)..... 11 6.10 Timing Diagrams..................................................... 12 6.11 Typical Characteristics............................................ 13 7 Parameter Measurement Information.......................... 23 7.1 Offset Error Measurement........................................ 23 7.2 Offset Drift Measurement..........................................23 7.3 Gain Error Measurement.......................................... 23 7.4 Gain Drift Measurement............................................23 7.5 NMRR Measurement................................................ 23 7.6 CMRR Measurement................................................ 24 7.7 PSRR Measurement................................................. 24 7.8 SNR Measurement................................................... 25 7.9 INL Error Measurement............................................ 25 7.10 THD Measurement..................................................25 7.11 SFDR Measurement............................................... 26 7.12 Noise Performance................................................. 26 8 Detailed Description......................................................29 8.1 Overview................................................................... 29 8.2 Functional Block Diagram......................................... 29 8.3 Feature Description...................................................30 8.4 Device Functional Modes..........................................44 8.5 Programming............................................................ 49 8.6 Registers...................................................................60 9 Application and Implementation.................................. 72 9.1 Application Information............................................. 72 9.2 Typical Application.................................................... 73 9.3 Power Supply Recommendations.............................76 9.4 Layout....................................................................... 77 10 Device and Documentation Support..........................78 10.1 Documentation Support.......................................... 78 10.2 Receiving Notification of Documentation Updates..78 10.3 Support Resources................................................. 78 10.4 Trademarks............................................................. 78 10.5 Electrostatic Discharge Caution..............................78 10.6 Glossary..................................................................78 11 Mechanical, Packaging, and Orderable Information.................................................................... 78 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2022) to Revision C (September 2022) Page • Changed RUK (WQFN) package from preview to production data ................................................................... 1 • Changed AVDD1 to DGND specification in Recommended Operating Conditions section................................5 • Changed high-speed mode analog input precharge buffers off current drift specifications in Electrical Characterisics section.........................................................................................................................................6 • Changed REFP input precharge buffer on current drift specification in Electrical Characterisics section.......... 6 • Added Long-Term Offset Drift and Long-Term Gain Drift plots to Typical Characteristics section....................13 • Added second paragraph to Internal Oscillator section.................................................................................... 34 • Added footnote to Wideband Filter Characteristics table in Wideband Filter section....................................... 35 • Added footnote to Sinc4 Filter Characteristics table in Sinc4 Filter section......................................................38 • Added footnote to Sinc4 + Sinc1 Filter Characteristics table in Sinc4 + Sinc1 Filter section........................... 39 • Changed Digital Supply Threshold and Analog Supply Threshold figures in Power-On Reset section........... 43 Changes from Revision A (October 2021) to Revision B (April 2022) Page • Changed INL specification in Electrical Characteristics section......................................................................... 6 • Changed SPI CRC section............................................................................................................................... 50 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 IOVDD VCM 6 15 CLK REFP 7 14 DRDY REFN 8 13 SDO/DRDY RESET 9 12 SCLK 10 11 SDI CS 15 CAPD AINN 2 14 DGND VCM 3 13 IOVDD REFP 4 12 CLK REFN 5 11 DRDY Not to scale Figure 5-1. PW Package, 20-Pin TSSOP (Top View) START 16 16 5 1 Thermal Pad 10 AINN AINP SDO/DRDY DGND AVSS 17 17 4 9 AINP SCLK CAPD CAPA 18 18 3 8 AVDD1 SDI START AVDD2 19 19 2 7 AVDD2 CS AVSS AVDD1 20 6 1 RESET CAPA 20 5 Pin Configuration and Functions Not to scale Figure 5-2. RUK Package, 20-Pin WQFN (Top View) Table 5-1. Pin Functions NAME PIN NO. TSSOP WQFN AINN 5 2 AINP 4 AVDD1 3 AVDD2 2 AVSS I/O DESCRIPTION Analog input Negative analog input; see the Analog Input section for details 1 Analog input Positive analog input; see the Analog Input section for details 20 Analog Supply Positive analog supply 1; see the Power Supplies section for details 19 Analog Supply Positive analog supply 2; see the Power Supplies section for details 20 17 Analog Supply Negative analog supply; see the Power Supplies section for details CAPA 1 18 Analog output Analog voltage regulator output capacitor bypass CAPD 18 15 Analog output Digital voltage regulator output capacitor bypass CLK 15 12 Digital input Clock input; see the Clock Operation section for details CS 10 7 Digital input Chip select, active low; see the Chip Select section for details DGND 17 14 Ground DRDY 14 11 Digital output Data ready, active low; see the Data Ready section for details IOVDD 16 13 Digital Supply I/O supply voltage; see the Power Supplies section for details REFN 8 5 Analog input Negative reference input; see the Reference Voltage section for details REFP 7 4 Analog input Positive reference input; see the Reference Voltage section for details RESET 9 6 Digital input Reset, active low; see the Reset section for details SCLK 12 9 Digital input Serial data clock; see the Serial Clock section for details SDI 11 8 Digital input Serial data input; see the Serial Data Input section for details SDO/DRDY 13 10 Digital output START 19 16 Digital input VCM 6 3 Analog output Thermal Pad — Pad — Digital ground Serial data output and data ready (optional); see the SDO/DRDY section for details Conversion start; see the Synchronization section for details Common-mode voltage buffered output; see the VCM Output Voltage section for details Thermal power pad; connect to AVSS Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 3 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted) (1) Power supply voltage MIN MAX AVDD1 to AVSS –0.3 6.5 AVDD2 to AVSS –0.3 6.5 –3 0.3 –0.3 6.5 AVSS – 0.3 AVDD1 + 0.3 CAPA AVSS 1.65 CAPD DGND 1.65 VCM AVSS AVDD1 SDO/DRDY, DRDY, START DGND – 0.3 IOVDD + 0.3 CS, SCLK, SDI, RESET, CLK DGND – 0.3 6.5 –10 10 AVSS to DGND IOVDD to DGND IOVDD to AVSS Analog input voltage Analog output voltage Digital input/output voltage Input current Temperature (1) (2) UNIT V 8.5 AINP, AINN, REFP, REFN Continuous, any pin except power-supply pins(2) Junction, TJ 150 Storage, Tstg –65 150 V V V mA °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional – this may affect device reliability, functionality, performance, and shorten the device lifetime. Analog input pins AINP, AINN, REFP, and REFN are diode-clamped to AVDD1 and AVSS. Limit the input current to 10 mA in the event the analog input voltage exceeds AVDD1 + 0.3 V or AVSS – 0.3 V. Digital input pin START and digital output pins SDO/DRDY and DRDY are diode-clamped to IOVDD and DGND. Digital input pins CS, SCLK, SDI, RESET and CLK are diode-clamped to DGND. Limit the input current to 10 mA in the event the digital input voltage exceeds IOVDD + 0.3 V (for effected pins) or exceeds DGND – 0.3 V. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY Analog power supply AVDD1 to AVSS, high-speed mode 4.5 5.5 AVDD1 to AVSS, low-speed mode 2.85 5.5 V AVDD1 to DGND 1.65 1.2 V/V Absolute ratio of AVSS / AVDD1 to DGND Digital power supply AVDD2 to AVSS 1.74 5.5 AVSS to DGND –2.75 0 IOVDD to DGND 1.65 5.5 Precharge buffer off AVSS – 0.05 AVDD1 + 0.05 Precharge buffer on AVSS + 0.1 AVDD1 – 0.1 V V ANALOG INPUTS VAINP, VAINN Absolute input voltage VIN Differential input voltage VIN = VAINP – VAINN 1x input range –VREF VREF 2x input range –2∙VREF 2∙VREF V V VOLTAGE REFERENCE INPUTS VREF Differential reference voltage VREF = VREFP – VREFN VREFN Negative reference voltage VREFP Positive reference voltage Low-reference range 0.5 2.5 2.75 High-reference range 1 4.096 AVDD1 – AVSS AVSS – 0.05 V V REFP precharge buffer off AVDD1 + 0.05 REFP precharge buffer on AVDD1 – 0.7 V EXTERNAL CLOCK SOURCE fCLK Clock frequency High-speed mode 0.5 25.6 26.2 Low-speed mode 0.5 3.2 3.28 MHz DIGITAL INPUTS VIL Logic input voltage, low VIH Logic input voltage, high DGND 0.3∙IOVDD V 0.7∙IOVDD IOVDD V –45 125 °C TEMPERATURE RANGE TA Operating ambient temperature 6.4 Thermal Information ADS127L11 THERMAL METRIC (1) WQFN (RUK) TSSOP (PW) 20 PINS 20 PINS UNIT RθJA Junction-to-ambient thermal resistance 46.0 92.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 43.9 32.9 °C/W RθJB Junction-to-board thermal resistance 19.9 44.4 °C/W ψJT Junction-to-top characterization parameter 0.7 2.2 °C/W ψJB Junction-to-board characterization parameter 19.9 43.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.1 n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 5 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.5 Electrical Characteristics minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 1.8 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VIN = 0 V, VCM = 2.5 V, VREFP = 4.096 V, VREFN = 0 V, high-reference range, 1x input range, fCLK = 25.6 MHz (high-speed mode), fCLK = 3.2 MHz (low-speed mode), input precharge buffers on, and reference precharge buffer on (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS, HIGH-SPEED MODE Input current, differential input voltage Precharge buffers off 95 Precharge buffers off, 2x input range 47 Precharge buffers on ±3 Precharge buffers off Input current drift, differential input voltage Input current, common-mode input voltage µA/V µA 3 Precharge buffers off, 2x input range nA/V/°C 1.5 Precharge buffers on 5 Precharge buffers off 5 Precharge buffers off, 2x input range 2.5 Precharge buffers on ±3 Precharge buffers off 12 nA/°C µA/V µA ANALOG INPUTS, LOW-SPEED MODE Input current, differential input voltage Precharge buffers off, 2x input range Precharge buffers on ±0.4 Precharge buffers off Input current drift, differential input voltage Input current, common-mode input voltage µA/V 6 µA 1 Precharge buffers off, 2x input range 0.5 Precharge buffers on 0.2 Precharge buffers off 0.6 Precharge buffers off, 2x input range 0.3 Precharge buffers on nA/V/°C nA/°C µA/V ±0.4 µA 24 Bits DC PERFORMANCE Resolution OSR ≥ 64 Noise See Noise Performance for details High-speed mode, low-latency filter fDATA Output data rate 0.08 1067 High-speed mode, wideband filter 3.125 400 Low-speed mode, low-latency filter 0.01 133 Low-speed mode, wideband filter INL Integral nonlinearity Best-fit method Offset error TA = 25°C 0.390625 TA = 25°C to 85°C TA = 25°C –2000 Gain drift NMRR Normal-mode rejection ratio CMRR Common-mode rejection ratio fIN = 50 Hz (±1 Hz), fDATA = 50 SPS 100 fIN = 60 Hz (±1 Hz), fDATA = 60 SPS 100 At dc 110 Up to 10 kHz 6 Power-supply rejection ratio 250 50 200 nV/°C ±200 2000 ppm of FSR 0.6 1.9 ppm of FSR/°C µV dB 130 dB 95 AVDD1, dc 100 120 AVDD2, dc 115 130 IOVDD, dc 115 130 Submit Document Feedback ppm of FSR ±30 115 At dc, 2x input range PSRR 5.5 4 Offset drift Gain error 50 0.9 –250 kSPS dB Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.5 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 1.8 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VIN = 0 V, VCM = 2.5 V, VREFP = 4.096 V, VREFN = 0 V, high-reference range, 1x input range, fCLK = 25.6 MHz (high-speed mode), fCLK = 3.2 MHz (low-speed mode), input precharge buffers on, and reference precharge buffer on (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 109 111.5 MAX UNIT AC PERFORMANCE, HIGH-SPEED MODE Wideband filter DR SNR Dynamic range Signal-to-noise ratio Inputs shorted, OSR = 64, fDATA = 200 kSPS fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64, fDATA = 200 kSPS, 9 harmonics Wideband filter, VREF = 2.5 V 107.5 Wideband filter, VREF = 2.5 V, 2x input range 108.5 Low-latency filter 112 114 Low-latency filter, VREF = 2.5 V 110.5 Low-latency filter, VREF = 2.5 V, 2x input range 111 Wideband filter 110 Wideband filter, VREF = 2.5 V 106 Wideband filter, VREF = 2.5 V, 2x input range 107 Low-latency filter 112 Low-latency filter, VREF = 2.5 V 108.5 Low-latency filter, VREF = 2.5 V, 2x input range 110 THD Total harmonic distortion fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64, fDATA = 200 kSPS, 9 harmonics SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 Wideband filter dB dB –120 dB 120 dB AC PERFORMANCE, LOW-SPEED MODE Wideband filter DR SNR Dynamic range Signal-to-noise ratio Inputs shorted, OSR = 64, fDATA = 25 kSPS fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64, fDATA = 25 kSPS 109 112 Wideband filter, VREF = 2.5 V 107.5 Wideband filter, VREF = 2.5 V, 2x input range 108.5 Low-latency filter 111.5 114.5 Low-latency filter, VREF = 2.5 V 110.5 Low-latency filter, VREF = 2.5 V, 2x input range 111.5 Wideband filter 110 Wideband filter, VREF = 2.5 V 106 Wideband filter, VREF = 2.5 V, 2x input range 108 Low-latency filter 112 Low-latency filter, VREF = 2.5 V 108 Low-latency filter, VREF = 2.5 V, 2x input range 110 dB dB Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 7 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.5 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 1.8 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VIN = 0 V, VCM = 2.5 V, VREFP = 4.096 V, VREFN = 0 V, high-reference range, 1x input range, fCLK = 25.6 MHz (high-speed mode), fCLK = 3.2 MHz (low-speed mode), input precharge buffers on, and reference precharge buffer on (unless otherwise noted) PARAMETER TEST CONDITIONS THD Total harmonic distortion fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64, fDATA = 25 kSPS, 9 harmonics SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 MIN Wideband filter TYP MAX UNIT –125 dB 120 dB WIDEBAND FILTER CHARACTERISTICS Within envelope of pass-band ripple Pass-band frequency 0.4125 ∙ fDATA –3-dB frequency 0.4374 ∙ fDATA Pass-band ripple Stop-band frequency 0.4 ∙ fDATA –0.1-dB frequency –0.0004 At stop-band attenuation Stop-band attenuation(1) Hz 0.0004 dB 0.5 · fDATA Hz 106 dB Group delay 34 / fDATA s Settling time 68 / fDATA s VOLTAGE REFERENCE INPUTS REFP precharge buffer off, high-speed mode 190 REFP precharge buffer off, low-speed mode 80 REFP precharge buffer on ±2 REFP and REFN input current drift REFP precharge buffer off, high-speed mode 10 REFP precharge buffer off, low-speed mode 10 REFP input current drift REFP precharge buffer on 10 REFP and REFN input current, differential reference voltage REFP input current, differential reference voltage µA/V µA nA/℃ INTERNAL OSCILLATOR Frequency High-speed mode 25.4 25.6 25.8 Low-speed mode 3.17 3.2 3.23 MHz VCM OUTPUT VOLTAGE Output voltage (AVDD1 + AVSS) / 2 Accuracy –1% Voltage noise 1-kHz bandwidth Start-up time CL = 100 nF ±0.1% V 1% 25 µVRMS 1 Capacitive load ms 100 Resistive load 2 Short-circuit current limit nF kΩ 10 mA DIGITAL INPUTS/OUTPUTS VOL Logic-low output level VOH Logic-high output level OUT_DRV = 0b, IOL = 2 mA 0.2 ∙ IOVDD OUT_DRV = 1b, IOL = 1 mA 0.2 ∙ IOVDD OUT_DRV = 0b, IOH = –2 mA 0.8 ∙ IOVDD OUT_DRV = 1b, IOH = –1 mA 0.8 ∙ IOVDD Input hysteresis Input current RESET pin pullup resistor 8 V 150 Excluding RESET pin –1 mV 1 20 Submit Document Feedback V µA kΩ Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.5 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 1.8 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VIN = 0 V, VCM = 2.5 V, VREFP = 4.096 V, VREFN = 0 V, high-reference range, 1x input range, fCLK = 25.6 MHz (high-speed mode), fCLK = 3.2 MHz (low-speed mode), input precharge buffers on, and reference precharge buffer on (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX High-speed mode 1.7 1.85 Low-speed mode 0.25 0.3 UNIT ANALOG SUPPLY CURRENT AVDD1 and AVSS current (All buffers off) Standby mode 35 Power-down mode IAVDD1, IAVSS AVDD1 and AVSS additional current (per buffer function) IAVDD2, IAVSS AVDD2 and AVSS current µA 5 AINx precharge buffer, high-speed mode 1.35 1.9 AINx precharge buffer, low-speed mode 0.2 0.3 REFP precharge buffer, high-speed mode 1.5 1.6 REFP precharge buffer, low-speed mode 0.4 0.45 VCM buffer 0.1 High-speed mode 3.5 3.8 Low-speed mode 0.85 0.95 Standby mode 60 Power-down mode mA mA mA µA 1 DIGITAL SUPPLY CURRENT IIOVDD IOVDD current High-speed mode, wideband filter, OSR = 32 2.1 High-speed mode, low-latency filter, OSR = 32 0.6 2.7 1 Low-speed mode, wideband filter, OSR = 32 0.3 0.4 Low-speed mode, low-latency filter, OSR = 32 0.1 0.2 Standby mode, external clock 10 Standby mode, internal oscillator 40 Power-down mode 10 mA µA POWER DISSIPATION PD (1) Power dissipation AVDD2 = 1.8 V, precharge buffers off High-speed mode, wideband filter 18.6 High-speed mode, low-latency filter 15.9 Low-speed mode, wideband filter 3.3 Low-speed mode, low-latency filter 3.0 mW Stop-band attenuation as provided by the digital filter. Input frequencies in the stop band intermodulate with the chop frequency beginning at fMOD / 32, which results in stop-band attenuation exceeding 106 dB. See the wideband filter stop-band attenuation figure for details. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 9 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.6 Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V) over operating ambient temperature range, unless otherwise noted MIN MAX CLK period, high-speed mode 38.2 2000 CLK period, low-speed mode, CLK_DIV = 1b 38.2 2000 CLK period, low-speed mode, CLK_DIV = 0b 305 2000 UNIT CLK PIN tc(CLK) tw(CLKL) tw(CLKH) Pulse duration, CLK low 17 Pulse duration, CLK low, low-speed mode, CLK_DIV = 0b ns 128 Pulse duration, CLK high 17 Pulse duration, CLK high, low-speed mode, CLK_DIV = 0b ns ns 128 SERIAL INTERFACE tc(SC) SCLK period 25 tw(SCL) Pulse duration, SCLK low 10 1/(4 ∙ fDATA) ns ns tw(SCH) Pulse duration, SCLK high 10 ns td(CSSC) Delay time, first SCLK rising edge after CS falling edge 10 ns tsu(DI) Setup time, SDI valid before SCLK falling edge 4 ns th(DI) Hold time, SDI valid after SCLK falling edge 6 ns td(SCCS) Delay time, CS rising edge after final SCLK falling edge 10 ns tw(CSH) Pulse duration, CS high 20 ns RESET PIN tw(RSL) Pulse duration, RESET low td(RSSC) Delay time, communication start after RESET rising edge or after SPI RESET pattern 4 tCLK 10000 tCLK START PIN tw(STL) Pulse duration, START low 4 tCLK tw(STH) Pulse duration, START high 4 tCLK tsu(STCLK) Setup time, START high before CLK rising edge (1) 9 ns th(STCLK) Hold time, START high after CLK rising edge (1) 9 ns tsu(STDR) Setup time, START falling edge or STOP bit before DRDY falling edge to stop next conversion (start/stop conversion mode) 8 tCLK (1) START rising edge should not be applied between the setup and hold time period at the rising edge of CLK 6.7 Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V) over operating ambient temperature range, OUT_DRV = 0b, CLOAD = 20 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tp(CSDO) Propagation delay time, CS falling edge to SDO/DRDY driven state 20 ns tp(CSDOZ) Propagation delay time, CS rising edge to SDO/DRDY high impedance state 20 ns th(SCDO) Hold time, SCLK rising edge to invalid SDO/DRDY tp(SCDO) Propagation delay time, SCLK rising edge to valid SDO/DRDY tw(DRH) Pulse duration, DRDY high tp(SCDR) Synchronized and start/stop Propagation delay time, 8th SCLK falling edge to DRDY return high control modes tp(DODR) Propagation delay time, last SCLK falling edge of read operation for SDO/DRDY transition from SDO to DRDY mode 10 3 ns 23 2 SDO_DRDY = 1b Submit Document Feedback ns tCLK 5 tCLK 50 ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.8 Timing Requirements (2 V < IOVDD ≤ 5.5 V) over operating ambient temperature range, unless otherwise noted MIN MAX CLK period, high-speed mode 38.2 2000 CLK period, low-speed mode, CLK_DIV = 1b 38.2 2000 CLK period, low-speed mode, CLK_DIV = 0b 305 2000 UNIT CLK PIN tc(CLK) tw(CLKL) tw(CLKH) Pulse duration, CLK low 17 Pulse duration, CLK low, low-speed mode ns 128 Pulse duration, CLK high 17 Pulse duration, CLK high, low-speed mode ns ns 128 SERIAL INTERFACE tc(SC) SCLK period tw(SCL) Pulse duration, SCLK low 20 8 1/(4 ∙ fDATA) ns ns tw(SCH) Pulse duration, SCLK high 8 ns td(CSSC) Delay time, first SCLK rising edge after CS falling edge 10 ns tsu(DI) Setup time, SDI valid before SCLK falling edge 4 ns th(DI) Hold time, SDI valid after SCLK falling edge 6 ns td(SCCS) Delay time, CS rising edge after final SCLK falling edge 10 ns tw(CSH) Pulse duration, CS high 20 ns RESET PIN tw(RSL) Pulse duration, RESET low td(RSSC) Delay time, communication start after RESET rising edge or after SPI RESET pattern 4 t 10000 tCLK START PIN tw(STL) Pulse duration, START low 4 tCLK tw(STH) Pulse duration, START high 4 tCLK tsu(STCLK) Setup time, START high before CLKIN rising edge (1) 9 ns th(STCLK) Hold time, START high after CLKIN rising edge (1) 9 ns tsu(STDR) Setup time, START falling edge or STOP bit before DRDY falling edge to stop next conversion (start/stop conversion mode) 8 tCLK (1) START rising edge should not be applied between the setup and hold time period at the rising edge of CLK 6.9 Switching Characteristics (2 V < IOVDD ≤ 5.5 V) over operating ambient temperature range, OUT_DRV = 0b, CLOAD = 20 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tp(CSDO) Propagation delay time, CS falling edge to SDO/DRDY driven 17 ns tp(CSDOZ) Propagation delay time, CS rising edge to SDO/DRDY high impedance state 17 ns th(SCDO) Hold time, SCLK rising edge to invalid SDO/DRDY tp(SCDO) Propagation delay time, SCLK rising edge to valid SDO/DRDY tw(DRH) Pulse duration, DRDY high tp(SCDR) Synchronized and start/stop Propagation delay time, 8th SCLK falling edge to DRDY return high control modes tp(DODR) Propagation delay time, last SCLK falling edge of read operation for SDO/DRDY transition from SDO to DRDY mode 3 ns 19 2 SDO_DRDY = 1b ns tCLK 5 tCLK 50 ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.10 Timing Diagrams tc(CLK) tw(CLKH) CLK tw(CLKL) tw(CSH) CS td(CSSC) tc(SC) tw(SCH) td(SCCS) SCLK tsu(DI) tw(SCL) th(DI) SDI LSB Figure 6-1. Clock and Serial Interface Timing Requirements tw(DRH) DRDY tp(SCDR) CS SCLK th(SCDO) tp(CSDO) DRDY SDO/DRDY tp(SCDO) tp(DODR) SDO SDO tp(CSDOZ) DRDY Figure 6-2. Serial Interface Switching Characteristics CLK RESET tsu(STCLK) tw(RSL) td(RSSC) START SCLK th(STCLK) tw(STH) Figure 6-3. RESET Pin Timing tw(STL) tsu(STDR) DRDY Figure 6-4. START Pin Timing IOVDD ½ IOVDD 50% DGND td, th, tp, tw, tc, tsu Figure 6-5. Timing Reference 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 20 40 60 80 100 120 Frequency (kHz) 140 160 180 200 0 Wideband filter, OSR = 32, high-speed mode, 524,288 samples 10 40 50 60 Frequency (Hz) 70 80 90 100 Figure 6-7. Shorted Input FFT 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 30 Wideband filter, OSR = 32, high-speed mode, 524,288 samples Figure 6-6. Shorted Input FFT -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 5 10 15 Frequency (kHz) 20 0 25 10 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) 0 -80 -100 -120 -160 -180 80 100 120 Frequency (kHz) 140 80 90 100 -120 -140 60 70 -100 -160 40 40 50 60 Frequency (Hz) -80 -140 20 30 Figure 6-9. Shorted Input FFT Figure 6-8. Shorted Input FFT 0 20 Wideband filter, OSR = 32, low-speed mode, 524,288 samples Wideband filter, OSR = 32, low-speed mode, 524,288 samples Amplitude (dB) 20 160 180 200 2x input range, VREF = 2.5 V, wideband filter, OSR = 32, high-speed mode, 524,288 samples -180 0 5 10 15 Frequency (kHz) 20 25 2x input range, VREF = 2.5 V, wideband filter, OSR = 32, low-speed mode, 524,288 samples Figure 6-10. Shorted Input FFT Figure 6-11. Shorted Input FFT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 13 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 0 20 40 60 80 100 120 Frequency (kHz) 140 160 180 -180 200 0 Sinc4 filter, OSR = 32, high-speed mode, 524,288 samples 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 20 25 Figure 6-13. Shorted Input FFT 0 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 50 10 15 Frequency (kHz) Sinc4 filter, OSR = 32, low-speed mode, 524,288 samples Figure 6-12. Shorted Input FFT 0 5 100 150 200 250 300 350 400 450 500 550 Frequency (kHz) -180 0 Sinc4 filter, OSR = 12, high-speed mode, 524,288 samples 10 20 30 40 Frequency (kHz) 50 60 70 Sinc4 filter, OSR = 12, low-speed mode, 524,288 samples Figure 6-14. Shorted Input FFT Figure 6-15. Shorted Input FFT 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 -180 0.01 0.1 1 Frequency (kHz) 10 100 200 Input precharge buffers on, wideband filter, OSR = 32, high-speed mode, VIN = –0.2 dBFS, 65,536 samples Input precharge buffers off, wideband filter, OSR = 32, high-speed mode, VIN = –0.2 dBFS, 65,536 samples Figure 6-17. Full-Scale Input FFT Figure 6-16. Full-Scale Input FFT 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 -180 0.001 0.01 0.1 1 Frequency (kHz) 10 30 Input precharge buffers on, wideband filter, OSR = 32, low-speed mode, VIN = –0.2 dBFS, 65,536 samples Input precharge buffers off, wideband filter, OSR = 32, low-speed mode, VIN = –0.2 dBFS, 65,536 samples Figure 6-18. Full-Scale Input FFT Figure 6-19. Full-Scale Input FFT 50 70 High-speed mode Low-speed mode High-speed mode Low-speed mode 60 40 Population (%) Population (%) 50 30 20 40 30 20 10 10 8 7.9 7.8 7.7 7.6 7.5 7.4 7.3 7.2 Noise (V RMS ) Shorted input, wideband filter, OSR = 32 Shorted input, wideband filter, OSR = 64, N = 30 Figure 6-20. Output Data Distributions Figure 6-21. Total Noise Performance Distributions 100 12.5 High-speed mode Low-speed mode High-speed mode, low-reference range Low-speed mode, low-reference range High-speed mode, high-reference range Low-speed mode, high-reference range 12 80 11.5 Noise (V RMS ) Population (%) 7.1 7 110 ADC Output (V) 100 90 80 70 60 50 40 30 20 0 10 -10 -20 0 -30 0 60 40 11 10.5 10 9.5 20 9 6 5.9 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5 0 8.5 0.5 1 Noise (V RMS ) 2 2.5 3 V REF (V) 3.5 4 4.5 5 Shorted input, wideband filter, OSR = 32 Shorted input, sinc4 filter, OSR = 64, N = 30 Figure 6-22. Total Noise Performance Distributions 1.5 Figure 6-23. Total Noise Performance vs Reference Voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 15 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 10 9 8 Noise (V RMS ) 7 6 5 4 3 2 1 0 -40 High-speed mode, wideband filter, OSR = 64 Low-speed mode, wideband filter, OSR = 64 High-speed mode, sinc4 Fflter, OSR = 64 Low-speed mode, sinc4 Filter, OSR = 64 -20 0 20 40 60 Temperature (C) 80 100 120 Shorted input Wideband filter, OSR = 64, N = 30 Figure 6-25. SNR Distributions Figure 6-24. Total Noise Performance vs Temperature 3 125 High-speed mode Low-speed mode Input Current (A) 75 50 25 1 0 -1 -2 -80 -60 -40 Input Amplitude (dBFS) -20 -3 0 -5 -4 Wideband filter, OSR = 64 High-Speed Mode Input Current (A) Input Current (A) 100 0 -100 -200 -300 -400 -80 -60 -40 -20 0 20 40 60 80 Differential Input Voltage (% of Full-Scale Range) 100 Precharge buffers off, 1x and 2x input range, VREF = 2.5 V, VCM = 2.5 V Figure 6-28. Input Current vs Differential Input Voltage 16 4 244 High-speed mode, AINN High-speed mode, AINP Low-speed mode, AINN Low-speed mode, AINP 200 -500 -100 3 5 Figure 6-27. Input Current vs Differential Input Voltage 500 300 -2 -1 0 1 2 Differential Input Voltage (V) Precharge buffers on, 2x input range, VREF = 2.5 V, VCM = 2.5 V Figure 6-26. SNR vs Signal Amplitude 400 -3 242 32 High-speed mode, 1x input range Low-speed mode, 1x input range High-speed mode, 2x input range Low-speed mode, 2x input range 31 240 30 238 29 236 -40 Low-Speed Mode Input Current (A) Signal-to-Noise Ratio (dB) 100 0 -100 High-speed mode, AINN High-speed mode, AINP Low-speed mode, AINN Low-speed mode, AINP 2 28 -20 0 20 40 60 Temperature (C) 80 100 120 VIN = full scale, VCM = 2.5 V, precharge buffers off Figure 6-29. Input Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 30 1 High-speed mode, 1x input range Low-speed mode, 1x input range High-speed mode, 2x input range Low-speed mode, 2x input range 0.8 0.4 Input Current (A) Input Current (A) 0.6 High-speed mode, 1x input range Low-speed mode, 1x input range High-speed mode, 2x input range Low-speed mode, 2x input range 25 0.2 0 -0.2 -0.4 -0.6 20 15 10 5 -0.8 -1 -40 -20 0 20 40 60 Temperature (C) 80 100 0 -40 120 -20 VIN = full scale, VCM = 2.5 V, precharge buffers on 100 120 110 High-speed mode, 1x input range Low-speed mode, 1x input range High-speed mode, 2x input range Low-speed mode, 2x input range High-speed mode, V REF = 4.096 V, 1x input range High-speed mode, V REF = 2.5 V, 1x input range High-speed mode, V REF = 2.5 V, 2x input range Low-speed mode, V REF = 4.096 V, 1x input range 100 90 80 Population (%) Input Current (A) 80 Figure 6-31. Input Current vs Temperature 1.2 0.4 20 40 60 Temperature (C) VIN = 0 V, VCM = 2.5 V, precharge buffers off Figure 6-30. Input Current vs Temperature 0.8 0 0 -0.4 -0.8 70 60 50 40 30 -1.2 20 -1.6 10 200 160 Figure 6-33. Offset Error Distribution 100 150 High-speed mode Low-speed mode High-speed mode, V REF = 4.096 V, 1x input range High-speed mode, V REF = 2.5 V, 2x input range High-speed mode, V REF = 2.5 V, 1x input range Low-speed mode, V REF = 4.096 V, 1x input range 90 100 80 75 70 Population (%) 50 25 0 -25 60 50 40 30 -50 20 -75 10 400 360 320 280 0 240 120 200 100 160 80 120 20 40 60 Temperature (C) 80 0 40 -20 0 Offset Error (V) 120 N = 30 Figure 6-32. Analog Input Current vs Temperature -100 -40 80 Offset Error (V) VIN = 0 V, VCM = 2.5 V, precharge buffers on 125 40 120 0 100 -40 80 -80 20 40 60 Temperature (C) -120 0 -160 0 -20 -200 -2 -40 Offset Drift (nV/C) N = 30 Figure 6-34. Offset Error vs Temperature Figure 6-35. Offset Drift Distribution Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 17 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 4 50 High-speed mode, buffers on High-speed mode, buffers off Low-speed mode, buffers on Low-speed mode, buffers off 45 40 35 Population (%) Offset Error (V) 2 0 30 25 20 15 -2 10 5 600 500 400 300 200 100 0 Gain Error (ppm of FSR) N = 30, offset error calibrated at t = 0 N = 30 Figure 6-36. Long-Term Offset Drift Figure 6-37. Gain Error Distribution 400 25 High-speed mode, buffers on High-speed mode, buffers off Low-speed mode, buffers on Low-speed mode, buffers off 200 High-speed mode Low-speed mode 20 Gain Error (ppm of FSR) 300 Gain Error (ppm of FSR) -100 1000 -200 750 -300 500 Time (hours) -400 250 -600 0 -500 0 -4 100 0 -100 -200 -300 -400 15 10 5 0 -5 -10 -500 -600 -40 -15 -20 0 20 40 60 Temperature (C) 80 100 120 0 10 20 30 40 50 60 70 80 90 Clock Frequency (% of Nominal Clock Frequency) 100 Gain error calibrated at nominal clock frequency N=3 Figure 6-39. Gain Error vs Clock Frequency Figure 6-38. Gain Error vs Temperature 100 Gain Error (ppm) 50 0 -50 -100 0 250 500 Time (hours) 750 1000 N = 30, gain error calibrated at t = 0 Figure 6-40. Long-Term Gain Drift 18 N = 30 Figure 6-41. Gain Drift Distributions Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 60 -80 High-speed mode Low-speed mode Total Harmonic Distortion (dB) Population (%) 50 40 30 20 10 -114 -116 -118 -120 -122 -124 -126 -128 -100 -110 -120 -130 -140 -100 0 -130 High-speed mode Low-speed mode -90 -80 -60 -40 Input Signal [dBFS] -20 0 THD (dB) Figure 6-43. THD vs Input Signal Amplitude Figure 6-42. THD Distribution 4 3 INL Error (ppm of FSR) 2 mode, mode, mode, mode, V REF V REF V REF V REF = 2.5 V, 1x input range = 2.5 V, 2x input range = 4.096 V, 1x input range = 4.096 V, extended range 3 INL Error (ppm of FSR) High-speed High-speed High-speed High-speed 1 0 -1 -2 -3 -100 2 V REF V REF V REF V REF = 2.5 V, 1x input range = 2.5 V, 2x input range = 4.096 V, 1x input range = 4.096 V, extended range 1 0 -1 -2 -3 -80 -60 -40 -20 0 20 40 60 Input Voltage (% of Full-Scale Range) 80 -4 -100 100 -80 -60 -40 -20 0 20 40 60 Input Voltage (% of Full-Scale Range) 80 100 Figure 6-45. INL Error vs Input Voltage Figure 6-44. INL Error vs Input Voltage 7 50 High-speed mode Low-speed mode 45 6 40 5 INL (ppm of FSR) 35 Population (%) Low-speed mode, Low-speed mode, Low-speed mode, Low-speed mode, 30 25 20 15 4 3 2 10 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0 -40 0.5 0 0.25 1 0 5 -20 INL (ppm of FSR) 0 20 40 60 Temperature (C) 80 100 120 N = 30 N = 30 Figure 6-47. INL vs Temperature Figure 6-46. INL Distributions Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 19 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) 30 150 25 140 20 130 CMRR (dB) Population (%) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 15 120 10 110 5 100 90 -40 155 150 145 140 135 130 125 120 115 0 -20 0 20 40 60 Temperature (C) 80 100 120 N = 30 CMRR (dB) N = 30 Figure 6-49. DC CMRR vs Temperature 140 140 120 120 100 100 CMMR (dB) CMMR (dB) Figure 6-48. DC CMRR Distribution 80 60 80 60 1x input range 2x input range 40 0.01 0.1 1x input range 2x input range 1 10 100 1000 Common-Mode Input Frequency (kHz) 40 0.01 10000 0.1 1 10 100 1000 Common-Mode Input Frequency (kHz) High-speed mode Low-speed mode Figure 6-50. CMRR vs Frequency Figure 6-51. CMRR vs Frequency 40 0.5 0.4 Oscillator Frequency Error (%) 35 30 Population (%) 10000 25 20 15 10 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.5 -40 -0.2 -0.4 0 -0.25 5 -20 0 20 40 60 Temperature (C) 80 100 120 N = 30 Oscillator Frequency Error (%) N = 30 Figure 6-52. Oscillator Frequency Distribution 20 Figure 6-53. Oscillator Frequency vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 30 0.5 0.4 0.3 VCM Voltage Error (%) Population (%) 25 20 15 10 0.2 0.1 0 -0.1 -0.2 -0.3 5 -0.4 -0.5 -40 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 -20 0 20 40 60 Temperature (C) 80 100 120 N = 30 VCM Voltage Error (%) N = 30 Figure 6-55. VCM Voltage vs Temperature Figure 6-54. VCM Voltage Distribution 10 1400 High-speed mode, low-reference range High-speed mode, high-reference range Low-speed mode, low-reference range Low-speed mode, high-reference range 1000 7.5 REFP Input Current (A) REFP Input Current (A) 1200 800 600 400 200 5 High-speed mode, low-reference range High-speed mode, high-reference range Low-speed mode, low-reference range Low-speed mode, high-reference range 2.5 0 -2.5 -5 -7.5 0 0.5 1 1.5 2 2.5 3 3.5 4 Reference Voltage (V) 4.5 5 -10 0.5 5.5 1 1.5 REFP precharge buffer off 2.5 3 3.5 4 Reference Voltage (V) 4.5 5 5.5 REFP precharge buffer on Figure 6-56. Reference Input Current vs Reference Voltage Figure 6-57. REFP Input Current vs Reference Voltage 50 150 AVDD1 IOVDD AVDD2 40 30 140 PSRR (dB) Population (%) 2 20 AVDD1 IOVDD AVDD2 130 120 110 10 155 150 145 140 135 130 125 120 115 0 100 -40 -20 0 20 40 60 Temperature (C) 80 100 120 PSRR (dB) N = 30 Figure 6-58. DC PSRR Distribution Figure 6-59. DC PSRR vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 21 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 6.11 Typical Characteristics (continued) 115 8 110 7 105 6 Supply Current (mA) PSRR (dB) AVDD1 = 5 V, AVDD2 = 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREF = 4.096 V, high-reference range, high-speed mode, wideband filter, OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C (unless otherwise noted) 100 95 90 AVDD1 AVDD2 IOVDD 85 AVDD1, buffers off AVDD1, AINP and AINN buffers on AVDD1, REFP buffer on AVDD2 IOVDD, wideband filter 5 4 3 2 1 80 1 10 100 Power-Supply Frequency (kHz) 1000 0 -40 -20 0 20 40 60 Temperature (C) 80 100 120 High-speed mode Figure 6-61. Power-Supply Current vs Temperature Figure 6-60. PSRR vs Power-Supply Frequency 1.6 Supply Current (mA) 1.2 IOVDD Supply Current (mA) 1.4 2.5 AVDD1, buffers off AVDD1, AINP and AINN buffers on AVDD1, REFP buffer on AVDD2 IOVDD, wideband filter 1 0.8 0.6 0.4 High-speed mode, wideband filter Low-speed mode, wideband filter High-speed mode, sinc4 filter Low-speed mode, sinc4 filter 2 1.5 1 0.5 0.2 0 -40 -20 0 20 40 60 Temperature (C) 80 100 120 0 10 100 Digital Filter OSR 1000 5000 Low-speed mode Figure 6-62. Power-Supply Current vs Temperature Figure 6-63. Power-Supply Current vs Oversampling Ratio 24 Supply Current (A) 20 AVDD1 AVDD2 IOVDD 16 12 8 4 0 -40 -20 0 20 40 60 Temperature (C) 80 100 120 Figure 6-64. Power-Down Mode Supply Current vs Temperature 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 7 Parameter Measurement Information 7.1 Offset Error Measurement Offset error is measured with the ADC inputs externally shorted together. The input common-mode voltage is fixed to the mid-point of the AVDD1 and AVSS power-supply range. Offset error is specified at TA = 25°C. 7.2 Offset Drift Measurement Offset drift is defined as the change in offset voltage measured at multiple points over the specified temperature range. Offset drift is calculated using the box method in which a box is formed over the maximum and minimum offset voltages and over the specified temperature range. The box method specifies limits for the temperature error but does not specify the exact shape and slope of the device under test. Equation 1 shows the offset drift calculation using the box method: Offset Drift (nV/°C) = 109 · (VOFSMAX – VOFSMIN) / (TMAX – TMIN) (1) where: • • VOFSMAX and VOFSMIN = Maximum and minimum offset voltages over the specified temperature range TMAX and TMIN = Maximum and minimum temperatures 7.3 Gain Error Measurement Gain error is defined as the difference between the actual and the ideal slopes of the ADC transfer function. Gain error is measured by applying dc test voltages at –95% and 95% of FSR. The error is calculated by subtracting the difference of the dc test voltages (ideal slope) from the difference in the ADC output voltages (actual slope). The difference in the slopes is divided by the ideal slope and multiplied by 106 to convert the error to ppm of FSR. Error resulting from the ADC reference voltage is excluded from the gain error measurement. The gain error is specified at TA = 25°C. Equation 2 shows the calculation of gain error: Gain Error (ppm of FSR) = 106 · (ΔVOUT – ΔVIN) / ΔVIN (2) where: • • ΔVOUT = Difference of two ADC output voltages ΔVIN = Difference of two input test voltages 7.4 Gain Drift Measurement Gain drift is defined as the change of gain error measured at multiple points over the specified temperature range. The box method is used in which a box is formed over the maximum and minimum gain errors over the specified temperature range. The box method specifies limits for the temperature error but does not specify the exact shape and slope of the device under test. Equation 3 describes gain drift using the box method. Gain Drift (ppm/°C) = (GEMAX – GEMIN) / (TMAX – TMIN) (3) where: • • GEMAX and GEMIN = Maximum and minimum gain errors over the specified temperature range TMAX and TMIN = Maximum and minimum temperatures 7.5 NMRR Measurement Normal-mode rejection ratio (NMRR) specifies the ability of the ADC to reject normal-mode input signals at specific frequencies, usually expressed at 50-Hz and 60-Hz input frequencies. Normal-mode rejection is uniquely determined by the frequency response of the digital filter. In this case, the nulls in the frequency response of the low-latency sinc3 filter option located at 50 Hz and 60 Hz provide rejection at these frequencies. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 23 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 7.6 CMRR Measurement Common-mode rejection ratio (CMRR) specifies the ability of the ADC to reject common-mode input signals. CMRR is expressed as dc and ac parameters. For measurement of CMRR (dc), three common-mode test voltages equal to AVSS + 50 mV, (AVDD1 + AVSS) / 2, and AVDD1 – 50 mV are applied with the inputs externally shorted together. The maximum change of the ADC offset voltage is recorded versus the change in common-mode test voltage. Equation 4 shows how CMRR (dc) is computed. CMRR (dc) (dB) = 20 · log(ΔVCM / ΔVOS) (4) where: • • ΔVCM = Change of dc common-mode test voltage ΔVOS = Change of corresponding offset voltage For the measurement of CMRR (ac), an ac common-mode signal is applied at various test frequencies at 95% full-scale range. An FFT is computed from the ADC data with the common-mode signal applied. As shown in Equation 5, the nine largest amplitude spurious frequencies in the frequency spectrum are summed as powers and related to the amplitude of the common-mode test signal. PSRR (ac) (dB) = 20 · log(VCM / VO) (5) where: • • VCM (RMS) = Common-mode input signal amplitude VO (RMS) = Root-sum-square amplitude of spurious frequencies = √(V0 2 + V1 2 + ...V8 2) 7.7 PSRR Measurement Power-supply rejection ratio (PSRR) specifies the ability of the ADC to reject power-supply interference. PSRR is expressed as ac and dc parameters. For measurement of PSRR (dc), the power-supply voltage is changed over the range of minimum, nominal, and maximum specified voltages with the inputs externally shorted together. The maximum change of ADC offset voltage is recorded versus the change in power-supply voltage. PSRR (dc) is computed as shown in Equation 6 as the ratio of change of the power-supply voltage step to the change of offset voltage. PSRR (dc) (dB) = 20 · log(ΔVPS / ΔVOS) (6) where: • • ΔVPS = Change of power-supply voltage ΔVOS = Change of offset voltage For the measurement of PSRR (ac), the power-supply voltage is modulated by a 100-mVpp (35 mVRMS) signal at various test frequencies. An FFT of the ADC data with power-supply modulation is performed. As shown in Equation 7, the nine largest amplitude spurious frequencies in the frequency spectrum are summed as powers and related to the amplitude of the power-supply modulation signal. PSRR (ac) (dB) = 20 · log(VPS / VO) (7) where: • • 24 VPS (RMS) = 100 mV ac power-supply modulation signal VO (RMS) = Root-sum-square amplitude of spurious frequencies = √(V0 2 + V1 2 + ...V8 2) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 7.8 SNR Measurement Signal-to-noise ratio (SNR) is a measure of noise performance with a full-scale ac input signal. For the SNR measurement, a –0.2-dBFS, 1-kHz test signal is used with VCM equal to the mid-supply voltage. As shown in Equation 8, SNR is the ratio of the rms value of the input signal to the root-sum-square of all other frequency components derived from the FFT result of the ADC output samples. DC and harmonics of the original signal are excluded from the SNR calculation. In a test case where an FFT window function is used because of non-coherent sampling, the spectral leakage of adjacent frequency bins surrounding dc, the original signal and signal harmonics are removed to calculate SNR. SNR (dB) = 20 · log(VIN / en) (8) where: • • VIN = Input test signal en = Root-sum-square of frequency components excluding dc and signal harmonics 7.9 INL Error Measurement Integral nonlinearity (INL) error specifies the linearity of the ADC dc transfer function. INL is measured by applying a series of dc test voltages along a straight line computed from the slope and offset transfer function of the ADC. INL is the difference between a set of dc test voltages [VIN(N)] to the corresponding set of output voltages [VOUT(N)]. Equation 9 shows the end-point method of calculating INL error. INL (ppm of FSR) = maximum absolute value of INL test series [106 · (VIN(N) – VOUT(N)) / FSR] (9) where: • • • • N = Index of dc test voltage [VIN(N)] = Set of test voltages over the range –95% to 95% of FSR [VOUT(N)] = Set of corresponding ADC output voltages FSR (full-scale range) = 2 · VREF (1x input range) or 4 · VREF (2x input range) The INL best-fit method uses a least-squared error (LSE) calculation to determine a new straight line to minimize the root-sum-square of the INL errors above and below the original end-point line. 7.10 THD Measurement Total harmonic distortion (THD) specifies the dynamic linearity of the ADC with an ac input signal. For the THD measurement, a –0.2-dBFS, 1-kHz differential input signal with VCM equal to the mid-supply voltage is applied. A sufficient number of data points are collected to yield an FFT result with frequency bin widths of 5 Hz or less. The 5-Hz bin width reduces the noise in the harmonic bins for consistent THD measurements. As shown in Equation 10, THD is calculated as the ratio of the root-sum-square amplitude of harmonics to the input signal amplitude. THD (dB) = 20 · log(VH / VIN) (10) where: • • VH = Root-sum-square of harmonics: √(V2 2+V3 2+ ...Vn 2), where Vn = Ninth harmonic voltage VIN = Input signal fundamental Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 25 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 7.11 SFDR Measurement Spurious-free dynamic range (SFDR) is the ratio of the rms value of a single-tone ac input to the highest spurious signal in the ADC frequency spectrum. SFDR measurement includes harmonics of the original signal. For the SFDR measurement, a –0.2-dBFS, 1-kHz input signal with VCM equal to the mid-supply voltage is applied. As shown in Equation 11, SFDR is the ratio of the rms values of the input signal to the single highest spurious signal, including harmonics of the original signal. SFDR (dB) = 20 · log(VIN / VSPUR) (11) where: • • VIN = Input test signal VSPUR = Single highest spurious level 7.12 Noise Performance The ADC provides two operational speed modes (high speed and low speed) that allow trade-offs between ADC resolution, power consumption, and signal bandwidth. Low-speed mode operates the modulator at 1/8th speed for decreased device power consumption and, as a result, the output data rates are reduced by 1/8th. The programmable oversampling ratio (OSR) determines the output data rate and associated signal bandwidth, and therefore also determines the total noise performance. Increasing the OSR lowers the signal bandwidth and total noise by averaging more samples from the modulator to yield one conversion result. The wideband filter provides data rates up to 400 kSPS in high-speed mode and 50 kSPS in low-speed mode. The low-latency sinc4 filter provides data rates up to 1.067 MSPS in high-speed mode and up to 133 kSPS in low-speed mode. The low-latency filter provides the options of sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1 configurations. Table 7-1 through Table 7-5 summarize the noise performance and signal bandwidth of the various filter modes. Noise performance is shown with 1x input range and a 4.096-V reference voltage. In comparison, decreasing the reference voltage to 2.5 V decreases dynamic range by 4 dB (typical). Operation in 2x input range and a 2.5-V reference voltage decreases dynamic range by 3 dB (typical) compared to 1x input range and 4.096-V reference voltage operation. The noise data are the result of the standard deviation (rms) of the conversion data with inputs shorted and biased to the mid-supply voltage and are representative of typical performance at TA = 25°C. A minimum of 1,000 or 10 seconds of consecutive conversions (whichever occurs first) are used to measure RMS noise (en). Because of the statistical nature of noise, repeated noise measurements can yield higher or lower noise results. Equation 12 converts RMS noise to dynamic range (dB) and Equation 13 converts RMS noise to effective resolution (bits). Dynamic Range (dB) = 20 · log[FSR / (2 · √2 · en)] (12) Effective Resolution (bits) = log2(FSR / en) (13) where: • FSR = 2 · VREF (1x input range) • FSR = 4 · VREF (2x input range) • en = Noise voltage (RMS) When evaluating ADC noise performance, consider the effect of external buffer and amplifier noise to the total noise performance. The noise performance of the ADC can be evaluated in isolation by selecting the input short test connection of the input multiplexer. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 7-1. Wideband Filter Performance (VREF = 4.096 V, 1x Input Range) OSR DATA RATE (kSPS) –0.1-dB FREQUENCY (kHz) NOISE (en) (µVRMS) DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) HIGH-SPEED MODE (fCLK = 25.6 MHz) 32 400 165.000 10.6 108.7 19.5 64 200 82.500 7.47 111.8 20.1 128 100 41.250 5.20 114.9 20.6 256 50 20.625 3.66 118.0 21.1 512 25 10.312 2.58 121.0 21.6 1024 12.5 5.156 1.83 124.0 22.1 2048 6.25 2.578 1.29 127.0 22.6 4096 3.125 1.289 0.92 130.0 23.1 LOW-SPEED MODE (fCLK = 3.2 MHz) 32 50 20.625 10.6 108.7 19.5 64 25 10.312 7.47 111.8 20.1 128 12.5 5.156 5.20 114.9 20.6 256 6.25 2.578 3.66 118.0 21.1 512 3.125 1.289 2.58 121.0 21.6 1024 1.5625 0.645 1.83 124.0 22.1 2048 0.78125 0.322 1.29 127.0 22.6 4096 0.390625 0.161 0.92 130.0 23.1 OSR DATA RATE (kSPS) Table 7-2. Sinc4 Filter Performance (VREF = 4.096 V, 1x Input Range) –3-dB FREQUENCY (kHz) NOISE (en) (µVRMS) DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) HIGH-SPEED MODE (fCLK = 25.6 MHz) 12 1066.666 242.666 76.3 91.6 16.7 16 800 182.000 27.3 100.5 18.2 24 533.333 121.333 10.4 108.9 19.6 32 400 91.000 7.96 111.2 20.0 64 200 45.500 5.57 114.3 20.5 128 100 22.750 3.90 117.4 21.0 256 50 11.375 2.80 120.3 21.5 512 25 5.687 1.98 123.3 22.0 1024 12.5 2.844 1.40 126.3 22.5 2048 6.25 1.422 0.99 129.3 23.0 4096 3.125 0.711 0.70 132.3 23.5 LOW-SPEED MODE (fCLK = 3.2 MHz) 12 133.333 30.333 76.3 91.6 16.7 16 100 22.750 27.3 100.5 18.2 24 66.666 15.166 10.4 108.9 19.6 32 50 11.375 7.96 111.2 20.0 64 25 5.687 5.57 114.3 20.5 128 12.5 2.844 3.90 117.4 21.0 256 6.25 1.422 2.80 120.3 21.5 512 3.125 0.711 1.98 123.3 22.0 1024 1.5625 0.355 1.40 126.3 22.5 2048 0.78125 0.177 0.99 129.3 23.0 4096 0.390625 0.089 0.70 132.3 23.5 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 27 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 7-3. Sinc4 + Sinc1 Filter Performance (VREF = 4.096 V, 1x Input Range) SINC4 OSR SINC1 OSR DATA RATE (kSPS) –3-dB FREQUENCY (kHz) NOISE (en) (µVRMS) DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) HIGH-SPEED MODE (fCLK = 25.6 MHz) 32 2 200 68.35 5.63 114.2 20.5 32 4 100 40.97 3.98 117.2 21.0 32 10 40 17.47 2.81 120.3 21.5 32 20 20 8.814 1.99 123.3 22.0 32 40 10 4.420 1.41 126.3 22.5 32 100 4 1.770 0.99 129.3 23.0 32 200 2 0.885 0.70 132.3 23.5 32 400 1 0.442 0.52 134.9 23.9 32 1000 0.4 0.177 0.39 137.4 24.3 LOW-SPEED MODE (fCLK = 3.2 MHz) 32 2 25 8.544 5.63 114.2 20.5 32 4 12.5 5.121 3.98 117.2 21.0 32 10 5 2.184 2.81 120.3 21.5 32 20 2.5 1.102 1.99 123.3 22.0 32 40 1.25 0.552 1.41 126.3 22.5 32 100 0.5 0.221 0.99 129.3 23.0 32 200 0.25 0.111 0.70 132.3 23.5 32 400 0.125 0.055 0.52 134.9 23.9 32 1000 0.05 0.022 0.39 137.4 24.3 Table 7-4. Sinc3 Filter Performance (VREF = 4.096 V, 1x Input Range) OSR DATA RATE (SPS) –3-dB FREQUENCY (Hz) NOISE (en) (µVRMS) (1) DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) HIGH-SPEED MODE (fCLK = 25.6 MHz) 26667 480 126 0.29 140.0 24.7 32000 400 105 0.27 140.6 24.8 LOW-SPEED MODE (fCLK = 3.2 MHz) 26667 60 16 0.29 140.0 24.7 32000 50 13 0.27 140.6 24.8 (1) The noise measurement may vary resulting from the effects of 24-bit quantization levels: 4.096 V / 223 = 0.488 μV / code. Table 7-5. Sinc3 + Sinc1 Filter Performance (VREF = 4.096 V, 1x Input Range) SINC3 OSR SINC1 OSR DATA RATE (SPS) –3-dB FREQUENCY (Hz) NOISE (en) (µVRMS) (1) DYNAMIC RANGE (dB) EFFECTIVE RESOLUTION (Bits) HIGH-SPEED MODE (fCLK = 25.6 MHz) 32000 3 133.3 54 0.19 143.7 25.3 32000 5 80 34 0.15 145.7 25.7 LOW-SPEED MODE (fCLK = 3.2 MHz) 32000 3 16.6 6.7 0.19 143.7 25.3 32000 5 10 4.3 0.15 145.7 25.7 (1) 28 The noise measurement may vary resulting from the effects of 24-bit quantization levels: 4.096 V / 223 = 0.488 μV / code. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8 Detailed Description 8.1 Overview The ADS127L11 is a high performance, 24-bit delta-sigma (ΔΣ) analog-to-digital converter (ADC) offering an excellent combination of dc accuracy and ac precision. The device is optimized to provide high resolution with low power consumption. Integrated input and reference precharge buffers simplify the driver requirements. The digital filter consists of two programmable modes: low-latency mode (typically used for measurement of dc signals) and wideband mode (typically used for measurement of ac signals). The delta-sigma modulator produces low-resolution, high-frequency data proportional to the signal magnitude. Noise shaping within the modulator shifts the quantization noise of the low-resolution data to an out-of-band frequency range where the noise is removed by the digital filter. The noise remaining within the pass band is white, which is reduced by the digital filter. The digital filter simultaneously decimates and filters the modulator data to provide the high-resolution final output data. The Functional Block Diagram shows the features of the ADS127L11. The modulator is a third-order, multibit delta-sigma design that measures the differential input signal, VIN = (VAINP – VAINN), against the differential reference, VREF = (VREFP – VREFN). Input and positive reference precharge buffers reduce the bandwidth and driving requirements of the external input driver. The VCM output provides a buffered mid-supply voltage to drive the common-mode voltage of an external driver stage. The digital filter offers two modes of operation: the low-latency filter and the wideband filter. The low-latency filter is programmable to sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1 modes, allowing optimization between noise performance and latency. The sinc3 + sinc1 filter provides rejection at 400 Hz, 60 Hz, 50 Hz, and 16.6 Hz. The wideband filter is a multi-tap finite impulse response (FIR) design providing outstanding frequency response with low pass-band ripple, steep transition-band, and high stop-band attenuation. Programmable oversampling ratio (OSR) and two speed modes allow optimized choices of bandwidth, resolution, and device power consumption. The SPI-compatible serial interface is used to configure the device and read conversion data. The interface features daisy-chaining capability for convenient connection of multichannel, simultaneous-sampled systems. Integrated cyclic redundancy check (CRC) error monitoring improves system-level reliability. DRDY is the conversion data-ready output signal. The device supports external clock operation for ac or dc applications, and internal oscillator operation for dc applications. The START pin synchronizes the digital filter process. The RESET pin resets the ADC. Supply voltage AVDD1 powers the precharge buffers and the input sampling switches. AVDD2 powers the modulator via an internal regulator (CAPA). Supply voltage IOVDD is the digital I/O voltage that also powers the digital core via an internal regulator (CAPD). The internal regulators minimize overall power consumption and provide consistent levels of performance. 8.2 Functional Block Diagram AVDD1 VCM REFP REFN CAPA AVDD2 ADS127L11 24-bit
Modulator AINN Wideband Filter Low-latency Filter IOVDD LDO LDO ÷2 AINP CAPD Osc Mux CLK CS SPI Interface SCLK SDI SDO/DRDY Control Logic DRDY START RESET DGND AVSS Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 29 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.3 Feature Description 8.3.1 Analog Input (AINP, AINN) The analog input of the ADC is differential, with the input defined as a difference voltage: VIN = VAINP – VAINN. For best performance, drive the input with a differential signal with the common-mode voltage centered to mid-supply (AVDD1 + AVSS) / 2. The ADC can accept either unipolar or bipolar input signals by configuring AVDD1 and AVSS accordingly. Figure 8-1 shows an example of a differential signal with the supplies configured to unipolar operation. Symmetric input voltage headroom is available when the common-mode voltage is at mid-supply (AVDD1 / 2). Use AVDD1 = 5 V and AVSS = 0 V for unipolar operation (AVDD1 can be reduced to 3 V in low-speed mode). The VCM output provides a buffered common-mode voltage to level-shift the output voltage in the external driver stage. Figure 8-2 shows an example of a differential signal configured for bipolar operation. The common-mode voltage of the signal is normally at 0 V. Use AVDD1 and AVSS = ±2.5 V for bipolar operation (AVDD and AVSS can be reduced to ±1.5 V in low-speed mode). AVDD1 AVDD1 AINP AINP VCM VCM AVDD1 / 2 0V AINN AINN AVSS AVSS = 0 V Figure 8-1. Unipolar Differential Input Signal Figure 8-2. Bipolar Differential Input Signal In both bipolar and unipolar power-supply configurations, the ADC can accept single-ended input signals by tying the AINN input to AVSS or ground, or to mid-supply. However, because AINN is now a fixed voltage, the voltage range of the ADC is limited by the input swing range of AINP (±2.5 V or 0 V to 5 V for a 5-V supply). The simplified circuit of Figure 8-3 represents the analog input structure. MUX[1:0] bits 1,0 of MUX register (address = 04h) 00b = Normal polarity (default) 01b = Inverted polarity 10b = Offset test 11b = CMRR test AINP_BUF bit 1 of CONFIG1 register (address = 05h) 0b = buffer OFF (default) 1b = buffer ON AVDD1 S9 S7 SW S1 CIN SW S2 AINP S10 Simplified input sampling network S8 SW S3 SW S5 AVSS S6 SW AVDD1 + AVSS 2 SW SW S4 AINN AINN_BUF bit 0 of CONFIG1 register (address = 05h) 0b = buffer OFF (default) 1b = buffer ON Figure 8-3. Analog Input Circuit 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Diodes protect the ADC inputs from electrostatic discharge (ESD) events that occur during the manufacturing process and during printed circuit board (PCB) assembly when manufactured in an ESD-controlled environment. If the inputs are driven below AVSS – 0.3 V, or above AVDD1 + 0.3 V, the protection diodes may conduct. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the input current to the specified value. The input multiplexer offers the option of normal or reverse input signal polarities. The multiplexer also provides two internal test modes to help verify ADC performance. The offset test mode is used to verify noise and offset error by providing a short to the ADC inputs. The resulting noise and offset voltage data are evaluated by the user. CMRR performance is tested using the CMRR test mode by applying a CMRR test signal to the AINP input. The resulting CMRR test data are also evaluated by the user. Table 8-1 shows the switch configurations of the input multiplexer circuit of Figure 8-3. Table 8-1. Input Multiplexer Configurations MUX[1:0] BITS SWITCHES 00b S1, S4 Normal polarity input DESCRIPTION 01b S2, S3 Reverse polarity input 10b S5, S6 Internal noise and offset error test 11b S1, S5 CMRR test using a signal applied to AINP The device has optional input precharge buffers to reduce the charge required by capacitor CIN during the input sampling phase. When the capacitor is near full charge, the precharge buffers are bypassed (S7 and S8 of Figure 8-3 in up positions). The external signal driver then provides the fine charge to the capacitor. At the completion of the sample phase, the sampling capacitor is discharged by the modulator to complete the cycle, at which time the sample process repeats. The buffers reduce the transient input current required to charge CIN, therefore reducing the settling time requirement of the signal. Incomplete settling of the input signal can lead to degraded ADC performance. The input buffers are enabled by the AINP_BUF and AINN_BUF bits of the CONFIG1 register. In many cases, if AINN is tied to ground or to a low-impedance fixed potential, the AINN buffer can be disabled to reduce power consumption. With the input precharge buffers disabled, the charge required by the input sampling capacitor can be modeled as an average input current flowing into the ADC inputs. As shown in Equation 14 and Equation 15, the input current is comprised of differential and absolute components. Input Current (Differential Input Voltage) = fMOD · CIN · 106 (μA/V) (14) where: • fMOD = fCLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode) • CIN = 7.4 pF (1x input range), 3.6 pF (2x input range) Input Current (Absolute Input Voltage) = fMOD·CCM · 106 (μA/V) (15) where: • fMOD = fCLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode) • CCM = 0.35 pF (1x input range), 0.17 pF (2x input range) For fMOD = 12.8 MHz, CIN = 7.4 pF, and CCM = 0.35 pF, the input current resulting from differential voltage is 95 μA/V and the input current resulting from the absolute voltage is 4.5 μA/V. For example, if AINP = 4.5 V and AINN = 0.5 V, then VIN = 4 V. The total AINP input current = (4 V · 95 μA/V) + (4.5 V · 4.5 μA/V) = 400 μA, and the total AINN current is (–4 V · 95 μA/V) + (0.5 V · 4.5 μA/V) = –378 μA. The charge demand of the input sampling capacitor requires the signal to settle within a half cycle at the modulator frequency t = 1 / (2 · fMOD). To satisfy this requirement, the driver bandwidth is typically required to be much larger than the original signal frequency. The bandwidth of the driver can be determined to be sufficient when the THD and SNR data sheet performance are achieved. In the low-speed mode of operation, the modulator sampling is eight times slower, therefore more time is available for driver settling. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 31 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.3.1.1 Input Range The ADC has two programmable input ranges: 1x and 2x, where the 1x range is defined by VIN = ±VREF and the 2x range is defined by VIN = ±2 · VREF. The 2x input range doubles the available range when using a reference voltage = 2.5 V or less. The 2x input range typically improves SNR by +1 dB, but this requires driving the inputs to the 5-V supply rails to achieve full SNR when using a 2.5-V reference voltage. The best available SNR performance (4 dB improvement typical) is by using a 4.096-V or 5-V reference voltage (be sure to program the ADC to the high-reference range mode). The 2x range operation is internally forced to the 1x range mode when the high-reference range is selected. See the CONFIG1 register to program the input range. Table 8-2 summarizes the ADC input range options. Table 8-2. ADC Input Range (1) INP_RNG BIT (1) INPUT RANGE (V) 0 ±VREF 1 ±2·VREF The input range is forced to 1x when the high-reference range is selected. In some cases, the full available input range is limited by the power supply voltage. For example, the input range exceeds the power supply voltage when using a 3-V power supply with a 2.5-V reference voltage in the 2x range mode. The ADC also provides the option of extending the input range beyond standard full-scale range. In this mode, the input range is extended by 25% to provide signal headroom before clipping of the signal occurs. Output data are scaled such that the positive and negative full-scale output codes (7FFFFFh and 800000h) are at ±1.25 · k · VREF, where k is the 1x or 2x input range option. The SNR performance degrades when the signal exceeds 110% standard full-scale range because of modulator saturation. The modulator MOD_FLAG bit of the STATUS register indicates when modulator saturation occurs. Figure 8-4 shows SNR performance when operating in the extended range. See the CONFIG2 register to program the extended range mode. 10 Relative SNR (dB) 0 -10 -20 -30 -40 -50 -60 100 105 110 115 Input Amplitude (% of FS) 120 125 Figure 8-4. Extended Range SNR Performance 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.3.2 Reference Voltage (REFP, REFN) A reference voltage is required for operation. The reference voltage input is differential, defined as: VREF = VREFP – VREFN, and applied to the REFP and REFN inputs. See the Reference Voltage Range section for details of the reference voltage operating range. As shown in Figure 8-5, the reference inputs have an input structure similar to the analog inputs. ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AVSS by more than 0.3 V, or above AVDD1 by 0.3 V. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the input current to the specified value. AVDD1 REFP_BUF bit 3 of CONFIG1 register (address = 05h) 0b = buffer OFF (default) 1b = buffer ON S2 S1 CREF REFP S3 Simplified reference sampling network REFN AVSS Figure 8-5. Reference Input Circuit The reference voltage is sampled by a sampling capacitor CREF. In unbuffered mode, current flows through the reference inputs to charge the sampling capacitor. The current consists of a dc component and an ac component that varies with the frequency of the modulator sampling clock. See the Electrical Characteristics table for the reference input current specification. The effect of charging the reference sampling capacitor requires the external reference driver to settle at the end of the sample phase t = 1 / (2 · fMOD). Incomplete settling of the reference voltage can lead to excessive gain error and gain error drift. Operation in low-speed mode reduces the modulator sampling clock frequency by 1/8th, therefore allowing more time for the reference driver to settle. The ADC provides a precharge buffer option for the REFP input to reduce the charge drawn by the sampling capacitor. The precharge buffer provides the coarse charge for the reference sampling capacitor CREF. Halfway through the sample phase, the precharge buffer is bypassed (S1 is in an up position as demonstrated in Figure 8-5), at which time the external driver provides the fine charge to the sampling capacitor. Because the buffer reduces the charge demand of the sampling capacitor, the bandwidth requirement of the external driver is greatly reduced. Many applications either ground REFN, or connect REFN to AVSS. A precharge buffer for REFN is not necessary for these cases. For applications when REFN is not a low impedance source, consider buffering the REFN input. 8.3.2.1 Reference Voltage Range The operation of the ADC is optimized by separating the reference voltage into two operating ranges: lowreference range and high-reference range. The reference voltage range must be programmed to match the applied reference voltage, such as 2.5 V or 4.096 V. The low-reference operating range is 0.5 V to 2.75 V, and the high-reference operating range is 1 V up to the AVDD1 – AVSS power supplies. For best performance where the ranges overlap, such as reference voltage = 2.5 V, use the low-reference range. Program the REF_RNG bit of the CONFIG1 register to the appropriate reference range to match the applied reference voltage. When the high-reference range is selected, the input range is internally forced to 1x. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 33 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.3.3 Clock Operation Figure 8-6 shows the block diagram of the internal clock circuit. The ADC can be operated by an external clock or the internal oscillator. The nominal value of fCLK is 25.6 MHz in high-speed mode and 3.2 MHz in low-speed mode. A divide-by-eight option is available at the CLK input to divide the high-speed mode clock frequency to provide the low-speed mode clock frequency. The clock frequency is divided by two to derive the modulator sampling clock (fMOD). ÷8 CLK 1 1 0 fCLK 0 CLK_DIV bit 6 of CONFIG4 register (address = 08h) ÷2 25.6 MHz Internal Oscillator fMOD CLK_SEL bit 7 of CONFIG4 register (address = 08h) ÷8 1 0 SPEED_MODE bit 2 of CONFIG2 register (address = 06h) Figure 8-6. Clock Block Diagram 8.3.3.1 Internal Oscillator At power-up and after reset, the ADC defaults to internal oscillator mode (CLK_SEL bit = 0b). The frequency of the internal oscillator automatically scales to high-speed or low-speed operation. Because of the clock jitter associated with the internal oscillator, the internal oscillator is only recommended for dc signal measurements. AC signal measurements are not recommended when using the internal oscillator. When changing the clock mode from an external clock to the internal oscillator, maintain the external clock for at least four cycles after completing the SPI register write command used to change the clock mode. After the clock mode changes, the ADC ignores control inputs (the START and RESET pins) for a period of 150 μs to allow time for the internal oscillator to stabilize. 8.3.3.2 External Clock To operate the ADC with an external clock, apply the clock signal to the CLK pin, then program the CLK_SEL bit to 1b. A divide-by-eight option is available to operate the ADC in low-speed mode using the high-speed mode clock frequency (set the CLK_DIV bit = 1b). The clock can be decreased from nominal to yield specific data rates between the integer OSR values. However, the conversion noise when operating at the reduced clock frequency is the same as the higher clock frequency. Reducing the conversion noise is only possible by increasing the OSR value or changing the filter mode. Clock jitter results in timing variations in the modulator sampling that leads to degraded SNR performance. A low-jitter clock is essential to meet data sheet SNR performance. For example, with a 200-kHz signal frequency, an external clock with < 10-ps (rms) jitter is required. For lower signal frequencies, the clock jitter requirement can be relaxed by –20 dB per decade of signal frequency. For example, with fIN = 20 kHz, a clock with 100-ps jitter can be used. Many types of RC oscillators exhibit high levels of jitter and should be avoided for ac signal measurement. Instead, use a crystal-based clock oscillator as the clock source. Avoid ringing on the clock input. A series resistor placed at the output of the clock buffer often helps reduce ringing. 8.3.4 Modulator The ADS127L11 uses a switched-capacitor, third-order, singe-loop modulator with a 5-bit internal quantizer. This modulator topology achieves excellent noise and linearity performance while consuming very low power. As with most high-order modulators driven by high amplitude out-of-band signals, modulator saturation can occur. When saturated, the in-band signal still converts, however the noise floor increases. Figure 8-7 illustrates the amplitude limit of out-of-band signals to avoid modulator saturation. The limit of dc and in-band signal amplitudes are 1 dB above standard full scale. 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 5 Amplitude (dBFS) 0 -5 -10 -15 -20 -25 0.01 0.1 fIN /fMOD (Hz) 1 Figure 8-7. Amplitude Limit to Avoid Modulator Saturation Modulator saturation is indicated by the MOD_FLAG bit of the STATUS register. The modulator saturation status is latched during the conversion period and is refreshed at completion of the next conversion. Modulator saturation resulting from out-of-band signals can be avoided by using an antialias filter at the ADC inputs. The Typical Application section describes an example of a fourth-order antialias filter, however a low-order filter can be used with equal effect provided the amplitude is below the saturation limit. 8.3.5 Digital Filter The digital filter low-pass filters and decimates the low-resolution, high-speed data from the modulator to produce high-resolution, low-speed output data. The programmable oversampling ratio (OSR) determines the amount of filtering that affects signal bandwidth and conversion noise, and the final data rate through decimation. The output data rate is defined by: fDATA = fMOD / OSR. The ADC offers the choice of two filter modes: wideband and low latency. The filter mode selection optimizes either the frequency response characteristics (wideband filter mode) or the time domain characteristics (lowlatency filter mode). 8.3.5.1 Wideband Filter The wideband filter is a multistage FIR filter design featuring linear phase response, low pass-band ripple, narrow transition band, and high stop-band attenuation. Because of the superior frequency response characteristics, the filter is well suited for measuring ac signals. The ADC provides eight programmable oversampling ratios (OSR) and two speed modes, offering a range of data rate and resolution to select from. 0.002 0 0.0015 -20 0.001 -40 Amplitude (dB) Amplitude (dB) Figure 8-8 through Figure 8-12 illustrate the frequency response of the wideband filter. Figure 8-8 shows the pass-band ripple. Figure 8-9 shows the detailed frequency response at the transition band. 0.0005 0 -0.0005 -60 -80 -100 -0.001 -120 -0.0015 -140 -0.002 0 0.1 0.2 0.3 0.4 Normalized Frequency (fIN /f DATA ) 0.5 Figure 8-8. Wideband Filter Pass-Band Ripple -160 0.4 0.42 0.44 0.46 0.48 Normalized Frequency (f IN /f DATA ) 0.5 0.52 Figure 8-9. Wideband Filter Transition Band Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 35 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Figure 8-10 shows the frequency response to fDATA for OSR ≥ 64. The stop band begins at fDATA / 2 to prevent aliasing at the Nyquist frequency. Figure 8-11 shows the stop-band attenuation to fMOD for OSR = 32. In the stop-band region, out-of-band input frequencies intermodulate with multiples of the chop frequency at fMOD / 32, creating a pattern of response peaks that exceed the stop-band attenuation of the digital filter. The width of the response peaks is twice the filter bandwidth. Stop-band attenuation is improved when used in conjunction with an antialias filter at the ADC input. See the Typical Application section for details of a fourth-order antialias filter. 0 0 -20 -20 -60 Amplitude (dB) Amplitude (dB) -40 -80 -100 -40 -60 -120 -80 -140 -160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Frequency (f IN /f DATA ) 0.9 1 -100 0 0.1 0.2 OSR ≥ 64 Figure 8-10. Wideband Filter Frequency Response 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Frequency (f in /f mod ) 0.9 1 OSR = 32 Figure 8-11. Wideband Filter Stop-Band Attenuation Figure 8-12 shows the filter response centered around fMOD. As shown, the filter response repeats at fMOD. If not removed by an antialiasing filter, input frequencies at fMOD appear as aliased frequencies in the pass band. Aliasing also occurs with input frequencies occurring at multiples of fMOD. These frequency bands are defined by: Alias frequency bands: (N · fMOD) ± fBW (16) where: • N = 1, 2, 3, and so on • fMOD = Modulator sampling frequency • fBW = Filter bandwidth 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 Normalized Frequency (f IN /f DATA − f MOD ) 0.8 1 Figure 8-12. Wideband Filter Frequency Response Centered at fMOD The group delay of the filter is the time for an input signal to propagate from the input to the output of the filter. Because the filter is a linear-phase design, the envelope of a complex input signal is undistorted by the filter. The group delay (expressed in units of time) is constant versus frequency equal to the value = 34 / fDATA. After a step input is applied, fully settled data occur at 68 data periods later. Figure 8-13 illustrates the filter group delay (34 / fDATA) and the settling time to a step input (68 / fDATA). 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 110 100 90 Final Value Amplitude (%) 80 70 Group Delay 60 50 40 30 20 Initial Value 10 0 -10 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 Data Periods (1\f DATA ) Figure 8-13. Wideband Filter Step Response The digital filter is restarted when the ADC is synchronized. The ADC suppresses the first 68 conversion periods until the filter is fully settled. There is no need to discard data after synchronization. The time of data suppression is the conversion latency time as listed in the latency time column of Table 8-3. A 0.4-μs fixed overhead time is incurred for all data rates. If a step input occurs asynchronous to the conversion period without synchronizing, then the next 69 conversions are partially settled data. Table 8-3. Wideband Filter Characteristics OSR DATA RATE (kSPS) –0.1-dB FREQUENCY (kHz) –3-dB FREQUENCY (kHz) LATENCY TIME (µs)(1) HIGH-SPEED MODE (fCLK = 25.6 MHz) 32 400 165 174.96 170.6 64 200 82.5 87.48 340.6 128 100 41.25 43.74 680.6 256 50 20.625 21.87 1360.6 512 25 10.312 10.935 2720.6 1024 12.5 5.156 5.467 5440.6 2014 6.25 2.578 2.734 10880.6 4096 3.125 1.289 1.367 21760.6 LOW-SPEED MODE (fCLK = 3.2 MHz) (1) 32 50 20.625 21.87 1364.8 64 25 10.312 10.935 2724.8 128 12.5 5.156 5.467 5444.8 256 6.25 2.578 2.734 10884.8 512 3.125 1.289 1.367 21764.8 1024 1.5625 0.645 0.683 43524.8 2048 0.78125 0.322 0.342 87044.8 4096 0.390625 0.161 0.171 174084.8 Latency time increases 8 / fCLK (µs) when analog input buffers are enabled. 8.3.5.2 Low-Latency Filter (Sinc) The low-latency filter is a cascaded-integrator-comb (CIC) topology that minimizes the delay (latency) as the conversion data propagates through the filter. The CIC filter is otherwise known as a sinc filter because of the characteristic sinx/x (sinc) frequency response. The latency time is shorter compared to the wideband filter, making the filter suitable for fast acquisition of dc signals. The device offers the choice of four sinc filter configurations: sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1 to provide trade-offs of acquisition time, noise performance, and line-cycle rejection. Latency is defined as the time from synchronization to the falling edge of DRDY, at which time, fully settled data are available. There is no need to discard data because the unsettled data are suppressed by the ADC. Detailed latency data for each sinc filter mode are given in Table 8-5 through Table 8-8. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 37 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 If the input is changed without synchronization, then the next conversion data are partially settled. The number of conversions required for fully settled data in this case is found by rounding the latency time value to the next whole number of conversion periods. Equation 17 is the general expression of the sinc-filter frequency response. For single-stage sinc filter options (for example, the single-stage sinc3 or sinc4 filter), the second stage is not used. n sin Aπf fMOD H(f) = Asin ABπf fMOD sin Bsin Aπf fMOD πf fMOD (17) where: • f = Signal frequency • A = Stage 1 OSR • B = Stage 2 OSR • fMOD = fCLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode) • n = Order of the stage 1 filter (3 or 4) 8.3.5.2.1 Sinc4 Filter The sinc4 filter averages and decimates the high-speed modulator data to yield data rates from 1066.6 kSPS to 3.125 kSPS in high-speed mode, and data rates from 133.333 kSPS to 0.390625 kSPS in low-speed mode. Increasing the OSR value decreases the data rate and simultaneously reduces signal bandwidth and total noise resulting from increased decimation and data averaging. Because of the reduced amount of data averaging performed in the filtering process for OSR values = 12, 16 and 24, the output resolution of the corresponding data rates is reduced. Table 8-4 summarizes the output data resolution for these OSR values. Table 8-4. Sinc4 Data Resolution OSR DATA RATE (kSPS) 12 RESOLUTION (bits) 1066.666 19 16 800 20.5 24 533.333 23 ≥32 ≤400 24 Table 8-5 lists the sinc4 filter characteristics. Table 8-5. Sinc4 Filter Characteristics OSR DATA RATE (kSPS) –3-dB FREQUENCY (kHz) LATENCY TIME (µs)(1) HIGH-SPEED MODE (fCLK = 25.6 MHz) 38 12 1066.666 242.666 4.38 16 800 182 5.63 24 533.333 121.333 8.13 32 400 91.0 10.63 64 200 45.5 20.63 128 100 22.75 40.63 256 50 11.375 80.63 512 25 5.687 160.63 1024 12.5 2.844 320.63 2048 6.25 1.422 640.63 4096 3.125 0.711 1280.63 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 8-5. Sinc4 Filter Characteristics (continued) OSR DATA RATE (kSPS) –3-dB FREQUENCY (kHz) LATENCY TIME (µs)(1) LOW-SPEED MODE (fCLK = 3.2 MHz) (1) 12 133.333 30.333 35.04 16 100 22.75 45.04 24 66.666 15.166 65.04 32 50 11.375 85.04 64 25 5.687 165.04 128 12.5 2.844 325.04 256 6.25 1.422 645.04 512 3.125 0.711 1285.04 1024 1.5625 0.355 2565.04 2048 0.78125 0.177 5125.04 4096 0.390625 0.089 10245.04 Latency time increases 8 / fCLK (µs) when analog input buffers are enabled. 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) Figure 8-14 and Figure 8-15 show the sinc4 filter frequency response at OSR = 32. The frequency response consists of a series of response nulls occurring at discrete frequencies. The null frequencies occur at multiples of fDATA. At the null frequencies, the filter has zero gain. A folded image of the overall frequency response appears at multiples of fMOD, as illustrated in the fMOD frequency plot of Figure 8-15. No attenuation is provided by the filter at input frequencies near n · fMOD (n = 1, 2, 3, and so on), and if present, alias into the pass band. -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 1 2 3 Normalized Frequency (f IN /f DATA ) 4 Figure 8-14. Sinc4 Frequency Response (OSR = 32) 0 4 8 12 16 20 24 Normalized Frequency (fIN /f DATA ) 28 32 Figure 8-15. Sinc4 Frequency Response to fMOD (OSR = 32) 8.3.5.2.2 Sinc4 + Sinc1 Filter The sinc4 + sinc1 filter is the cascade of two filter sections: sinc4 and sinc1. The OSR of the sinc4 stage is a constant value (32) and the programmable OSR of the sinc1 stage determines the output data rate. The sinc4 + sinc1 filter mode has comparably less latency time than that of the single-stage sinc4 filter. Table 8-6 summarizes the sinc4 + sinc1 filter characteristics. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 39 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 8-6. Sinc4 + Sinc1 Filter Characteristics SINC4 OSR SINC1 OSR DATA RATE (kSPS) –3-dB FREQUENCY (kHz) LATENCY TIME (µs)(1) HIGH-SPEED MODE (fCLK = 25.6 MHz) 32 2 200 68.35 13.13 32 4 100 40.97 18.13 32 10 40 17.47 33.13 32 20 20 8.814 58.13 32 40 10 4.420 108.13 32 100 4 1.770 258.13 32 200 2 0.885 508.13 32 400 1 0.442 1008.13 32 1000 0.4 0.177 2508.13 LOW-SPEED MODE (fCLK = 3.2 MHz) (1) 32 2 25 8.544 105.04 32 4 12.5 5.121 145.04 32 10 5 2.184 265.04 32 20 2.5 1.102 465.04 32 40 1.25 0.552 865.04 32 100 0.5 0.221 2065.04 32 200 0.25 0.111 4065.04 32 400 0.125 0.055 8065.04 32 1000 0.05 0.022 20065.04 Latency time increases 8 / fCLK (µs) when analog input buffers are enabled. Figure 8-16 shows the frequency response of the sinc4 + sinc1 filter for three values of OSR. The combined frequency response is the overlay of the sinc1 filter with the sinc4 filter. For low values of OSR, the response profile is dominated by the rolloff of the sinc4 filter. Nulls in the frequency response occur at n · fDATA, n = 1, 2, 3, and so on. At the null frequencies, the filter has zero gain. 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 OSR = 2 OSR = 20 OSR = 200 -140 -160 0 1 2 3 4 Normalized Frequency (f IN /f DATA ) 5 6 Figure 8-16. Sinc4 + Sinc1 Frequency Response 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.3.5.2.3 Sinc3 Filter The sinc3 filter mode is a single-stage filter. Relatively high values of OSR provide line-cycle rejection with data rates = 480 SPS, 400 SPS, 60 SPS, and 50 SPS. Because of the large width of the frequency response notch, excellent line-frequency NMRR and CMRR can be achieved with this filter. Table 8-7 summarizes the characteristics of the sinc3 filter. Table 8-7. Sinc3 Filter Characteristics DATA RATE (SPS) OSR –3-dB FREQUENCY (Hz) REJECTION OF FIRST NULL (dB) LATENCY (ms) 2% CLOCK TOLERANCE 6% CLOCK TOLERANCE HIGH-SPEED MODE (fCLK = 25.6 MHz) 26667 480 126 6.25 100 71 32000 400 105 7.50 100 71 LOW-SPEED MODE (fCLK = 3.2 MHz) 26667 60 15.7 50.01 100 71 32000 50 13.1 60.01 100 71 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) Figure 8-17 shows the frequency response of the sinc3 filter (OSR = 32000). Figure 8-18 shows the detailed response in the region of 0.9 to 1.1 · fIN / fDATA. -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 0 0.5 1 1.5 2 2.5 3 3.5 4 Normalized Frequency (f IN /f DATA ) 4.5 5 Figure 8-17. Sinc3 Frequency Response (OSR = 32000) -160 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 Normalized Frequency (f IN /f DATA ) 1.1 Figure 8-18. Detail Sinc3 Frequency Response (OSR = 32000) 8.3.5.2.4 Sinc3 + Sinc1 Filter The sinc3 + sinc1 filter mode is the cascade of the sinc3 and the sinc1 filter. The OSR of the sinc3 stage is fixed (32000) and the OSR of the sinc1 stage is programmable to 3 and 5. Table 8-8 summarizes the characteristics of the sinc3 + sinc1 filter. Table 8-8. Sinc3 + Sinc1 Filter Characteristics SINC3 OSR SINC1 OSR DATA RATE (SPS) REJECTION OF FIRST NULL (dB) –3-dB FREQUENCY (HZ) LATENCY (ms) 2% CLOCK TOLERANCE 6% CLOCK TOLERANCE HIGH-SPEED MODE (fCLK = 25.6 MHz) 32000 3 133.3 54 12.5 37 26 32000 5 80 34 17.5 37 26 LOW-SPEED MODE (fCLK = 3.2 MHz) 32000 3 16.7 6.7 100.1 34 26 32000 5 10 4.2 140.01 34 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 41 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) Figure 8-19 shows the frequency response of the sinc3 + sinc1 filter. The frequency response exhibits the characteristic sinc filter response lobes and nulls. The nulls occur at fDATA and at multiples thereof. Figure 8-20 shows the detailed response in the region of 0.9 to 1.1 · fIN / fDATA. -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 0 1 2 3 4 5 6 7 Normalized Frequency (f IN /f DATA ) 8 -160 0.9 9 Figure 8-19. Sinc3 + Sinc1 Frequency Response 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 Normalized Frequency (f IN /f DATA ) 1.1 Figure 8-20. Detail Sinc3 + Sinc1 Frequency Response 8.3.6 Power Supplies The device has three analog power-supply pins (AVDD1, AVSS, and AVDD2) and one digital power-supply pin (IOVDD). The power supplies can be sequenced in any order and are tolerant of slow or fast power-supply voltage ramp rates. However, in no case must any analog or digital input exceed the respective AVDD1 and AVSS (analog) or IOVDD (digital) power supply. 8.3.6.1 AVDD1 and AVSS AVDD1 and AVSS power the precharge buffers and the internal sampling switches. The ADC can be configured either for bipolar input operation (such as using ±2.5-V power supplies), or for unipolar input operation (such as AVDD1 = 5 V and AVSS = DGND). Use a parallel combination of 1-µF and 0.1-µF bypass capacitors across the AVDD1 supply voltage and the AVSS pin, with a 3-Ω series resistor placed in series between the capacitors and the AVDD1 pin. Place the resistor and capacitors as close as possible to the AVDD1 pin. 8.3.6.2 AVDD2 AVDD2 is with respect to AVSS and powers the modulator core. AVDD2 can be connected to AVDD1 to simplify the required supply voltages, or AVDD2 can be operated by a lower supply voltage to minimize device power consumption. Use a combination of 1-µF and 0.1-µF bypass capacitors across the AVDD2 to AVSS supply pins. Table 8-9 shows examples of AVDD1, AVSS, and AVDD2 power-supply configurations. Table 8-9. AVDD1, AVSS, and AVDD2 Power-Supply Voltages (All Voltages with Respect to DGND) HIGH-SPEED MODE LOW-SPEED MODE SUPPLY CONFIGURATION AVDD1 AVSS AVDD2 AVDD1 AVSS AVDD2 Unipolar 5V 0V 1.8 V to 5 V 3 V to 5 V 0V 1.8 V to 5 V Bipolar 2.5 V –2.5 V 0 V to 2.5 V 1.5 V to 2.5 V –1.5 V to –2.5 V 0.3 V to 2.5 V 8.3.6.3 IOVDD IOVDD is the digital I/O supply voltage pin for the device. IOVDD is internally regulated to 1.25 V to supply power to the digital core. Bypass IOVDD to DGND with a parallel combination of 1-µF and 0.1-µF capacitors. The voltage level of IOVDD is independent of the analog supply configuration. 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.3.6.4 Power-On Reset (POR) The ADC uses power-supply monitors to detect power-up and supply brownout events. Power-up or powercycling of the IOVDD digital supply results in device reset. Power-up or power-cycling of the analog power supplies does not reset the ADC. Figure 8-21 shows the digital power-on thresholds of the IOVDD and the internal CAPD voltages. When the voltages are above their respective thresholds, the ADC is released from reset. DRDY later transitions high when the SPI is ready for communication. If the START pin is high, the ADC immediately begins conversions with the DRDY pin pulsing for each conversion. However, valid conversion data only occur after the power supplies and reference voltage are stabilized. The POR_FLAG bit of the STATUS register indicates the device POR. Write 1b to clear the bit in order to detect the next POR event. IOVDD – DGND 1.56 V typ. VCAPD – DGND 1.25 V typ. + – + – POR_FLAG latched ALV_FLAG latched DRDY SPI Ready Figure 8-21. Digital Supply Threshold Figure 8-22 shows the power-on thresholds of the analog power supplies. Four monitors are used for four analog supply voltage conditions (AVDD1 – DGND), (AVDD1 – AVSS), (AVDD2 – AVSS), and (CAPA – AVSS). Valid conversion data are available after all power supplies and the reference voltage are stabilized after power-on. The ALV_FLAG bit of the STATUS register sets when any analog power voltage falls below the respective threshold. Write 1b to clear the bit to detect the next analog supply low-voltage condition. Power cycling the analog power supplies does not reset the ADC. Because a low voltage on the IOVDD supply also resets the internal analog LDO (CAPA), the analog low-voltage flag (ALV_FLAG) is also set. AVDD1 – AVSS 2.17 V typ. AVDD1 – DGND 1.31 V typ. AVDD2 – AVSS 1.38 V typ. VCAPA – AVSS 1.21 V typ. + – + – + – + – ALV_FLAG latched Figure 8-22. Analog Supply Threshold 8.3.6.5 CAPA and CAPD CAPA and CAPD are the output voltages of the internal analog and digital voltage regulators. The regulators are used to reduce the supply voltage to operate internal sub-circuits and are not designed to drive external loads. CAPA is the analog regulator voltage output and is powered from AVDD2. The output voltage is 1.6 V with respect to AVSS. Bypass CAPA with a 1-µF capacitor to AVSS. CAPD is the digital regulator voltage output, powered from IOVDD. The regulator output is 1.25 V with respect to DGND. Bypass CAPD with a 1-µF capacitor to DGND. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 43 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.3.7 VCM Output Voltage The VCM pin provides a buffered output voltage at the mid-point of the AVDD1 – AVSS power supply. The VCM voltage is intended to drive the output common-mode control input of a fully differential amplifier (FDA) to establish the common-mode voltage for the ADC input signal. With many types of FDAs, the same commonmode voltage is provided when the common-mode control input of these devices are floated when using the same power supply. If VCM is not used, the pin can be left unconnected. The VCM output is enabled by the VCM bit of the CONFIG1 register. 8.4 Device Functional Modes 8.4.1 Power-Scalable Speed Modes The ADC offers two power-scalable speed modes that determine the range of conversion data rates and power consumed by the ADC. The modes allow optimization of signal bandwidth, data rate, and power consumption. High-speed mode provides maximum data rate and signal bandwidth, and low-speed mode minimizes power consumption for applications that do not require large signal bandwidths. The ADC clock frequency must be adapted to the operating mode. For high-speed mode the clock frequency is 25.6 MHz, and for low-speed mode the clock frequency is 3.2 MHz (see the Clock Operation section for the internal clock divider option). The speed mode is programmed by the SPEED_MODE bit of the CONFIG2 register. 8.4.2 Idle Mode When conversions are stopped, the ADC can be programmed to remain in a full-powered idle mode or enter a low-power standby mode. In idle mode, the analog circuit remains fully operational, including sampling of the signal and voltage reference inputs. Only the digital filter is forced inactive. When conversions are restarted, the digital filter is reactivated to begin the conversion process. Idle mode (default) is programmed by the STBY_MODE bit of the CONFIG2 register. 8.4.3 Standby Mode The ADC has the option of engaging the standby mode when conversions are stopped. Standby mode is an automatic power-down mode enabled by the STBY_MODE bit of the CONFIG2 register. Standby is entered and exited when conversions stop and start, respectively. During standby, sampling of the signal and reference voltage are stopped. When conversions are restarted, sampling of the signal and reference voltages resume. Exiting standby mode requires an additional 24 clock cycles to the normal conversion latency time. 8.4.4 Power-Down Mode Power-down mode is engaged by setting the PWDN bit of the CONFIG2 register. In power-down mode, the analog and digital sections are powered off, except for a small bias current required to maintain SPI operation needed to exit power-down mode by clearing the register bit. The digital LDO also remains active to maintain user register settings. The sampling of the signal and voltage reference are stopped during power-down mode. Exit power-down mode by writing 0b to the PWDN bit or by resetting the device. 8.4.5 Reset The ADC performs an automatic reset at power-on and can also be manually reset by the RESET pin or SPI operation. At reset the control logic, digital filter, and SPI restart and the user registers reset to the default values. See Figure 6-3 for details when the ADC is available for operation after reset. 8.4.5.1 RESET Pin The RESET pin is an active low input. The ADC is reset by taking RESET low then back high. Because the RESET pin has an internal 20-kΩ pullup resistor, RESET can be left unconnected if not used. The RESET pin is a Schmitt-triggered input designed to reduce noise sensitivity. See Figure 6-3 for RESET pin timing and for the start of SPI communications after reset. Because the ADC performs an automatic reset at power-on, a reset is not required after device power-on. 44 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.4.5.2 Reset by SPI Register Write The device is reset through SPI operation by writing 01011000b to the CONTROL register. Writing any other value to this register does not result in reset. In 4-wire SPI mode, reset takes effect at the end of the frame at the time CS is taken high. In 3-wire SPI mode, reset takes effect on the last falling edge of SCLK of the register write operation. Reset in 3-wire SPI mode requires that the SPI is synchronized to the SPI host. If SPI synchronization is not assured, use the pattern described in the Reset by SPI Input Pattern section to reset the device. Reset can be validated by checking the POR_FLAG of the STATUS register. 8.4.5.3 Reset by SPI Input Pattern The device is also reset through SPI operation by inputting a special bit pattern. The input pattern does not follow the input command format. There are two input patterns in which to reset the ADC. Pattern 1 consists of a minimum 1023 consecutive ones followed by one zero. The device resets on the falling edge of SCLK when the final zero is shifted in. This pattern can be used for either 3- or 4-wire SPI modes. Figure 8-23 shows a pattern 1 reset example. CS 1 1024 SCLK Reset SDI Figure 8-23. Reset Pattern 1 (3-Wire or 4-Wire SPI Mode) Reset pattern 2 is only for use with the 4-wire SPI mode. To reset, input a minimum of 1024 consecutive ones (no ending zero value), followed by taking CS high at which time reset occurs. Use pattern 2 when the devices are connected in daisy-chain mode. Figure 8-24 shows a pattern 2 reset example. CS Reset 1 1024 SCLK SDI Figure 8-24. Reset Pattern 2 (4-Wire SPI Mode) 8.4.6 Synchronization Conversions are synchronized and controlled by the START pin or, optionally, through SPI operation. If controlling conversions through SPI operation, keep the START pin low to avoid contention with the pin. Writing to any register from 04h through 0Eh causes the conversion to restart, thus resulting in loss of synchronization. Resynchronization of the ADC may be necessary in this case. The ADC has three modes to synchronize and control conversions: synchronized, start/stop, and oneshot modes, each with specific functionalities. Program the selected mode of synchronization by the START_MODE[1:0] bits of the CONFIG2 register. Only the start/stop and one-shot control modes can be controlled through SPI operation. After the ADC is synchronized, the first conversion is fully settled data but incurs a delay (latency time) compared to the normal data period. This latency is needed to account for full settling of the digital filter. The latency time depends on the data rate and the filter mode (see the Digital Filter section for filter latency details). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 45 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.4.6.1 Synchronized Control Mode In synchronized control mode, the ADC converts continuously regardless if START is high or low. The ADC is synchronized on the rising edge of START. When synchronized, the first DRDY falling edge is delayed to account for the filter settling time (latency time). Both a single-pulse input and a continuous-clock input can be applied to the START pin in this mode. The ADC synchronizes at the rising edge of START. If the time to the next rising edge of START is an n multiple of the conversion period, within a ±1 / fCLK window, the ADC does not resynchronize (n = 1, 2, 3, and so on). Synchronization does not occur because the ADC conversion period is already synchronized to the period of the START signal. If the period of the START signal is not an n multiple of the conversion period, the ADC resynchronizes. As a result of the propagation delay of the digital filter, a phase difference exists between the START signal and the DRDY output. Figure 8-25 shows synchronization to the START signal when the period of START pulses is not equal to an n multiple of the conversion period. START pin 1/fDATA DRDY latency latency Figure 8-25. Synchronized Control Mode 8.4.6.2 Start/Stop Control Mode Start/stop control mode is a gate-control mode used to start and stop conversions. Conversions are started by taking the START pin high or, if conversions are controlled through SPI operation, by writing 1b to the START bit of the CONTROL register. Preclear the CONTROL register by writing 00h before setting the START bit. Conversions continue until stopped by taking the START pin low, or by writing 1b to the STOP bit through SPI operation. DRDY is driven high at conversion start and is driven low when each conversion data are ready. If START is taken low or 1b is written to the STOP bit while conversions are in progress, the ongoing conversion finishes as normal and then stops. (See Figure 6-4 for detailed START timing). To restart an ongoing conversion, pulse START low to high, or write 1b to the START bit a second time. Figure 8-26 shows the START and DRDY operation. If conversions are stopped in standby mode, DRDY returns high three clock cycles after falling low, otherwise DRDY remains low until being forced high at the eighth SCLK edge during conversion data readout. If data are not read, DRDY remains low and pulses high just before the next DRDY falling edge. START bit = 1b START bit = 1b START pin or START/STOP bits STOP bit = 1b 1/fDATA DRDY (Idle mode) idle latency standby DRDY (Standby mode) latency Figure 8-26. Start/Stop Control Mode 46 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.4.6.3 One-Shot Control Mode One-shot control mode initiates a single conversion when START is taken high or, through SPI operation, when the START bit of the CONTROL register is set to 1b. DRDY drives high to indicate the conversion is started and drives low when the conversion is complete. Data are available for readback at that time. Taking START low, or writing 1b to the STOP bit, does not interrupt the ongoing conversion. The STOP bit has no effect. To restart the conversion, pulse START low to high, or write 1b to the START bit a second time. Figure 8-27 shows the one-shot control mode operation. In standby mode, DRDY returns high three clock cycles after transitioning low, otherwise DRDY remains low until forced high at the next rising edge of START. START bit = 1b START bit = 1b START pin or START bit DRDY (Idle mode) latency idle latency standby DRDY (Standby mode) Figure 8-27. One-Shot Control Mode 8.4.7 Conversion-Start Delay Time A programmable delay time is provided to delay the start of the conversion cycle after the START pin or START bit is asserted. This delay time allows for settling of external components, such as the voltage reference after exiting standby mode, or for additional settling time when switching the signal through an external multiplexer. After the initial delay time, subsequent conversions are not delayed. The programmed value of this delay time adds to the value of the conversion latency time of the digital filter. See the DELAY[2:0] bits of the CONFIG3 register for programming details. 8.4.8 Calibration The ADS127L11 provides the ability to calibrate offset and gain errors by using user-programmable offset and gain correction registers. As shown in Figure 8-28, the 24-bit offset correction value is subtracted from the conversion data before being multiplied by the 24-bit gain correction value. Output data are rounded to the final resolution (16- or 24-bit) and clipped to +FS and –FS code values after the scaling operation. DATA bit 3 of CONFIG4 register (register address = 08h) 0b = 24 bit 1b = 16 bit VAINN ADC VAINP ADC Digital Filter + Σ Data clipped and rounded to width - Final Output 1/400000h OFFSET registers (register addresses = 09h, 0Ah, 0Bh) GAIN registers (register addresses = 0Ch, 0Dh, 0Eh) Figure 8-28. Calibration Block Diagram Equation 18 shows how conversion data are calibrated: Final Output Data = (Data – OFFSET) × GAIN / 400000h (18) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 47 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 9h, Ah, Bh) The offset calibration value is a 24-bit value consisting of three 8-bit registers coded in 2's-complement format. The offset value is subtracted from the conversion data. Register 09h is the most-significant byte, register 0Ah is the middle byte, and register 0Bh is the least-significant byte. If the ADC is programmed to provide 16-bit resolution, the least-significant offset byte provides sub-LSB offset accuracy. Table 8-10 shows example offset calibration values. Table 8-10. Offset Calibration Values OFFSET CALIBRATION VALUE OFFSET APPLIED 000010h –16 LSB 000001h –1 LSB FFFFFFh 1 LSB FFFFF0h 16 LSB 8.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh) The gain calibration value is a 24-bit value consisting of three 8-bit registers coded in straight binary format and normalized to unity gain at 400000h. Register 0Ch is the most-significant byte, register 0Dh is the middle byte, and register 0Eh is the least-significant byte. For example, to correct a gain error greater than 1, the calculated gain calibration value is less than 400000h. Table 8-11 shows example gain calibration values. Table 8-11. Gain Calibration Values GAIN CALIBRATION VALUE GAIN APPLIED 433333h 1.05 400000h 1 3CCCCCh 0.95 8.4.8.3 Calibration Procedure The recommended calibration procedure is as follows: 1. Preset the offset and gain calibration registers to 000000h and 400000h, respectively. 2. Perform offset calibration by shorting the ADC inputs, or short the inputs at the system level to include the offset error of the external amplifier stages. Acquire conversion data and write the average value of the data to the offset calibration registers. Averaging the data reduces conversion noise to improve calibration accuracy. 3. Perform gain calibration by applying a calibration signal to the ADC input or at the system level to include the gain error of the external buffer stages. For the standard input range mode, choose the calibration voltage to be less than the full-scale input range to avoid clipping the output code. Clipped output codes result in inaccurate calibration. For example, use a 3.9-V calibration signal with VREF = 4.096 V. When operating in the extended range mode, the calibration signal can be equal to VREF without causing clipped output codes. Acquire conversion data and average the results. Use Equation 19 to calculate the gain calibration value. Gain Calibration Value = (expected output code / actual output code) · 400000h (19) For example, the expected output code of a 3.9-V calibration voltage using a 4.096-V reference voltage is: (3.9 V / 4.096 V) · 7FFFFFh = 79E000h. 48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.5 Programming 8.5.1 Serial Interface (SPI) The serial interface is used to read conversion data, configure device registers, and control ADC conversions. The optional CRC mode is used to validate error-free data transmission between the host and ADC. A separate CRC based on the register map is used to detect register map changes after the initial register data are loaded. The serial interface consists of four lines: CS, SCLK, SDI, and SDO/DRDY. The interface operates in the peripheral mode (passive) where SCLK is driven by the host. The interface is compatible to SPI mode 1 (CPOL = 0 and CPHA = 1). In SPI mode 1, SCLK idles low, and data are updated on SCLK rising edges and read on SCLK falling edges. The interface supports full-duplex operation, meaning input data and output data can be transmitted simultaneously. The interface also supports daisy-chain connection of multiple ADCs to simplify the SPI connection. 8.5.1.1 Chip Select (CS) CS is an active-low input that enables the interface for communication. The communication frame is started by taking CS low and is ended by taking CS high. When CS is taken high, the device ends the frame by interpreting the last 16-bits of input data (24 bits in CRC mode) regardless of the total number of bits shifted in. When CS is high, the SPI interface resets, commands are blocked, and SDO/DRDY enters a high-impedance state. DRDY is an active output regardless of the state of CS. CS can be tied low to operate the interface in 3-wire SPI mode. 8.5.1.2 Serial Clock (SCLK) SCLK is the serial clock input used to shift data into and out of the ADC. Output data are updated on the rising edge of SCLK and input data are latched on the falling edge of SCLK. SCLK is a Schmitt-triggered input designed to increase noise immunity. Even though SCLK is noise resistant, keep SCLK as noise-free as possible to avoid unintentional SCLK transitions. Avoid ringing and overshoot on the SCLK input. A series termination resistor at the SCLK driver can often reduce ringing. 8.5.1.3 Serial Data Input (SDI) SDI is the serial interface data input. SDI is used to input data to the device. Input data are latched on the falling edge of SCLK. SDI can be idled high or low when not active. 8.5.1.4 Serial Data Output/Data Ready (SDO/DRDY) SDO/DRDY is a dual-function output pin. This pin is programmable to provide output data only, or to provide output data and the data-ready indication. The dual-function mode multiplexes output data and data-ready operations on a single pin. Output data are updated on the rising edge of SCLK. The SDO/DRDY pin is in a high-Z state when CS is high. See the SDO/DRDY section for details of dual-function operation. The SDO_MODE bit of the CONFIG2 register programs the mode. 8.5.2 SPI Frame Communication through the serial interface is based on the concept of frames. A frame consists of a prescribed number of SCLKs required to shift in or shift out data. A frame is started by taking CS low and is ended by taking CS high. When CS is taken high, the device interprets the last 16 bits (or 24 bits in CRC mode) of input data regardless of the amount of data shifted into the device. In typical use, the input frame is sized to match the output frame by padding the frame with leading zeros if needed. However, if not transmitting and receiving data in full-duplex mode, the input data frame can be the minimum size of 16 bits (or 24 bits in CRC mode). The output frame size, as given in Table 8-12, depends on the programmed data resolution (16 or 24 bits) and optional STATUS header and CRC bytes. After the ADC is powered up or reset, the default output frame size is 24 bits. In 3-wire SPI mode, the input frame must match the size of the output frame for the SPI to remain synchronized. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 49 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 8-12. Output Frame Size RESOLUTION STATUS BYTE CRC BYTE FRAME SIZE 24 bit No No 24 bit 24 bit No Yes 32 bit 24 bit Yes No 32 bit 24 bit Yes Yes 40 bit 16 bit No No 16 bit 16 bit No Yes 24 bit 16 bit Yes No 24 bit 16 bit Yes Yes 32 bit 8.5.3 SPI CRC The SPI cyclic redundancy check (CRC) is an SPI check code used to detect transmission errors to and from the host controller. A CRC byte is transmitted with the ADC input data by the host and a CRC byte is transmitted with the output data by the ADC. The SPI CRC error check is enabled by the SPI_CRC bit of the CONFIG4 register. The CRC code is calculated by the host on the two command bytes. Any input bytes padded to the start of the frame are not included in the CRC calculation. The ADC checks the input command CRC code against an internal code calculated over the two input command bytes. If the CRC codes do not match, the command is not executed and the SPI_ERR bit is set in the STATUS byte. Register write operations are blocked except to the STATUS register to allow clearing the SPI CRC error by writing 1b to the SPI_ERR bit. Register read operations are not blocked unless an SPI_CRC error is detected in the immediately preceding register-read command frame. The number of bytes used to calculate the output CRC code depends on the amount of data bytes transmitted in the frame. All data bytes that precede the output CRC code are used in the CRC calculation. Table 8-13 shows the number of bytes used for the output CRC calculation. Table 8-13. Byte Count of Output CRC Code BYTE COUNT BYTE FIELD DESCRIPTION 2 16 bits of conversion data 2 One byte of register data + 00h pad byte 3 16 bits of conversion data + STATUS byte 3 24 bits of conversion data 3 One byte of register data + two 00h pad bytes 4 24 bits of conversion data + STATUS byte 4 One byte of register data + three 00h pad bytes The CRC code calculation is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the variablelength argument with the CRC polynomial. The CRC is based on the CRC-8-ATM (HEC) polynomial: X8 + X2 + X1 + 1. The nine coefficients of the polynomial are: 100000111. The input argument is XORed with FFh allowing error detection in the event that SDI or SDO/DRDY fail low. The following procedure is used to compute the CRC code value: 1. Left shift the initial data value by eight bits by appending 0s in the LSB, creating a new data value. 2. XOR the MSB of the new data value from step 1 with FFh. 3. Align the MSB of the CRC polynomial (100000111) to the left-most, logic 1 of the data. 4. The bits of the data value that are not in alignment with the CRC polynomial drop down and append to the right of the new XOR result. XOR the data value with the aligned CRC polynomial. The XOR operation creates a new, shorter-length value. 50 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 5. If the XOR result is less than 100h, the procedure ends, yielding the 8-bit CRC code result. Otherwise, continue with the XOR operation at step 3 using the current XOR result. The number of loop iterations depend on the value of the initial data. 8.5.4 Register Map CRC The register map CRC is used to check the register map contents for unintended changes. Write a new register map CRC code to the CRC register whenever the registers are changed. The CRC code is calculated over the 00h to 0Eh register addresses, skipping the 02h and 03h addresses (STATUS and CONTROL registers). The ADC continuously compares the CRC code written to the CRC register to an internal value. If the values do not match, the REG_ERR bit in the STATUS register is set. If set, correct the register values or update the CRC code then write 1b to the bit to clear the error flag. No other action is taken by the ADC in the event of a register map error. The register map CRC check is optional and is enabled by the REG_CRC bit of the CONFIG4 register. Read the REV_ID register of the individual ADC when calculating the CRC code because the REV_ID can change during device production without notice. Set the REG_CRC bit to 1 (enabled) when calculating the CRC code because this bit must be set to enable the CRC check. The register map CRC code computation is the same as the one shown in the SPI CRC section. 8.5.5 Full-Duplex Operation The serial interface supports full-duplex operation. Full-duplex operation allows the simultaneous transmission and reception of data in one frame. For example, the register read command for the next register can be input at the same time that data of the previously addressed register are output, which doubles the throughput when reading multiple registers. An example of full-duplex operation is illustrated in Figure 8-30. 8.5.6 Device Commands Commands are used to read and write register data. The register map of Table 8-16 consists of a series of one-byte registers, accessible by read and write operations. The minimum frame length of the input command sequence is two bytes (three bytes in CRC mode). If desired, the input command sequence can be padded with leading zeros to match the length of the output data frame. In CRC mode, the device interprets the two bytes immediately preceding the CRC byte at the end of the frame. Table 8-14 shows the ADS127L11 device commands. Table 8-14. SPI Commands DESCRIPTION BYTE1 BYTE2 BYTE 3 (Optional CRC Byte) No operation 00h 00h D7h Read register command 40h + address [3:0] don't care CRC of byte 1 and byte 2 Write register command 80h + address [3:0] register data CRC of byte 1 and byte 2 There are special extended-length bit patterns that are longer than the standard command length. These patterns are used to reset the ADC and to reset the frame in three-wire SPI operation. The extended bit patterns are explained in the Reset by SPI Input Pattern and 3-Wire SPI Mode sections. 8.5.6.1 No-Operation The no-operation command bytes are 00h and 00h. Use this command if no input command is desired. If the SPI CRC check is enabled, the CRC byte is required (byte 3), which is always D7h for bytes 00h and 00h. SDI can be held low during data readback, but in CRC mode the SPI_ERR flag is set, which blocks future register write operations. The SPI_ERR flag can be ignored while reading conversion data until the next register write operation. At that point, the SPI_ERR flag of the STATUS register must be manually cleared by writing 1b. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 51 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.5.6.2 Read Register Command The read register command is used to read register data. The command follows an off-frame protocol in which the read command is sent in one frame and the ADC responds with register data in the next frame. The first byte of the command is the base command value (40h) added to the 4-bit register address. The value of the second command byte is arbitrary, but is used together with the first byte for the CRC. The response to registers outside the valid address range is 00h. The register data format is most-significant-bit first. Figure 8-29 shows an example of reading register data using the 16-bit output frame size. Frame 1 is the command frame and frame 2 is the data response frame. The frames are delimited by taking CS high. The data response frame is padded with 00h after the register data byte to fill the 16-bit frame. If desired, the data response frame can be shortened after the data byte by taking CS high. If operating in full-duplex mode (such as a simultaneous read of 24-bit conversion data during the input of the register read command), pad the command frame with a leading 00h value to match the length of the data response frame. When configuring multiple registers, full-duplex operation can be used to double the throughput of the read register operations by inputting the next read register command during the data response frame of the previous register. Frame 1 CS Frame 2 16 8 8 16 SCLK SDI SDO/DRDY A. B. 40h + Address[3:0] (A) Data (B) Arbitrary 00h 00h Data (B) Reg data 00h pad Previous state of SDO/DRDY before first SCLK. Data are either 16 bits of conversion data, or if the read register command is sent in the prior frame, the data field is the register data byte + 00h. Figure 8-29. Read Register Data, Minimum 16-Bit Frame Size 52 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Figure 8-30 shows an example of the read register operation using the maximum 40-bit frame size in full-duplex operation. In frame 1, conversion data are output at the same time as the input of the read register command (if the previous frame was not a read register command). The input command is padded with two don't care bytes in order to match the length of the output data frame. The padded input bytes are excluded from the CRC-IN code calculation. Frame 2 shows the input of the next read register command concurrent with the output of the previous register data. Zeros are padded after the register data to place CRC-OUT in the same location as with a conversion data output frame. The CRC-OUT code includes all preceding bytes within the data output frame. The SPI_ERR bit of the STATUS header indicates if an SPI CRC error occurred and whether the read register command is accepted. Frame 1 CS 8 24 16 40 32 SCLK SDI SDO/DRDY (D) don’t care don’t care STATUS (B) Data (C) 40h + Address[3:0] CRC-IN (A) Arbitrary Data (C) Data (C) CRC-OUT (A) Frame 2 CS 8 16 24 32 40 SCLK SDI SDO/DRDY A. B. C. D. (D) don’t care don’t care STATUS (B) Reg Data 40h + Address[3:0] 00h pad CRC-IN (A) Arbitrary CRC-OUT (A) 00h pad Optional CRC byte. If CRC is disabled, the frame shortens by one byte. Optional STATUS byte. If STATUS is disabled, the frame shortens by one byte. Depending on the previous operation, the data field is either conversion data or register data + two 00h pad bytes Previous state of SDO/DRDY before the first SCLK. Figure 8-30. Read Register Data, Maximum 40-Bit Frame Size Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 53 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.5.6.3 Write Register Command The write register command is used to write register data. The write register operation is performed in a single frame. The first byte of the command is the base value (80h) added to the 4-bit register address. The second byte of the command is the register data. Writing to registers outside the valid address range is ignored. Figure 8-31 shows an example of a register write operation using the 16-bit frame size. If operating in full-duplex mode (simultaneous reading of 24-bit conversion data during the input of the register write command), include one or more leading pad bytes to the input data to match the length of the output frame. When configuring a series of registers (when conversion data can be ignored), the minimum 16-bit frame size can be used to improve throughput. CS 16 8 SCLK SDI SDO/DRDY 80h + Address[3:0] Reg data Data (B) Data (B) (A) A. Previous state of SDO/DRDY before the first SCLK. B. Data are either the conversion data, or if the read register command was sent in a prior frame, the data field is register data byte + one 00h pad byte. Figure 8-31. Write Register Data, Minimum 16-Bit Frame Size Figure 8-32 shows an example of a write register operation using the maximum 40-bit frame size. Full-duplex operation is also illustrated to show simultaneous input of the command and output of conversion data. The input frame is prefixed with two don't care bytes to match the output frame so all conversion data bytes are transmitted. Successful write operations are verified by reading back the register data, or by checking the SPI_ERR bit of the STATUS byte for input byte CRC errors. If an SPI CRC input error occurred, SPI_ERR is set and further register write operations are blocked (except for the STATUS register) until reset by writing 1b to the same SPI_ERR bit. CS 8 24 16 40 32 SCLK SDI SDO/DRDY A. B. C. D. (D) don’t care don’t care STATUS (B) Data (C) 80h + Address[3:0] Data (C) Reg data Data (C) CRC-IN (A) CRC-OUT (A) Optional CRC byte. If CRC is disabled, the frame shortens by one byte. Optional STATUS byte. If STATUS is disabled, the frame shortens by one byte. The data field is either 24-bits of conversion data, or if the read register command was sent in the prior frame, register data byte + two 00h pad bytes. Previous state of SDO/DRDY before the first SCLK. Figure 8-32. Write Register Data, Maximum 40-Bit Frame Size 8.5.7 Read Conversion Data Conversion data are read by taking CS low and by applying SCLK to shift out the data directly (no command is used). Conversion data are buffered, which allows data to be read up to one fMOD clock cycle before the next DRDY falling edge. Conversion data may be read multiple times until the next conversion data are ready. If the register read command was sent in the previous frame then register data replaces the conversion data. 54 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Figure 8-33 shows an example of reading 24-bit conversion data with the STATUS and CRC bytes disabled. (C) DRDY CS 8 24 16 SCLK SDI 00h SDO/DRDY A. B. C. (A) 00h 00h LSB Data(B) MID Data(B) MSB Data(B) Before the first SCLK, SDO/DRDY is the previous state when SDO_MODE = 0b. Otherwise, SDO/DRDY follows DRDY. The data field is two bytes (16-bit resolution) or three bytes (24-bit resolution). In synchronized and start/stop control modes, DRDY returns high at the eighth SCLK falling edge. In one-shot control mode, DRDY remains low until a new conversion is started. Figure 8-33. Conversion Data Read, Short Format Figure 8-34 is an example of the long-format read data operation, which includes the STATUS header byte and the CRC byte. This example also shows the optional use of a full-duplex transmission when a register command is input at the same time the conversion data are output. If no input command is desired, the input bytes are 00h, 00h, and D7h. The output CRC (CRC-OUT) code computation includes the STATUS byte. If the conversion data readback is stopped after the eighth SCLK of the MSB data, DRDY returns high and the DRDY bit of the STATUS header goes low to indicate a data-read attempt. (E) DRDY CS 8 24 16 40 32 SCLK SDI SDO/DRDY A. B. C. D. E. (D) don’t care don’t care Command Byte 1 STATUS (B) MSB Data (C) MID Data (C) Command Byte 2 LSB Data (C) CRC-IN (A) CRC-OUT (A) Optional CRC byte. If the CRC is disabled, the frame shortens by one byte. Optional STATUS header. If STATUS is disabled, the frame shortens by one byte. Data are two bytes (16-bit resolution) or three bytes (24-bit resolution). If the SDO_MODE bit = 0, the previous state of SDO/DRDY remains until SCLK begins. Otherwise, SDO/DRDY follows DRDY. In synchronized and start/stop control modes, DRDY returns high at the 16th SCLK falling edge (eighth bit of the MS data byte). In one-shot control mode, DRDY stays low until a new conversion is started. Figure 8-34. Conversion Data Read, Long Format Conversion data can be read asynchronous to DRDY. However, when conversion data are read close to the DRDY falling edge, there is uncertainty whether previous data or new data are output. If the SCLK shift operation starts at least one fMOD clock cycle before the DRDY falling edge, then old data are provided. If the shift operation starts at least one fMOD clock cycle after DRDY, then new data are output. The DRDY bit of the STATUS header indicates if the data are old (previously read data) or new. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 55 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.5.7.1 Conversion Data Conversion data are coded in 2's-complement format, MSB first (sign bit), with resolution programmable to 24 bits or 16 bits. The resolution is programmed by the DATA bit of the CONFIG4 register. The SNR of 16-bit data is limited to 98.1 dB as a result of 16-bit quantization noise. Table 8-15 shows the output code for standard and extended input ranges shown for 24-bit resolution. The conversion data clips to positive and negative full-scale code values when the input signal exceeds the respective positive and negative full-scale values. Table 8-15. 24-Bit Output Data Format DIFFERENTIAL INPUT VOLTAGE (V)(1) 1.25 · k · VREF · (223 – 1) / k · VREF · (223 – 1) / 223 k · VREF / 223 0 –k · VREF / (1) (2) 223 223 24-BIT OUTPUT DATA(2) STANDARD RANGE EXTENDED RANGE 7FFFFFh 7FFFFFh 7FFFFFh 666666h 000001h 000001h 000000h 000000h FFFFFFh FFFFFFh –k · VREF 800000h 99999Ah –1.25 · k · VREF 800000h 800000h k = 1x or 2x input range option. Ideal output data, excluding offset, gain, linearity, and noise errors, and reduced data resolution with 12, 16, and 24 OSR values. 8.5.7.2 Data Ready There are several methods available to determine when conversion data are ready for readback. 1. Hardware: Monitor the DRDY or the SDO/DRDY pin 2. Software: Monitor the DRDY bit of the STATUS header byte 3. Clock count: Count the number of ADC clocks to predict when data are ready 8.5.7.2.1 DRDY DRDY is the data-ready output signal. DRDY drives high when conversions are started or resynchronized, and drives low when conversion data are ready. DRDY is driven back high at the eighth SCLK during conversion data read. This behavior applies to the synchronized and the start/stop control modes. In one-shot control mode, DRDY stays low during conversion data read. If the ADC is programmed to enter standby mode (STBY_MODE bit = 1b), DRDY is driven back high three fCLK cycles after transitioning low. If conversion data are not read, DRDY pulses high just prior to the next falling edge. See the Synchronization section for details of DRDY operation for each of the conversion control modes. DRDY is an active output whether CS is high or low. 8.5.7.2.2 SDO/DRDY SDO/DRDY is a dual-function output pin that can be programmed to automatically change modes from data ready, when not reading data, to data output mode, when reading data. This pin can replace the function of the DRDY pin to conserve the number of SPI I/O lines. When programmed to the dual-function mode (SDO_MODE bit = 1b) and when CS is low, SDO/DRDY mirrors DRDY until the first rising edge of SCLK, at which time the pin changes mode to provide data output. When the data read operation is complete (24th falling edge of SCLK, or 40th edge if the CRC and STATUS header bytes are included), the pin reverts back to mirroring DRDY. Figure 8-35 illustrates the operation of SDO/DRDY. 56 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 (A) DRDY CS 8 24 16 SCLK SDO/DRDY (SDO_MODE bit = 1b) SDO/DRDY (SDO_MODE bit = 0b) A. MSB Data Previous Data MSB Data MID Data LSB Data MID Data LSB Data DRDY function In synchronized and start/stop control modes, DRDY returns high at the eighth SCLK falling edge (eighth bit of MSB data). In one-shot control mode, DRDY stays low until a new conversion is started. Figure 8-35. SDO/DRDY and DRDY Function 8.5.7.2.3 DRDY Bit The software method of determining data ready is by polling the DRDY bit (bit 0 of the STATUS header). When DRDY = 1b, the data are new from the last data read operation, otherwise the data supplied are the previous data. After data are read, the bit stays cleared until the next conversion data are ready. To avoid missing data, poll the bit at least as often as the output data rate. 8.5.7.2.4 Clock Counting Another method to determine when data are ready is to count clock cycles. This method is only possible using an external clock because the internal clock oscillator is not observable. After synchronization or conversion start, the number of clock cycles is larger compared to the normal conversion data period. The initial number of clock cycles is equal to the latency time of the digital filter as listed in the Digital Filter section. 8.5.7.3 STATUS Header A STATUS header is an optional byte prefixed to the conversion data. See Table 8-20 for the STATUS header field descriptions. The STATUS header is enabled by setting the STATUS bit of the CONFIG4 register. The STATUS header byte sent with conversion data has the same content as the STATUS register. 8.5.8 Daisy-Chain Operation In simultaneous-sampling systems using multiple ADCs, the devices can be connected in a daisy-chain string to reduce the number of SPI connections. A daisy-chain connection links together the SPI output of one device to the SPI input of the next device so the devices in the chain appear as a single logical device to the host controller. There is no special programming required for daisy-chain operation, simply apply additional shift clocks to access all devices in the chain. For simplified operation, program the same SPI frame size for each device (for example, when enabling the CRC option of all devices, thus producing a 32-bit frame size). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 57 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Figure 8-36 shows four devices connected in a daisy-chain configuration. The SDI of ADS127L11 (1) connects to the host SPI data out, and SDO/DRDY of ADS127L11 (4) connects to the host SPI data input. The shift operation is simultaneous for all devices in the chain. After each ADC shifts out the conversion data, the data of SDI appears on SDO/DRDY to drive the SDI of the next device in the chain. The shift operation continues until the last device in the chain is reached. The SPI frame ends when CS is taken high, at which time the data shifted into each device is interpreted. The SDO/DRDY pin must be programmed to data output-only mode. IOVDD IOVDD IOVDD IOVDD ADS127L11 (4) ADS127L11 (3) ADS127L11 (2) ADS127L11 (1) SDO/DRDY SDI SDO/DRDY SDI SDO/DRDY SDI SDO/DRDY SDI CS CS CS CS SCLK SCLK SCLK SCLK SPI Controller Data Out Chip Select SCLK Data In Figure 8-36. Daisy-Chain Connection Figure 8-37 shows the 24-bit frame size of each device used at initial communication after device power up. CS SDI (ADC #1) ADC #4 DATA ADC #3 DATA ADC #2 DATA ADC #1 DATA SCLK 96 SCLK with 24-bit frames Figure 8-37. 24-Bit Data Input Sequence To input data, the host first shifts in the data intended for the last device in the chain. The number of input bytes for each ADC is sized to match the output frame size. The default frame size is 24 bits, so initially each ADC requires three bytes by prefixing a pad byte in front of the two command bytes. The input data of ADC #4 is first, followed by the input data of ADC #3, and so forth. Figure 8-38 shows the detailed input data sequence for the daisy-chain write register operation of Figure 8-36. 40-bit frames for each ADC are shown (24-bits of data, with the STATUS and CRC bytes enabled). Command operations can be different for each ADC. The read register operation requires a second frame operation to read out the register data. Daisy-chain frame CS 8 24 16 40 32 48 160 152 SCLK SDI (Device #1) SDO/DRDY (Device #4) A. B. C. 00h (B) STATUS 4 (C) 00h MSB data 4 80h + address[3:0] 4 MID data 4 Reg data 4 LSB data 4 CRC-IN 4 (A) 00h Reg data 1 CRC-IN 1 CRC-OUT 4 (A) STATUS 3 LSB data 1 CRC-OUT 1 Optional CRC byte. If CRC is disabled, the individual frames shortens one byte. Previous state of SDO/DRDY before SCLK is applied. Optional STATUS header. If STATUS is disabled, the individual frames shorten one byte. Figure 8-38. Write Register Data in Daisy-Chain Connection 58 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Figure 8-39 shows the clock sequence to read conversion data from the device connection provided in Figure 8-36. This example illustrates a 32-bit output frame (24-bits of data, with the CRC byte enabled). The output data of ADC (4) is first in the sequence, followed by the data of ADC (3), and so on. The total number of clocks required to shift out the data is given by the number of bits per frame × the number of devices in the chain. In this example, 32-bit output frames × four devices result in 128 total clocks. Daisy-chain frame CS 8 24 16 40 32 120 128 SCLK SDI (Device #1) SDO/DRDY (Device #4) A. B. 00h (B) 00h 00h LSB data 4 MID data 4 MSB data 4 D7h (A) CRC-OUT 4 00h 00h LSB data 1 MSB data 3 D7h CRC-OUT 1 Optional CRC byte. If CRC is disabled, the individual frames shortens one byte. Previous state of SDO/DRDY before SCLK is applied. Figure 8-39. Read Conversion Data in Daisy-Chain Connection As shown in Equation 20, the maximum number of devices connected in daisy-chain configuration is limited by the SCLK signal frequency, data rate, and number of bits per frame. The same limitation applies to parallelconnected SPI because the data from each ADC is also read serially. Maximum devices in a chain = ⌊fSCLK / (fDATA · bits per frame)⌋ (20) For example, if fSCLK = 20 MHz, fDATA = 100 kSPS, and 32-bit frames are used, the maximum number of daisy-chain connected devices is the floor of: ⌊20 MHz / (100 kHz · 32)⌋ = 6. 8.5.9 3-Wire SPI Mode The ADC has the option of 3-wire SPI operation by grounding CS. 3-wire mode is detected by the ADC when CS is grounded at power up or after reset. 3-wire SPI mode is indicated by bit 7 (CS_MODE) of the STATUS register. The device changes to 4-wire SPI mode any time CS is taken high. Because CS no longer controls frame timing in 3-wire SPI mode, SCLKs are counted by the ADC to determine the beginning and ending of a frame. The number of SCLK bits must be controlled by the host and must match the size of the output frame. The number of bits per frame depends on device configuration. The size of the output frame is shown in Table 8-12. Because frame timing is determined by the number of SCLKs, avoid inadvertent SCLK transitions, such as those possibly occurring at power up. 3-wire SPI mode supports the same command format and clocking as the 4-wire mode, except there is no CS toggling and therefore no wait time between frames. 8.5.9.1 3-Wire SPI Mode Frame Reset In 3-wire SPI mode, an unintended SCLK can misalign the frame, resulting in loss of frame synchronization to the ADC. As shown in Figure 8-40, the SPI is resynchronized without requiring an ADC reset by sending an SPI reset pattern. The reset pattern is a minimum of 63 consecutive 1s followed by one 0 at the 64th SCLK. The 65th SCLK starts a new SPI frame. Optionally, the ADC can be completely reset by toggling RESET or by the reset pattern shown in the Reset by SPI Input Pattern section. 1 64 SCLK SPI Reset SDI Figure 8-40. 3-Wire Mode SPI Reset Pattern Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 59 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6 Registers Table 8-16 lists the register map of the ADS127L11. Register data are read or written one register at a time for each read or write operation in a frame. Writing to any register address 4h through Eh results in a conversion restart and loss of synchronization. If the ADC is idle (conversions are stopped), new conversions are not started. Table 8-16. ADS127L11 Register Map Overview ADDRESS REGISTER DEFAULT 0h DEV_ID 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADC_ERR MOD_FLAG DRDY START STOP DEV_ID[7:0] 1h REV_ID xxh 2h STATUS x1100xxxb REV_ID[7:0] 3h CONTROL 00h RESET[5:0] 4h MUX 00h RESERVED 5h CONFIG1 00h RESERVED REF_RNG INP_RNG 6h CONFIG2 00h EXT_RNG RESERVED SDO_MODE 7h CONFIG3 00h 8h CONFIG4 00h 9h OFFSET2 00h OFFSET[23:16] Ah OFFSET1 00h OFFSET[15:8] Bh OFFSET0 00h OFFSET[7:0] Ch GAIN2 40h GAIN[23:16] Dh GAIN1 00h GAIN[15:8] Eh GAIN0 00h GAIN[7:0] Fh CRC 00h CRC[7:0] CS_MODE ALV_FLAG POR_FLAG SPI_ERR REG_ERR MUX[1:0] VCM REFP_BUF START_MODE[1:0] DELAY[2:0] CLK_SEL RESERVED AINP_BUF AINN_BUF SPEED_MODE STBY_MODE PWDN REG_CRC STATUS FILTER[4:0] CLK_DIV OUT_DRV RESERVED DATA SPI_CRC Table 8-17 lists the access codes of the registers. Table 8-17. Register Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W Reset or Default Value -n Value after reset or the default value 8.6.1 DEV_ID Register (Address = 0h) [reset = 00h] Return to the Register Map Overview. Figure 8-41. DEV_ID Register 7 6 5 4 3 2 1 0 DEV_ID[7:0] R-00h Table 8-18. DEV_ID Register Field Descriptions 60 Bit Field Type Reset Description 7:0 DEV_ID[7:0] R 00h Device ID. 00h = ADS127L11 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6.2 REV_ID Register (Address = 1h) [reset = xxh] Return to the Register Map Overview. Figure 8-42. REV_ID Register 7 6 5 4 3 2 1 0 REVID[7:0] R-xxxxxxxxb Table 8-19. REV_ID Register Field Descriptions Bit Field Type Reset Description 7:0 REV_ID[7:0] R xxxxxxxxb Die revision ID The die revision ID can change during device production without notice. 8.6.3 STATUS Register (Address = 2h) [reset = x1100xxxb] Return to the Register Map Overview. Figure 8-43. STATUS Register 7 6 5 4 3 2 1 0 CS_MODE ALV_FLAG POR_FLAG SPI_ERR REG_ERR ADC_ERR MOD_FLAG DRDY R-xb R/W-1b R/W-1b R/W-0b R/W-0b R-xb R-xb R-xb Table 8-20. STATUS Register Field Descriptions Bit 7 Field Type Reset Description CS_MODE R xb CS mode. This bit indicates 4-wire or 3-wire SPI mode. The mode is determined by the state of CS at power up or after reset. 0b = 4-wire SPI operation (CS is active) 1b = 3-wire SPI operation (CS is tied low) 6 ALV_FLAG R/W 1b Analog supply low-voltage flag. This bit indicates a low-voltage condition occurred on the analog power supplies. Write 1b to clear the flag to detect the next lowvoltage condition. 0b = No analog supply low-voltage condition from when flag last cleared 1b = Analog supply low-voltage condition detected 5 POR_FLAG R/W 1b Power-on reset (POR) flag. This bit indicates a reset from device power-on, by a brownout of the IOVDD supply, CAPD bypass output, or by a user-initiated reset. Write 1b to clear the flag to detect the next reset. 0b = No reset from when the flag last cleared 1b = Device reset occurred Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 61 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 8-20. STATUS Register Field Descriptions (continued) Bit 4 Field Type Reset Description SPI_ERR R/W 0b SPI communication CRC error. This bit indicates an SPI CRC error. If set, register write operations are blocked, except for the STATUS register that allows clearing the error (write 1b to clear the error). Register read operations remain functional. The SPI CRC error detection is enabled by the SPI_CRC bit (CONFIG4 register). 0b = No error 1b = SPI CRC error 3 REG_ERR R/W 0b Register map CRC error. REG_ERR indicates if the written register map CRC (0Fh) value does not match the internal ADC calculated value. Write 1b to clear the register map CRC error or clear the REG_CRC bit. Set the REG_CRC bit (CONFIG4 register) to enable the register map error check. 0b = No error 1b = Register map CRC error 2 ADC_ERR R xb Internal ADC error. ADC_ERR indicates an internal error. Perform a power cycle or reset the device. 0b = No ADC error 1b = ADC error detected 1 MOD_FLAG R xb Modulator saturation flag. This bit indicates a transient or continuous modulator saturation occurred during the conversion cycle. The flag is updated at the completion of each conversion. 0b = Modulator not saturated 1b = Modulator saturation detected during the conversion cycle 0 DRDY R xb Data-ready bit. DRDY indicates when new conversion data are ready. The DRDY bit is the inverse of the DRDY pin. Poll the bit to determine if conversion data are new or are repeated data from the last read operation. DRDY = 1 indicates data are new. In one-shot control mode, the bit remains at 1b until a new conversion is started. 0b = Data are not new 1b = Data are new 62 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6.4 CONTROL Register (Address = 3h) [reset = 00h] Return to the Register Map Overview. Figure 8-44. CONTROL Register 7 6 5 1 0 RESET[5:0] 4 3 2 START STOP W-000000b W-0b W-0b Table 8-21. CONTROL Register Field Descriptions Bit Field Type Reset Description 7:2 RESET[5:0] W 000000b Device reset. Write 010110b to reset the ADC. The adjacent START and STOP bits must be set to 00b in the same write operation to reset the ADC. These bits always read 000000b. START W 0b Start conversion. Conversions are started or restarted by writing 1b. Preclear the CONTROL register by writing 00h prior to writing the START bit. In one-shot control mode, one conversion is started. In start/stop control mode, conversions are started and continue until stopped by the STOP bit. Writing 1b to START while a conversion is ongoing restarts the conversion. This bit has no effect in synchronized control mode. Writing 1b to both the START and STOP bits has no effect. START is self-clearing and always reads 0b. 1 0b = No operation 1b = Start or restart conversion 0 STOP W 0b Stop conversion. This bit stops conversions after the current conversion completes. This bit has no effect in synchronized control mode. Writing 1b to both the START and STOP has no effect. STOP is self-clearing and always reads 0b. 0b = No operation 1b = Stop conversion after the current conversion completes Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 63 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6.5 MUX Register (Address = 4h) [reset = 00h] Return to the Register Map Overview. Figure 8-45. MUX Register 7 6 5 4 3 2 1 0 RESERVED MUX[1:0] R-000000b R/W-00b Table 8-22. MUX Register Field Descriptions Bit Field Type Reset Description 7:2 RESERVED R 000000b Reserved 1:0 MUX[1:0] R/W 00b Input multiplexer selection. These bits select the polarity of the analog input and selects the test modes. See the Analog Input section for details. 00b = Normal input polarity 01b = Inverted input polarity 10b = Offset and noise test: AINP and AINN disconnected, ADC inputs internally shorted to (AVDD1 + AVSS) / 2 11b = Common-mode test: ADC inputs internally shorted and connected to AINP 64 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6.6 CONFIG1 Register (Address = 5h) [reset = 00h] Return to the Register Map Overview. Figure 8-46. CONFIG1 Register 7 6 5 4 3 2 1 0 RESERVED REF_RNG INP_RNG VCM REFP_BUF RESERVED AINP_BUF AINN_BUF R-0b R/W-0b R/W-0b R/W-0b R/W-0b R-0b R/W-0b R/W-0b Table 8-23. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0b Reserved 6 REF_RNG R/W 0b Voltage reference range selection. Program this bit to select the low- or high-reference voltage range to match the applied reference voltage. See the Recommended Operating Conditions table for the range of reference voltages. When the high-reference range is selected, the INP_RNG bit is internally overridden to the 1x input range. 0b = Low-reference range 1b = High-reference range 5 INP_RNG R/W 0b Input range selection. This bit selects the 1x or 2x input range. See the Input Range section for more details. 0b = 1x input range 1b = 2x input range 4 VCM R/W 0b VCM output enable. This bit enables the VCM output voltage pin. The VCM voltage is (AVDD1 + AVSS) / 2. 0b = Disabled 1b = Enabled 3 REFP_BUF R/W 0b Reference positive buffer enable. This bit enables the REFP reference input precharge buffer. 0b = Disabled 1b = Enabled 2 RESERVED R 0b Reserved 1 AINP_BUF R/W 0b Analog input positive buffer enable. This bit enables the AINP analog input precharge buffer. 0b = Disabled 1b = Enabled 0 AINN_BUF R/W 0b Analog input negative buffer enable. This bit enables the AINN analog input precharge buffer. 0b = Disabled 1b = Enabled Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 65 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6.7 CONFIG2 Register (Address = 6h) [reset = 00h] Return to the Register Map Overview. Figure 8-47. CONFIG2 Register 7 6 5 2 1 0 EXT_RNG RESERVED SDO_MODE START_MODE[1:0] 4 3 SPEED_MODE STBY_MODE PWDN R/W-0b R-0b R/W-0b R/W-00b R/W-0b R/W-0b R/W-0b Table 8-24. CONFIG2 Register Field Descriptions Bit 7 Field Type Reset Description EXT_RNG R/W 0b Extended input range selection. This bit extends the input range by 25%. See the Input Range section for more details. 0b = Standard input range 1b = 25% extended input range 6 RESERVED R 0b Reserved 5 SDO_MODE R/W 0b SDO/DRDY mode selection. This bit programs the mode of the SDO/DRDY pin to either dataoutput function only, or to dual-mode function of data output and data ready. For daisy-chain connection of ADCs, use the data-output function only mode. See the SDO/DRDY section for more details. 0b = Data output only mode 1b = Dual mode: data output and data ready 4:3 START_MODE[1:0] R/W 00b START mode selection. These bits program the mode of the START pin. See the Synchronization section for more details. 00b = Start/stop control mode 01b = One-shot control mode 10b = Synchronized control mode 11b = Reserved 2 SPEED_MODE R/W 0b Speed mode selection. This bit programs the power-scalable speed mode of the device. The clock frequency corresponds to the mode. 0b = High-speed mode (fCLK = 25.6 MHz) 1b = Low-speed mode (fCLK = 3.2 MHz) 1 STBY_MODE R/W 0b Standby mode selection. This bit enables the auto engagement of the low-power standby mode after conversions are stopped. 0b = Idle mode; ADC remains fully powered when conversions are stopped. 1b = Standby mode; ADC powers down when conversions are stopped. Standby mode is exited when conversions restart. 66 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 8-24. CONFIG2 Register Field Descriptions (continued) Bit 0 Field Type Reset Description PWDN R/W 0b Power-down mode selection. When set, the ADC is powered down. All functions are powered down except for SPI operation and the digital LDO to retain user register settings. 0b = Normal operation 1b = Power-down mode 8.6.8 CONFIG3 Register (Address = 7h) [reset = 00h] Return to the Register Map Overview. Figure 8-48. CONFIG3 Register 7 6 5 4 3 2 DELAY[2:0] FILTER[4:0] R/W-000b R/W-00000b 1 0 Table 8-25. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7:5 DELAY[2:0] R/W 000b Conversion-start delay time selection. Programmable delay time before the start of the first conversion when START is applied. Delay time is given in number of fMOD clock cycles (fMOD = fCLK / 2). 000b = 0 001b = 4 010b = 8 011b = 16 100b = 32 101b = 128 110b = 512 111b = 1024 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 67 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 8-25. CONFIG3 Register Field Descriptions (continued) Bit Field Type Reset Description 4:0 FILTER[4:0] R/W 00000b Digital filter mode and oversampling ratio selection. These bits configure the digital filter. The digital filter has five modes: wideband, sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1, each with a range of OSR values. See Table 7-1 through Table 7-5 for data rate and bandwidth information. 00000 = wideband, OSR = 32 00001 = wideband, OSR = 64 00010 = wideband, OSR = 128 00011 = wideband, OSR = 256 00100 = wideband, OSR = 512 00101 = wideband, OSR = 1024 00110 = wideband, OSR = 2048 00111 = wideband, OSR = 4096 01000 = sinc4, OSR = 12 01001 = sinc4, OSR = 16 01010 = sinc4, OSR = 24 01011 = sinc4, OSR = 32 01100 = sinc4, OSR = 64 01101 = sinc4, OSR = 128 01110 = sinc4, OSR = 256 01111 = sinc4, OSR = 512 10000 = sinc4, OSR = 1024 10001 = sinc4, OSR = 2048 10010 = sinc4, OSR = 4096 10011 = sinc4, OSR = 32 + sinc1, OSR = 2 10100 = sinc4, OSR = 32 + sinc1, OSR = 4 10101 = sinc4, OSR = 32 + sinc1, OSR = 10 10110 = sinc4, OSR = 32 + sinc1, OSR = 20 10111 = sinc4, OSR = 32 + sinc1, OSR = 40 11000 = sinc4, OSR = 32 + sinc1, OSR = 100 11001 = sinc4, OSR = 32 + sinc1, OSR = 200 11010 = sinc4, OSR = 32 + sinc1, OSR = 400 11011 = sinc4, OSR = 32 + sinc1, OSR = 1000 11100 = sinc3, OSR = 26667 11101 = sinc3, OSR = 32000 11110 = sinc3, OSR = 32000 + sinc1, OSR = 3 11111 = sinc3, OSR = 32000 + sinc1, OSR = 5 68 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6.9 CONFIG4 Register (Address = 8h) [reset = 00h] Return to the Register Map Overview. Figure 8-49. CONFIG4 Register 7 6 5 4 3 2 1 0 CLK_SEL CLK_DIV OUT_DRV RESERVED DATA SPI_CRC REG_CRC STATUS R/W-0b R/W-0b R/W-0b R-0b R/W-0b R/W-0b R/W-0b R/W-0b Table 8-26. CONFIG4 Register Field Descriptions Bit 7 Field Type Reset Description CLK_SEL R/W 0b Clock selection. Selects internal or external clock operation. 0b = Internal clock operation 1b = External clock operation 6 CLK_DIV R/W 0b External clock divider selection. This bit is used to divide the external clock by 8. 0b = No clock division 1b = Clock division by 8 5 OUT_DRV R/W 0b Digital output drive selection. Select the drive strength of the digital outputs. 0b = Full-drive strength 1b = Half-drive strength 4 RESERVED R 0b Reserved 3 DATA R/W 0b Data resolution selection. This bit selects the output data resolution. 0b = 24-bit resolution 1b = 16-bit resolution 2 SPI_CRC R/W 0b SPI CRC enable. This bit enables the SPI CRC error check. When enabled, the device verifies the CRC input byte and appends a CRC output byte to the output data. The SPI_ERR bit of the STATUS byte sets if an input SPI CRC error is detected. Write 1b to the SPI_ERR bit to clear the error. 0b = SPI CRC function disabled 1b = SPI CRC function enabled 1 REG_CRC R/W 0b Register map CRC enable. This bit enables the register map CRC error check. Write the register map CRC value to the 0Fh register, calculated over registers 0h to 1h and 4h to Eh. An internal CRC value is compared to the value written to the register map CRC register. The REG_ERR bit of the STATUS byte sets if the CRC values do not match. 0b = Register map CRC function disabled 1b = Register map CRC function enabled Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 69 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 Table 8-26. CONFIG4 Register Field Descriptions (continued) Bit 0 Field Type Reset Description STATUS R/W 0b STATUS byte output enable. Program this bit to prefix the STATUS byte to the conversion data output. 0b = Status byte not prefixed to the conversion data 1b = Status byte prefixed to the conversion data 8.6.10 OFFSET2, OFFSET1, OFFSET0 Registers (Addresses = 9h, Ah, Bh) [reset = 00h, 00h, 00h] Return to the Register Map Overview. Figure 8-50. OFFSET2, OFFSET1, OFFSET0 Registers 7 6 5 4 3 2 1 0 2 1 0 2 1 0 OFFSET[23:16] R/W-00000000b 7 6 5 4 3 OFFSET[15:8] R/W-00000000b 7 6 5 4 3 OFFSET[7:0] R/W-00000000b Table 8-27. OFFSET Registers Field Description Bit 23:0 70 Field Type Reset Description OFFSET[23:0] R/W 000000h User offset calibration value. Three registers form the 24-bit offset calibration word. OFFSET[23:0] is in 2's-complement representation and is subtracted from the conversion result. The offset operation precedes the gain operation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 8.6.11 GAIN2, GAIN1, GAIN0 Registers (Addresses = Ch, Dh, Eh) [reset = 40h, 00h, 00h] Return to the Register Map Overview. Figure 8-51. GAIN2, GAIN1, GAIN0 Registers 7 6 5 4 3 2 1 0 2 1 0 2 1 0 GAIN[23:16] R/W-01000000b 7 6 5 4 3 GAIN[15:8] R/W-00000000b 7 6 5 4 3 GAIN[7:0] R/W-00000000b Table 8-28. GAIN Registers Field Description Bit 23:0 Field Type Reset Description GAIN[23:0] R/W 400000h User gain calibration value. Three registers form the 24-bit gain calibration word. GAIN[23:0] is in straight-binary representation and normalized to 400000h for gain = 1. The conversion data is multiplied by GAIN[23:0] / 400000h after the offset operation. 8.6.12 CRC Register (Address = Fh) [reset = 00h] Return to the Register Map Overview. Figure 8-52. CRC Register 7 6 5 4 3 2 1 0 CRC[7:0] R/W-00000000b Table 8-29. CRC Register Field Descriptions Bit Field Type Reset Description 7:0 CRC[7:0] R/W 00h Register map CRC value. The register map CRC is a user-computed value of registers 0h to 1h together with registers 4h through Eh. The value written to this register is compared to an internal CRC calculation. If the values do not match, the REG_ERR bit is set in the STATUS header byte and register. The register CRC check is enabled by the REG_CRC bit. If the register CRC function is disabled, this register is available for scratchpad purposes. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 71 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The high-performance capability of the ADS127L11 is achievable when familiar with the requirements of the input driver, antialias filter, reference voltage, SPI clocking, and PCB layout. The following sections provide design guidelines. 9.1.1 SPI Operation Although the ADC provides flexible clock options for the SPI interface and the range of IOVDD voltages, the following guidelines are recommended to achieve full data sheet performance. 1. Use an SCLK that is phase coherent to CLK; that is, ratios of 2:1, 1:1, 1:2, 1:4, and so on. 2. Minimize phase skew between SCLK and CLK (< 5 ns). 3. Operate IOVDD at the lowest voltage possible to reduce digital noise. 4. If IOVDD ≥ 3.3 V, consider operating SCLK continuously over the full conversion period to spread noise coupling over the full conversion period. 5. Keep the trace capacitance of SDO/DRDY ≤ 20 pF to reduce the peak currents associated with digital output transitions. 9.1.2 Input Driver The ADC incorporates precharge buffers that reduce the settling and bandwidth requirement of the analog input driver. If a 10-MHz or less bandwidth driver is used, or if there is a long distance between the driver and the ADC inputs (such as a cable connection), enable the input precharge buffers. For higher gain-bandwidth drivers, the precharge buffers may be disabled to reduce power consumption, but in any case, full-rated THD and SNR data sheet performance is realized with the input precharge buffers active. In low-speed mode operation, the modulator sample rate is significantly reduced, therefore the driver has more time to settle between the input sampling pulses. Using a lower bandwidth input driver or disabling the precharge buffers can be practical options for low-speed operation. 9.1.3 Antialias Filter Input signals occurring near fMOD (12.8 MHz in high-speed mode and 1.6 MHz in low-speed mode) fold back (or alias) to the pass band, resulting in data errors. When aliased, the frequency errors cannot be removed by post processing. An analog antialias filter at the ADC inputs removes the frequencies from the input signal before they are aliased by the ADC. The required order of the antialias filter is dependent on the selected OSR and the target value of signal attenuation at fMOD. A large value of OSR means more frequency range between the fDATA Nyquist frequency and fMOD for the filter to provide the desired roll off. For example, for OSR = 128, more than two decades of frequency separates fDATA and fMOD. With a corner frequency = fDATA, a third-order, 60-dB per decade filter provides a 120-dB alias rejection at fMOD. 9.1.4 Reference Voltage For data sheet performance, the ADC requires a reference voltage with low noise and good drive strength to charge the sampled reference input. Because the modulator continuously samples the reference voltage whether conversions are ongoing or not (except in standby and power-down modes), the reference loading is constant, therefore incomplete settling of the reference voltage appears as a gain error to the system. The total system gain error can be calibrated. A 22-μF decoupling capacitor at the reference output and 1-μF and 0.1-μF capacitors directly across the reference input pins filters the reference input. The ADC also incorporates an optional reference precharge buffer for the positive input to buffer the reference voltage. 72 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 9.1.5 Simultaneous-Sampling Systems When using the ADC in a multichannel system, the same design principles apply with additional considerations for clock routing, synchronization, shared reference voltage and SPI clocking. See the ADS127L11 in Simultaneous-Sampling Systems application brief for details for use in simultaneous-sampling systems. 9.2 Typical Application 5V 1 F 0.1 F THS4551 (VQFN package) R3 1 k ADS127L11 C3 180 pF R1 499 R2 499  R4 499  VIN (-) PD IN+ C1 220 pF VIN (+) R5 5 FB- 499 C2 330 pF C4 470 pF 499  IN- AVDD1 AVDD2 AINP 0.1 F OUT- VOCM 180 pF 1 F 2.2 nF OUT+ AINN FB+ 499  R6 22  5V 3 220 pF 5 22  AVSS 220 pF 1.8 V VCM IOVDD 1 k 0.1 F 0.1 F 1 F 1 F CAPA DGND 1 F 5V CAPD START REF6041 CLK VIN SS OUT_S FILT GND_S 120 k DRDY OUT_F EN 1 µF GND_F 1 µF 47 m 1 µF 0.1
F 22 µF REFP SDO/DRDY SCLK ADC digital I/O SDI REFN CS RESET Figure 9-1. ADS127L11 Circuit Diagram 9.2.1 Design Requirements Figure 9-1 shows an application of the ADS127L11 used in a precision data acquisition system. The goal of this design is an antialias filter at the ADC input to attenuate out-of-band signals at the modulator sample rate (fMOD). The requirement of the antialias filter is 90-dB attenuation at the critical fMOD frequency (12.8 MHz in high-speed mode) using the OSR = 32 setting in wideband filter mode. The filter is designed for a flat amplitude response and low group delay error within the pass band of the signal. Table 9-1 lists the target design values and the actual values in this design example. Table 9-1. Antialias Filter Design Requirements FILTER PARAMETER Voltage gain Alias rejection at 12.8 MHz TARGET VALUE ACTUAL VALUE 0 dB 0 dB 90 dB 90 dB –0.1-dB frequency 250 kHz 260 kHz –3-dB frequency 500 kHz 550 kHz Amplitude peaking 20 mdB 12 mdB Group delay linearity 0.1 μs 0.017 μs Total noise of filter and ADC (165-kHz bandwidth) 12 μV 11.8 μV Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 73 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 9.2.2 Detailed Design Procedure The antialias filter consists of a passive first-order input filter, an active second-order filter, and a passive first-order output filter. The filter is fourth-order overall. The filter design accommodates the worst-case wideband filter OSR value (32), which results in less than two decades of frequency range between the Nyquist frequency at fDATA and the fMOD frequency. The fourth-order filter provides 90-dB rolloff over this frequency range. The filter rolloff at fMOD is the key function of the filter. The THS4551 amplifier is selected for the active filter stage because of the 135-MHz gain-bandwidth product (GBP) and 50-ns settling time. The amplifier GBP is sufficient to maintain the filter rolloff at 12.8 MHz, even with the dc gain of 15 dB. For example, for applications where gain is desired, a 10-MHz amplifier has marginal GBP to fully support the required rolloff at the fMOD frequency. The settling time specification of the THS4551 also makes the device a good choice for driving the ADC sampled inputs. The design of the active filter section begins with an equal-R assumption to reduce the number of component values to select. The dc gain of the filter is R3 / (R1 + R2). 1-kΩ resistors are selected to be low enough in value to keep resistor noise and amplifier input current noise from affecting the noise of the ADC. The 1-kΩ input resistor is divided into two 499-Ω resistors (R1 and R2) to implement the first-order filter using C1. The first-order filter is decoupled from the second-order active filter, but shares R1 and R2 to determine each filter stage corner frequency. The corner frequency is given by C1 and the Thevenin resistance at the terminals of C1 (RTH = 2 × 250 Ω). Given an arbitrary selection of R4 (2 × 499 Ω in this case), the values of the 2 × 180 pF (C3) feedback capacitors and the single 330-pF differential capacitor (C2) are calculated by the filter design equations given in the Design Methodology for MFB Filters in ADC Interface Applications application note. The design inputs are filter fO and filter Q for the multiple-feedback active filter topology. The differential capacitor (C4) is not part of the filter design but is used to improve filter phase margin. The 5-Ω resistors (R5) isolate the amplifier outputs from stray capacitance to further improve filter phase margin. The final RC filter at the ADC inputs serves two purposes. First, the filter provides a fourth pole to the overall filter response, thereby increasing filter rolloff. The other purpose of the filter is a charge reservoir to filter the sampled input of the ADC. The charge reservoir reduces the instantaneous charge demand of the amplifier, maintaining low distortion and low gain error that otherwise can degrade because of incomplete amplifier settling. The input filter values are 2 × 22 Ω and 2.2 nF. The 22-Ω resistors are outside the THS4551 filter loop to isolate the amplifier outputs from the 2.2-nF capacitor to maintain phase margin. Low voltage-coefficient C0G capacitors are used everywhere in the signal path for their low distortion properties. The amplifier gain resistors are 0.1% tolerance to provide best possible THD performance. The ADC VCM output connection to the amplifier VOCM input pin is optional because the same function is provided by the amplifier. See the THS4551 data sheet for additional examples of active filter designs and application. 74 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 9.2.3 Application Curves The following figures are produced by the TINA-TI™, SPICE-based analog simulation program. The THS4551 SPICE model can be downloaded at the THS4551 product folder. Figure 9-2 shows the frequency response of the antialias filter and the total response of the antialias filter and ADC. As shown in this image, the filter provides 90-dB stop-band attenuation from the Nyquist frequency to the 12.8-MHz fMOD frequency. Figure 9-3 shows the analog filter group delay. The 0.575-μs group delay is small in comparison to the 85-μs group delay of the ADC digital filter (34 / fDATA). The analog filter group delay linearity is 0.017 μs, peaking at the edge of the 165-kHz pass band. 0 Antialias filter Total response Amplitude (dB) -25 -50 -75 -100 -125 1 10 100 1000 Frequency (kHz) 10000 100000 Figure 9-3. Antialias Filter Group Delay Figure 9-2. Antialias Filter Frequency Response Figure 9-4 shows the noise density of the antialias filter circuit, the noise density of the ADC, and the combined noise density of the filter and ADC. Noise density is the noise voltage per √Hz of bandwidth plotted versus frequency. Figure 9-5 shows the total noise from the 1-Hz start frequency up to the ADC final bandwidth. Below 200 Hz, noise is dominated by 1 / f voltage and current noise of the THS4551 amplifier. Above 200 Hz, noise is dominated by ADC noise. The combined noise of the filter and ADC over the 165-kHz bandwidth is 11.8 μV, meeting the 12-μV target value. 150 20 ADC noise density AA filter noise density Combined noise density 100 75 50 ADC noise AA filter noise Combined noise 10 Total Noise (V) Noise Density (nV /Hz) 125 1 0.1 25 0.01 0 1 10 100 1000 10000 Frequency (Hz) 100000 1000000 1 10 100 1000 10000 Frequency (Hz) 100000 1000000 Figure 9-5. Total Noise Figure 9-4. Noise Density Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 75 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 9.3 Power Supply Recommendations The ADC has three analog power supplies and one digital power supply. Power-supply voltages AVDD1 and AVSS establish the type of analog input signal range. Bipolar input signals are only possible using bipolar supply voltages, such as AVDD1 = 2.5 V and AVSS = –2.5 V, and only unipolar input signals are possible using unipolar supply voltages, such as AVDD1 = 5 V and AVSS = DGND. The AVDD2 power-supply voltage is with respect to AVSS and the IOVDD power-supply voltage is with respect to DGND. The specified range of the power supplies are listed in the Recommended Operating Conditions table. The ADC can be operated using a single 5-V voltage for all supplies (or one 3-V voltage in low-speed mode) with AVSS = DGND. The ADC supply pins must always have separate bypass capacitors. Power-supply bypassing at the device pins is essential to achieve data sheet performance. The ADC also requires capacitors for the CAPA and CAPD pins, and for the analog input and reference pins. Place the capacitors close to the device pins using short, direct traces with the smaller capacitor value placed closest to the device pins. The recommended bypass components of the device pins are as follows: 1. AVDD1 to AVSS: a. Parallel combination of 1-µF and 0.1-µF capacitors across the AVDD1 power supply and AVSS b. A 3-Ω resistor placed in series between the bypass capacitors and the device AVDD1 pin 2. AVDD2 to AVSS: Parallel combination of 1-µF and 0.1-µF capacitors across the pins 3. IOVDD to DGND: Parallel combination of 1-µF and 0.1-µF capacitors across the pins 4. CAPA to AVSS: 1-µF capacitor placed across the pins 5. CAPD to DGND: 1-µF capacitor placed across the pins 6. REFP, REFN: Parallel combination of 1-µF and 0.1-µF capacitors across the pins 7. AINP, AINN: 22-Ω resistors in series, followed by 2.2 nF across the pins, 220 pF from each pin to AVSS Figure 9-6 shows the component placement for the device configured for unipolar power-supply operation. ADS127L11 3 220 pF 5V AVDD1 1 F 0.1 F 22 AINP SIG + 2.2 nF 22  AVSS AINN SIG 220 pF 1.8 V to 5 V AVDD2 0.1 F REF + 1 µF 0.1
F 1 F REFP REFN REF - 1.8 V to 5 V 1 F CAPA IOVDD 1 F 0.1 F DGND 1 F CAPD Figure 9-6. Device Bypass Recommendation The power supplies do not require special sequencing and can be powered up in any order, but in no case must any analog or digital input exceed the respective AVDD1 and AVSS (analog) or IOVDD (digital) power-supply voltages. An internal reset is performed after the IOVDD power-supply voltage is applied. 76 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 9.4 Layout 9.4.1 Layout Guidelines To achieve data sheet performance, use a minimum four-layer PCB board with the inner layers dedicated to ground and power planes. Best performance is achieved by combining the analog and digital grounds on a single, unbroken ground plane. In some layout geometries, however, using separate analog and digital grounds may be necessary to help direct digital currents away from the analog ground (such as pulsing LED indicators, relays, and so on). In this case, consider separate ground return paths for these loads. When separate analog and digital grounds are used, join the grounds at the ADC. Use the power plane layer to route the power supplies to the ADC. The top and bottom layers route the analog and digital signals. Route the input signal as a matched differential pair throughout the signal chain to reduce differential noise coupling. Avoid crossing or adjacent placement of digital signals with the analog signals. This layout is especially true for high-frequency digital signals such as the clock input, and SPI signals, SCLK, and SDO/DRDY. The pin placement of both ADC package options minimizes the need to cross digital and analog signals. Place the voltage reference close to the ADC. Orient the reference such that the reference ground pin is close to the ADC REFN pin. Place the reference input bypass capacitors directly at the ADC pins. Use reference bypass capacitors for each ADC in multichannel systems and connect the reference ground pin to the ground plane (or to AVSS in some bipolar supply systems) at one point and route REFP and REFN as paired traces to each ADC. 9.4.2 Layout Example Figure 9-7 is a layout example based on the circuit diagram of Figure 9-1. The ADC is shown in the WQFN package option. A four-layer PCB is used, with the inner layers dedicated as ground and power planes. Cutouts are used on the plane layers under the amplifier input pins to reduce stray capacitance to increase amplifier phase margin. Thermal vias for the ADS127L11 and THS4551 WQFN package thermal pad are not used so that bypass capacitors can be placed on the bottom layer underneath the devices. Place the smaller of the parallel supply bypass capacitors closest to the device supply pins. 5V THS4551 ADS127L11 5V Differential Input 1.8 V ADC digital connections 5V VREF 5V REF6041 Figure 9-7. Layout Example of Typical Application Circuit See the QFN and SON PCB Attachment application note for details of attaching the WQFN package to the printed circuit board. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 77 ADS127L11 www.ti.com SBAS946C – APRIL 2021 – REVISED SEPTEMBER 2022 10 Device and Documentation Support 10.1 Documentation Support 10.1.1 Related Documentation For related documentation see the following: • • • • • • • Texas Instruments, ADS127L11 in Simultaneous-Sampling Systems application brief Texas Instruments, ADS127L11 CRC Calculator Texas Instruments, IEPE Vibration Sensor Interface Reference Design for PLC Analog Input design guide Texas Instruments, THS4551 Low-Noise, Precision, 150-MHz, Fully Differential Amplifier data sheet Texas Instruments, REF60xx High-Precision Voltage Reference with Integrated ADC Drive Buffer data sheet Texas Instruments, Design Methodology for MFB Filters in ADC Interface Applications application note Texas Instruments, QFN and SON PCB Attachment application note 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 78 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS127L11 PACKAGE OPTION ADDENDUM www.ti.com 16-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS127L11IPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A127L11 Samples ADS127L11IPWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A127L11 Samples ADS127L11IRUKR ACTIVE WQFN RUK 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A27L11 Samples ADS127L11IRUKT ACTIVE WQFN RUK 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A27L11 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of