ADS1281IPW

ADS1281 AD S 12 81 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 High-Resolution Analog-to-Digital Converter Check for Samples: ADS1281 FEATURES DESCRIPTION • The ADS1281 is an extremely high-performance, single-chip analog-to-digital converter (ADC) designed for the demanding needs of energy exploration and seismic monitoring environments. The single-chip design promotes board area savings for improvements in high-density applications. 1 2 • • • • • • • • • High Resolution: – 130dB SNR (250SPS) – 127dB SNR (500SPS) High Accuracy: – THD: –122dB (typ), –115dB (max) – INL: 0.6ppm Inherently Stable Modulator with Fast Responding Over-Range Detection Flexible Digital Filter: – Sinc + FIR + IIR (Selectable) – Linear or Minimum Phase Response – Programmable High-Pass Filter – Selectable FIR Data Rates: – 250SPS to 4kSPS Filter Bypass Option Low Power Consumption: – Operating: 12mW – Shutdown: 10mW Calibration Engine for Offset and Gain Correction SYNC Input Analog Supply: – Unipolar (+5V) or Bipolar (±2.5V) Digital Supply: 1.8V to 3.3V APPLICATIONS • • • Energy Exploration Seismic Monitoring High-Accuracy Instrumentation AVDD VREFN VREFP The converter uses a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator that provides outstanding noise and linearity performance. The modulator is used either in conjunction with the on-chip digital filter, or can be bypassed for use with post-processing filters. The digital filter consists of sinc and finite impulse response (FIR) low-pass stages followed by an infinite impulse response (IIR) high-pass filter (HPF) stage. Selectable decimation provides data rates from 250 to 4000 samples per second (SPS). The FIR low-pass stage provides both linear and minimum phase response. The HPF features an adjustable corner frequency. On-chip gain and offset scaling registers support system calibration. The synchronization input (SYNC) can be used to synchronize the conversions of multiple ADS1281s. The SYNC input also accepts a clock input for continuous alignment of conversions from an external source. Together, the modulator and filter dissipate only 12mW. The ADS1281 is available in a compact TSSOP-24 package and is fully specified from –40°C to +85°C, with a maximum operating range to +125°C. DVDD ADS1281 AINP 4th-Order DS Modulator AINN Programmable Digital Filter Calibration CLK Serial Interface SCLK DOUT DIN DRDY Control SYNC RESET PWDN Over-Range Modulator Output 3 AVSS DGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2010, Texas Instruments Incorporated ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS1281 UNIT AVDD to AVSS –0.3 to +5.5 V AVSS to DGND –2.8 to +0.3 V DVDD to DGND –0.3 to +3.9 V Input current 100, momentary mA Input current 10, continuous mA AVSS – 0.3 to AVDD + 0.3 V Analog input voltage Digital input voltage to DGND –0.3 to DVDD + 0.3 V +150 °C Operating temperature range –40 to +125 °C Storage temperature range –60 to +150 °C Maximum junction temperature (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 ELECTRICAL CHARACTERISTICS Limit specifications at –40°C to +85°C, typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. (1) = 4.096MHz, VREFP = +2.5V, ADS1281 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage VIN = AINP – AINN Absolute input range AINP or AINN ±VREF/2 AVSS – 0.1 Differential input impedance V AVDD + 0.1 V 55 kΩ AC PERFORMANCE fDATA = 250SPS 130 fDATA = 500SPS Signal-to-noise ratio (2) SNR fDATA = 1000SPS 127 120 fDATA = 2000SPS 118 THD Spurious-free dynamic range (3) SFDR dB 121 fDATA = 4000SPS Total harmonic distortion 124 –122 VIN = 31.25Hz, –0.5dBFS –115 dB 123 dB DC PERFORMANCE Resolution No missing codes Data rate fDATA Integral nonlinearity (4) INL 31 FIR filter mode 250 Sinc filter mode 8,000 Differential input Offset error Offset error after calibration (6) Shorted input Offset drift Gain error 128,000 SPS 0.0005 % FSR (5) 10 200 mV 1 mV 0.06 mV/°C fCM = 60Hz AVDD, AVSS DVDD fPS = 60Hz 0.3 % 0.0002 % 0.4 ppm/°C 105 120 dB 85 95 85 105 Gain drift Common-mode rejection SPS 0.00006 0.1 Gain error after calibration (6) Power-supply rejection Bits 4000 dB FIR DIGITAL FILTER RESPONSE Passband ripple ±0.003 Passband (–0.01dB) 0.375 × fDATA Stop band attenuation (7) dB Hz 135 dB Stop band 0.500 × fDATA Hz Bandwidth (–3dB) 0.413 × fDATA Hz Group delay Settling time (latency) High-pass filter corner (1) (2) (3) (4) (5) (6) (7) (8) FIR filter, minimum phase (8) 5/fDATA FIR filter, linear phase 31/fDATA FIR filter, minimum phase 62/fDATA FIR filter, linear phase 62/fDATA 0.1 s s 10 Hz fCLK = system clock. SNR = signal-to-noise ratio = 20 log (VRMS Full-Scale/VRMS Noise), VIN = 20mVDC. Highest spurious component including harmonics. Best-fit method. FSR: Full-scale range = ±VREF/2. Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings). Input frequencies in the range of NfCLK/512 ± fDATA/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency ranges intermodulation = 120dB, typ. At dc; see Figure 32. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 3 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limit specifications at –40°C to +85°C, typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. ADS1281 PARAMETER CONDITIONS MIN TYP MAX UNIT 0.5 5 (AVDD – AVSS) + 0.2 V V VOLTAGE REFERENCE INPUTS Reference input voltage VREF = VREFP – VREFN Negative reference input VREFN AVSS – 0.1 VREFP – 0.5 Positive reference input VREFP VREFN + 0.5 AVDD + 0.1 Reference input impedance 85 V kΩ DIGITAL INPUT/OUTPUT VIH 0.8 × DVDD DVDD V VIL DGND 0.2 × DVDD V VOH IOH = 1mA VOL IOL = 1mA 0.2 × DVDD V 0 < VDIGITAL IN < DVDD ±10 mA 4.096 MHz Input leakage Clock input fCLK 0.8 × DVDD V 1 POWER SUPPLY AVSS –2.6 0 V AVDD AVSS + 4.75 AVSS + 5.25 V DVDD 1.65 3.6 V AVDD, AVSS current DVDD current Power dissipation (9) 4 Operating mode 2 3 | mA | Standby mode 1 15 | mA | Power-Down mode 1 15 | mA | Operating mode 0.6 0.8 mA Modulator mode 0.1 Standby mode 25 50 Power-Down mode (9) 1 15 mA Operating mode 12 18 mW Standby mode 90 250 mW Power-Down mode 10 150 mW mA mA CLK input stopped. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 DEVICE INFORMATION TSSOP-24 Top View CLK 1 24 BYPAS SCLK 2 23 DGND DRDY 3 22 DVDD DOUT 4 21 PINMODE MOD/DIN 5 20 RESET DGND 6 19 PWDN PHS/MCLK 7 18 VREFP DR1/M1 8 17 VREFN DR0/M0 9 16 AVSS HPF/SYNC 10 15 AVDD MFLAG 11 14 AINN DGND 12 13 AINP ADS1281 TERMINAL FUNCTIONS DESCRIPTION NAME NO. FUNCTION PIN MODE (PINMODE = 1) CLK 1 Digital input Master clock input REGISTER MODE (PINMODE = 0) Master clock input SCLK 2 Digital input SPI serial clock input SPI serial clock input DRDY 3 Digital output Data ready output: read data on falling edge Data ready output: read data on falling edge DOUT 4 Digital output SPI serial data output SPI serial data output DIN: SPI serial data input MOD/DIN 5 Digital input MOD: 0 = Digital filter mode 1 = Filter bypass (modulator output) PHS/MCLK 7 Digital I/O (MOD = 0) PHS: 0 = Linear phase filter, 1 = Minimum phase filter (MOD = 1) MCLK: Modulator clock output If in modulator mode: MCLK: Modulator clock output Otherwise, the pin is an unused input (must be tied). DR1/M1 8 Digital I/O (MOD = 0) DR1 = Data rate select input 1 (MOD = 1) M1 = Modulator data output 1 If in modulator mode: M1: Modulator data output 1 Otherwise, the pin is an unused input (must be tied). DR0/M0 9 Digital I/O (MOD = 0) DR0 = Data rate select input 0 (MOD = 1) M0 = Modulator data output 0 If in modulator mode: M0: Modulator data output 0 Otherwise, the pin is an unused input (must be tied). HPF/SYNC 10 Digital input (MOD = 0) HPF: 0 = High-pass filter off, 1 = HPF on (MOD = 1) SYNC = Synchronize Input SYNC: Synchronize input MFLAG 11 Digital output Modulator over-range flag: 0 = Normal, 1 = Modulator over-range Modulator over-range flag: 0 = Normal, 1 = Modulator over-range DGND 6, 12, 23 Digital ground Digital ground, pin 12 is the key ground point Digital ground, pin 12 is the key ground point AINP 13 Analog input Positive analog input Positive analog input AINN 14 Analog input Negative analog input Negative analog input AVDD 15 Analog supply Positive analog power supply Positive analog power supply AVSS 16 Analog supply Negative analog power supply Negative analog power supply VREFN 17 Analog input Negative reference input Negative reference input VREFP 18 Analog input Positive reference input Positive reference input PWDN 19 Digital input Power-down input, active low Power-down input, active low RESET 20 Digital input Synchronize input Reset input PINMODE 21 Digital input 1 = Pin mode 0 = Register mode DVDD 22 Digital supply Digital power supply: +1.8V to +3.3V Digital power supply: +1.8V to +3.3V BYPAS 24 Capacitor bypass Digital core bypass; 1mF bypass capacitor to GND Digital core bypass; 1mF bypass capacitor to GND Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 5 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com TIMING DIAGRAM tSCDL tSCLK tSPWH SCLK tDIST tSPWL tSCDL DIN tDIHD tDOHD DOUT tDOPD TIMING REQUIREMENTS At TA = –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted. PARAMETER DESCRIPTION MIN MAX UNITS 2 16 1/fCLK SCLK pulse width, high and low (1) 0.8 10 1/fCLK tDIST DIN valid to SCLK rising edge: setup time 50 50 tSCLK tSPWH, (1) (2) 6 SCLK period L ns tDIHD Valid DIN to SCLK rising edge: hold time tDOPD SCLK falling edge to valid new DOUT: propagation delay (2) ns tDOHD SCLK falling edge to DOUT invalid: hold time 0 ns tSCDL Final SCLK rising edge of command to first SCLK rising edge for register read/write data. (Also between consecutive commands.) 24 1/fCLK 100 ns Holding SCLK low for 64 DRDY falling edges resets the SPI interface. Load on DOUT = 20pF || 100kΩ. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. OUTPUT SPECTRUM 0 OUTPUT SPECTRUM 0 VIN = -0.5dBFS, 31.25Hz THD = -121.8dB -20 -40 Amplitude (dB) -40 -60 -80 -100 -120 -140 -60 -80 -100 -120 -140 -160 -160 -180 -180 0 50 100 150 200 250 300 350 400 450 Frequency (Hz) 500 0 50 100 150 200 250 300 350 400 450 Frequency (Hz) Figure 1. OUTPUT SPECTRUM 0 OUTPUT SPECTRUM 0 Shorted Input SNR = 124.1dB -20 -40 Amplitude (dB) -60 -80 -100 -120 -140 -60 -80 -100 -120 -140 -160 -160 -180 -180 0 50 100 150 200 250 300 350 400 450 Frequency (Hz) 500 0 50 100 150 200 250 300 350 400 450 Frequency (Hz) Figure 3. THD vs INPUT FREQUENCY SNR HISTOGRAM 14 -100 VIN = -0.5dBFS 12 -105 500 Figure 4. THD Limited by Signal Generator 25 Units Shorted Input 10 Occurences -110 -115 -120 8 6 4 -125 2 125.00 124.75 124.50 124.25 100 124.00 90 123.75 80 123.00 40 50 60 70 Input Frequency (Hz) 122.75 30 122.50 20 122.25 10 122.00 0 -130 123.50 Amplitude (dB) VIN = 20mVDC SNR = 124.3dB -20 -40 THD (dB) 500 Figure 2. 123.25 Amplitude (dB) VIN = -20dBFS, 31.25Hz THD = -120.1dB -20 SNR (dB) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 7 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. SNR AND THD vs TEMPERATURE NOISE AND THD vs VREF 125 -117 123 -119 122 -121 6 -105 5 -110 4 -115 THD: VIN = 31.25Hz, -0.5dBFS 3 -120 2 THD (dB) 124 THD (dB) SNR (dB) SNR: Shorted Input Noise (mVRMS) -115 -125 Noise: Shorted Input 121 -123 1 -130 THD: VIN = 31.25Hz, -0.5dBFS 120 -55 -35 5 -15 25 45 65 Temperature (°C) 85 -125 125 105 0 140 121 -115 THD: VIN = 31.25Hz, -0.5dBFS PSR and CMR (dB) -110 -120 DVDD 100 80 AVSS AVDD 60 40 40 Data Rate = fCLK/4096 117 2.5 3.0 fCLK (MHz) 3.5 -125 4.5 4.0 0 10 100 1k 10k 100k Power-Supply and Common-Mode Frequency (Hz) Figure 9. 1M Figure 10. LINEARITY ERROR vs INPUT LEVEL INL AND POWER vs TEMPERATURE 16 4 Integral Nonlinearity = ±0.5ppm Power 2 3 12 2 8 INL (ppm) 1 0 -1 1 -3 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 Input Level (V) 1.0 1.5 2.0 2.5 0 -55 4 INL -2 -35 Figure 11. Power (mW) Linearity Error (ppm) 6 CMR 120 119 8 5 POWER-SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY THD (dB) SNR (dB) 4 SNR AND THD vs fCLK SNR: Shorted Input 3 3 Figure 8. 123 2.0 2 Figure 7. -105 1.5 1 VREF (V) 125 1.0 -135 0 -15 5 45 25 65 Temperature (°C) 85 105 0 125 Figure 12. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. POWER vs fCLK GAIN AND OFFSET vs TEMPERATURE 16 100 200 5 Units Power (mW) 12 10 8 6 4 100 75 Gain Error 0 50 -100 25 0 -200 Offset Normalized Offset (mV) Normalized Gain Error (ppm) 14 -25 -300 2 0 0 0.5 1.0 1.5 2.0 2.5 fCLK (MHz) 3.0 3.5 4.0 4.5 -400 -55 -35 -15 Figure 13. 25 45 65 Temperature (°C) 85 105 -50 125 Figure 14. OFFSET HISTOGRAM 10 5 GAIN ERROR HISTOGRAM 18 25 Units 25 Units 16 9 Occurences Occurences 14 7 5 3 12 10 8 6 4 2 2 0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 Offset (mV) Gain Error (%) Figure 15. Figure 16. OFFSET DRIFT HISTOGRAM 90 80 25 Units Based on 20°C Intervals Over the Range -40°C to +85°C. 25 Units Based on 20°C Intervals Over the Range -40°C to +85°C. 45 40 35 Occurences 60 50 40 30 30 25 20 15 10 10 5 0 0 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 20 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Occurences 70 GAIN DRIFT HISTOGRAM 50 Offset Drift (mV/°C) Gain Drift (ppm/°C) Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 9 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com OVERVIEW The ADS1281 is a high-performance analog-to-digital converter (ADC) intended for energy exploration, seismic monitoring, chromatography, and other exacting applications. The converter provides 24- or 32-bit output data in data rates from 4000SPS to 250SPS. Figure 19 shows the block diagram of the ADS1281. The device features unipolar and bipolar analog power supplies (AVDD and AVSS, respectively) for input range flexibility and a digital supply accepting 1.8V to 3.3V. The analog supplies may be set to +5V to accept unipolar signals (with input offset) or set lower in the range of ±2.5V to accept true bipolar input signals (ground referenced). An internal low-dropout (LDO) regulator is used to power the digital core from DVDD. The BYPAS pin is the LDO output and requires a 0.1mF capacitor for noise reduction (BYPAS should not be used to drive external circuitry). The inherently-stable, fourth-order, ΔΣ modulator measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). A digital output (MFLAG) indicates that the modulator is in over-range resulting from an input overdrive condition. The modulator output is available directly on the MCLK, M0, and M1 output pins. The modulator connects to an on-chip digital filter that provides the output code readings. AVDD VREFN The PINMODE input pin determines the mode of the device: Pin control or Register control. In Pin control mode, the device is controlled by simple pin settings; there are no registers to program. In Register control mode, the device is controlled by register settings. The functionality of several device pins depends on the control mode selected (see the Pin and Register Modes section). The SYNC input resets the operation of both the digital filter and the modulator, allowing synchronized conversions of multiple ADS1281 devices to an external event. The SYNC input supports a continuously-toggled input mode that accepts an external data frame clock locked to an integer of the conversion rate. CLK 4th-Order DS Modulator AINN Gain and offset registers scale the digital filter output to produce the final code value. The scaling feature can be used for calibration and sensor gain matching. The output data are provided with either a 24-bit word or a full 32-bit word, allowing full utilization of the inherently high resolution. VREFP ADS1281 AINP The digital filter is comprised of a variable decimation rate, fifth-order sinc filter followed by a decimate-by-32, FIR low-pass filter with programmable phase, and then by an adjustable high-pass filter for dc removal of the output reading. The output of the digital filter can be taken from the sinc, the FIR low-pass, or the IIR high-pass section. BYPAS +1.8V (Digital Core) Programmable Digital Filter LDO DRDY SCLK MOD/DIN DOUT Serial Interface Calibration Over-Range Detection DVDD PINMODE PWDN Control DR1/M1 DR0/M0 AVSS PHS/MCLK MFLAG HPF/SYNC RESET DGND Figure 19. ADS1281 Block Diagram 10 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 The RESET input resets the register settings (Register mode) and also restarts the conversion process. The PWDN input sets the device into a micro-power state. Note that register settings are not retained in PWDN mode. Use the STANDBY command in its place if it is desired to retain register settings (the quiescent current in the Standby mode is slightly higher). Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) provide increased reliability in high-noise environments. The serial interface is used to read conversion data, in addition to reading from and writing to the configuration registers. NOISE PERFORMANCE ADC The ADC block of the ADS1281 is composed of two blocks: a high-accuracy modulator and a programmable digital filter. MODULATOR The high-performance modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as shown in Figure 20. It shifts the quantization noise to a higher frequency (out of the passband) where digital filtering can easily remove it. The modulator can be filtered either by the on-chip digital filter or by use of post-processing filters. fCLK/4 Analog Input (VIN) The ADS1281 offers outstanding noise performance. Table 1 summarizes the SNR performance. Table 1. Noise Performance (Typical) FILTER –3dB BW (Hz) SNR (dB) 250 FIR 103 130 500 FIR 206 127 1000 FIR 413 124 2000 FIR 826 121 4000 FIR 1652 118 (1) VIN = 20mVDC. IDLE TONES The ADS1281 modulator incorporates an internal dither signal that randomizes the idle tone energy. Low-level idle tones may still be present, typically –137dB below full-scale. The low-level idle tones can be shifted out of the passband with the application of an external 20mV offset. 2nd-Order DS 1st-Stage DR0/M0 2nd-Order DS 2nd-Stage (1) DATA RATE PHS/MCLK DR1/M1 4th-Order Modulator Figure 20. Fourth-Order Modulator The modulator first stage converts the analog input voltage into a pulse-code modulated (PCM) stream. When the level of differential analog input (AINP – AINN) is near one-half the level of the reference voltage 1/2 × (VREFP – VREFN), the ‘1’ density of the PCM data stream is at its highest. When the level of the differential analog input is near zero, the PCM ‘0’ and ‘1’ densities are nearly equal. At the two extremes of the analog input levels (+FS and –FS), the ‘1’ density of the PCM streams are approximately +90% and +10%, respectively. The modulator second stage produces a '1' density data stream designed to cancel the quantization noise of the first stage. The data streams of the two stages are then combined before input to the digital filter stage, as shown in Equation 1. Y[n] = 3M0[n - 2] - 6M0[n - 3] + 4M0[n - 4] + 9(M1[n] - 2M1[n - 1] + M1[n - 2]) (1) M0[n] represents the most recent first-stage output while M0[n – 1] is the previous first-stage output. When the modulator output is enabled, the digital filter shuts down to save power. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 11 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com The modulator is optimized for input signals within a 4kHz passband. As Figure 21 shows, the noise shaping of the modulator results in a sharp increase in noise above 6kHz. The modulator has a chopped input structure that further reduces noise within the passband. The noise is moved out of the passband and appears at the chopping frequency (fCLK/512 = 8kHz). The component at 6.5kHz is the tone frequency, shifted out of band by a 20mV offset. The frequency of the tone is proportional to the applied dc input and is given by VIN/0.003 (in kHz). 0 1Hz Resolution VIN = 20mVDC -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 -180 1 10 100 1k 10k 100k Frequency (Hz) Figure 21. Modulator Output Spectrum MODULATOR OVER-RANGE The ADS1281 modulator is inherently stable and, therefore, has predictable recovery behavior that results from an input overdrive condition. The modulator does not exhibit self-resetting behavior, which often results in an unstable output data stream. The ADS1281 modulator outputs a 1s density data stream at 90% duty cycle with the positive full-scale input signal applied (10% duty cycle with the negative full-scale signal). If the input is overdriven past 90% modulation, but below 100% modulation (10% and 0% for negative overdrive, respectively), the modulator remains stable and continues to output the 1s density data stream. The digital filter may or may not clip the output codes to +FS or –FS, depending on the duration of the overdrive. When the input is returned to the normal range from a long duration overdrive (worst case), the modulator returns immediately to the normal range, but the group delay of the digital filter delays the return of the conversion result to within the linear range (31 readings for linear phase FIR). 31 additional readings (62 total) are required for completely settled data. 12 If the inputs are sufficiently overdriven to drive the modulator to full duty cycle, all 1s or all 0s, the modulator enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on the duration. A small duration overdrive may not always clip the output code. When the input returns to the normal range, the modulator requires up to 12 modulator clock cycles (fMOD) to exit saturation and return to the linear region. The digital filter requires an additional 62 conversion for fully settled data (linear phase FIR). In the extreme case of over-range, either input is overdriven exceeding that either analog supply voltage plus an internal ESD diode drop. The internal ESD diodes begin to conduct and the signal on the input is clipped. If the differential input signal range is not exceeded, the modulator remains in linear operation. If the differential input signal range is exceeded, the modulator is saturated but stable, and outputs all 1s or 0s. When the input overdrive is removed, the diodes recovery quickly and the ADS1281 recovers as normal. Note that the linear input range is ±100mV beyond the analog supply voltages; with input levels above this, use care to limit the input current to 100mA peak transient and 10mA continuous. MODULATOR OVER-RANGE DETECTION (MFLAG) The ADS1281 has a fast-responding over-range detection, indicating when the differential input exceeds approximately +100% or –100% full-scale. The threshold tolerance is ±2.5%.The MFLAG output asserts high when in an over-range condition. As Figure 22 and Figure 23 illustrate, the absolute value of the input is compared to 100% of range. The output of the comparator is sampled at the rate of fMOD/2, yielding the MFLAG output. The minimum MFLAG pulse width is fMOD/2. AINP å AINN IABSI P 100% FS Threshold Tolerance: ±2.5% Typical Q MFLAG fMOD/2 Figure 22. Modulator Over-Range Block Diagram Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 VIN (% of Full-Scale) www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 FILTR[1:0] = 00. Pins DR0/M0 and DR1/M1 then become the modulator data outputs and the PHS/MCLK becomes the modulator clock output. When not in the modulator mode, these pins are inputs and must not float. +100 (AINP - AINN) 0 -100 MFLAG Figure 23. Modulator Over-Range Flag Operation MODULATOR OUTPUT MODE The modulator digital stream output is available directly, bypassing and disabling the internal digital filter. The modulator output mode is activated in the Pin mode by setting MOD/DIN = 1, and in Register mode by setting the CONFIG0 register bits The modulator output is composed of three signals: one output for the modulator clock (PHS/MCLK) and two outputs for the modulator data (DR0/M0 and DR1/M1). The modulator clock output rate is fMOD (fCLK/4). Synchronization resets the MODCLK phase, as shown in Figure 24. The SYNC input is latched on the rising edge of CLK. The MODCLK resets and the next rising edge of MODCLK occurs three CLK periods later, as shown in Figure 24. The modulator output data are two bits wide, which must be merged together before being filtered. Use the time domain equation of Equation 1 to merge the data outputs. tCSHD CLK tCMD tSCSU SYNC tSYMD PHS/MCLK (MCLK = CLK/4) tMCD0, 1 DR0/M0 DR1/M1 Figure 24. Modulator Mode Timing Table 2. Modulator Output Timing for Figure 24 PARAMETER tMCD0, (1) 1 DESCRIPTION MIN TYP MODCLK rising edge to M0, M1 valid propagation delay (1) tCMD CLK rising edge to MODCLK rising edge reset time after synchronization tCSHD CLK to SYNC hold time to not latch on CLK edge 10 tSCSU SYNC to CLK setup time to latch on CLK edge 10 tSYMD SYNC to stable bit stream MAX UNIT 100 ns 3 1/fCLK ns ns 16 1/fMOD Load on M0 and M1 = 20pF || 100kΩ. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 13 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Table 4. Digital Filter Selection, Pin Mode DIGITAL FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rate. The digital filter is comprised of three cascaded filter stages: a variable-decimation, fifth-order sinc filter; a fixed-decimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter (HPF), as shown in Figure 25. The output can be taken from one of the three filter blocks, as shown in Figure 25. To implement the digital filter completely off-chip, select the filter bypass setting (modulator output). For partial filtering by the ADS1281, select the sinc filter output. For complete on-chip filtering, activate both the sinc and FIR stages. The HPF can then be included to remove dc and low frequencies from the data. Table 3 shows the filter options in Register mode. Table 4 shows the filter options in Pin mode. MOD/DIN PIN HPF/SYNC PIN DIGITAL FILTERS SELECTED 1 X Bypass; modulator output mode 0 0 Sinc + FIR 0 1 Sinc + FIR + HPF (low-pass and high-pass) Sinc Filter Stage (sinx/x) The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD (fCLK/4). The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter; it is set by the DR[1:0] and MODE selections, as shown in Table 5. Equation 2 shows the scaled Z-domain transfer function of the sinc filter. 5 -N Table 3. Digital Filter Selection, Register Mode FILTR[1:0] BITS DIGITAL FILTERS SELECTED 00 Bypass; modulator output mode 01 Sinc 10 Sinc + FIR 11 Sinc + FIR + HPF (low-pass and high-pass) H(Z) = 1-Z -1 N(1 - Z ) Where: N = decimation ratio (2) 3 Direct Modulator Bit Stream Filter Mode (Register Select) 30 Filter MUX Sinc Filter (Decimate by 8 to 128) From Modulator Coefficient Filter (FIR) (Decimate by 32) High-Pass Filter (IIR) Code Clip CAL Block To Output Register 31 Figure 25. Digital Filter and Output Code Processing Table 5. Sinc Filter Data Rates (CLK = 4.096MHz) 14 DR[1:0] PINS DR[2:0] REGISTER DECIMATION RATIO (N) SINC DATA RATE (SPS) 00 000 128 8,000 01 001 64 16,000 10 010 32 32,000 11 011 16 64,000 — 100 8 128,000 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 The frequency domain transfer function of the sinc filter is shown in Equation 3. 0 -0.5 5 pN ´ f sin fMOD Gain (dB) ½H(f)½ = -1.0 p´f fMOD N sin -1.5 -2.0 (3) -2.5 where: N = decimation ratio (see Table 5) -3.0 0 0.05 The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has zero gain. Figure 26 shows the frequency response of the sinc filter and Figure 27 shows the roll-off of the sinc filter. 0.10 0.15 0.20 Normalized Frequency (fIN/fDATA) Figure 27. Sinc Filter Roll-Off FIR Stage 0 -20 Gain (dB) -40 -60 -80 -100 -120 -140 0 1 2 3 4 Normalized Frequency (fIN/fDATA) 5 The second stage of the ADS1281 digital filter is an FIR low-pass filter. Data are supplied to this stage from the sinc filter. The FIR stage is segmented into four sub-stages, as shown in Figure 28. The first two sub-stages are half-band filters with decimation ratios of 2. The third sub-stage decimates by 4 and the fourth sub-stage decimates by 2. The overall decimation of the FIR stage is 32. Note that two coefficient sets are used for the third and fourth sections, depending on the phase selection. Table 24 in the Appendix section at the end of this document lists the FIR stage coefficients. Table 6 lists the data rates and overall decimation ratio of the FIR stage. Figure 26. Sinc Filter Frequency Response Table 6. FIR Filter Data Rates DR[1:0] PINS DR[2:0] REGISTER DECIMATION RATIO (N) FIR DATA RATE (SPS) 00 000 4096 250 01 001 2048 500 10 010 1024 1000 11 011 512 2000 — 100 256 4000 Sinc Filter FIR Stage 2 Decimate by 2 FIR Stage 1 Decimate by 2 FIR Stage 3 Decimate by 4 FIR Stage 4 Decimate by 2 Output Coefficients Linear Minimum PHASE Select Figure 28. FIR Filter Sub-Stages Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 15 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com As shown in Figure 29, the FIR frequency response provides a flat passband to 0.375 of the data rate (±0.003dB passband ripple). Figure 30 shows the transition from passband to stop band. back (or alias) into the passband and cause errors. Placing an anti-alias, low-pass filter in front of the ADS1281 inputs is recommended to limit possible out-of-band input signals. Often, a single RC filter is sufficient. 2.0 GROUP DELAY AND STEP RESPONSE 1.5 The FIR block is implemented as a multi-stage FIR structure with selectable linear or minimum phase response. The passband, transition band, and stop band responses of the filters are nearly identical but differ in the respective phase responses. Magnitude (mdB) 1.0 0.5 0 -0.5 -1.0 Linear Phase Response -1.5 Linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). Linear phase filters have the property that the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of the signal nature. This filter behavior results in essentially zero phase error when analyzing multi-tone signals. However, the group delay and settling time of the linear phase filter are somewhat larger than the minimum phase filter, as shown in Figure 31. -2.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Normalized Input Frequency (fIN/fDATA) Figure 29. FIR Passband Response (fDATA = 500Hz) 0 -20 Minimum Phase Filter 1.2 -60 1.0 -80 Step Size Magnitude (dB) 1.4 -40 -100 -120 -140 0.35 0.8 0.6 0.4 0.2 0.40 0.45 0.50 0.55 0.60 Normalized Input Frequency (fIN/fDATA) 0.65 Linear Phase Filter 0 -0.2 Figure 30. FIR Transition Band Response 0 Although not shown in Figure 30, the passband response repeats at multiples of the modulator frequency (NfMOD – f0 and NfMOD + f0, where N = 1, 2, etc. and f0 = passband). These image frequencies, if present in the signal and not externally filtered, fold 16 Submit Documentation Feedback 5 10 15 20 25 30 35 40 45 50 55 60 65 Time Index (1/fDATA) Figure 31. FIR Step Response Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 Minimum Phase Response The minimum phase filter provides a short delay from the arrival of an input signal to the output, but the relationship (phase) is not constant versus frequency, as shown in Figure 32. The filter phase is selected by the PHS bit (Register mode) or the PHS/MCLK pin (Pin mode); Table 7 shows additional information. Table 7. FIR Phase Selection PHS BIT or PHS/MCLK PIN FILTER PHASE 0 Linear 1 Minimum HPF[dec] = 65,536 1 - cos wN + sin wN - 1 cos wN (4) Where: HPF = High-pass filter register value (converted to hexadecimal) wN = 2pfHP/fDATA (normalized frequency, radians) fHP = High-pass corner frequency (Hz) fDATA = Data rate (Hz) Table 8. High-Pass Filter Value Examples(1) 35 Linear Phase Filter 30 Group Delay (1/fDATA) 1-2 25 fHP (Hz) DATA RATE (SPS) HPF[1:0] 0.5 250 0337h 1.0 500 0337h 1.0 1000 019Ah (1) In Pin Control mode the HPF value is fixed at 0332h. 20 The HPF causes a small gain error, in which case the magnitude depends on the ratio of fHP/fDATA. For many common values of (fHP/fDATA), the gain error is negligible. Figure 33 shows the gain error of the HPF. The gain error factor is illustrated in Equation 11 (see the Appendix at the end of this document). 15 10 Minimum Phase Filter 5 0 20 40 60 80 100 120 Frequency (Hz) 140 160 180 200 0 Figure 32. FIR Group Delay (fDATA = 500Hz) The last stage of the ADS1281 filter block is a first-order HPF implemented as an IIR structure. This filter stage blocks dc signals and rolls off low-frequency components below the cut-off frequency. The transfer function for the filter is shown in Equation 12 of the Appendix. The high-pass corner frequency is programmed by registers HPF[1:0], in hexadecimal. Equation 4 is used to set the high-pass corner frequency. Table 8 lists example values for the high-pass filter. Gain Error (dB) HPF Stage -0.10 -0.20 -0.30 -0.40 -0.50 0.0001 0.001 0.01 Figure 33. HPF Gain Error Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 0.1 Frequency Ratio (fHP/fDATA) 17 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com ANALOG INPUT CIRCUITRY (AINP, AINN) The ADS1281 measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN) using internal capacitors that are continuously charged and discharged. Figure 36 shows the simplified schematic of the ADC input circuitry; the right side of the figure illustrates the input circuitry with the capacitors and switches replaced by an equivalent circuit. Figure 35 demonstrates the ON/OFF timings for the switches of Figure 36. 90 -7.5 75 -15.0 60 Amplitude 45 -22.5 Phase -30.0 30 -37.5 15 -45.0 0.01 0 0.1 1 10 Normalized Frequency (f/fC) 100 Figure 34. HPF Amplitude and Phase Response In Figure 36, S1 switches close during the input sampling phase. With switch S1 closed, CA1 charges to AINP, CA2 charges to AINN, and CB charges to (AINP – AINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately to AVSS + 2.5V and CB discharges to 0V. This two-phase sample/discharge cycle repeats with a period of tSAMPLE = 1/fMOD. fMOD is the operating frequency of the modulator. See the Master Clock Input (CLK) section. AVDD 0 Phase (°) Amplitude (dB) Figure 34 shows the first-order amplitude and phase response of the HPF. Note that in the case of applying step inputs or synchronizing, the settling time of the filter should be taken into account. tSAMPLE = 1/fMOD ON S1 OFF ON S2 OFF Figure 35. S1 and S2 Switch Timing for Figure 36 AVSS + 2.5V AVSS + 2.5V S2 REFF A = 325kW CA1 = 3pF S1 Equivalent Circuit AINP AINP REFF B = 61kW CB = 16pF S1 (fMOD = 1.024MHz) AINN AINN REFF A = 325kW CA2 = 3pF S2 AVSS AVSS + 2.5V REFF = 1 fMOD ´ CX AVSS + 2.5V RAIN = REFF B || 2REFF A Figure 36. Simplified ADC Input Structure 18 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 The charging of the input sampling capacitors draws a transient current from the source driving the ADS1281 ADC inputs. The average value of this current can be used to calculate an effective impedance (REFF) where REFF = VIN/IAVERAGE. These impedances scale inversely with fMOD. For example, if fMOD is reduced by a factor of two, the impedances double. ESD diodes protect the analog inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 300mV, and likewise do not exceed AVDD by more than 300mV, as shown in Equation 5. AVDD ESD Diodes VREFP 11.5pF VREFN ESD Diodes AVSS - 300mV < (AINP or AINN) < AVDD + 300mV The ADS1281 is a very high-performance ADC. For optimum performance, it is essential that the ADS1281 inputs be driven with a buffer with noise and distortion commensurate with the ADS1281 performance; see the Applications section. Most applications require an external capacitor (C0G/NPO dielectric) directly across the input pins. Depending on the input driver settling characteristics, some experimentation may be necessary to optimize the value to minimize THD (generally 10nF). Best performance is achieved with the common-mode signal centered at mid-supply. Although optimized for differential signals, the ADS1281 inputs may be driven with a single-ended signal by fixing one input to mid-supply. To take advantage of the full dynamic range, the driven input should swing 5VPP for VREF = 5V. VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1281 ADC is the differential voltage between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs with the circuitry on the reference inputs shown in Figure 37. The average load presented by the switched capacitor reference input can be modeled with an effective differential impedance of REFF = tSAMPLE/CIN (tSAMPLE = 1/fMOD). Note that the effective impedance of the reference inputs loads an external reference with non-zero source impedance. REFF = 1 fMOD ´ CX AVSS (5) Some applications of the device may require external clamp diodes and/or series resistors to limit the input voltage to within this range. REFF = 85kW (fMOD = 1.024MHz) Figure 37. Simplified Reference Input Circuit The ADS1281 reference inputs are protected by ESD diodes. In order to prevent these diodes from turning on, the voltage on either input must stay within the range shown in Equation 6: AVSS - 300mV < (VREFP or VREFN) < AVDD + 300mV (6) A high-quality reference voltage is necessary for achieving the best performance from the ADS1281. Noise and drift on the reference degrade overall system performance, and it is critical that special care be given to the circuitry generating the reference voltages in order to achieve full performance. For most applications, a 1mF ceramic capacitor applied directly to the reference inputs pins is suggested. MASTER CLOCK INPUT (CLK) The ADS1281 requires a clock input for operation. The clock is applied to the CLK pin. The data conversion rate scales directly with the CLK frequency. Power consumption versus CLK frequency is relatively constant (see the Typical Characteristics). As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keep the clock trace as short as possible and use a 50Ω series resistor close to the source. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 19 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com PIN AND REGISTER MODES SYNCHRONIZATION (SYNC PIN AND SYNC COMMAND) The PINMODE input (pin 21) is used to set the control mode of the device: Pin mode or Register mode. In Pin mode (PINMODE = 1), control of the device is set by pins; there are no registers to program. In Register mode, control of the device is set by the configuration registers. As a result of the increased flexibility provided by the register space, Register mode has more control options. Table 9 describes the differences between the control modes. The ADS1281 can be synchronized to an external event, as well as synchronized to other ADS1281 devices if the sync event is applied simultaneously to all devices. The ADS1281 has two sources for synchronization: the SYNC input pin and the SYNC command. The ADS1281 also has two synchronizing modes: Pulse-sync and Continuous-sync. In Pulse-sync mode, the ADS1281 synchronizes to a single sync event. In Continuous-sync mode, either the device synchronizes to a single sync event or a continuous clock is applied to the pin with a period equal to integer multiples of the data rate. When the periods of the sync input and the DRDY output do not match, the ADS1281 re-synchronizes and conversions are restarted. Note that in Pin control mode, the RESET input serves as the sync control. Table 10 summarizes the functions of the dual-purpose pins, depending on the control mode selected. Table 9. Functions for Pin Mode and Register Mode FUNCTION PIN MODE (PINMODE = 1) REGISTER MODE (PINMODE = 0) Synchronization options Pulse only Continuous or Pulse Digital filter options Sinc + LPF or Sinc + LPF + HPF Sinc, Sinc + LPF, or Sinc + LPF + HPF Digital high-pass filter frequency Fixed low-cut as ratio of fDATA Programmable Calibration registers No Yes Interface commands No Yes Table 10. Mode-Dependent Pin Functions 20 PIN PIN MODE (PINMODE = 1) REGISTER MODE (PINMODE = 0) MOD/DIN MOD input (select Modulator mode) SPI DIN input HPF/SYNC HPF input (select high-pass filter) SYNC input RESET Sync input Reset input PHS/MCLK LPF phase input or MCLK output MCLK output DR0/M0 DR0 input or M0 output M0 output DR1/M1 DR1 input or M1 output M1 output Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 PULSE-SYNC MODE In Pulse-sync mode, the ADS1281 stops and restarts the conversion process when a sync event occurs (by pin or command). When the sync event occurs, the device resets the internal memory; DRDY goes high, and after the digital filter has settled, new conversion data are available, as shown in Figure 38 and Table 11. Synchronization occurs on the next rising CLK edge after the SYNC pin rising edge; or after the eighth rising SCLK edge (opcode SYNC). To be effective, the SYNC opcode should broadcast simultaneously to all ADS1281s. tCSHD System Clock (fCLK) tSCSU SYNC Command CONTINUOUS-SYNC MODE tSPWH In Continuous-sync mode, either a single sync pulse or a continuous clock may be applied. When a single sync pulse is applied (rising edge), the device behaves similar to the Pulse-sync mode. However, in this mode, DRDY continues to toggle unaffected but the DOUT output is held low until data are ready. When the conversion data are non-zero, new conversion data are ready (as shown in Figure 38). When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data rate or the device re-synchronizes. Note that synchronization results in the restarting of the digital filter and an interruption of 63 readings. SYNC Pin tSPWL tDR New Data Ready tDR New Data Ready DRDY (Pulse-Sync) DRDY (Continuous-Sync) DOUT Figure 38. Pulse-Sync Timing, Continuous-Sync Timing with Single Sync When the sync input is first applied on the first rising edge of CLK, the device re-synchronizes (under the condition tSYNC ≠ N/fDATA). DRDY continues to output but DOUT is held low until the new data are ready. Then, if the period of the applied sync clock matches an integral multiple of the output data rate, the device freely runs without re-synchronization. The phase of the applied clock and output data rate (DRDY) are not matched as a result of the initial delay of DRDY after SYNC is applied. Figure 39 shows the timing for Continuous-sync mode. tSCSU tCSHD System Clock (fCLK) tSPWL tSPWH SYNC tSYNC DRDY 1/fDATA Figure 39. Continuous-Sync Timing with Sync Clock Table 11. Pulse-Sync Timing for Figure 38 and Figure 39 PARAMETER DESCRIPTION MIN MAX UNITS tSYNC SYNC period (1) 1 Infinite n/fDATA tCSHD CLK to SYNC hold time to not latch on CLK edge 10 tSCSU SYNC to CLK setup time to latch on CLK edge 10 ns SYNC pulse width, high or low 2 1/fCLK tSPWH, tDR (1) L Time for data ready (SINC filter) Time for data ready (FIR filter) ns See Appendix, Table 25 62.98046875/fDATA + 468/fCLK Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 21 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com RESET (RESET Pin and Reset Command) The ADS1281 may be reset in two ways: toggle the RESET pin low or send a Reset command. When using the RESET pin, take it low and hold for at least 2/fCLK to force a reset. The ADS1281 is held in reset until the pin is released. By command, RESET takes effect on the next rising edge of fCLK after the eighth rising edge of SCLK of the command. Note: to ensure that the Reset command can function, the SPI interface may require a reset; see the Serial Interface section. In reset, registers are set to default and the conversions are synchronized on the next rising edge of CLK. New conversion data are available, as shown in Figure 40 and Table 12. Settled Data DRDY tDR tCRHD Wakeup Command DRDY tDR Figure 41. PWDN Pin and Wake-Up Command Timing (Table 13 shows tDR) The ADS1281 has three power supplies: AVDD, AVSS, and DVDD. Figure 42 shows the power-on sequence of the ADS1281. The power supplies can be sequenced in any order. The supplies [the difference of (AVDD – AVSS) and DVDD] generate an internal reset whose outputs are summed to generate a global internal reset. After the supplies have crossed the minimum thresholds, 216 fCLK cycles are counted before releasing the internal reset. After the internal reset is released, new conversion data are available, as shown in Figure 42 and Table 13. tRCSU RESET Pin or RESET Command Figure 40. Reset Timing Table 12. Reset Timing for Figure 40 PARAMETER DESCRIPTION PWDN Pin POWER-ON SEQUENCE System Clock (fCLK) tRST In power-down, note that the device outputs remain active and the device inputs must not float. When the Standby command is sent, the SPI port and the configuration registers are kept active. Figure 41 and Table 13 show the timing. MIN UNITS tCRHD CLK to RESET hold time 10 ns tRCSU RESET to CLK setup time 10 ns tRST RESET low 2 1/fCLK tDR Time for data ready 62.98046875/ fDATA + 468/fCLK 3.5V nom AVDD - AVSS 1V nom DVDD CLK 16 POWER-DOWN (PWDN Pin and Standby Command) 2 fCLK Internal Reset There are two ways to power-down the ADS1281: take the PWDN pin low or send a Standby command. When the PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the register settings are reset. DRDY tDR Figure 42. Power-On Sequence Table 13. Power-On, PWDN Pin, and Wake-Up Command Timing for New Data PARAMETER DESCRIPTION FILTER MODE 16 tDR (1) (2) 22 Time for data ready 2 CLK cycles after power-on; and new data ready after PWDN pin or Wake-Up command SINC (1) See Appendix, Table 25 62.98046875/fDATA + 468/fCLK (2) FIR Supply power-on and PWDN pin default is 1000SPS FIR. Subtract 2 CLK cycles for the Wake-Up command. The Wake-Up command is timed from the next rising edge of CLK to after the eighth rising edge of SCLK during command to DRDY falling. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 DVDD POWER SUPPLY Serial Clock (SCLK) The DVDD supply operates over the range of +1.65V to +3.6V. If DVDD is operated at less than 2.25V, connect the DVDD pin to the BYPAS pin. If DVDD is greater than or equal to 2.25V, do not connect DVDD to the BYPAS pin. Figure 43 shows this connection. The serial clock (SCLK) is an input that is used to clock data into (DIN) and out of (DOUT) the ADS1281. This input is a Schmitt-trigger input that has a high degree of noise immunity. However, it is recommended to keep SCLK as clean as possible to prevent possible glitches from inadvertently shifting the data. 1.65V to 3.6V DVDD Data are shifted into DIN on the rising edge of SCLK and data are shifted out of DOUT on the falling edge of SCLK. If SCLK is held low for 64 DRDY cycles, data transfer or commands in progress terminate and the SPI interface resets. The next SCLK pulse starts a new communication cycle. This timeout feature can be used to recover the interface when a transmission is interrupted or SCLK inadvertently glitches. SCLK should remain low when not active. ADS1281 Tie DVDD to BYPAS if DVDD power is < 2.25V. Otherwise float BYPAS. BYPAS 1 mF Figure 43. DVDD Power Data Input (DIN) SERIAL INTERFACE A serial interface is used to read the conversion data and access the configuration registers. The interface consists of three basic signals: SCLK, DIN, and DOUT. An additional output, DRDY, transitions low in Read Data Continuous mode when data are ready for retrieval. Figure 44 shows the connection when multiple converters are used. FPGA or Processor SCLK DOUT1 ADS1281 DIN2 DRDY1 SCLK DOUT2 ADS1281 DIN2 DRDY2 SCLK DOUT1 The data input pin (DIN) is used to input register data and commands to the ADS1281. Keep DIN low when reading conversion data in the Read Data Continuous mode (except when issuing a STOP Read Data Continuous command). Data on DIN are shifted into the converter on the rising edge of SCLK. In Pin mode, DIN is not used. Data Output (DOUT) The data output pin (DOUT) is used to output data from the ADS1281. Data are shifted out on DOUT on the falling edge of SCLK. In Pin mode, only conversion data are read from this pin. DIN1 IRQ SCLK (optional) DOUT2 DIN2 IRQ (optional) Figure 44. Pin Mode Interface for Multiple Devices Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 23 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Data Ready (DRDY) DATA FORMAT DRDY is an output; when it transitions low, this transition indicates new conversion data are ready, as shown in Figure 45. When reading data by the continuous mode, the data must be read within four CLK periods before DRDY goes low again or the data are overwritten with new conversion data. When reading data by the command mode, the read operation can overlap the occurrence of the next DRDY without data corruption. The ADS1281 provides 32 bits of conversion data in binary twos complement format, as shown in Table 14. The LSB of the data is a redundant sign bit: '0' for positive numbers and '1' for negative numbers. However, when the output is clipped to +FS, the LSB = 1; when the output is clipped to –FS, the LSB = 0. If desired, the data readback may be stopped at 24 bits. Note that in sinc filter mode, the output data are scaled by 1/2. Table 14. Ideal Output Code versus Input Signal DRDY 32-BIT IDEAL OUTPUT CODE(1) DOUT Bit 31 Bit 30 Bit 29 INPUT SIGNAL VIN (AINP – AINN) SCLK VREF > 2 VREF Figure 45. DRDY with Data Retrieval 2 DRDY resets high on the first falling edge of SCLK. Figure 45 and Figure 46 show the function of DRDY with and without data readback, respectively. VREF 2 ´ (230 - 1) 0 If data are not retrieved (no SCLK provided), DRDY pulses high for four fCLK periods during the update time, as shown in Figure 46. 4/fCLK -VREF 2 ´ (230 - 1) -VREF Data Updating 2 DRDY < Figure 46. DRDY with No Data Retrieval 24 ´ -VREF 2 230 230 - 1 ´ 230 FIR FILTER SINC FILTER(2) 7FFFFFFFh (3) 7FFFFFFEh 3FFFFFFFh 00000002h 00000001h 00000000h 00000000h FFFFFFFFh FFFFFFFFh 80000001h C0000000h 80000000h (3) 230 - 1 (1) Excludes effects of noise, linearity, offset, and gain errors. (2) As a result of the reduction in oversampling ratio (OSR) related to the sinc filter high data rates, the available resolution may be reduced. (3) In sinc filter mode, the output does not clip when the full-scale range is exceeded. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 READING DATA The ADS1281 has two ways to read conversion data: Read Data Continuous and Read Data By Command. Read Data Continuous In the Read Data Continuous mode, the conversion data are shifted out directly from the device without the need for sending a read command. This mode is the default mode at power-on. This mode is also enabled by the RDATAC command. When DRDY goes low, indicating that new data are available, the MSB of data appears on DOUT, as shown in Figure 47. The data are normally read on the rising edge of SCLK and at the occurrence of the first falling edge of SCLK, DRDY returns high. After 32 bits of data have been shifted out, further SCLK transitions cause DOUT to go low. If desired, the read operation may be stopped at 24 bits. The data shift operation must be completed within four CLK periods before DRDY falls again or the data may be corrupted. The Read Data Continuous mode is the default data mode for Pin mode. When a Stop Read Data Continuous command is issued, the DRDY output is blocked but the ADS1281 continues conversions. In stop continuous mode, the data can only be read by command. DRDY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 28 29 30 31 32 SCLK DOUT Data Byte 1 (MSB) Data Byte 2 (MSB - 1) Data Byte 4 (LSB) tDDPD DIN Figure 47. Read Data Continuous Table 15. Timing Data for Figure 47 PARAMETER tDDPD (1) DESCRIPTION MIN DRDY to valid MSB on DOUT propagation delay (1) TYP MAX UNITS 100 ns Load on DOUT = 20pF || 100kΩ. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 25 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Read Data By Command ONE-SHOT OPERATION The Read Data Continuous mode is stopped by the SDATAC command. In this mode, conversion data are read by command. In the Read Data By Command mode, a read data command must be sent to the device for each data conversion (as shown in Figure 48). When the read data command is received (on the eighth SCLK rising edge), data are available to read only when DRDY goes low (tDR). When DRDY goes low, conversion data appear on DOUT. The data may be read on the rising edge of SCLK. The ADS1281 can perform very power-efficient, one-shot conversions using the STANDBY command while under software control. Figure 49 shows this sequence. First, issue the STANDBY command to set the Standby mode. When ready to make a measurement, issue the WAKEUP command. Monitor DRDY; when it goes low, the fully settled conversion data are ready and may be read directly in Read Data Continuous mode. Afterwards, issue another STANDBY command. When ready for the next measurement, repeat the cycle starting with another WAKEUP command. DRDY tDR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 SCLK DOUT Don't Care Data Byte 1 (MSB) Date Byte 4 (LSB) tDDPD DIN Command Byte (0001 0010) Figure 48. Read Data By Command, RDATA (tDDPD timing is given in Table 15) Table 16. Read Data Timing for Figure 48 PARAMETER DESCRIPTION tDR MIN Time for new data after data read command Standby ADS1281 Status TYP MAX UNITS 1 fDATA 0 Performing One-Shot Conversion Standby DRDY DIN STANDBY (1) STANDBY WAKEUP Settled Data DOUT (1) See Figure 41 and Table 13 for time to new data. Figure 49. One-Shot Conversions Using the STANDBY Command 26 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 Table 17. Offset Calibration Values OFFSET AND FULL-SCALE CALIBRATION REGISTERS The conversion data can be scaled for offset and gain before yielding the final output code. As shown in Figure 50, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC). Equation 7 shows the scaling: FSC[2:0] Final Output Data = (Input - OFC[2:0]) ´ 400000h (7) The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically by calibration commands. OFC[2:0] Registers The offset calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 19. The offset register is left-justified to align with the 32-bits of conversion data. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from the conversion data. A register value of 00000h has no offset correction (default value). Note that while the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 17), to avoid input overload, the analog inputs cannot exceed the full-scale range. AINP Digital Filter Modulator AINN FINAL OUTPUT CODE(1) OFC REGISTER 7FFFFFh 80000000h 000001h FFFFFF00h 000000h 00000000h FFFFFFh 00000100h 800000h 7FFFFF00h (1) Full 32-bit final output code with zero code input. FSC[2:0] Registers The full-scale calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 20. The full-scale calibration value is 24-bit, straight offset binary, normalized to 1.0 at code 400000h. Table 18 summarizes the scaling of the full-scale register. A register value of 400000h (default value) has no gain correction (gain = 1). Note that while the gain calibration register value corrects gain errors above 1 (gain correction < 1), the full-scale range of the analog inputs should not exceed 103% to avoid input overload. Table 18. Full-Scale Calibration Register Values FSC REGISTER GAIN CORRECTION 800000h 2.0 400000h 1.0 200000h 0.5 000000h 0 + Output Data Clipped to 32 Bits S ´ OFC Register FSC Register 400000h - Final Output Figure 50. Calibration Block Diagram Table 19. Offset Calibration Word REGISTER BYTE OFC0 LSB BIT ORDER B7 B6 B5 B4 B3 B2 B1 B0 (LSB) OFC1 MID B15 B14 B13 B12 B11 B10 B9 B8 OFC2 MSB B23 (MSB) B22 B21 B20 B19 B18 B17 B16 B1 B0 (LSB) Table 20. Full-Scale Calibration Word REGISTER BYTE FSC0 LSB BIT ORDER B7 B6 B5 B4 B3 B2 FSC1 MID B15 B14 B13 B12 B11 B10 B9 B8 FSC2 MSB B23 (MSB) B22 B21 B20 B19 B18 B17 B16 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 27 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com CALIBRATION COMMANDS OFSCAL Command Calibration commands may be sent to the ADS1281 to calibrate the conversion data. The values of the offset and gain calibration registers are internally written to perform calibration. The appropriate input signals must be applied to the ADS1281 inputs before sending the commands. Use slower data rates to achieve more consistent calibration results; this effect is a byproduct of the lower noise that these data rates provide. Also, if calibrating at power-on, be sure the reference voltage is fully settled. The OFSCAL command performs an offset calibration. Before sending the offset calibration command, a zero input signal must be applied to the ADS1281 and the inputs allowed to stabilize. When the command is sent, the ADS1281 averages 16 readings and then writes this value to the OFC register. The contents of the OFC register may be subsequently read or written. During offset calibration, the full-scale correction is bypassed. Figure 51 shows the calibration command sequence. After the analog input voltage (and reference) have stabilized, send the Stop Data Continuous command followed by the SYNC and Read Data Continuous commands. 64 data periods later, DRDY goes low. After DRDY goes low, send the Stop Data Continuous, then the Calibrate command followed by the Read Data Continuous command. After 16 data periods, calibration is complete and conversion data may be read at this time. The SYNC input must remain high during the calibration sequence. Note that calibration is bypassed in sinc filter mode. GANCAL Command The GANCAL command performs a gain calibration. Before sending the GANCAL command sequence (Figure 51), a dc input must be applied (typically full-scale input, but not to exceed 103% full-scale). After the signal has stabilized, the command sequence can be sent. The ADS1281 averages 16 readings, then computes a gain value that makes the applied input the new full-scale. The gain value is written to the FSC register, whose contents may be subsequently read or written. VIN Fully stable signal input and reference voltage. Commands SDATAC DRDY SYNC RDATAC SDATAC OFSCAL or GANCAL RDATAC 16 Data Periods 64 Data Periods Calibration Complete SYNC Figure 51. Offset/Gain Calibration Timing 28 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 USER CALIBRATION System calibration of the ADS1281 can be performed without using the calibration commands. This procedure requires the calibration values to be externally calculated and then written to the calibration registers. The steps for this procedure are: 1. Set the OFSCAL[2:0] register = 0h and GANCAL[2:0] = 400000h. These values set the offset and gain registers to 0 and 1, respectively. 2. Apply a zero differential input to the input of the system. Wait for the system to settle and then average n output readings. Higher numbers of averaged readings result in more consistent calibration. Write the averaged value to the OFC register. 3. Apply a differential dc signal, or an ac signal (typically full-scale, but not to exceed 103% full-scale). Wait for the system to settle and then average the n output readings. The value written to the FSC registers is calculated by Equation 8 and Equation 9. DC signal calibration is shown in Equation 8 and Equation 9. The expected output code is based on 31-bit output data. FSC[2:0] = 400000h ´ Expected Output Code Actual Output Code (8) 31 Expected Output Code = 2 ´ VIN ´ 2 VREF (9) For ac signal calibration, use an RMS value of collected data (as shown in Equation 10). Expected RMS Value FSC[2:0] = 400000h ´ Actual RMS Value (10) Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 29 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com COMMANDS The commands listed in Table 21 control the operation of the ADS1281. Command operations are only possible in Register mode. Most commands are stand-alone (that is, 1 byte in length); the register reads and writes require a second command byte in addition to the actual data bytes. In Read Data Continuous mode, the ADS1281 places conversion data on the DOUT pin as SCLK is applied. As a consequence of the potential conflict of conversion data on DOUT and data placed on DOUT resulting from a register or Read Data By Command operation, it is necessary to send a STOP Read Data Continuous command before Register or Data Read By Command. The STOP Read Data Continuous command disables the direct output of conversion data on the DOUT pin. A delay of 24 fCLK cycles between commands and between bytes within a command is required, starting from the last SCLK rising edge of one command to the first SCLK rising edge of the following command. This delay is shown in Figure 52. DIN Command Byte Command Byte SCLK (1) tSCLKDLY (1) tSCLKDLY = 24/fCLK (min). Figure 52. Consecutive Commands Table 21. Command Descriptions 1st COMMAND BYTE (1) (2) COMMAND TYPE DESCRIPTION WAKEUP Control Wake-up from Standby mode 0000 000X (00h or 01h) STANDBY Control Enter Standby mode 0000 001X (02h or 03h) SYNC Control Synchronize the A/D conversion 0000 010X (04h or 5h) RESET Control Reset registers to default values 0000 011X (06h or 07h) RDATAC Control Read data continuous 0001 0000 (10h) SDATAC Control Stop read data continuous 0001 0001 (11h) RDATA Data Read data by command (4) RREG Register Read nnnnn register(s) at address rrrrr 0001 0010 (12h) (4) 001r rrrr (20h + 000r rrrr) 000n nnnn (00h + n nnnn) 000n nnnn (00h + n nnnn) WREG Register Write nnnnn register(s) at address rrrrr 010r rrrr (40h + 000r rrrr) OFSCAL Calibration Offset calibration 0110 0000 (60h) GANCAL Calibration Gain calibration 0110 0001 (61h) (1) (2) (3) (4) 30 2nd COMMAND BYTE (3) X = don't care. rrrrr = starting address for register read and write commands. nnnnn = number of registers to be read/written – 1. For example, to read/write three registers, set nnnnn = 2 (00010). Required to cancel Read Data Continuous mode before sending a command. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 WAKEUP: Wake-Up From Standby Mode SDATAC: Stop Read Data Continuous Description: This command is used to exit the standby mode. Upon sending the command, the time for the first data to be ready is illustrated in Figure 41 and Table 14. Sending this command during normal operation has no effect; for example, reading data by the Read Data Continuous method with DIN held low. Description: This command stops the Read Data Continuous mode. Exiting the Read Data Continuous mode is required before sending Register and Data read commands. This command suppresses the DRDY output, but the ADS1281 continues conversions. STANDBY: Standby Mode RDATA: Read Data By Command Description: This command places the ADS1281 into Standby mode. In Standby, the device enters a reduced power state where a low quiescent current remains to keep the register settings and SPI interface active. For complete device shutdown, take the PWDN pin low (register settings are not saved). To exit Standby mode, issue the WAKEUP command. The operation of Standby mode is shown in Figure 53. Description: This command reads the conversion data. See the Read Data By Command section for more details. DIN 0000 001X (STANDBY) 0000 000X (WAKEUP) Standby Mode Description: This command is used to read single or multiple register data. The command consists of a two-byte op-code argument followed by the output of register data. The first byte of the op-code includes the starting address, and the second byte specifies the number of registers to read – 1. First command byte: 001r rrrr, where rrrrr is the starting address of the first register. SCLK Operating RREG: Read Register Data Operating Figure 53. STANDBY Command Sequence SYNC: Synchronize the A/D Conversion Description: This command synchronizes the A/D conversion. Upon receipt of the command, the reading in progress is cancelled and the conversion process is re-started. In order to synchronize multiple ADS1281s, the command must be sent simultaneously to all devices. Note that the SYNC pin must be high for this command. RESET: Reset the Device Description: The RESET command resets the registers to default values, enables the Read Data Continuous mode, and restarts the conversion process; the RESET command is functionally the same as the RESET pin. See Figure 40 for the RESET command timing. RDATAC: Read Data Continuous Description: This command enables the Read Data Continuous mode (default mode). In this mode, conversion data can be read from the device directly without the need to supply a data read command. Each time DRDY falls low, new data are available to read. See the Read Data Continuous section for more details. Second command byte: 000n nnnn, where nnnnn is the number of registers – 1 to read. Starting with the 16th falling edge of SCLK, the register data appear on DOUT. The RREG command is illustrated in Figure 54. Note that a delay of 24 fCLK cycles is required between each byte transaction. WREG: Write to Register Description: This command writes single or multiple register data. The command consists of a two-byte op-code argument followed by the input of register data. The first byte of the op-code contains the starting address and the second byte specifies the number of registers to write – 1. First command byte: 001r rrrr, where rrrrr is the starting address of the first register. Second command byte: 000n nnnn, where nnnnn is the number of registers – 1 to write. Data byte(s): one or more register data bytes, depending on the number of registers specified. Figure 55 illustrates the WREG command. Note that a delay of 24 fCLK cycles is required between each byte transaction. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 31 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com OFSCAL: Offset Calibration GANCAL: Gain Calibration Description: This command performs an offset calibration. The inputs to the converter (or the inputs to the external pre-amplifier) should be zeroed and allowed to stabilize before sending this command. The offset calibration register updates after this operation. See the Calibration Commands section for more details. Description: This command performs a gain calibration. The inputs to the converter should have a stable dc input (typically full-scale, but not to exceed 103% full-scale). The full-scale calibration register updates after this operation. See the Calibration Commands section for more details. tDLY 1 2 3 4 5 6 7 8 9 tDLY 10 11 12 13 14 15 16 tDLY 17 18 19 20 21 22 23 24 25 26 SCLK DIN Command Byte 1 DOUT Command Byte 2 Don't Care Register Data 5 Register Data 6 Example: Read six registers, starting at register 05h (OFC0) Command Byte 1 = 0010 0101 Command Byte 2 = 0000 0101 Figure 54. Read Register Data (Table 22 shows tDLY) tDLY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tDLY tDLY 17 18 19 20 21 22 23 24 25 26 SCLK DIN Command Byte 1 Command Byte 2 Register Data 5 Register Data 6 Example: Write six registers, starting at register 05h (OFC0) Command Byte 1 = 0100 0101 Command Byte 2 = 0000 0101 Figure 55. Write Register Data (Table 22 shows tDLY) Table 22. tDRY Value 32 PARAMETER MIN tDLY 24/fCLK Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 REGISTER MAP The Register mode (PINMODE = 0) allows read and write access to the device registers. Collectively, the registers contain all the information needed to configure the device, such as data rate, filter selection, calibration, etc. The registers are accessed by the RREG and WREG commands. The registers can be accessed individually or as a block of registers by sending or receiving consecutive bytes. Note that after a register write operation, the ADC resets, resulting in 63 reading interruption. Table 23. Register Map ADDRESS REGISTER RESET VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 00h ID X0h ID3 ID2 ID1 ID0 0 0 0 0 01h CONFIG0 52h SYNC 1 DR2 DR1 DR0 PHS FILTR1 FILTR0 02h Reserved 08h 0 0 0 0 1 0 0 0 03h HPF0 32h HPF07 HPF06 HPF05 HPF04 HPF03 HPF02 HPF01 HPF00 04h HPF1 03h HPF15 HPF14 HPF13 HPF12 HPF11 HPF10 HPF09 HPF08 05h OFC0 00h OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 06h OFC1 00h OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 07h OFC2 00h OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 08h FSC0 00h FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 09h FSC1 00h FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 0Ah FSC2 40h FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 BIT 0 ID: ID REGISTER (ADDRESS 00h) 7 6 5 4 3 2 1 0 ID3 ID2 ID1 ID0 0 0 0 0 Reset value = X8h. Bits[7:4] ID[3:0] Factory-programmed identification bits (read-only) Bits[3:0] Reserved Always write '0' Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 33 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com CONFIG0: CONFIGURATION REGISTER 0 (ADDRESS 01h) 7 6 5 4 3 2 1 0 SYNC 1 DR2 DR1 DR0 PHASE FILTR1 FILTR0 Reset value = 52h. Bit[7] SYNC Synchronization mode 0: Pulse SYNC mode (default) 1: Continuous SYNC mode Bit[6] Reserved Always write '1' (default) Bits[5:3] Data Rate Select DR[2:0] 000: 001: 010: 011: 100: Bit[2] 250SPS 500SPS 1000SPS (default) 2000SPS 4000SPS FIR Phase Response PHASE 0: Linear phase (default) 1: Minimum phase Bits[1:0] Digital Filter Select FILTR[1:0] Digital filter configuration 00: On-chip filter bypassed, modulator output mode 01: Sinc filter block only 10: Sinc + LPF filter blocks (default) 11: Sinc + LPF + HPF filter blocks RESERVED: (ADDRESS 02h) 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 Reset value = 08h. Bits[7:0] Reserved Always write '08h' 34 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 HPF1 and HPF0 These two bytes (high-byte and low-byte, respectively) set the corner frequency of the HPF. HPF0: High-Pass Filter Corner Frequency, Low Byte (Address 03h) 7 6 5 4 3 2 1 0 HP07 HP06 HP05 HP04 HP03 HP02 HP01 HP00 Reset value = 32h. HPF1: High-Pass Filter Corner Frequency, High Byte (Address 04h) 7 6 5 4 3 2 1 0 HP15 HP14 HP13 HP12 HP11 HP10 HP09 HP08 Reset value = 03h. OFC2, OFC1, OFC0 These three bytes set the OFC value. OFC0: Offset Calibration, Low Byte (Address 05h) 7 6 5 4 3 2 1 0 OC07 OC06 OC05 OC04 OC03 OC02 OC01 OC00 Reset value = 00h. OFC1: Offset Calibration, Mid Byte (Address 06h) 7 6 5 4 3 2 1 0 OC15 OC14 OC13 OC12 OC11 OC10 OC09 OC08 Reset value = 00h. OFC2: Offset Calibration, High Byte (Address 07h) 7 6 5 4 3 2 1 0 OC23 OC22 OC21 OC20 OC19 OC18 OC17 OC16 Reset value = 00h. FSC2, FSC1, FSC0 These three bytes set the FSC value. FSC0: Full-Scale Calibration, Low Byte (Address 08h) 7 6 5 4 3 2 1 0 FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 Reset value = 00h. FSC1: Full-Scale Calibration, Mid Byte (Address 09h) 7 6 5 4 3 2 1 0 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 Reset value = 00h. FSC2: Full-Scale Calibration, High Byte (Address 0Ah) 7 6 5 4 3 2 1 0 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 Reset value = 40h. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 35 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com CONFIGURATION GUIDE The ADS1281 offers two modes of operation: Pin Control mode and Register Control mode. In Pin Control mode, the operation of the device is controlled by the pins; there are no registers to program. In Register Control mode, the registers are used to control device operation. After RESET or power-on, the registers can be configured using the following procedure: 1. Reset the SPI interface. Before using the SPI interface, it may be necessary to recover the SPI interface (undefined I/O power-up sequencing may cause false SCLK detection). To reset the SPI interface, toggle the RESET pin or, when in Read Data Continuous mode, hold SCLK low for 64 DRDY periods. 2. Configure the registers. The registers are configured by either writing to them individually or as a group. Software may be configured in either mode. The STOPC command must be sent before register read/write operations to cancel the Read Data Continuous mode. 36 3. Verify register data. The register may be read back for verification of device communications. 4. Set the data mode. After register configuration, the device may be configured for Read Data Continuous mode, either by the Read Data Continuous command or configured in Read Data By Register mode using STOPC command. 5. Synchronize readings. Whenever SYNC is high, the ADS1281 freely runs the data conversions. To stop and restart the conversions, take SYNC low and then high. 6. Read data. If the Read Data Continuous mode is active, the data are read directly after DRDY falls by applying SCLK pulses. If the Read Data Continuous mode is inactive, the data can only be read by Read Data By Command. The Read Data command must be sent in this mode to read each conversion result (note that DRDY only asserts after each read data command is sent). Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 APPLICATION INFORMATION The ADS1281 is a very high-resolution ADC. Optimal device performance requires giving special attention to the support circuitry and printed circuit board (PCB) design. Locate noisy digital components, such as microcontrollers and oscillators, in an area of the PCB away from the converter or front-end components. Place the digital components close to the power-entry point to keep the digital current path short and separate from sensitive analog components. The REF02 +5V reference provides the reference to the ADS1281. The reference output is filtered by the optional R3 and C1 filter network. The filter requires several seconds to settle after power-on. Capacitor C2 provides high-frequency bypassing of the reference inputs and should be placed close to the ADS1281 pins. Note that R3 (1kΩ) results in a systematic gain error (1.2%). The filter can be externally buffered to eliminate the gain error. Alternatively, the REF5050 (5V) or REF5045 (4.5V) reference can be used. The REF5045 reference has the advantage of +5V power supply operation. The REF5050 requires +5.2V minimum power supply. Figure 56 shows a typical geophone interface. This application circuit shows the ADS1281 and the OPA211 pre-amplifiers operating with ±2.5V supplies. The OPA211s are shown with gain = +4 [G = 1 + 2 (R2/R1)]. This pre-amplifier configuration has inherently good common-mode rejection. The 49.9Ω resistors isolate the driver outputs from the bypass capacitor. As with any precision circuit, use good supply bypassing techniques. Place the capacitors close to the device pins. If switching dc/dc supplies are used to power the device, check for frequency components of the supply present within the ADS1281 passband. Voltage ripple should be kept as low as possible. The 20kΩ input resistors provide the common-mode bias for the amplifiers. The optional differential and common-mode input filters attenuate possible out-of-band interference (such as RFI). Recommended 75kΩ resistors provide a 20mVDC input offset. The offset moves the low-level idle tones out of the passband. +2.5V +2.5V 100W +2.5V 100W -2.5V 49.9W OPA211 C0G 1nF 20kW C0G 10nF Geophone R1 200W 100W 1mF 15 16 AVDD AVSS R2 301W C0G 1nF 20kW 1mF R2 301W 49.9W 100W 13 10nF C0G 14 OPA211 AINP AINN -2.5V G=1+2 R2 ADS1281 R1 || 2 ´ 75kW -2.5V 75kW 75kW +6.5V (REF5050 +2.8V) 1mF R3 1kW REF02 REF5050 1mF 18 C1 100mF C2 0.1mF 17 VREFP VREFN DGND -2.5V 6, 12, 23 Figure 56. Geophone Interface, Dual Power-Supply Configuration Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 37 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Figure 57 shows the digital connection to an FPGA (field programmable gate array) device. In this example, two ADS1281s are shown connected. The DRDY output from each ADS1281 can be used; however, when the devices are synchronized, the DRDY output from only one device is sufficient. A shared SCLK line between the devices is optional. For best performance, the FPGA and the ADS281s should operate from the same clock. Avoid ringing on the digital inputs. 47Ω resistors in series with the digital traces can help to reduce ringing by controlling impedances. Place the resistors at the source (driver) end of the trace. Unused digital inputs should not float; tie them directly to DVDD or GND. The modulator over-range flag (MFLAG) from each device ties to the FPGA. For synchronization, one SYNC control line connects all ADS1281 devices. The RESET line also connects to all ADS1281 devices. 4.096MHz Clock 47W +3.3V 22 (1) CLK DVDD 1mF 1 ADS1281 20 RESET 24 5 1mF DOUT BYPAS DIN PINMOD SCLK HPF/SYNC MFLAG DGND 4 47W RESET 47W DOUT1 47W 5 DIN1 47W 2 SCLK1 47W 10 SYNC 47W 11 CLK Input MFLAG1 4, 12, 23 +3.3V (1) DVDD CLK ADS1281 1mF RESET 24 5 1mF DOUT BYPAS PINMOD DIN SCLK HPF/SYNC MFLAG DGND DRDY 1 FPGA 20 4 47W DOUT2 5 DIN2 2 SCLK2 47W 10 47W 11 3 47W MFLAG2 DRDY 6, 12, 23 NOTE: Dashed lines are optional. (1) For DVDD < 2.25V, see the DVDD Power Supply section. Figure 57. FPGA Device 38 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 APPENDIX Table 24. FIR Stage Coefficients SESSION 1 SESSION 2 SESSION 3 SESSION 4 Scaling = 134217728 Scaling = 134217728 COEFFICIENT LINEAR PHASE SCALING = 1/512 LINEAR PHASE SCALING = 1/8388608 LINEAR PHASE MINIMUM PHASE LINEAR PHASE b0 3 –10944 0 819 –132 11767 b1 0 0 0 8211 –432 133882 b2 –25 103807 –73 44880 –75 769961 b3 0 0 –874 174712 2481 2940447 b4 150 –507903 –4648 536821 6692 8262605 b5 256 0 –16147 1372637 7419 17902757 b6 150 2512192 –41280 3012996 –266 30428735 b7 0 4194304 –80934 5788605 –10663 40215494 b8 –25 2512192 –120064 9852286 –8280 39260213 b9 0 0 –118690 14957445 10620 23325925 b10 3 –507903 –18203 20301435 22008 –1757787 b11 0 224751 24569234 348 –21028126 b12 103807 580196 26260385 –34123 –21293602 b13 0 893263 24247577 –25549 –3886901 b14 –10944 891396 18356231 33460 14396783 b15 293598 9668991 61387 16314388 b16 –987253 327749 –7546 1518875 b17 –2635779 –7171917 –94192 –12979500 b18 –3860322 –10926627 –50629 –11506007 b19 –3572512 –10379094 101135 2769794 b20 –822573 –6505618 134826 12195551 b21 4669054 –1333678 –56626 6103823 b22 12153698 2972773 –220104 –6709466 b23 19911100 5006366 –56082 –9882714 b24 25779390 4566808 263758 –353347 b25 27966862 2505652 231231 8629331 b26 25779390 126331 –215231 5597927 b27 19911100 –1496514 –430178 –4389168 b28 12153698 –1933830 34715 –7594158 b29 4669054 –1410695 580424 –428064 b30 –822573 –502731 283878 6566217 b31 –3572512 245330 –588382 4024593 b32 –3860322 565174 –693209 –3679749 b33 –2635779 492084 366118 –5572954 b34 –987253 231656 1084786 332589 b35 293598 –9196 132893 5136333 b36 891396 –125456 –1300087 2351253 b37 893263 –122207 –878642 –3357202 b38 580196 –61813 1162189 –3767666 b39 224751 –4445 1741565 1087392 b40 –18203 22484 –522533 3847821 b41 –118690 22245 –2490395 919792 b42 –120064 10775 –688945 –2918303 MINIMUM PHASE Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 39 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Table 24. FIR Stage Coefficients (continued) COEFFICIENT 40 SESSION 1 SESSION 2 LINEAR PHASE SCALING = 1/512 LINEAR PHASE SCALING = 1/8388608 SESSION 3 SESSION 4 Scaling = 134217728 LINEAR PHASE Scaling = 134217728 MINIMUM PHASE LINEAR PHASE MINIMUM PHASE b43 –80934 940 2811738 –2193542 b44 –41280 –2953 2425494 1493873 b45 –16147 –2599 –2338095 2595051 b46 –4648 –1052 –4511116 –79991 b47 –874 –43 641555 –2260106 b48 –73 214 6661730 –963855 b49 0 132 2950811 1482337 b50 0 33 –8538057 1480417 b51 0 0 –10537298 –586408 b52 9818477 –1497356 b53 41426374 –168417 b54 56835776 1166800 b55 41426374 644405 b56 9818477 –675082 b57 –10537298 –806095 b58 –8538057 211391 b59 2950811 740896 b60 6661730 141976 b61 641555 –527673 b62 –4511116 –327618 b63 –2338095 278227 b64 2425494 363809 b65 2811738 –70646 b66 –688945 –304819 b67 –2490395 –63159 b68 –522533 205798 b69 1741565 124363 b70 1162189 –107173 b71 –878642 –131357 b72 –1300087 31104 b73 132893 107182 b74 1084786 15644 b75 366118 –71728 b76 –693209 –36319 b77 –588382 38331 b78 283878 38783 b79 580424 –13557 b80 34715 –31453 b81 –430178 –1230 b82 –215231 20983 b83 231231 7729 b84 263758 –11463 b85 –56082 –8791 b86 –220104 4659 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 Table 24. FIR Stage Coefficients (continued) SESSION 1 SESSION 2 LINEAR PHASE SCALING = 1/512 LINEAR PHASE SCALING = 1/8388608 SESSION 3 SESSION 4 Scaling = 134217728 Scaling = 134217728 LINEAR PHASE MINIMUM PHASE b87 –56626 7126 b88 134826 –732 b89 101135 –4687 b90 –50629 –976 b91 –94192 2551 b92 –7546 1339 b93 61387 –1103 b94 33460 –1085 b95 –25549 314 b96 –34123 681 COEFFICIENT LINEAR PHASE MINIMUM PHASE b97 348 16 b98 22008 –349 b99 10620 –96 b100 –8280 144 b101 –10663 78 b102 –266 –46 b103 7419 –42 b104 6692 9 b105 2481 16 b106 –75 0 b107 –432 –4 b108 –132 0 b109 0 0 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 41 ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 1+ 1-2 HPF Gain Error Factor = 2- www.ti.com cos wN + sin wN - 1 cos wN cos wN + sin wN - 1 cos wN (11) See the HPF Stage section for an example of how to use this equation. HPF Transfer Function -1 2-a 1-Z ´ HPF(Z) = -1 1 - bZ 2 (12) where b is calculated as shown in Equation 13: 2 1 + (1 - a) b= 2 (13) Table 25. tDR Time for Data Ready (Sinc Filter) fDATA (1) fCLK (1) 128k 440 64k 616 32k 968 16k 1672 8k 2824 For SYNC and Wake-Up commands, fCLK = number of CLK cycles from next rising CLK edge directly after eighth rising SCLK edge to DRDY falling edge. For Wake-Up command only, subtract two fCLK cycles. Table 25 is referenced by Table 11 and Table 13. 42 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2009) to Revision D Page • Added footnote 8 to Electrical Characteristics table ............................................................................................................. 3 • Moved Equation 12 and Equation 13 to the Appendix from the HPF Stage section .......................................................... 17 • Added footnote 2 to Table 14, Ideal Output Code .............................................................................................................. 24 • Corrected sign typo in Equation 11 .................................................................................................................................... 42 • Updated Equation 13 .......................................................................................................................................................... 42 Changes from Revision B (August 2008) to Revision C Page • Changed tCMD specification from 5 to 3 CLK cycles in Modulator Output Timing table ...................................................... 13 • Updated Equation 2 to include decimation ratio ................................................................................................................. 14 • Corrected typo in Equation 3 .............................................................................................................................................. 15 • Updated Figure 29 .............................................................................................................................................................. 16 • Minor graphical edits to Figure 38 ...................................................................................................................................... 21 • Minor graphical edits to Figure 39 ...................................................................................................................................... 21 • Changed 466/fCLK to 468/fCLK in tDR row of Table 11 .......................................................................................................... 21 • Added 103% FS limit to gain calibration ............................................................................................................................. 28 • Changed Figure 56, showing alternate bias resistor location ............................................................................................. 37 • Corrected Table 24 (Appendix, FIR Stage Coefficients) .................................................................................................... 39 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 43 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1281IPW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1281 ADS1281IPWG4 ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1281 ADS1281IPWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1281 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of