ADS1285IRHBT

ADS1285 SBAS559A – MAY 2022 – REVISED DECEMBER 2022 ADS1285 32-Bit, Delta-Sigma ADC for Seismic Applications 1 Features 3 Description • The ADS1285 is a 32-bit, low-power, analog-to-digital converter (ADC), with a programmable gain amplifier (PGA) and a finite impulse response (FIR) filter. The ADC is designed for the demanding needs of seismology equipment requiring low-noise precision digitization and extended battery run time. • • • • • • • • • • • • • Selectable resolution-power modes: – Dynamic range: 134 dB at 2 ms, 11.5 mW – Dynamic range: 129 dB at 2 ms, 4.8 mW Flexible digital filter: – Selectable sinc + FIR + IIR – Linear or minimum phase – High-pass filter THD: < –120 dB CMRR: 125 dB Data rates: 125 SPS to 4000 SPS Programmable gains: 1 to 64 PGA bypass option SYNC input Clock error compensation Two-channel multiplexer Offset and gain calibration General-purpose digital I/Os Analog supply operation: 5 V, 3.3 V, or ±2.5 V Reference voltage options: 5 V, 4.096 V, or 2.5 V The low-noise PGA allows direct connection of geophones and transformer-coupled hydrophones without the need of an external amplifier. The ADC incorporates a high-resolution, delta-sigma (ΔΣ) modulator and a FIR filter with programmable phase response. The high-pass filter removes dc and low-frequency content from the signal. Clock frequency error is compensated by the sample rate converter with 7-ppb resolution. Choice of power modes optimize dynamic range verses power consumption. Power consumption is further reduced by PGA bypass operation. 2 Applications • • • • The ADC is available in a compact 5-mm × 5-mm VQFN package and is fully specified over the –40°C to +85°C ambient temperature range. Energy exploration Passive seismic monitoring Earth sciences and geology Precision instrumentation Package Information(1) PART NUMBER ADS1285 (1) AVDD1 PACKAGE RHB (VQFN, 32) IOVDD CLK DRDY ADS1285 AIN2P PGA MUX BUF
Modulator Sample Rate Converter Digital Filter Serial Interface CS SCLK DOUT DIN Control PWDN RESET SYNC AIN2N Noise/Offset Test AVSS AGND 5.00 mm × 5.00 mm For all available packages, see the package option addendum at the end of the data sheet. AVDD2 AIN1P AIN1N BODY SIZE (NOM) REFP REFN GPIO1 GPIO0 GND Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V......................................... 10 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V...............................10 6.8 Timing Diagrams....................................................... 11 6.9 Typical Characteristics.............................................. 13 7 Parameter Measurement Information.......................... 23 7.1 Noise Performance................................................... 23 8 Detailed Description......................................................25 8.1 Overview................................................................... 25 8.2 Functional Block Diagram......................................... 26 8.3 Feature Description...................................................27 8.4 Device Functional Modes..........................................40 8.5 Programming............................................................ 44 8.6 Register Map.............................................................49 9 Application and Implementation.................................. 54 9.1 Application Information............................................. 54 9.2 Typical Application.................................................... 54 9.3 Power Supply Recommendations.............................56 9.4 Layout....................................................................... 57 10 Device and Documentation Support..........................58 10.1 Receiving Notification of Documentation Updates..58 10.2 Support Resources................................................. 58 10.3 Trademarks............................................................. 58 10.4 Electrostatic Discharge Caution..............................58 10.5 Glossary..................................................................58 11 Mechanical, Packaging, and Orderable Information.................................................................... 58 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (May 2022) to Revision A (December 2022) Page • First public release, changed document status from Advance Information to Production Data ........................ 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 AVSS CAPR REFP REFN PWDN RESET SYNC DRDY 32 31 30 29 28 27 26 25 5 Pin Configuration and Functions AIN1P 1 24 DOUT AIN1N 2 23 DIN AIN2P 3 22 SCLK AIN2N 4 21 CS CAPP 5 20 CLK CAPN 6 19 IOVDD CAPBP 7 18 DGND CAPBN 8 17 CAPD 9 10 11 12 13 14 15 16 CAPC AVSS AVDD1 AVDD2 AGND CAPI GPIO0 GPIO1 Thermal pad Not to scale Figure 5-1. RHB Package, 32-Pin, 5-mm × 5-mm VQFN (Top View) Table 5-1. Pin Functions PIN NO. NAME FUNCTION DESCRIPTION 1 AIN1P Analog input Channel 1 positive input 2 AIN1N Analog input Channel 1 negative input 3 AIN2P Analog input Channel 2 positive input 4 AIN2N Analog input Channel 2 negative input 5 CAPP Analog internal PGA positive capacitor. Connect a 10-nF C0G capacitor across CAPP and CAPN. 6 CAPN Analog internal PGA negative capacitor. Connect a 10-nF C0G capacitor across CAPP and CAPN. 7 CAPBP Analog internal Buffer positive capacitor. Connect a 47-nF C0G capacitor to AVSS. 8 CAPBN Analog internal Buffer negative capacitor. Connect a 47-nF C0G capacitor to AVSS. 9 CAPC Analog internal Charge-pump capacitor. Connect a 4.7-nF, minimum 10-V rated capacitor to AGND. 10 AVSS Analog supply PGA negative analog supply. See the Analog Power Supplies section for details. 11 AVDD1 Analog supply PGA positive analog supply. See the Analog Power Supplies section for details. 12 AVDD2 Analog supply Modulator analog supply. See the Analog Power Supplies section for details. 13 AGND Analog ground Analog ground 14 CAPI Analog internal Input bias capacitor. Connect a 100-nF ceramic capacitor to AGND. 15 GPIO0 Digital I/O General-purpose I/O 16 GPIO1 Digital I/O General-purpose I/O 17 CAPD Analog output 18 DGND Ground 19 IOVDD Digital supply 20 CLK Digital input ADC clock input 21 CS Digital input Serial interface select, active low 22 SCLK Digital input Serial interface clock 23 DIN Digital input Serial interface data in 24 DOUT Digital output Serial interface data out 25 DRDY Digital output Data ready, active low 26 SYNC Digital input ADC synchronization, active high 27 RESET Digital input ADC reset, active low 28 PWDN Digital input ADC power down, active low 29 REFN Analog input Negative reference input. See the Voltage Reference Input section for details. 30 REFP Analog input Positive reference input. See the Voltage Reference Input section for details. 31 CAPR Analog internal Reference bias capacitor. Connect a 100-nF ceramic capacitor to AVSS. 32 AVSS Analog supply PGA negative supply Thermal pad Digital low-dropout regulator (LDO) output. Connect a 220-nF ceramic capacitor to DGND. Digital ground Digital I/O power supply. See the IOVDD Power Supply section for details. Connect the thermal pad to AVSS. Thermal vias placed in the printed circuit board (PCB) land are optional for placement of bottom side components. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 3 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX AVDD1 to AVSS –0.3 5.5 AVSS to AGND –2.8 0.3 AVDD2 to AGND –0.3 5.5 AVDD2 to AVSS –0.3 5.5 IOVDD to DGND –0.3 3.9 IOVDD to DGND (IOVDD connected to CAPD) –0.3 2.2 Grounds AGND to DGND – 0.3 0.3 V Analog input voltage AIN1P, AIN1N, AIN2P, AIN2N, REFP, REFN V Digital input voltage CLK, DIN, SCLK, CS, GPIO0, GPIO1, SYNC, RESET, PWDN Input current Continuous, any digital or analog pin (2) Power supply voltages Temperature (1) (2) UNIT V AVSS – 0.3 AVDD1 + 0.3 DGND – 0.3 IOVDD + 0.3 –10 10 mA 150 °C 150 °C Junction, TJ Storage, Tstg –60 V Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional – this may affect device reliability, functionality, performance, and shorten the device lifetime. Analog input pins AIN1P, AIN1N, AIN2P, AIN2N, REFP and REFN are diode-clamped to AVDD1 and AVSS. Limit the input current to 10 mA in the event the analog input voltage exceeds AVDD1 + 0.3 V or AVSS – 0.3 V. Digital input pins are clamped to IOVDD and DGND. Limit the input current if the digital input voltage exceeds IOVDD + 0.3 V or DGND – 0.3 V. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) UNIT 2000 Charged-device model (CDM), per JEDEC JESD22-C101(2) V 1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT 5.25 V POWER SUPPLY AVDD1 to AVSS 3 AVDD1 to AGND Analog power supplies AVSS to AGND 2.375 –2.625 0 2.375 5.25 AVDD2 to AGND AVDD2 to AVSS Digital power supply V 5.25 IOVDD to DGND IOVDD connected to CAPD 2.7 3.6 1.65 1.95 V ANALOG INPUTS Reference voltage = 5 V VIN Differential input voltage VIN = VAINP – VAINN Absolute input voltage Absolute output voltage 4 ±VREF / (2 × Gain) Reference voltage = 4.096 V ±VREF / (1.6384 × Gain) Reference voltage = 2.5 V V ±VREF / Gain Buffer operation AVSS + 0.1 AVDD1 – 0.1 PGA operation AVSS + 1.1 AVDD1 – 0.85 Buffer operation AVSS + 0.1 AVDD1 – 0.1 PGA operation AVSS + 0.15 AVDD1 – 0.15 Submit Document Feedback V V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions (continued) over operating ambient temperature range (unless otherwise noted) MIN NOM Calibration range (1) MAX UNIT 6% FSR VOLTAGE REFERENCE INPUT VREFN Negative reference input VREFP Positive reference input VREF VREF = VREFP – VREFN AVSS – 0.05 V AVDD1 + 0.1 V Reference voltage = 5 V 4.9 5 AVDD1 – AVSS + 0.1 V Reference voltage = 4.096 V 4.0 4.096 4.2 V Reference voltage = 2.5 V 2.4 2.5 2.6 V 0.2 × IOVDD V DIGITAL INPUTS VINL Low-level input voltage VINH High-level input voltage fCLK 0.8 × IOVDD Clock input frequency V High-power mode 6 8.192 8.3 Mid-power mode 6 8.192 8.3 Low-power mode 3 4.096 4.15 MHz TEMPERATURE TA (1) Ambient temperature Operational –50 85 Specification –40 85 °C Calibration range is the sum of the offset and gain error correction. 6.4 Thermal Information ADS1285 THERMAL METRIC(1) RHB (VQFN) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 30 °C/W RθJC(top) RθJB Junction-to-case (top) thermal resistance 19.4 °C/W Junction-to-board thermal resistance 10.9 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 10.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 5 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.5 Electrical Characteristics minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1, fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Input mux on-resistance Input 1 to input 2 cross connection 60 Ω nA PGA OPERATION IB PGA Input bias current High-power mode 45 IOS PGA Input offset current High-power mode ±3 PGA Gain High-power mode en-PGA PGA Input voltage noise density Mid-power mode PGA Input current noise density V/V 5.5 PGA Gain = 16 7 Low-power mode in-PGA nA 1, 2, 4, 8, 16, 32, 64 nV/√Hz 7 Differential Antialias filter frequency 2.5 pA/√Hz 30 kHz BUFFER OPERATION High-power mode IB Input current Mid-power mode ±1.2 VIN = 2.5 V ±1.2 Low-power mode µA ±0.3 DC PERFORMANCE en Noise See Noise Performance section for details PGA operation VOS Offset error –350/gain - 10 ±30/gain + 5 350/gain + 10 –600 ±50 600 Buffer operation After calibration Offset error drift PGA operation 0.5/gain Buffer operation Gain match Relative to PGA gain = 1 Gain drift All PGA gains Common-mode rejection ratio f = 60 Hz Power-supply rejection ratio –0.07% ±0.05% 0.07% –0.2% ±0.06% 0.2% 2 AVSS, AVDD1 At dc IOVDD 6 ±0.02% 0.05% 2 AVDD2 PSRR –0.05% After calibration Buffer operation CMRR µV/°C 1 PGA operation, gain = 1 Gain error µV ±1 Submit Document Feedback ppm ppm/°C 104 120 dB 80 95 dB 85 110 dB 100 120 dB Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.5 Electrical Characteristics (continued) minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1, fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE en-MOD Modulator voltage noise density VREF = 4.096 V 25 High-power mode, VREF = 2.5 V, AVDD1 = 3.3 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Mid-power mode, VREF = 2.5 V, AVDD1 = 3.3 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Low-power mode, VREF = 2.5 V, AVDD1 = 3.3 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS THD Total harmonic distortion High-power mode, VREF = 4.096 V, AVDD1 = 5 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Mid-power mode, VREF = 4.096 V, AVDD1 = 5 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Low-power mode, VREF = 4.096 V, AVDD1 = 5 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS SFDR nV/√Hz Buffer operation –123 PGA gain = 2 –119 -114 PGA gain = 4 –125 PGA gain = 8 –124 PGA gain = 16 –123 PGA gain = 32 and 64 –125 Buffer operation –122 PGA gain = 2 –120 PGA gain = 4 –125 PGA gain = 8 –124 PGA gain = 16 –123 PGA gain = 32 and 64 –125 Buffer operation –124 PGA gain = 2 –122 PGA gain = 4 –124 PGA gain = 8 –125 PGA gain = 16 –123 PGA gain = 32 and 64 –124 Buffer operation –119 -114 PGA gain = 1 –119 -111 PGA gain = 2 –125 PGA gain = 4 –122 PGA gain = 8 –118 -116 dB -116 -113 -118 dB -115 -117 -116 dB -115 -114 PGA gain = 16 –117 PGA gain = 32 and 64 –125 Buffer operation –119 -112 PGA gain = 1 –119 -111 PGA gain = 2 –125 PGA gain = 4 –124 PGA gain = 8 –119 dB -111 -115 PGA gain = 16 –117 PGA gain = 32 and 64 –124 Buffer operation –123 -117 PGA gain = 1 –121 -115 PGA gain = 2 –124 PGA gain = 4 –125 PGA gain = 8 –122 PGA gain = 16 –121 PGA gain = 32 and 64 –123 dB -111 -115 dB -113 Spurious-free dynamic range fIN = 31.25 Hz, VIN = –0.5 dBFS 115 dB Crosstalk fIN = 31.25 Hz, VIN = –0.5 dBFS –140 dB Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 7 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.5 Electrical Characteristics (continued) minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1, fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE INPUT Reference input current High-power mode 110 Mid-power mode 110 Low-power mode 80 µA/V FIR DIGITAL FILTER fDATA Data rate High-power mode 250 4000 Mid-power mode 250 4000 Low-power mode Pass-band ripple 125 2000 –0.003 0.003 SPS dB Pass-band (–0.01 dB) 0.375 × fDATA Hz Bandwidth (–3 dB) 0.413 × fDATA Hz 0.5 × fDATA Hz Stop band Stop-band attenuation (1) Group delay Settling time (latency) 135 dB Minimum phase filter, at dc 5 / fDATA Linear phase filter 31/ fDATA Minimum phase filter 62 / fDATA Linear phase filter 62 / fDATA s s IIR DIGITAL FILTER High-pass corner frequency 0.1 10 Hz SAMPLE RATE CONVERTER Clock compensation range –244 Resolution 244 ppm of fCLK 7.45 ppb of fCLK DIGITAL INPUT/OUTPUT VOH High-level output voltage IOH = 1 mA VOL Low-level output voltage IOL = –1 mA Ilkg Input leakage 0.8 × IOVDD V –1 0.2 × IOVDD V 1 μA POWER SUPPLY IAVDD1, IAVSS AVDD1, AVSS current High-power mode AVDD1 = 3.3 V PGA operation 1.4 Buffer operation 0.25 Mid-power mode AVDD1 = 3.3 V PGA operation 0.85 Buffer operation 0.25 Low-power mode AVDD1 = 3.3 V PGA operation 0.8 Buffer operation 0.2 High-power mode AVDD1 = 5 V PGA operation 1.5 1.85 Buffer operation 0.35 0.45 Mid-power mode AVDD1 = 5 V PGA operation 0.9 1.2 Buffer operation 0.35 0.45 Low-power mode AVDD1 = 5 V PGA operation 0.85 1.1 Buffer operation 0.25 0.45 Power-down mode High-power mode IAVDD2 AVDD2 current Mid-power mode Low-power mode AVDD2 = 2.5 V Power-down mode 8 Submit Document Feedback mA mA mA 1 5 1.2 1.5 1.2 1.5 0.7 0.85 1 5 mA mA mA µA mA µA Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.5 Electrical Characteristics (continued) minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1, fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted) PARAMETER IOVDD current TYP MAX High-power mode TEST CONDITIONS 0.43 0.6 Mid-power mode 0.43 0.6 Low-power mode 0.24 0.4 1 10 Power-down mode IIOVDD Standby mode 200 High-power mode IOVDD additional current Mid-power mode (1) (2) Power dissipation (2) UNIT mA μA 1.2 Sample rate converter operation Low-power mode Pd MIN 1.2 mA 0.6 High-power mode AVDD1 = 3.3 V AVDD2 = 2.5 V PGA operation 8.3 Buffer operation 4.5 Mid-power mode AVDD1 = 3.3 V AVDD2 = 2.5 V PGA operation 6.5 Buffer operation 4.5 Low-power mode AVDD1 = 3.3 V AVDD2 = 2.5 V PGA operation 4.8 Buffer operation 2.8 High-power mode AVDD1 = 5 V AVDD2 = 2.5 V PGA operation 11.5 14.1 Buffer operation 5.3 6.7 Mid-power mode AVDD1 = 5 V AVDD2 = 2.5 V PGA operation 8.3 10.8 Buffer operation 5.3 6.7 Low-power mode AVDD1 = 5 V AVDD2 = 2.5 V PGA operation 6.4 8.4 Buffer operation 3.4 5.1 mW mW mW mW mW mW Input frequencies at N × 32 kHz (16 kHz low-power mode) ± fDATA / 2 (where N = 1, 2, 3...) intermodulate with the chopper clock. At these frequencies stop band attenuation = –90 dBFS (typ). Excluding current consumed by the voltage reference input or by sample rate converter operation. See voltage reference input current and IOVDD current of sample rate converter operation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 9 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V over operating ambient temperature range (unless otherwise noted) MIN NOM MAX High-power mode 120.5 122.07 166 Mid-power mode 120.5 122.07 166 Low-power mode 241 244.14 332 High-power mode 55 UNIT CLOCK tc(CLK) CLK period tw(CLKH) tw(CLKL) Pulse duration, CLK high Pulse duration, CLK low Mid-power mode 55 Low-power mode 110 High-power mode 55 Mid-power mode 55 Low-power mode 110 ns ns ns SERIAL INTERFACE tw(CSH) Pulse duration, CS high 20 ns td(CSSC) Delay time, first SCLK rising edge after CS falling edge 20 ns tc(SCLK) SCLK period 120 ns tw(SCH) Pulse duration, SCLK high 50 ns tw(SCL) Pulse duration, SCLK low 50 ns tsu(DI) Setup time, DIN valid before SCLK rising edge 10 ns th(DI) Hold time, DIN valid after SCLK rising edge 10 ns tsu(SRC-W) Setup time, SRC[1:0] register write before DRDY falling edge 256 1 / f(CLK) SYNC tw(SYNL) Pulse duration, SYNC low 2 1 / f(CLK) tw(SYNH) Pulse duration, SYNC high 2 1 / f(CLK) tsu(SYNCLK) Setup time, SYNC high before CLK rising edge 10 ns th(SYNCLK) Hold time, SYNC high after CLK rising edge 10 ns RESET tw(RSTL) Pulse duration, RESET low 2 1 / f(CLK) tsu(RSTCLK) Setup time, RESET high before CLK rising edge 10 ns th(RSTCLK) Hold time, RESET high after CLK rising edge 10 ns 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V over operating ambient temperature range and CLOAD = 20pF (unless otherwise noted) PARAMETER MIN TYP MAX UNIT SERIAL INTERFACE tw(DRH) Pulse duration, DRDY high tp(CSDO) Propagation delay time, CS falling edge to DOUT driven valid tp(SCDO) Propagation delay time, SCLK falling edge to new DOUT valid th(SCDO) Propagation delay time, SCLK falling edge to DOUT invalid 5 8 1 / f(CLK) 50 ns 50 ns ns SYNC tp(SYNDR) Propagation delay time, SYNC rising edge to valid data DRDY falling edge 62.98145 / fDATA + 930 / fCLK s Propagation delay time, RESET rising edge to DRDY falling edge 516,874 1/ fCLK Propagation delay time, PWDN rising edge to DRDY falling edge 62.98145 / fDATA + 946 / f(CLK) s 650,000 1 / fCLK RESET tp(RSTDR) PWDN tp(PDDR) POWER UP tp(SUPDR) 10 Propagation delay time, power supply and CLK applied to first DRDY pulse Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.8 Timing Diagrams tc(CLK) tw(CLKL) CLK tw(CLKH) Figure 6-1. Clock Timing Requirements tw(CSH) CS td(CSSC) tc(SCLK) tw(SCH) SCLK tsu(DI) tw(SCL) DIN th(DI) Figure 6-2. Serial Interface Timing Requirements tw(DRH) DRDY CS SCLK tp(CSDO) th(SCDO) MSB DOUT LSB 0 tp(SCDO) Figure 6-3. Serial Interface Switching Characteristics CLK th(SYNCLK) tsu(SYNCLK) SYNC tw(SYNL) tw(SYNH) DRDY (settled data) (Pulse sync mode) tp(SYNDR) (settled data) DRDY (Continuous sync mode) Figure 6-4. SYNC Timing Requirements and Switching Characteristics Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 11 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 CLK th(RSTCLK) tsu(RSTCLK) RESET tw(RSTL) tp(RSTDR) DRDY Figure 6-5. RESET Timing Requirements and Switching Characteristics PWDN DRDY tp(PDDR) Figure 6-6. PWDN Switching Characteristics DRDY SPI SRC[1:0] Register Write tsu(SCR-W) Figure 6-7. Sample Rate Converter Register-Write Timing Requirements AVDD1 – AVSS 1.65 V typ. AVDD2 – AGND 1.65 V typ. CAPD – DGND 1.35 V typ. + – + – + – CLK DRDY tp(SUPDR) Figure 6-8. Power-Up Switching Characteristics 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 25 50 Shorted input, PGA gain = 1 0 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 0 -80 -100 -120 -160 -180 175 200 225 Buffer operation PGA gain = 1 operation -180 250 0 5 10 15 Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V 20 25 30 Frequency (Hz) 35 40 45 50 225 250 RS = 1 kΩ Figure 6-11. High-Power Mode FFT Spectrum Figure 6-12. High-Power Mode FFT Spectrum 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 250 -120 -160 100 125 150 Frequency (Hz) 225 -100 -140 75 200 -80 -140 50 175 Figure 6-10. High-Power Mode FFT Spectrum -20 25 100 125 150 Frequency (Hz) Shorted input, PGA gain = 8 Figure 6-9. High-Power Mode FFT Spectrum 0 75 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1 Figure 6-13. High-Power Mode FFT Spectrum 250 0 25 50 75 100 125 150 Frequency (Hz) 175 200 fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1 Figure 6-14. High-Power Mode FFT Spectrum Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 13 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 fIN = 31.25 Hz, VIN = –0.5 dBFS, buffer operation 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 75 100 125 150 Frequency (Hz) 175 200 225 250 Figure 6-16. High-Power Mode FFT Spectrum -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8 Figure 6-17. High-Power Mode FFT Spectrum Figure 6-18. High-Power Mode FFT Spectrum 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) 0 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 25 Shorted input, PGA gain = 1 50 75 100 125 150 Frequency (Hz) 175 200 225 250 Shorted input, PGA gain = 8 Figure 6-19. Mid-Power Mode FFT Spectrum 14 50 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V, AVDD1 = 3.3 V, 2048 data points Figure 6-15. High-Power Mode FFT Spectrum Amplitude (dB) 25 Figure 6-20. Mid-Power Mode FFT Spectrum Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V 75 100 125 150 Frequency (Hz) 175 200 225 250 Figure 6-22. Mid-Power Mode FFT Spectrum 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 50 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1 Figure 6-21. Mid-Power Mode FFT Spectrum -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V, AVDD1 = 3.3 V, 2048 data points Figure 6-23. Mid-Power Mode FFT Spectrum Figure 6-24. Mid-Power Mode FFT Spectrum 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 25 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8 Figure 6-25. Mid-Power Mode FFT Spectrum 250 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8 Figure 6-26. Mid-Power Mode FFT Spectrum Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 15 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 Shorted input, PGA gain = 8 Shorted input, PGA gain = 1 Figure 6-28. Low-Power Mode FFT Spectrum 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) Figure 6-27. Low-Power Mode FFT Spectrum 0 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V 75 100 125 150 Frequency (Hz) 175 200 225 250 Figure 6-30. Low-Power Mode FFT Spectrum 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) 50 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1 Figure 6-29. Low-Power Mode FFT Spectrum -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1 Figure 6-31. Low-Power Mode FFT Spectrum 16 25 250 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V, AVDD1 = 3.3 V, 2048 data points Figure 6-32. Low-Power Mode FFT Spectrum Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) 0 0 -20 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 250 0 fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8 50 75 Figure 6-33. Low-Power Mode FFT Spectrum 175 200 225 250 Figure 6-34. Low-Power Mode FFT Spectrum 140 TA = -40C TA = 25C TA = 85C Buffer Operation -20 135  -40 130 DR (dB) -60 -80 -100 -120 125 120 115 -140 110 -160 -180 0 25 50 75 100 125 150 Frequency (Hz) 175 200 225 105 250 1 10 PGA Gain (V/V) AIN1 = fIN = 31.25 Hz, –0.5-dBFS signal, AIN2 = shorted 100 High-power mode Figure 6-35. Channel-to-Channel Crosstalk Figure 6-36. Dynamic Range vs PGA Gain 140 140 TA = -40C TA = 25C TA = 85C Buffer operation 135  130 130 125 125 120  120 115 115 110 110 105 TA = -40C TA = 25C TA = 85C Buffer Buffer operation Operation 135 DR (dB) DR (dB) 100 125 150 Frequency (Hz) fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8 0 Amplitude (dB) 25 105 1 10 PGA Gain (V/V) 100 1 10 PGA Gain (V/V) Mid-power mode 100 Low-power mode Figure 6-37. Dynamic Range vs PGA Gain Figure 6-38. Dynamic Range vs PGA Gain Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 17 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) 100 100 PGA gain = 1 PGA gain = 8 Buffer operation 90 80 80 70 70 Population (%) 60 50 40 30 60 50 40 30 20 20 10 10 100 80 60 40 20 0 -20 -40 -60 -80 -100 0 0 0 Offset Error (V) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Offset Drift (V/C) 30 units Figure 6-39. Offset Error Distribution Figure 6-40. Offset Drift Distribution 100 100 PGA gain = 1 PGA gain = 2 PGA gain = 4 90 80 80 50 Gain Error (ppm) 700 600 500 400 300 200 0 100 Gain Error (ppm) 30 units 30 units Figure 6-41. Gain Error Distribution Figure 6-42. Gain Error Distribution 100 100 PGA gain = 1 PGA gain = 2 PGA gain = 4 90 80 PGA gain = 8 PGA gain = 16, 32 and 64 Buffer operation 90 80 70 50 Gain Drift (ppm/C) 6 5.5 5 4.5 4 3.5 3 6 5.5 5 4.5 4 3 3.5 2.5 2 0 1.5 10 0 1 10 0.5 20 0 30 20 2 40 30 1.5 40 60 1 50 0.5 60 0 Population (%) 70 Population (%) -100 -200 -700 700 600 500 400 300 200 0 100 -100 -200 0 -300 10 0 -400 20 10 -500 20 -600 30 -300 40 30 -400 40 -500 50 60 -600 Population (%) 70 60 -700 Population (%) PGA gain = 8 PGA gain = 16, 32 and 64 Buffer operation 90 70 Gain Drift (ppm/C) 30 units 30 units Figure 6-43. Gain Drift Distribution 18 2 30 units 2.5 Population (%) PGA gain = 1 PGA gain = 8 Buffer operation 90 Figure 6-44. Gain Drift Distribution Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) 100 90 80 Population (%) 70 60 50 40 30 20 10 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0 0 Gain Match (%) VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5 dBFS 30 units Figure 6-46. High-Power Mode THD vs PGA Gain Figure 6-45. Gain Match Distribution -105 -105 TA = -40C TA = 25C TA = 85C -115 Buffer operation  -110 THD (dB) THD (dB) -110 -120 -125 TA = -40C TA = 25C TA = 85C -115 -120 Buffer operation  -125 -130 -130 1 10 PGA Gain (V/V) 100 VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Figure 6-47. Mid-Power Mode THD vs PGA Gain 1 10 PGA Gain (V/V) 100 VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Figure 6-48. Low-Power Mode THD vs PGA Gain -105 TA = -40C TA = 25C TA = 85C -110 THD (dB) Buffer operation -115  -120 -125 -130 1 10 PGA Gain (V/V) 100 VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Figure 6-49. High-Power Mode THD vs PGA Gain VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Figure 6-50. Mid-Power Mode THD vs PGA Gain Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 19 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) -105 -70 TA = -40C TA = 25C TA = 85C -110 PGA gain = 1 PGA gain = 4 PGA gain = 16 Buffer operation -80 THD (dB) THD (dB) -90 -115 Buffer operation -120  -100 -110 -125 -120 -130 -130 1 10 PGA Gain (V/V) 100 VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Figure 6-51. Low-Power Mode THD vs PGA Gain 0 10 20 30 40 50 60 70 Input Frequency (Hz) 80 90 100 VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Figure 6-52. High- and Mid-Power Mode THD vs Input Frequency -70 PGA gain = 1 PGA gain = 4 PGA gain = 16 Buffer operation -80 THD (dB) -90 -100 -110 -120 -130 0 10 20 30 40 50 60 70 Input Frequency (Hz) 80 90 100 VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS Figure 6-53. Low-Power Mode THD vs Input Frequency High-speed mode Figure 6-54. PGA Input Current vs Input Voltage 33 30 27 Population (%) 24 21 18 15 12 9 6 3 5 4.6 4.2 3.8 3.4 3 2.6 2.2 1.8 1.4 1 0 PGA Input Current Noise Density (pA/Hz) Figure 6-55. PGA Input Current Noise Distribution 20 High- and mid-power modes Figure 6-56. Buffer Input Current vs Input Voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) 100 500 High-power mode Mid-power mode Low-power mode 400 80 70 Population (%) 300 200 60 50 40 30 100 20 High- and mid-power modes Low-power mode 575 550 525 500 475 450 425 0 80 400 60 375 20 40 Temperature (C) 350 0 325 -20 10 275 0 -40 300 Reference Input Current (A) 90 Reference Input Current (A) 30 units Figure 6-57. Reference Input Current vs Temperature Figure 6-58. Reference Input Current Distribution 100 160 High-power mode, PGA operation Mid-power mode, PGA operation Low-power mode, PGA operation 90 140 80 70 Population (%) CMRR (dB) 120 100 80 60 50 40 30 20 PGA gain = 1 Buffer operation 10 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0 1000000 0.9 100 1000 10000 100000 Common-Mode Input Frequency (Hz) 0.7 40 10 0.8 60 AVDD1 Current (mA) 30 units Figure 6-59. CMRR vs Common-Mode Input Frequency Figure 6-60. AVDD1 Current Distribution 2 100 High-power mode, buffer Mid-power mode, buffer Low-power mode, buffer 90 AVDD1 Current (mA) 80 70 Population (%) High-power mode, PGA operation Mid-power mode, PGA operation Low-power mode, PGA operation 60 50 40 30 20 1.6 1.2 0.8 10 0.5 0.475 0.45 0.425 0.4 0.375 0.35 0.325 0.3 0.275 0.25 0.225 0 0.4 -40 AVDD1 Current (mA) -20 0 20 40 Temperature (C) 60 80 30 units Figure 6-61. AVDD1 Current Distribution Figure 6-62. AVDD1 Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 21 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted) 100 0.5 High-power mode Mid-power mode Low-power mode 90 80 0.4 70 Population (%) AVDD1 Current (mA) High-power mode, PGA operation Mid-power mode, PGA operation Low-power mode, PGA operation 0.3 60 50 40 30 0.2 20 10 1.5 1.4 1.3 1.2 1.1 1 0 80 0.9 60 0.8 20 40 Temperature (C) 0.7 0 0.6 -20 0.5 0.1 -40 AVDD2 Current (mA) 30 units Figure 6-63. AVDD1 Current vs Temperature Figure 6-64. AVDD2 Current Distribution 140 1.5 High- and mid-power modes Low-power mode 120 100 1.1 PSRR (dB) AVDD2 Current (mA) 1.3 0.9 80 60 0.7 AVDD1 AVDD2 IOVDD 40 0.5 -40 -20 0 20 40 Temperature (C) 60 80 20 10 Figure 6-65. AVDD2 Current vs Temperature 100 1000 10000 100000 Power Supply Frequency (Hz) 1000000 Figure 6-66. PSRR vs Power-Supply Frequency 0.6 High- and mid-power modes Low-power mode IOVDD Current (mA) 0.5 0.4 0.3 0.2 0.1 100 500 1000 Data Rate (SPS) 5000 Figure 6-67. IOVDD Current vs Data Rate 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 7 Parameter Measurement Information 7.1 Noise Performance The ADS1285 is a 32-bit ADC providing three power-resolution modes, allowing optimization of noise performance verses device power consumption. The four determining factors of noise performance are the power mode, output data rate, PGA gain setting, and reference voltage selection. The high-power mode operates the PGA and modulator sampling rate at the highest capacity for best overall noise performance. The mid-power mode scales down the PGA quiescent current to reduce power consumption but results in increased PGA noise. The low-power mode reduces both the modulator sampling rate and PGA quiescent current. The result is the low-power mode has the lowest power consumption but the highest level of overall noise. For all power modes, decreasing the output data rate reduces signal bandwidth, and therefore decreases total noise. Increasing the PGA gain reduces noise when noise is referred to the input. Dynamic range performance decreases when PGA gain is increased because the ratio of input voltage range to input-referred noise also decreases. Noise performance also depends on the reference voltage. Operation with VREF = 4.096 V or 5 V provides the best noise performance. Operation with VREF = 2.5 V (required when operating AVDD1 = 3.3 V) reduces noise performance. Dynamic range and input noise are equivalent parameters that describe the available resolution of the ADC. Equation 1 derives dynamic range from the input-referred noise data: Dynamic Range (dB) = 20×log 1.768 V Gain × en (1) where: • en = Input-referred voltage noise (RMS) Figure 7-1 and Figure 7-2 show dynamic range performance at fDATA = 500 SPS for operation with VREF = 4.096 V and VREF = 2.5 V. 140 140 High-power mode Mid-power mode Low-power mode Buffer operation  130 130 125 125 120 120 115 115 110 110 105 High-power mode Mid-power mode Low-power mode Buffer operation (gain = 1) 135 DR (dB) DR (dB) 135 105 1 10 PGA Gain (V/V) 100 1 fDATA = 500 SPS, VREF = 4.096 V 10 PGA Gain (V/V) 100 fDATA = 500 SPS, VREF = 2.5 V Figure 7-1. Dynamic Range vs PGA Gain Figure 7-2. Dynamic Range vs PGA Gain Table 7-1 through Table 7-3 list dynamic range and input-referred noise performance with VREF = 4.096 V and AVDD1 = 5 V, tested with input source resistance (RS) = 0 Ω. Table 7-4 through Table 7-6 list dynamic range and input noise performance with VREF = 2.5 V and AVDD1 = 3.3 V, tested with RS = 0 Ω. Noise data are at TA = 25°C and are representative of typical ADC performance. The data are the standard deviation of 4096 consecutive ADC conversion results with the ADC inputs shorted, measured over the 0.413 × fDATA bandwidth. Because of the statistical nature of noise, repeated measurements can yield varying noise performance results. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 23 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table 7-1. High-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω) DYNAMIC RANGE (dB) GAIN MODE en, INPUT-REFERRED NOISE (μVRMS) fDATA fDATA 250 500 1000 2000 4000 250 500 1000 2000 4000 1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25 1 PGA 137 134 131 128 125 0.25 0.35 0.50 0.70 0.99 2 PGA 136 133 130 127 124 0.14 0.20 0.28 0.39 0.56 4 PGA 134 131 128 125 122 0.09 0.12 0.18 0.25 0.35 8 PGA 130 127 124 121 118 0.07 0.10 0.14 0.20 0.28 16 PGA 126 123 120 117 114 0.06 0.08 0.11 0.16 0.22 32 PGA 120 117 114 111 108 0.06 0.08 0.11 0.16 0.22 64 PGA 114 111 108 105 102 0.06 0.08 0.11 0.16 0.22 Table 7-2. Mid-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω) GAIN DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS) fDATA fDATA MODE 250 500 1000 2000 4000 250 500 1000 2000 4000 1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25 1 PGA 137 134 131 128 125 0.25 0.35 0.50 0.70 0.99 2 PGA 135 132 129 126 123 0.16 0.22 0.31 0.44 0.63 4 PGA 133 130 127 124 121 0.10 0.14 0.20 0.28 0.39 8 PGA 128 125 122 119 116 0.09 0.12 0.18 0.25 0.35 16 PGA 123 120 117 114 111 0.08 0.11 0.16 0.22 0.31 32 PGA 117 114 111 108 105 0.08 0.11 0.16 0.22 0.31 64 PGA 111 108 105 102 99 0.08 0.11 0.16 0.22 0.31 Table 7-3. Low-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω) DYNAMIC RANGE (dB) GAIN MODE en, INPUT-REFERRED NOISE (μVRMS) fDATA fDATA 125 250 500 1000 2000 125 250 500 1000 2000 1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25 1 PGA 138 135 132 129 126 0.22 0.31 0.44 0.63 0.89 2 PGA 137 134 131 128 125 0.12 0.18 0.25 0.35 0.50 4 PGA 135 132 129 126 123 0.08 0.11 0.16 0.22 0.31 8 PGA 131 128 125 122 119 0.06 0.09 0.12 0.18 0.25 16 PGA 126 123 120 117 114 0.06 0.08 0.11 0.16 0.22 32 PGA 120 117 114 111 108 0.06 0.08 0.11 0.16 0.22 64 PGA 114 111 108 105 102 0.06 0.08 0.11 0.16 0.22 Table 7-4. High-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω) DYNAMIC RANGE (dB) GAIN 24 MODE en, INPUT-REFERRED NOISE (μVRMS) fDATA fDATA 250 500 1000 2000 4000 250 500 1000 2000 4000 1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25 1(1) PGA 128 125 122 119 116 0.35 0.50 0.70 0.99 1.40 2 PGA 133 130 127 124 121 0.20 0.28 0.39 0.56 0.79 4 PGA 132 129 126 123 120 0.11 0.16 0.22 0.31 0.44 8 PGA 129 126 123 120 117 0.08 0.11 0.16 0.22 0.31 16 PGA 125 122 119 116 113 0.06 0.09 0.12 0.18 0.25 32 PGA 119 116 113 110 107 0.06 0.09 0.12 0.17 0.25 64 PGA 113 110 107 104 101 0.06 0.09 0.12 0.17 0.25 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table 7-5. Mid-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω) DYNAMIC RANGE (dB) GAIN MODE en, INPUT-REFERRED NOISE (μVRMS) fDATA fDATA 250 500 1000 2000 4000 250 500 1000 2000 4000 1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25 1(1) PGA 128 125 122 119 116 0.35 0.50 0.70 0.99 1.40 2 PGA 133 130 127 124 121 0.20 0.28 0.39 0.56 0.79 4 PGA 131 128 125 122 119 0.12 0.18 0.25 0.35 0.50 8 PGA 127 124 121 118 115 0.10 0.14 0.20 0.28 0.39 16 PGA 123 120 117 114 111 0.08 0.11 0.16 0.22 0.31 32 PGA 117 114 111 108 105 0.08 0.11 0.16 0.22 0.31 64 PGA 111 108 105 102 99 0.08 0.11 0.16 0.22 0.31 Table 7-6. Low-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω) GAIN (1) MODE DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS) fDATA fDATA 125 250 500 1000 2000 125 250 500 1000 2000 1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25 1(1) PGA 129 126 123 120 117 0.31 0.44 0.83 0.89 1.25 2 PGA 134 131 128 125 122 0.18 0.25 0.35 0.50 0.70 4 PGA 133 130 127 124 121 0.10 0.14 0.20 0.28 0.39 8 PGA 130 127 124 121 118 0.07 0.10 0.14 0.20 0.28 16 PGA 125 122 119 116 113 0.06 0.09 0.12 0.17 0.25 32 PGA 119 116 113 110 107 0.06 0.09 0.12 0.17 0.25 64 PGA 113 110 107 104 101 0.06 0.09 0.12 0.17 0.25 Because of the limited input headroom with AVDD1 = 3.3 V operation, the available input range with PGA gain operation = 1 is ±1.35 VPP. The dynamic range data for PGA gain = 1 and AVDD1 = 3.3 V reflects the reduced input range. 8 Detailed Description 8.1 Overview The ADS1285 is a high-resolution, low-power analog-to-digital converter (ADC) designed for applications in energy exploration, geology, and seismic monitoring where low-power consumption and high resolution are required. The converter provides 32 bits of resolution spanning data rates from 125 SPS to 4000 SPS. The programmable gain amplifier (PGA) expands the system dynamic range by accepting signals ranging from ±2.5 VPP to ±0.039 VPP. As illustrated in the Functional Block Diagram, the ADC consists of the following sections: input multiplexer (MUX), programmable gain amplifier (PGA), unity-gain buffer, delta-sigma (ΔΣ) modulator, sample rate converter, infinite impulse response (IIR) high-pass filter (HPF), finite impulse response (FIR) low-pass filter (LPF), and an SPI-compatible serial interface used for both device configuration and conversion data readback. The input multiplexer selects between inputs 1 and 2, and internal options designed for self-test, including an input-short option used to test offset and noise. The input multiplexer is followed by a low-noise PGA. The PGA gain range is 1 to 16, with gains 32 and 64 provided as digital gains. The PGA is chopper-stabilized to reduce 1/f noise and input offset voltage. The PGA output connects to a buffer which drives the modulator. An external 10-nF capacitor, connected to PGA output pins CAPP and CAPN, provides an antialias filter for the input signal. The PGA can be disabled to lower device power consumption by operating the ADC with the unity-gain buffer. External 47-nF capacitors connected to each buffer output filters the modulator sampling pulses. The ΔΣ modulator measures the differential input signal (VIN) against the differential reference voltage (VREF). The modulator provides three reference voltage options (2.5 V, 4.096 V, or 5 V). The reference voltage is programmed by the user. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 25 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Modulator data are processed by the digital filter providing the final conversion result. The digital filter consists of a sinc filter followed by a programmable phase, FIR low-pass filter, and an IIR high-pass filter. The high-pass filter removes dc and low-frequency components from the data. The sample rate converter (SRC) compensates clock frequency error by resampling the output data. The clock frequency compensation range is ±244 ppm with 7-ppb resolution. User-programmable gain and offset calibration registers correct offset and gain errors. The SYNC pin synchronizes the ADC. Synchronization has two modes of operation: pulse synchronization and continuous synchronization. The RESET pin resets the ADC, including user configuration settings. The pins are noise-resistant, Schmitt-trigger inputs to increase reliability in high-noise environments. The PWDN pin powers down the ADC when not in use. The software power-down mode (STANDBY) is available through the serial interface The 4-wire, SPI-compatible, serial interface reads conversion data and reads or writes device register data. Two general-purpose digital I/Os are available for system level control. Power for the PGA and buffer is supplied by AVDD1 and AVSS. A charge pump voltage regulator increases the input voltage range of the buffer that follows the PGA. Power for the modulator is supplied by AVDD2. IOVDD supplies the digital logic core through a 1.8-V low-dropout regulator (LDO). IOVDD is the digital I/O supply. 8.2 Functional Block Diagram CAPC CAPBP CAPBN AVDD2 AVDD1 AVDD1 MUX PGA 1.8 V (digital core) Charge Pump AIN1P AIN1N AIN2P CAPD BUF IOVDD LDO CLK DRDY û Modulator Sample Rate Converter Digital Filter Serial Interface CS SCLK DOUT DIN Control PWDN RESET SYNC AIN2N AVSS GPIO 2 x 400 Ÿ VCM AGND 26 AVSS CAPP CAPN CAPI REFP REFN CAPR GPIO1 GPIO0 Submit Document Feedback DGND Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.3 Feature Description 8.3.1 Analog Input Figure 8-1 shows the analog input circuit and input multiplexer. AVDD1 S1 AIN1P ESD Diodes S2 (+) AIN2P 400 S3 AVSS To PGA To Buffer AVDD1 + AVSS S7 2 AVDD1 400 S4 S5 (-) AIN1N ESD Diodes S6 AIN2N AVSS Figure 8-1. Analog Input and Multiplexer Electrostatic discharge (ESD) diodes are incorporated to protect the ADC inputs from ESD events that occur during device manufacturing and printed circuit board (PCB) assembly process when assembled in an ESDcontrolled environment. For system-level protection, consider using external ESD protection devices to protect the input that are exposed to ESD events. If the inputs are driven below AVSS – 0.3 V, or above AVDD1 + 0.3 V, the protection diodes can conduct. If these conditions are possible, use external clamp diodes, series resistors, or both to limit input current to the specified maximum value. Overdriving an unused input channel can affect the conversion results of the active input channel. Clamp the overdriven voltage with Schottky diodes to prevent channel crosstalk. The ADC incorporates two differential input channels The multiplexer selects between the two differential inputs for measurement. A test mode to measure noise and offset is also provided by the multiplexer. The shorted input test configuration is available with or without the 400-Ω resistors to simulate the thermal noise generated by an 800-Ω geophone. Table 8-1 summarizes the multiplexer configurations. Table 8-1. Input Multiplexer Modes MUX[2:0] BITS SWITCHES DESCRIPTION 000 S1, S5 Input AIN1P, AIN1N connection 001 S2, S6 Input AIN2P, AIN2N connection 010 S3, S4 400-Ω input-short test mode for offset and noise test. 011 S1, S5,S2, S6 Cross-connection test mode. Inputs AIN1P, AIN2P and AIN2P, AIN2N are connected 100 — Reserved 101 S3,S4,S7 0-Ω input-short test mode for offset and noise test. To test geophone THD performance, apply a test signal to the test channel through series resistors. The series resistors are typically half the value of the geophone impedance. Select the multiplexer for the cross-connection test mode (MUX[2:0] = 011b). In cross-connection mode, the test signal is cross-fed to the geophone input. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 27 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Geophone THD test performance can be affected by the nonlinear on-resistance of the multiplexer (RSW). Figure 8-2 shows a model of the input multiplexer resistance for the geophone THD test. Figure 8-3 shows THD performance versus a test resistor (RLOAD) used to simulate geophone resistance. Small amplitude test signals (such as, VIN = 0.221 V), shows less THD performance degradation for geophone resistance < 500 Ω. -100 ½ RLOAD Test Signal PGA gain = 1, VIN = 1.77 VRMS PGA gain = 8, VIN = 0.221 VRMS Input2 -105 ½ RLOAD RSW RSW THD (dB) PGA RSW -110 -115 RSW -120 RLOAD Input1 -125 0 2000 4000 6000 Resistive Load () 8000 10000 Figure 8-3. THD Performance vs RLOAD Figure 8-2. THD versus RLOAD Test Circuit 8.3.2 PGA and Buffer Figure 8-4 shows the simplified PGA and buffer block diagram. 4.7 nF 10 nF, C0G AVDD1 CAPP CAPN AVDD1 CAPC AGND Charge Pump MUX(+) + CAPBP 47 nF, C0G AVSS GAIN[2:0] bits of register CONFIG1 (address = 02h) Buffer mode GAIN[2:0] = 111b
Modulator CAPBN MUX(-) + 47 nF, C0G AVSS AVSS AVSS Figure 8-4. PGA and Buffer Block Diagram The device can be operated with the PGA or the unity-gain buffer. Buffer operation disables the PGA bias, reducing device power consumption. Because of the limited input headroom for PGA gain = 1 when operating with AVDD1 = 3.3 V, the buffer must be used under this condition. 8.3.2.1 Programmable Gain Amplifier (PGA) The PGA is a low-noise, chopper-stabilized differential amplifier that extends the ADC dynamic range performance. The PGA provides analog gains from 1 to 16, with gains of 32 and 64 provided by digital scaling. The PGA output signal is routed to the CAPP and CAPN pins through 270-Ω resistors. Connect an external 10-nF, C0G-dielectric capacitor across these pins. An antialias filter is formed by these components to attenuate the signal level at the modulator aliasing frequency (fMOD). As shown in Figure 8-4, the buffer is used between the PGA and the modulator. Connect two 47-nF, C0Gdielectric capacitors from each buffer output to AVSS (CAPBP and CAPBN). A voltage charge pump increases 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 the buffer input voltage headroom. Connect an external 4.7-nF capacitor between CAPC and AGND for charge pump operation. The PGA gain is programmed by the GAIN[2:0] bits of the CONFIG1 register. Table 8-2 shows the PGA gain settings and buffer selection. The PGA gains and input signal range are irrespective of the voltage reference. Table 8-2. PGA Gains GAIN[2:0] REGISTER BITS PGA GAIN INPUT SIGNAL RANGE (VPP) 000 1 ±2.5 001 2 ±1.25 010 4 ±0.625 011 8 ±0.3125 100 16 ±0.15625 101 32 ±0.078125 110 64 ±0.0390625 111 Buffer mode, gain = 1 ±2.5 Observe the PGA input and output voltage headroom specification. Figure 8-5 shows the input and output voltage headroom when operating with AVDD1 = 5 V, an input common-mode voltage (VCM) = 2.5 V, a differential input voltage = ±2.5 VPP, and at gain = 1. The absolute minimum and maximum PGA input voltage (1.25 V and 3.75 V) is ±1/2 of the differential signal voltage plus the common-mode voltage. The PGA provides 0.15-V input voltage margin at the negative peak and 0.4-V input voltage margin at the positive peak. As shown in the figure, the PGA gain increases by × 1.5 when the ADC is operated with 4.096-V or 5-V voltage references. The PGA provides 0.475-V output voltage margin at the positive and negative peaks. PGA Input Headroom PGA Output Headroom AVDD1 AVDD1 - 0.15 V AVDD1 VCM + 1.875 V AVDD1 - 0.85 V VCM + 1.25 V VCM = 2.5 V VCM - 1.25 V AVSS + 1.1 V VCM - 1.875 V AVSS + 0.15 V AVSS AVSS Figure 8-5. PGA Headroom (AVDD1 = 5 V, PGA Gain = 1) When operating with AVDD1 = 3.3 V, the PGA cannot support ±2.5-VPP input signals. Use the buffer for ±2.5-VPP input signals. For ±1.25-VPP input signals (PGA gain = 2), the input headroom is increased by increasing the common-mode voltage by 0.1 V to AVSS + 1.75 V. Figure 8-6 illustrates the input and output operating headroom for AVDD1 = 3.3 V, VCM = 1.75 V, input signal = ±1.25 VPP, and gain = 2. The PGA uses normal gain scaling when VREF = 2.5 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 29 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 PGA Input Headroom PGA Output Headroom AVDD1 AVDD1 - 0.15 V VCM + 1.25 V AVDD1 AVDD1 - 0.85 V VCM + 0.6125 V VCM = 1.75 V VCM - 0.6125 V AVSS + 1.1 V VCM - 1.25 V AVSS + 0.15 V AVSS AVSS Figure 8-6. PGA Headroom (AVDD1 = 3.3 V, Gain = 2) 8.3.2.2 Buffer Operation (PGA Bypass) The ADC provides a buffer option, bypassing the PGA. Bypassing the PGA reduces device power consumption. Use the buffer for ±2.5-VPP input signals when operating AVDD1 at 3.3 V. Buffer operation is enabled by setting the GAIN[2:0] bits = 111b of the CONFIG1 register. Figure 8-7 shows the buffer voltage headroom with AVDD1 = 3.3 V, VCM = 1.65 V, and the input signal = ±2.5 VPP. The buffer has sufficient voltage headroom for ±2.5-VPP input signals when operating with AVDD1 = 3.3 V. AVDD1 AVDD1 - 0.1 V VCM + 1.25 V Buffer Input Headroom Buffer Output Headroom AVDD1 AVDD1 - 0.1 V VCM + 1.25 V VCM = 1.65 V VCM - 1.25 V AVSS + 0.1 V AVSS VCM - 1.25 V AVSS + 0.1 V AVSS Figure 8-7. Buffer Headroom (3.3-V Operation Shown) Regardless of PGA or buffer operation, connect two 47-nF, C0G-dielectric capacitors from each buffer output to AVSS (CAPBP and CAPBN). The voltage charge pump increases the buffer input operating headroom. Connect an external 4.7-nF capacitor between CAPC and AGND for the charge pump operation. 8.3.3 Voltage Reference Input The ADC requires a reference voltage for operation. The reference voltage input is differential, defined as the voltage between the REFP and REFN pins: VREF = VREFP – VREFN. Because of the differential input, the VREFN trace can be routed to the voltage reference ground terminal to avoid ground noise pickup. The device offers the choice of three reference voltages: 5 V, 4.096 V, or 2.5 V. Maximum dynamic range performance is achieved using V REF = 5 V or 4.096 V, which requires AVDD1 = 5 V for operation. If AVDD1 = 3.3 V, the reference voltage is limited to 2.5 V. Program the reference voltage to match the physical voltage by the REF[1:0] bits of the CONFIG1 register. Use a precision voltage reference with low noise, optimally less than 0.5 μVRMS over the measurement bandwidth. Figure 8-8 illustrates a simplified reference input circuit. Similar to the analog inputs, the reference inputs are protected by ESD diodes. If the reference inputs are driven below AVSS – 0.3 V or above AVDD1 + 0.3 V, the protection diodes can conduct. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the reference input current to the specified value. 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 AVDD1 CREF REFP REFN AVSS Figure 8-8. Simplified Voltage Reference Input Circuit The ADC samples the reference voltage by an internal capacitor (CREF) and then discharges the capacitor at the modulator sampling frequency (fMOD). The sampling operation results in transient current flow into the reference inputs. The transient current is filtered by a 0.1-µF ceramic capacitor placed directly at the reference pins with a larger 10-μF to 47-μF capacitor at the voltage reference output. In applications where the voltage reference drives multiple ADCs, use 0.1-µF capacitors at each ADC. The external capacitor filters the current transients, resulting in an average reference current. The average reference current is 110 μA/V for high- and mid-power operating modes and 80 μA/V for low-power operating mode. For example, with VREF = 4.096 V, the reference input current is 110 μA / V × 4.096 V = 451 μA. 8.3.4 IOVDD Power Supply The IOVDD digital supply operates in two voltage ranges: 1.65 V to 1.95 V and 2.7 V to 3.6 V. If operating IOVDD in the 1.65-V to 1.95-V range, connect IOVDD directly to the CAPD pin. Figure 8-9 shows the required connection if IOVDD is operating in the 1.65-V to 1.95-V range. Otherwise, if operating IOVDD in the 2.7-V to 3.6-V range, do not connect these pins together. 1.65 V to 1.95 V 2.7 V to 3.6 V Connect IOVDD to CAPD if IOVDD 1.65 V to 1.95 V. Otherwise, do not connect these pins together. IOVDD CAPD Figure 8-9. IOVDD Power-Supply Connection 8.3.5 Modulator The modulator is a multibit delta-sigma architecture featuring low power and outstanding dynamic range performance with very low levels of spurious tones in the frequency spectrum. The modulator shapes the quantization noise of the internal quantizer to an out-of-band frequency range where the noise is removed by the digital filter. Noise remaining within the pass-band region is thermal noise with constant density (white noise). The integrated noise within the pass band is determined by the digital filter OSR. 8.3.5.1 Modulator Overdrive The modulator is an inherently stable design and, therefore exhibits predictable recovery from input overdrive. If the modulator is overdriven at the peaks of the input signal, the filter output data may or may not clip depending on the duration of the signal overdrive resulting from the data averaging of the digital filter. If the modulator is Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 31 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 heavily overdriven, then the likelihood of clipped conversion data increases. Be aware the group delay of the digital filter delays the occurrence of an input overdrive event from appearing in the output data. 8.3.6 Digital Filter The digital filter decimates and filters the modulator data to provide the high-resolution output data. By adjusting the amount of filtering though the OSR, trade-offs can be made between total noise and bandwidth. Increasing the OSR lowers total noise while decreasing the signal bandwidth. As shown in Figure 8-10, the sample rate converter (SRC) receives data from the modulator prior to input to the digital filter block. See the Sample Rate Converter section for details. SRC SWBypass IIR Bypass SW Final Output Data From Modulator Sinc Filter Variable decimation (8 to 128) SRC FIR Filter Fixed decimation (32) IIR Filter No decimation User calibration and code clip FILTR[1:0] bits 1,0 CONFIG0 (register address = 01h) 00: Reserved 01: Sinc filter 10: FIR filter (default) 11: FIR and IIR filter Figure 8-10. Digital Filter Block Diagram The digital filter is comprised of three sections: a variable-decimation sinc filter; a variable-coefficient, fixeddecimation FIR filter; and a programmable high-pass filter (IIR). The desired filter path is selected by the FILTER[1:0] bits of the CONFIG0 register. The sinc filter provides partially filtered data, bypassing the FIR and HPF filters and user calibration. For fully filtered data, select the FIR filter option. The IIR filter stage removes dc and low-frequency data The FIR and the combined FIR + IIR filter are routed to the user calibration block and output code clipping block. See the Offset and Gain Calibration section for details of user calibration. 8.3.6.1 Sinc Filter Section The first section of the digital filter is a variable-decimation, fifth-order sinc filter (sinx/x). Modulator data are passed through the sample rate converter to the sinc filter at the nominal rate of fMOD = fCLK / 4 = 2.048 MHz (1.024-MHz low-power mode). The sinc filter partially filters the data for the FIR filter that produces the final frequency response. The sinc filter data are intended to be used with post-processing filters to shape the final frequency response. Table 8-3 shows the decimation ratio and the resulting output data rate of the sinc filter. The sinc filter data rate is programmed by the DR[2:0] bits of the CONFIG0 register. Table 8-3. Sinc Filter Data Rates DATA RATE (SPS) DR[2:0] BITS SINC DECIMATION RATIO (N) HIGH- AND MID-POWER MODES LOW-POWER MODE 000 256 8,000 4,000 001 128 16,000 8,000 010 64 32,000 16,000 011 32 64,000 32,000 100 16 128,000 64,000 Equation 2 shows the Z-domain transfer function of the sinc filter. 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 5 1 - Z-N H(Z) = -1 N(1 - Z ) (2) where: • N = Decimation ratio of Table 8-3 Equation 3 shows the frequency domain transfer function of the sinc filter. 5 pN ´ f fMOD sin ½H(f)½ = N sin p´f fMOD (3) where: • • • N = Decimation ratio shown in Table 8-3 f = Input signal frequency fMOD = Modulator sampling frequency = fCLK / 4 (sample rate converter disabled) The sinc filter frequency response has notches (or zeros) occurring at the output data rate and multiples thereof. At these frequencies, the filter has zero gain. Figure 8-11 shows the wide-band frequency response of the sinc filter and Figure 8-12 shows details of the –3-dB response. 0 0 -20 -0.5 -40 Gain (dB) Gain (dB) -1.0 -60 -80 -1.5 -2.0 -100 -2.5 -120 -140 -3.0 0 1 2 3 4 Normalized Frequency (fIN/fDATA) 5 0 0.05 0.10 0.15 0.20 Normalized Frequency (fIN/fDATA) Figure 8-11. Sinc Filter Frequency Response Figure 8-12. Sinc Filter –3-dB Response Figure 8-13 illustrates the sinc filter frequency response at fDATA = 32 kSPS. The tones at 1 kHz and harmonics are the result of dither added to the modulator input to suppress idle tones. The frequency of the dither signal is fMOD divided by the combined decimation ratio shown in Table 8-4. The rise of the noise floor at 2 kHz is resultant of modulator noise shaping. For sinc filter decimation N = 64 (data rate = 32 kSPS), the usable bandwidth by the use of external post filtering is 500 Hz. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 33 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 -180 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 8-13. FFT Output of the Sinc Filter (fDATA = 32 kSPS) The sinc filter data bypasses the data scaling, clip stage, and user calibration, and as a result, the sinc filter data are scaled differently compared to the FIR filter. See the Conversion Data Format section for details of sinc filter data scaling. 8.3.6.2 FIR Filter Section The second section of the digital filter is a multistage, FIR low-pass filter. Partially filtered data from the sinc filter are input to the FIR filter. The FIR filter determines the final frequency and phase response of the data. Figure 8-14 shows that the FIR filter consists of four stages. From sinc filter FIR Filter 1 2 FIR Filter 2 2 FIR Filter 3 4 FIR Filter 4 2 To user calibration PHASE bit 2 of CONFIG0 (register address = 01h) 0: Linear phase coefficients (default) 1: Minimum phase coefficients Figure 8-14. FIR Filter The first two FIR stages are half-band filters with decimation = 2 for each stage. The third and fourth FIR stages determine the final frequency and phase response. Decimation is 4 and 2, for FIR stages three and four. The overall decimation ratio of the FIR filter is 32. Unique coefficient sets in stage 3 and 4 determine linear and minimum phase filter response. The phase response is selected by the PHASE bit of the CONFIG0 register. Table 8-4 lists the combined decimation ratio of the sinc and FIR filter stages and the corresponding FIR filter data rate. Table 8-4. FIR Filter Data Rate DATA RATE (SPS) DR[2:0] BITS COMBINED DECIMATION RATIO HIGH- AND MID-POWER MODES LOW-POWER MODE 000 8192 250 125 001 4096 500 250 010 2048 1000 500 011 1024 2000 1000 100 512 4000 2000 Table 8-5 lists the FIR filter coefficients and the data scaling for the linear and minimum phase coefficients. 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table 8-5. FIR Filter Coefficients COEFFICIENT STAGE 1 STAGE 2 STAGE 3 STAGE 4 SCALE = 1/512 SCALE = 1/8388608 SCALE = 1/134217728 SCALE = 1/134217728 LINEAR PHASE LINEAR PHASE LINEAR PHASE MINIMUM PHASE LINEAR PHASE b0 3 –10944 0 819 –132 11767 b1 0 0 0 8211 –432 133882 b2 –25 103807 –73 44880 –75 769961 b3 0 0 –874 174712 2481 2940447 b4 150 –507903 –4648 536821 6692 8262605 b5 256 0 –16147 1372637 7419 17902757 b6 150 2512192 –41280 3012996 –266 30428735 b7 0 4194304 –80934 5788605 –10663 40215494 b8 –25 2512192 –120064 9852286 –8280 39260213 b9 0 0 –118690 14957445 10620 23325925 b10 3 –507903 –18203 20301435 22008 –1757787 b11 0 224751 24569234 348 –21028126 b12 103807 580196 26260385 –34123 –21293602 b13 0 893263 24247577 –25549 –3886901 b14 –10944 891396 18356231 33460 14396783 b15 293598 9668991 61387 16314388 b16 –987253 327749 –7546 1518875 b17 –2635779 –7171917 –94192 –12979500 b18 –3860322 –10926627 –50629 –11506007 b19 –3572512 –10379094 101135 2769794 b20 –822573 –6505618 134826 12195551 b21 4669054 –1333678 –56626 6103823 b22 12153698 2972773 –220104 –6709466 b23 19911100 5006366 –56082 –9882714 b24 25779390 4566808 263758 –353347 b25 27966862 2505652 231231 8629331 b26 25779390 126331 –215231 5597927 b27 19911100 –1496514 –430178 –4389168 b28 12153698 –1933830 34715 –7594158 b29 4669054 –1410695 580424 –428064 b30 –822573 –502731 283878 6566217 b31 –3572512 245330 –588382 4024593 b32 –3860322 565174 –693209 –3679749 b33 –2635779 492084 366118 –5572954 b34 –987253 231656 1084786 332589 b35 293598 –9196 132893 5136333 b36 891396 –125456 –1300087 2351253 b37 893263 –122207 –878642 –3357202 b38 580196 –61813 1162189 –3767666 b39 224751 –4445 1741565 1087392 b40 –18203 22484 –522533 3847821 b41 –118690 22245 –2490395 919792 b42 –120064 10775 –688945 –2918303 b43 –80934 940 2811738 –2193542 b44 –41280 –2953 2425494 1493873 b45 –16147 –2599 –2338095 2595051 b46 –4648 –1052 –4511116 –79991 b47 –874 –43 641555 –2260106 b48 –73 214 6661730 –963855 b49 0 132 2950811 1482337 b50 0 33 –8538057 1480417 b51 0 0 –10537298 –586408 9818477 –1497356 b52 MINIMUM PHASE Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 35 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table 8-5. FIR Filter Coefficients (continued) COEFFICIENT 36 STAGE 1 STAGE 2 STAGE 3 STAGE 4 SCALE = 1/512 SCALE = 1/8388608 SCALE = 1/134217728 SCALE = 1/134217728 LINEAR PHASE LINEAR PHASE LINEAR PHASE MINIMUM PHASE b53 LINEAR PHASE MINIMUM PHASE 41426374 –168417 b54 56835776 1166800 b55 41426374 644405 b56 9818477 –675082 b57 –10537298 –806095 b58 –8538057 211391 b59 2950811 740896 b60 6661730 141976 b61 641555 –527673 b62 –4511116 –327618 b63 –2338095 278227 b64 2425494 363809 b65 2811738 –70646 b66 –688945 –304819 b67 –2490395 –63159 b68 –522533 205798 b69 1741565 124363 b70 1162189 –107173 b71 –878642 –131357 b72 –1300087 31104 b73 132893 107182 b74 1084786 15644 b75 366118 –71728 b76 –693209 –36319 b77 –588382 38331 b78 283878 38783 b79 580424 –13557 b80 34715 –31453 b81 –430178 –1230 b82 –215231 20983 b83 231231 7729 b84 263758 –11463 b85 –56082 –8791 b86 –220104 4659 b87 –56626 7126 b88 134826 –732 b89 101135 –4687 b90 –50629 –976 b91 –94192 2551 b92 –7546 1339 b93 61387 –1103 b94 33460 –1085 b95 –25549 314 b96 –34123 681 b97 348 16 b98 22008 –349 b99 10620 –96 b100 –8280 144 b101 –10663 78 b102 –266 –46 b103 7419 –42 b104 6692 9 b105 2481 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table 8-5. FIR Filter Coefficients (continued) COEFFICIENT STAGE 1 STAGE 2 STAGE 3 STAGE 4 SCALE = 1/512 SCALE = 1/8388608 SCALE = 1/134217728 SCALE = 1/134217728 LINEAR PHASE LINEAR PHASE LINEAR PHASE MINIMUM PHASE LINEAR PHASE MINIMUM PHASE b106 –75 0 b107 –432 –4 b108 –132 0 b109 0 0 Figure 8-15 shows the FIR pass-band frequency response to 0.375 × fDATA with ±0.003-dB pass-band ripple. Figure 8-16 shows the pass-band, transition-band, and stop-band performance from 0 Hz to fDATA. The filter is designed for –135-dB stop-band attenuation at the Nyquist frequency. 20 1.5 0 1.0 -20 Magnitude (dB) Magnitude (mdB) 2.0 0.5 0 -0.5 -1.0 -40 -60 -80 -100 -120 -1.5 -140 -2.0 -160 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 Normalized Input Frequency (fIN/fDATA) Figure 8-15. FIR Filter Pass-Band Response 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Input Frequency (fIN/fDATA) 0.9 1.0 Figure 8-16. FIR Filter Transition Band Response As with many sampled systems, the filter response repeats at multiples of the modulator sample rate (fMOD). The filter response repeats at frequencies = N × fMOD ± f0, where N = 1, 2, and so on, and f0 = filter pass-band). These frequencies, if not filtered and are otherwise present in the signal, fold back (or alias) into the pass-band causing errors. A low-pass input filter reduces the aliasing error. For a band-limited signal typical of many geophones, a single-pole filter at the PGA output is sufficient to suppress the aliasing frequencies. 8.3.6.3 Group Delay and Step Response The FIR filter offers linear and minimum phase filter options. The pass-band, transition band, and stop-band responses of the linear and minimum phase filters are the same but differ in phase and step response behavior. 8.3.6.3.1 Linear Phase Response A linear phase filter has the unique property that the delay from input to output is constant across all input frequencies (that is, constant group delay). The constant delay property is independent of the nature of the input signal (impulse or swept-tone), and therefore the phase is linear across frequency, which can be important when analyzing multitone signals. However, as depicted in Figure 8-17, the group delay is longer for the linear phase filter compared to minimum phase. For both the linear and minimum filters, fully settled data are available 62 conversions after a step input change occurs. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 37 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 1.4 Minimum Phase Filter 1.2 Amplitude (dB) 1.0 0.8 0.6 0.4 0.2 Linear Phase Filter 0 -0.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Time Index (1/fDATA) Figure 8-17. FIR Step Response 8.3.6.3.2 Minimum Phase Response The minimum phase filter provides a short group delay for data from filter input to filter output. Figure 8-18 shows the group delay for minimum and linear phase filters. The group delay of the minimum phase filter is a function of signal frequency. The PHASE bit of the CONFIG0 register programs the filter phase. 35 Linear Phase Filter Group Delay (1/fDATA) 30 25 20 15 10 Minimum Phase Filter 5 0 20 40 60 80 100 120 Frequency (Hz) 140 160 180 200 Figure 8-18. FIR Group Delay (fDATA = 500 SPS) 8.3.6.4 HPF Stage The last stage of the digital filter is the high-pass filter (HPF). The high-pass filter is implemented as a firstorder, IIR filter. The high-pass filter removes dc and low frequencies from the data. The HPF is enabled by programming the FILTR[1:0] bits = 11b of the CONFIG0 register. Equation 4 shows the z-domain transfer function of the filter: H(z) = 2-a 1 - z-1 2 1 - (1 - a)z-1 (4) where: a= • • • • 38 2sin(&N) cos(&N) + sin(&N) ωN = π × fC / fDATA (normalized corner frequency, radians) fC = Corner frequency (Hz) fDATA = Output data rate (Hz) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Be aware the corner frequency programming is a function of fDATA. As shown by Equation 5, the value written to the HPF1, HPF0 registers is value a, computed by Equation 4, × 216. HPF[15:0] = a × 216 (5) Table 8-6 shows examples of the high-pass filter programming. Table 8-6. High-Pass Filter Value Examples HPF[15:0] fC (Hz) fDATA (SPS) 0332h 0.5 250 0332h 1.0 500 019Ah 1.0 1000 The HPF accumulates data to perform the high-pass function. Similar to the operation of an analog HPF after a dc step change is applied to the input, the filter takes time to accumulate data to remove dc from the signal. The lower the corner frequency, the longer the filter takes to settle. To shorten the HPF settling time, the offset register is used as a seed value for the HPF accumulator. The accumulator is loaded with the offset register each time the HPF state is changed from disabled to enabled. The offset register can be preset with an estimated value, or a calibrated value if the dc level is known. To improve accuracy, scale the offset value by the inverse value of GAIN[3:0] / 400000h. The normal offset operation is disabled when the HPF is enabled. To initialize the HPF accumulator with the OFFSET[2:0] registers: 1. Disable the HPF. 2. Write the desired value to the OFFSET[2:0] registers. 3. Enable the HPF. OFFSET[2:0] is loaded to the HPF data accumulator. 4. The HPF tracks the remaining dc value from the signal. Subsequent writes to the OFFSET[2:0] registers are ignored. To reload the contents of the OFFSET[2:0] registers to the HPF, disable and re-enable the HPF. 8.3.7 Clock Input A clock signal is required for operation. The clock signal is applied to the CLK pin at fCLK = 8.192 MHz for highand mid-power modes and 4.096 MHz for low-power mode. As with many precision data converters, a low-jitter clock is required to achieve data sheet performance. Avoid the use of R-C clock oscillators. A crystal-based clock source is recommended. Avoid ringing on the clock signal by placing a series resistor in the clock PCB trace to source-terminate. Keep the clock signal routed away from other clock signals, input pins, and analog components. 8.3.8 GPIO The ADC provides two general-purpose I/O (GPIO) pins that can be used as digital inputs or outputs. The GPIO voltage levels are IOVDD and DGND. Figure 8-19 illustrates the GPIO block diagram. The GPIOs are programmed by the GPIO register. The GPIOs are programmed as an input or output by the GPIOx_DIR bits. The GPIO state is read or written by the GPIOx_DAT bits. When programmed as an output, reading the GPIOx_DAT bits returns the register bit value previously written. If the GPIOs are unused, terminate the GPIOs with pulldown resistors to prevent the pins from floating. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 39 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 IOVDD GPIO0_DIR bit 1 of GPIO (register address = 0Bh) 0: GPIO0 is an input (default) 1: GPIO0 is an output Write SW GPIO0_DAT bit 3 of GPIO (register address = 0Bh) 0: GPIO0 data is low 1: GPIO0 data is high GPIO0 100 k
Read GPIO1_DIR bit 2 of GPIO (register address = 0Bh) 0: GPIO1 is an input (default) 1: GPIO1 is an output Write GPIO1_DAT bit 4 of GPIO (register address = 0Bh) 0: GPIO1 data is low 1: GPIO1 data is high SW GPIO0 100 k Read Read DGND Figure 8-19. GPIO Operation 8.4 Device Functional Modes 8.4.1 Power Modes There are three power-resolution modes offering trade-offs between power consumption and dynamic range. The modes are high power, mid power, and low power. See the Noise Performance section for details of noise performance. The MODE[1:0] bits of the CONFIG0 register selects the power mode. The clock frequency for low-power mode is 4.096 MHz (half-speed clock); therefore, the output data rates are also scaled by one half. 8.4.2 Power-Down Mode Power-down is engaged by taking the PWDN pin low, or by software control, by sending the STANDBY command. To exit power-down, take PWDN high or send the WAKEUP command to exit software power-down (with the clock running). Power-down disables the analog circuit; however, the digital LDO (CAPD pin) remains biased, drawing a small bias current from IOVDD. In comparison, software power-down draws larger IOVDD bias current. In both power-down modes, the ac signals of the digital outputs are stopped but remain driven high or low. The digital inputs must not be allowed to float; otherwise, leakage current can flow from the IOVDD supply. Reset the ADC if the clock is interrupted in power-down. Synchronization is lost in power-down; therefore, resynchronize the ADC. 8.4.3 Reset The ADC is reset by three methods: power-on reset (POR), the RESET pin, or the RESET command. Poweron reset occurs when the power-supply voltages cross the respective thresholds. See Power-Up Switching Characteristics for details. To reset the ADC by pin, drive RESET low for at least two fCLK cycles and return high for reset. By command, reset takes effect on the next rising fCLK edge after the eighth rising edge of SCLK of the reset command. At reset, the filter is restarted and the user registers reset to default. Reset timing is illustrated in Figure 6-5. 8.4.4 Synchronization The ADC is synchronized by the SYNC pin or by the SYNC command, resulting in restart of the digital filter cycle. Synchronization by the pin occurs on the next rising edge of CLK after SYNC is taken high on the falling edge of CLK. Synchronization by the SYNC command occurs on the rising edge of CLK following the eighth bit of the command. 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 The following results in loss of synchronization: • • Power-up cycle, ADC reset, or when hardware or software power down modes are entered The following mode changes: – DR[2:0] (data rate) – PHASE (filter phase) – MODE[1:0] (power mode) – SYNC (synchronization mode) – SRC[1:0] (sample rate converter enabled or disabled) There are two synchronization control modes: pulse sync and continuous sync. The synchronization mode is programmed by the SYNC bit of the ID/SYNC register. 8.4.4.1 Pulse-Sync Mode The pulse-sync mode unconditionally synchronizes the ADC on the rising edge of SYNC. When synchronized, the internal filter memory is reset, DRDY goes high, and the filter cycle restarts. The following 63 DRDY periods are disabled to allow for digital filter settling. DRDY asserts low when the conversion data are ready. See Figure 6-4 for synchronization timing details. 8.4.4.2 Continuous-Sync Mode The continuous-sync mode offers the option of accepting a continuous clock signal to the SYNC pin. The ADC compares the period of the SYNC clock signal to N periods of the DRDY signal to qualify resynchronization. Initially, the first SYNC positive edge synchronizes the ADC. Resynchronization occurs only when the time period between rising edges of SYNC over N multiple DRDY periods differ by at least ± one fCLK cycle, where N = 1, 2, 3 and so on. Otherwise, the SYNC clock period is in synchronization with the existing DRDY pulses, so no resynchronization occurs. Be aware the continuous sync mode cannot be used when the sample rate converter is enabled. After synchronization, DRDY continues to pulse; however, data are held low for 63 data periods to allow for the digital filter to settle. See Figure 6-4 for the DRDY behavior. Because of the initial delay of the digital filter, the SYNC input signal and the DRDY pulses exhibit an offset time. The offset time is a function of the data rate. 8.4.5 Sample Rate Converter The sample rate converter (SRC) compensates clock frequency error by resampling the modulator data at a new rate set by the compensation factor written to the SRC registers. The frequency compensation range is ±244 ppm with 7.45-ppb (1 / 227) resolution. Clock frequency error is compensated by writing a value to the SCR0 and SRC1 registers. The register value is in 2's-complement format for positive and negative frequency error compensation. Positive register data values decrease the data rate frequency (increases the period). The new data rate frequency is observed by the frequency of the DRDY signal. Table 8-7 shows example values of frequency compensation. 8000h disables the sample rate converter. 0000h passes the data through with no compensation but adds an 8 / fCLK delay to the time delay of SYNC input to the DRDY pulses. Table 8-7. Example SRC Values SRC[15:0] VALUE COMPENSATION FACTOR 7FFFh (1 – 32,767 / 227) × fDATA 0001h (1 – 1 / 227) × fDATA 0000h 1 × fDATA 7FFFh (1 + 1 / 227) × fDATA 8001h (1 + 32,767 / 227) × fDATA 8000h 1 × fDATA (SRC disabled) Resynchronize the ADC after the sample rate converter is enabled or disabled. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 41 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Because the SRC is a digital function, operation is deterministic without error. The SRC trim value can be written all at the same time, or written incrementally up to a target value to minimize the step change of frequency. Use the multibyte command operation to write to the SRC registers and complete the write operation 256 CLK cycles before the DRDY falling edge. This procedure loads the high and low bytes simultaneously before they are internally processed. See Figure 6-7 for details. 8.4.6 Offset and Gain Calibration The ADC integrates calibration registers to correct offset and gain errors. As shown in Equation 6 and Figure 8-20, the 24-bit offset value (OFFSET[23:0]) is subtracted from the filter data before multiplication by the 24-bit gain value (GAIN[23:0]), divided by 400000h. The data are clipped to 32 bits to yield the final output. The offset operation is bypassed when the high-pass filter is enabled. Output = (Input - OFFSET[23:0])
GAIN[23:0] 400000h (6) offset bypassed in HPF mode from digital filter +
SW output data clipped to 32 bits X final output OFFSET[23:0] GAIN[23:0] 400000h Figure 8-20. Calibration Block Diagram 8.4.6.1 OFFSET Register Offset correction is by a 24-bit word consisting of three 8-bit registers (high address is the MSB). The offset value is left-justified to align to the 32-bit data. The offset value is 2's-complement coding with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. OFFSET is subtracted from the conversion data; see Table 8-8. Offset error is corrected by the offset calibration command with the input-short multiplexer option, or by collecting shorted-input ADC data and writing the value to the registers. Although the offset correction range is from –FS to +FS, the sum of offset and gain correction must not exceed 106% of the uncalibrated range. When the high-pass filter is enabled, offset correction is disabled. The offset value is used instead as a starting value to shorten the high-pass filter settling time. To reload the offset value to the HPF, disable and re-enable the high-pass filter. See the HPF Stage section for more details. Table 8-8. Offset Calibration Values (1) OFFSET[31:0] CALIBRATED OUTPUT CODE (1) 00007Fh FFFF8100h 000000h 00000000h FFFF7Fh 00008100h Ideal code value with no offset error. 8.4.6.2 GAIN Register Gain correction is through a 24-bit word, consisting of three 8-bit registers (high address = MSB). The gain value is 24 bits, coded in straight binary and normalized to 1.0 for GAIN[23:0] equal to 400000h. With a calibration signal applied, gain error is calibrated by either the gain calibration command, or by collecting ADC data and writing a computed value to the gain registers. Table 8-9 lists examples of the GAIN[23:0] register values. Although the range of gain values can be much greater or less than 1, the sum of offset and gain correction must not exceed 106% of the uncalibrated range. 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table 8-9. Gain Calibration Values GAIN[31:0] GAIN CORRECTION FACTOR 433333h 1.05 400000h 1.00 3CCCCCh 0.95 8.4.6.3 Calibration Procedure ADC calibration can be performed using the ADC calibration commands or by performing manual calibration. The calibration procedure is as follows: 1. Select the PGA or buffer operation, input channel, and PGA gain condition for calibration. 2. Preset the OFFSET register = 000000h and the GAIN register = 400000h. 3. Disable the high-pass filter for offset calibration. Short the inputs to the system, or use the input MUX to provide the input short. A system-level input short can yield more accurate calibration. After the input settles, either send the OFSCAL command or perform a manual calibration. a. OFSCAL command. After the command is sent, DRDY is driven low 81 conversion periods later to indicate calibration is complete. The OFFSET register is updated with the new calibration value. As shown in Figure 8-21, the first data output uses the new OFFSET value. b. Manual calibration. Wait at least 64 conversions for the digital filter to settle then average a number of data points to improve calibration accuracy. Write the value to the 24-bit OFFSET register. 4. Apply a gain calibration voltage. After the input settles, either send the GANCAL command or perform a manual calibration. a. GANCAL command. Apply a positive dc full-scale calibration voltage. After the command is sent, DRDY is driven low 81 conversion periods later to indicate calibration is complete. The ADC calculates GAIN such that the full-scale code is equal to the applied calibration signal. As shown in Figure 8-21, the first data output uses the new GAIN value. b. Manual calibration. Apply an ac signal coherent to the sample rate or dc calibration signal that are slightly below full-scale (for example, 2.4 V for gain = 1). Using a calibration signal less than full-scale range prevents clipped output codes that otherwise lead to incorrect calibration. Wait 64 conversions for the digital filter to settle then average a number of data points to improve calibration accuracy. For ac-signal calibration, use a number of coherent signal periods to compute the RMS value. Equation 7 computes the value of GAIN for manual calibration. GAIN[23:0] = 400000K Â Expected Output Code Actual Output Code DRDY (7) 81 conversion periods CS 8 SCLK DIN DOUT CAL Command 00h Figure 8-21. Calibration Command Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 43 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.5 Programming 8.5.1 Serial Interface Conversion data are read and ADC configuration is made through the SPI-compatible serial interface. The interface consists of four signals: CS, SCLK, DIN, and DOUT. DRDY asserts low when conversion data are ready. The serial interface is passive (peripheral mode), where the serial clock (SCLK) is an input. The ADC operates in SPI mode 0, where CPOL = 0 and CPHA = 0. In mode 0, SCLK idles low and data are updated on the SCLK falling edges and are read on the SCLK rising edges. 8.5.1.1 Chip Select (CS) CS is an active-low input that selects the serial interface for communication. A communication frame is started by taking CS low and is ended by taking CS high. Because only one command per frame is permitted, toggle CS between commands. Taking CS high before the command is completed resets the operation and blocks further SCLK inputs. CS high forces DOUT to a high-impedance state. DRDY remains active regardless of the state of CS. 8.5.1.2 Serial Clock (SCLK) SCLK is the serial clock input that shifts data into and out of the ADC. The ADC latches DIN data on the rising edge of SCLK. DOUT data are shifted out on the falling edge of SCLK. Keep SCLK low when not active. The SCLK pin is a Schmidt-trigger input that reduces sensitivity to SCLK noise. However, keep the SCLK signal as noise free as possible to prevent inadvertent shifting of the data. 8.5.1.3 Data Input (DIN) DIN is used to input data to the ADC. DIN data are latched on the rising edge of SCLK. 8.5.1.4 Data Output (DOUT) DOUT is the data output pin. Data are shifted out on the falling edge of SCLK and are latched by the host on the rising edge. Because the conversion data MSB is on DOUT when CS is driven low (DRDY low), the MSB of the data is read on the first rising edge of SCLK. Minimize trace length to reduce load capacitance on the pin. Place a series termination resistor close to the pin to terminate the PCB trace impedance. Taking CS high forces DOUT to a high-impedance state. 8.5.1.5 Data Ready (DRDY) DRDY is an active-low output that indicates conversion data are ready. DRDY is active regardless of the state of CS. DRDY is driven high on the first falling edge of SCLK, regardless if data is being read or a command is input. As shown in Figure 8-22, if data are not retrieved, DRDY pulses high for eight fCLK periods. Dara Updating 8/fCLK DRDY Figure 8-22. DRDY With No Data Retrieval 44 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.5.2 Conversion Data Format As listed in Table 8-10, the conversion data are coded in 32-bit, 2's-complement format to represent positive and negative numbers. If desired, the data read operation can be shortened to 24 bits by taking CS high. Data scaling from the Sinc filter is dependent on the value of VREF and whether PGA or buffer operation. Table 8-10. Output Data Format CONVERSION CODES(1) SINC FILTER(2) FIR FILTER VIN (V) VREF = 2.5 V, 4.096 V or 5 V VREF = 2.5 V VREF = 4.096 V VREF = 5 V ≥ 2.5 V × (231 – 1) / 231 / Gain 7FFFFFFFh 3FFFFFFFh 3A980000h 30000000h 2.5 V / (Gain × (231 – 1)) 00000001h FFFFFFFFh 80000000h C0000000h C5680000h D0000000h –2.5 V / (Gain × 231) ≤ –2.5 V / Gain (1) (2) Excluding the effects of reference voltage error, noise, linearity, offset, and gain errors. In buffer operation when VREF = 4.096 V or 5 V, the data from the sinc filter are scaled 66.6% compared to PGA mode. Because of the relatively low value of OSR, full 32-bit resolution is not available in sinc filter operation. When overdriven, the sinc filter continues to output code values beyond nominal ± full-scale until the point of modulator saturation. 8.5.3 Commands Table 8-11 lists the commands for the ADC. Most commands are one byte in length. However, the number of bytes for the register read and write commands depend on the amount of register data specified in the command. Table 8-11. Command Descriptions MNEMONIC TYPE DESCRIPTION BYTE 1(1) WAKEUP Control Wake from standby mode or NOP 0000 000x (00h or 01h) — STANDBY Control Enter standby (software power-down mode) 0000 001x (02h or 03h) — SYNC Control Synchronize 0000 010x (04h or 5h) — RESET Control Reset 0000 011x (06h or 07h) — RDATA Data Read conversion data 0001 0010 (12h) — BYTE 2 rrrr)(2) 0000 nnnn (00h + nnnn)(3) 0000 nnnn (00h + nnnn)(3) RREG Register Read nnnn registers beginning at address rrrr 0010 rrrr (20h + WREG Register Write nnnn registers beginning at address rrrr 0100 rrrr (40h + rrrr)(2) OFSCAL Calibration Offset calibration 0110 0000 (60h) — GANCAL Calibration Gain calibration 0110 0001 (61h) — (1) (2) (3) x = Don't care. rrrr = Starting address for register read and write commands. nnnn = Number of registers to be read or written – 1. For example, to read or write three registers, nnnn = 2. 8.5.3.1 Single Byte Command Figure 8-23 shows the general format of a single byte command (for the response bytes of the RDATA command, see the RDATA command). CS 8 SCLK DIN Command Figure 8-23. Single Byte Command Format Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 45 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.5.3.2 WAKEUP: Wake Command The WAKEUP command exits standby mode to resume normal operation. If the ADC is already powered, the command is no operation (NOP). When exiting standby mode, the ADC requires resynchronization. See the Power-Down Mode section for details of power-down mode. 8.5.3.3 STANDBY: Software Power-Down Command The STANDBY command enters the software power-down mode. The ADC exits software power-down mode by the WAKEUP command. See the Power-Down Mode section for details of power-down mode. 8.5.3.4 SYNC: Synchronize Command The SYNC command synchronizes the ADC. Synchronization occurs at the eighth bit of the SYNC command byte. When synchronized, the current conversion is stopped and restarted. In order to synchronize multiple ADCs by software command, send the command simultaneously to all devices. The SYNC pin must be high when using the command. See the Synchronization section for details of synchronization. 8.5.3.5 RESET: Reset Command The RESET command resets the ADC. See the Reset section for details of the reset operation. 8.5.3.6 Read Data Direct There are two methods in which to read conversion data: read data direct and read data by command. Read data direct does not require a command, instead after DRDY falls low, simply apply SCLK to read the data. Figure 8-24 shows the read data direct operation. When DRDY falls low, take CS low to start the read operation. CS low causes DOUT to transition from tri-state mode to the output of the data MSB. Data are read on the rising edge of SCLK and updated on the falling edge of SCLK. DRDY returns high on the first falling edge of SCLK. DOUT is low after 32 data bits are read. To read the same data again before new data are available, use the RDATA command. Keep DIN low when reading conversion data. If the RDATA (read conversion data) or RREG (read register data) command is sent, output data are interrupted in response to the command. If DRDY falls low during the read operation, the new data are lost unless a minimum of three bytes of the old data are read. DRDY CS 16 8 24 32 SCLK DIN DOUT 00h MSB Data 00h MSB-1 Data 00h MSB-2 Data 00h LSB Data Figure 8-24. Read Data Direct 8.5.3.7 RDATA: Read Conversion Data Command The RDATA command (Figure 8-25) is useful to re-read data within the same conversion period or to read data interrupted by a read register command. In both cases, DRDY is high because DRDY is driven high on the first SCLK of the previous operation. If DRDY is high, the first output byte is zero followed by data. If low, the first output byte is byte 1 of the conversion data, which is restarted for output byte 2. 46 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 DRDY CS 16 8 24 40 32 SCLK DIN 12h DOUT 00h 00h 00h 00h MSB-1 Data MSB Data 00h MSB-2 Data LSB Data Figure 8-25. Read Conversion Data by Command 8.5.3.8 RREG: Read Register Command The RREG command reads register data. The command is comprised of two bytes followed by output of the designated number of register bytes. The ADC auto-increments the address up to the number of registers specified in byte 2 of the command. The incrementing address does not wrap. The first byte of the command is the opcode added to the register starting address, and the second byte is the number of registers to read minus one. • First command byte: 0010 rrrr, where rrrr is the starting register address • Second command byte: 0000 nnnn, where nnnn is the number of registers to read minus one Figure 8-26 shows an example of a three-register read operation starting at register address 01h. The first register data appears on DOUT at the 16th falling edge of SCLK. The data are latched on the rising edge of SCLK. CS 16 8 24 40 32 SCLK DIN DOUT 21h GRQ¶W FDUH 02h GRQ¶W FDUH 00h Reg 01h Data 00h Reg 02h Data 00h Reg 03h Data Figure 8-26. Read Register Data 8.5.3.9 WREG: Write Register Command The WREG command is used to write register data. The command is two bytes followed by the designated number of register bytes to be written. The ADC auto-increments the address up to the number of registers specified in the command. The incrementing address does not wrap. The first byte of the command is the opcode added to the register starting address, and the second byte is the number of registers to write minus one. First command byte: 0100 rrrr, where rrrr is the starting address of the first register. Second command byte: 0000 nnnn, where nnnn is the number of registers to write minus one. Data bytes: Depending on the number of registers specified. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 47 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Figure 8-27 shows an example of a three-register write operation starting at register address 01h. CS 16 8 24 40 32 SCLK DIN 41h 02h Reg 01h Data Reg 02h Data Reg 03h Data Figure 8-27. Write Register Data 8.5.3.10 OFSCAL: Offset Calibration Command The OFSCAL command performs offset calibration. See the Calibration Procedure section for details of operation. 8.5.3.11 GANCAL: Gain Calibration Command The GANCAL command performs a gain calibration. See the Calibration Procedure section for details of operation. 48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.6 Register Map Collectively, the registers contain all the information needed to configure the device (such as data rate, filter mode, specific reference voltage, and so on). The registers are accessed by the read and write commands (RREG and WREG). Registers can be accessed individually, or accessed in multiples given by the number of registers specified in the command field. Changes made to certain register bits result in a filter reset, thus requiring resynchronization of the ADC. See the Synchronization section for details. Table 8-12. Register Map ADDRESS REG LINK RESET BIT 7 00h ID/SYNC xxxx0000b BIT 6 BIT 5 BIT 4 BIT 3 01h CONFIG0 00010010b 02h CONFIG1 00000000b 03h HPF0 00110010h HPF[7:0] 04h HPF1 00000011b HPF[15:8] 05h OFFSET0 00000000b OFFSET[7:0] 06h OFFSET1 00000000b OFFSET[15:8] 07h OFFSET2 00000000b OFFSET[23:16] 08h GAIN0 00000000b GAIN[7:0] 09h GAIN1 00000000b GAIN[15:8] 0Ah GAIN2 01000000b 0Bh GPIO 000xx000b 0Ch SRC0 00000000b SRC[7:0] 0Dh SRC1 10000000b SRC[15:8] REVID[3:0] BIT 2 BIT 1 DEVID[2:0] MODE[1:0] DR[2:0] MUX[2:0] PHASE REF[1:0] BIT 0 SYNC FILTR[1:0] GAIN[2:0] GAIN[23:16] RESERVED GPIO1_DAT GPIO0_DAT GPIO1_DIR GPIO0_DIR RESERVED 8.6.1 Register Descriptions Table 8-13 shows the register access codes for the ADS1285 registers. Table 8-13. ADS1285 Access Codes Access Type Code Description R R Read R-W R/W Read or write W W Write -n Value after reset or the default value Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 49 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b] Figure 8-28. ID/SYNC Register 7 6 5 4 3 2 1 0 REVID[3:0] DEVID[2:0] SYNC R-xxxxb R-000b R/W-0b Table 8-14. ID/SYNC Register Field Descriptions Bit Field Type Reset Description 7:4 REVID[3:0] R xxxxb Factory-programmed die revision. These bits identify the revision of the die. The die revision is subject to change without notification. 3:1 DEVID[2:0] R 000b Factory-programmed device identification. These bits identify the ADC. 000b = ADS1285 SYNC R/W 0b Synchronization mode selection. See the Synchronization section for details. 0b = Pulse-sync mode 1b = Continuous-sync mode 0 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h] Figure 8-29. CONFIG0 Register 7 6 5 4 3 2 1 0 MODE[1:0] DR[2:0] PHASE FILTR[1:0] R/W-00b R/W-010b R/W-0b R/W-10b Table 8-15. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7:6 MODE[1:0] R/W 00b Power mode selection. See the Power Modes section for details. 00b = High 01b = Mid 10b = Low 11b = Reserved 5:3 DR[2:0] R/W 010b Data rate selection. See the Digital Filter section for details. 000b = 250 SPS (125 SPS in low-power mode) 001b = 500 SPS (250 SPS in low-power mode) 010b = 1000 SPS (500 SPS in low-power mode) 011b = 2000 SPS (1000 SPS in low-power mode) 100b = 4000 SPS (2000 SPS in low-power mode) 101b–111b = Reserved 2 PHASE R/W 0b FIR filter phase selection. See the Digital Filter section for details. 0b = Linear phase 1b = Minimum phase FILTR[1:0] R/W 10b Digital filter configuration. See the Digital Filter section for details. 00b = Reserved 01b = Sinc filter output 10b = FIR filter output 11b = FIR + IIR filter output 1:0 50 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h] Figure 8-30. CONFIG1 Register 7 6 5 4 3 2 1 MUX[2:0] REF[1:0] GAIN[2:0] R/W-000b R/W-00b R/W-000b 0 Table 8-16. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7:5 MUX[2:0] R/W 000b Input MUX selection. See the Analog Input section for details. 000b = Input 1 001b = Input 2 010b = Internal short with a 400-Ω resistor 011b = Input 1 and input 2 100b = Reserved 101b = Internal short with a 0-Ω resistor 110b, 111b = Reserved 4:3 REF[1:0] R/W 00b Select reference voltage operation. See the Voltage Reference Input section for details. 00b = 5 V 01b = 4.096 V 10b = 2.5 V 11b = Reserved 2:0 GAIN[2:0] R/W 000b PGA gain selection. See the PGA and Buffer section for details. 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = Buffer operation 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h] Figure 8-31. HPF0 Register 7 6 5 4 3 2 1 0 2 1 0 HPF[7:0] R/W-32h Figure 8-32. HPF1 Register 7 6 5 4 3 HPF[15:8] R/W-03h Table 8-17. HPF0, HPF1 Registers Field Description Bit 15:0 Field Type Reset Description HPF[15:0] R/W 0332h High-pass filter programming. These registers program the corner frequency of the high-pass filter. See the HPF Stage section for details. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 51 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h] Figure 8-33. OFFSET0 Register 7 6 5 4 3 2 1 0 2 1 0 2 1 0 OFFSET[7:0] R/W-00h Figure 8-34. OFFSET1 Register 7 6 5 4 3 OFFSET[15:8] R/W-00h Figure 8-35. OFFSET2 Register 7 6 5 4 3 OFFSET[23:16] R/W-00h Table 8-18. OFFSET0, OFFSET1, OFFSET2 Registers Field Description Bit 23:0 Field Type Reset Description OFFSET[23:0] R/W 000000h Offset calibration. These bits are the 24-bit offset calibration word. The format is 2's-complement coding. The ADC subtracts the value of offset from the conversion result prior to the gain calibration operation. See the Offset and Gain Calibration section for details. 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h] Figure 8-36. GAIN0 Register 7 6 5 4 3 2 1 0 2 1 0 2 1 0 GAIN[7:0] R/W-00h Figure 8-37. GAIN1 Register 7 6 5 4 3 GAIN[15:8] R/W-00h Figure 8-38. GAIN2 Register 7 6 5 4 3 GAIN[23:16] R/W-40h Table 8-19. GAIN0, GAIN1, GAIN2 Registers Field Description Bit 23:0 52 Field Type Reset Description GAIN[23:0] R/W 400000h Gain calibration. These bits are the 24-bit, gain calibration word. Gain calibration is straight binary coding. The register value is divided by 400000h (222) and multiplied with the conversion data. The gain operation occurs after the offset operation. See the Offset and Gain Calibration section for details. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b] Figure 8-39. GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_DAT GPIO0_DAT GPIO1_DIR GPIO0_DIR RESERVED R/W-000b R/W-xb R/W-xb R/W-0b R/W-0b R/W-0b Table 8-20. GPIO Register Field Descriptions Bit Field Type Reset Description 7:5 RESERVED R/W 000b Always write 000b. 4 GPIO1_DAT R/W xb GPIO1 data. See the GPIO section for details. 0b = GPIO1 is low 1b = GPIO1 is high 3 GPIO0_DAT R/W xb GPIO0 data. 0b = GPIO0 is low 1b = GPIO0 is high 2 GPIO1_DIR R/W 0b GPIO1 direction. 0b = GPIO1 is an input 1b = GPIO1 is an output 1 GPIO0_DIR R/W 0b GPIO0 direction. 0b = GPIO0 is an input 1b = GPIO0 is an output 0 RESERVED R/W 0b Always write 0b. 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h] Figure 8-40. SRC0 Register 7 6 5 4 3 2 1 0 2 1 0 SRC[7:0] R/W-00h Figure 8-41. SRC1 Register 7 6 5 4 3 SRC[15:8] R/W-80h Table 8-21. SRC0, SRC1 Registers Field Description Bit 15:0 Field Type Reset Description SRC[15:0] R/W 8000h Sample rate converter. These registers program the sample rate converter. See the Sample Rate Converter section for details of operation. 8000h = SRC function is disabled Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 53 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The ADS1285 is a high-resolution ADC designed for low-power seismic data acquisition equipment. Optimizing performance requires special attention to the support circuitry and printed-circuit board (PCB) layout. As much as possible, locate noisy circuit components (such as microcontrollers, oscillators, switching regulators, and so forth) away from the ADC input circuit components, reference voltage, and the ADC clock signal. 9.2 Typical Application 5V 1 F 2.5 V 0.1 F 0.1 F 11 12 AVDD1 AVDD2 3.3 V ADS1285 IOVDD 19 0.1 F 5V 1 DAC SPI 1 F AINP1 CAPD 1 F 17 0.22 F DAC1282 2 AINN1 CLK 14 BAS70 CS CAPI DOUT R5 100  R3 100
SCLK 3 C1 100 pF C0G R1 20 k Geophone DIN 0.1 µF 5V R4 100 R2 20 k C2 100 pF C0G C3 1000 pF C0G R6 100  RESET 4 Optional ESD Protection 10 nF C0G AINN2 CAPP GPIO0 GPIO1 CAPBP 6 – + 5V VIN EN SS 1M R7 100  10 F ADC SPI 24 22 25 26 27 Control 28 15 16 100 k 100 k 7 47 nF C0G CAPBN 8 47 nF C0G CAPC 30 F 60 m 23 CAPN CAPR Clock Input 21 0.1 µF REF6241 S FLT 1 F 31 0.1 µF 1.69 M 2.5 V OPA391 120 k PWDN 5V 0.1 µF 1 F DRDY SYNC 5 TVS0701 AINP2 20 9 4.7 nF REFP + C4 68 µF THERMAL PAD 0.1 F 29 REFN AVSS Optional Reference Voltage Noise Filter 10 32 AGND 13 DGND 18 Figure 9-1. Geophone Input Application Example 54 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 9.2.1 Design Requirements Figure 9-1 depicts a typical application of a geophone input circuit. The application shows the ADC operating with a 5-V power supply and a 2.5-V level-shift voltage applied to the ADC inputs. The goal of this evaluation is to analyze the effect of noise resulting from source resistance. The source resistance is the sum of the series input resistors and the geophone output resistance. 9.2.2 Detailed Design Procedure Referring to Figure 9-1, Schottky diodes (BAS70 or equivalent) protect the ADC inputs from voltage overloads. The ADC inputs are protected from ESD events by the optional ESD protection diodes (TVS0701). The geophone signal is level-shifted to mid-supply by driving the input termination resistors (R1 and R2) common point to 2.5 V. The level-shift voltage is derived from the reference voltage and is buffered by the OPA391 op amp. The input termination resistors also provide the input bias current return path for the ADC inputs. The input signal is filtered to reduce out-of-band noise. The filter is comprised of common-mode and differential sections. The common-mode section filters noise common to both inputs, consisting of R3, R4, C1, and C2. The differential section filters differential noise, consisting of R3 through R6 and C3. The resistor values are kept low to reduce thermal noise. The REF6241 4.096-V voltage reference is used. The ADC must be programmed to match the value of the reference voltage. The optional noise filter consisting of R7 and C3 reduces reference noise. Resistor R7 increases gain error resulting from the impedance of the reference input. The AVDD1 power supply voltage = 5 V, with AVSS connected to AGND. The AVDD2 voltage is 2.5 V to minimize power consumption. If IOVDD = 1.8V, connect the CAPD pin to IOVDD. Besides the power supply pins, place additional capacitors at certain pins. Capacitors are required between CAPP – CAPN, REFP – REFN, and at the CAPBP, CAPBN, CAPI, CAPR, CAPC, and CAPD pins with the capacitance values given in Figure 9-1. The CAPP – CAPN, CAPBP, and CAPBN capacitors are C0G type. The DAC1282 provides a low-distortion signal to test THD performance, and through the DAC1282 dc test mode, test geophone impulse response. Increase the value of the DAC1282 capacitors CAPP and CAPN to 10 nF to optimize the ADS1285 THD test performance. See the DAC1282 data sheet for additional circuit details. 9.2.3 Application Curves Table 9-1 lists the effect of source resistance (RS) and device input current noise on dynamic range performance. Selected values of RS and input current noise, obtained from the input current noise distribution of Figure 9-2 (1.5 pA/√Hz and 3 pA/√Hz), are evaluated. Thermal noise voltage of the source resistance, input current noise × source resistance, and ADC input-referred noise voltage are summed as RMS values to derive the total noise. Dynamic range is calculated from the total noise result. 33 30 27 Population (%) 24 21 18 15 12 9 6 3 5 4.6 4.2 3.8 3.4 3 2.6 2.2 1.8 1.4 1 0 PGA Input Current Noise Density (pA/Hz) Figure 9-2. PGA Input Current Noise Distribution Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 55 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 Table 9-1. Source Resistance Noise RS (Ω) GAIN 1 0 16 1 1000 16 1 5000 16 in NOISE (pA/√Hz) RS NOISE (μV) in × RS NOISE (μV) 1.5 0 3 0 1.5 0 0.44 0 0.11 3 0 1.5 0.024 3 0.048 1.5 0.06 0.024 3 0.048 1.5 0.11 3 0.22 1.5 0.13 3 ADC SELF-NOISE (μV) 0.11 0.21 0.44 0.11 0.44 0.11 TOTAL NOISE (μV) DR (dB) 0.44 132.1 0.44 132.1 0.11 120.1 0.11 120.1 0.445 132.0 0.446 132.0 0.127 118.8 0.134 118.4 0.472 131.5 0.508 130.8 0.202 114.8 0.277 112.0 Data for the analysis is shown for low-power mode operation over a 206-Hz noise bandwidth (fDATA = 500 SPS). For PGA gain = 1, 5000-Ω source resistance has a minor effect on dynamic range performance. However, at PGA gain = 16, dynamic range performance can degrade from –5 dB to –8 dB depending on the level of device input current noise. 1000-Ω source resistance has 1.6-dB degradation at gain = 16 for input current noise density = 3 pA/√Hz. 9.3 Power Supply Recommendations The ADC has four power supplies: AVDD1, AVDD2, AVSS, and IOVDD. Among the power-supply options, the number of power supplies can be reduced to a single 3.3-V supply used for AVDD1, AVDD2, and IOVDD, with AVSS connected to ground. Be aware that 3.3-V operation limits the reference voltage to 2.5 V and requires using the buffer for gain = 1. The power supplies can be sequenced in any order. The ADC is held in reset until the power supplies have crossed the retrospective power-on voltage thresholds and the clock signal is applied (see Figure 6-8 for details of the voltage thresholds). 9.3.1 Analog Power Supplies The ADC has three analog power supplies, AVDD1, AVDD2, and AVSS, all of which must be well regulated and free from switching power-supply noise (voltage ripple < 1 mV). The AVDD1 power-supply voltage is relative to AVSS and powers the PGA and buffer. AVSS is the negative power supply. The ADC can be configured for single-supply operation with AVDD1 = 5 V or 3.3 V with AVSS connected to ground. Because the minimum voltage of AVDD1 to AGND = 2.375 V, dual-supply operation is only possible when AVDD1 – AVSS = ±2.5 V. Single-power supply operation requires a level-shift voltage at the geophone input through the input termination resistors. The level-shift voltage is typically equal to AVDD1 / 2. Bypass AVDD1 with 1-μF and 0.1-μF parallel capacitors to AVSS. The AVDD2 power supply powers the modulator. To simplify system power management, AVDD2 can be connected AVDD1, regardless whether AVDD1 and AVSS are configured for single- or dual-supply operation (AVDD2 voltage range is 2.375 V to 5.25 V with respect to AGND). Bypass AVDD2 with 1-μF and 0.1-μF parallel capacitors to AGND. 9.3.2 Digital Power Supply IOVDD is the digital power supply. IOVDD is the digital pin I/O voltage and also powers the digital core by an 1.8-V low-dropout regulator (LDO). The LDO output is the CAPD pin and is bypassed with a 0.22-µF capacitor to DGND. Do not externally load the CAPD voltage output. Bypass the IOVDD pin with 1-μF and 0.1-μF parallel capacitors to DGND. 56 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 If IOVDD is in the range of 1.65 V to 1.95 V, tie the IOVDD and CAPD pins together. This connection forces the internal LDO off, thereby the IOVDD voltage now directly powers the digital core. Pay close attention to the absolute maximum voltage rating of IOVDD driving the CAPD pin to avoid damaging the device. 9.3.3 Grounds The ADC has two ground pins, AGND and DGND. Connect the AGND and DGND pins together at the ADC to a single ground plane using short direct connections. 9.3.4 Thermal Pad The thermal pad does not carry device current but must be soldered and connected to the most negative power-supply voltage (AVSS). Because of the low power dissipation, PCB thermal vias can be omitted to provide space for bottom layer components under the device. 9.4 Layout 9.4.1 Layout Guidelines Figure 9-3 shows the layout of the geophone input application example of Figure 9-1. In most cases, a single unbroken ground plane connecting the grounds of the analog and digital components is preferred. A four-layer PCB is used, with the inner layers dedicated for ground and power-supply planes. Low resistance power-supply planes are necessary to maintain THD performance. Connect the REFN pin of the ADC directly to the ground terminal of the voltage reference to avoid ground noise coupling. Similarly, avoid ground noise between the tie-points of termination resistors R1 and R2 by connecting the resistors together first, then connect to ground (dual-supply operation). Place the smaller of the parallel power-supply bypass capacitors closest to the device supply pins. The thermal pad of the package connects to the most negative power-supply voltage (AVSS). Figure 9-3 shows single-supply operation, with AVSS tied to AGND. In this case, the thermal pad connects to AGND. For dual-supply operation, connect the thermal pad to AVSS. 9.4.2 Layout Example 5V REF6241 DAC1282 Test Signal OPA391 5V BAS70 5V PWDN RESET SYNC TVS0701 DRDY - DOUT Signal Input DIN SCLK CS CLK ADS1285 ADS1285 3.3 V IOVDD TVS0701 GPIO1 BAS70 GPIO0 5V 5V AVDD1 2.5 V AVDD2 Figure 9-3. Example Layout Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 57 ADS1285 www.ti.com SBAS559A – MAY 2022 – REVISED DECEMBER 2022 10 Device and Documentation Support 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 58 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADS1285 PACKAGE OPTION ADDENDUM www.ti.com 15-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS1285IRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1285 Samples ADS1285IRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1285 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of