ADS1286

® ADS 128 6 ADS1286 ADS 128 6 12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q q q q SERIAL INTERFACE GUARANTEED NO MISSING CODES 20kHz SAMPLING RATE LOW SUPPLY CURRENT: 250µA DESCRIPTION The ADS1286 is a 12-bit, 20kHz analog-to-digital converter with a differential input and sample and hold amplifier and consumes only 250µA of supply current. The ADS1286 offers an SPI and SSI compatible serial interface for communications over a two or three wire interface. The combination of a serial two wire interface and micropower consumption makes the ADS1286 ideal for remote applications and for those requiring isolation. The ADS1286 is available in a 8-pin plastic mini DIP and a 8-lead SOIC. APPLICATIONS q q q q REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION TRANSDUCER INTERFACE BATTERY OPERATED SYSTEMS SAR Control VREF DOUT +In CDAC –In S/H Amp Comparator Serial Interface DCLOCK CS/SHDN International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1335B Printed in U.S.A. October, 1998 SBAS053 SPECIFICATIONS At TA = TMIN to TMAX, +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, , fCLK = 16 • fSAMPLE, unless otherwise specified. ADS1286, ADS1286A PARAMETER ANALOG INPUT Full-Scale Input Range Absolute Input Voltage Capacitance Leakage Current SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Differential Linearity Offset Error Gain Error Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Small Signal Bandwidth DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range REFERENCE INPUT REF Input Range Input Resistance Current Drain VIN = VIN = VIN = VIN = 5.0Vp-p 5.0Vp-p 5.0Vp-p 5.0Vp-p at at at at 1kHz 5kHz 1kHz 1kHz 1.25 CS = VCC CS = GND, fCLK = 0Hz CS = VCC tCYC ≥ 640µs, fCLK ≤ 25kHz tCYC = 80µs, fCLK = 200kHz CONDITIONS MIN TYP MAX ADS1286K, ADS1286B MIN T T T T T T T ±1 ±0.5 0.75 ±2 50 82 ±2 ±1.0 ±3 ±8 T T T T T T T ±0.75 T T T ±0.5 ±0.25 T T T T ±1 ±0.75 T T TYP MAX T T T ADS1286C, ADS1286L MIN T T T T T T TYP MAX T T T UNITS +In – (–In) +In –In 0 –0.2 –0.2 25 ±1 12 12 VREF VCC +0.2 +0.2 V V V pF µA Bits Bits LSB LSB LSB LSB µVrms dB Clk Cycles Clk Cycles kHz dB dB dB dB 12 1.5 500 –85 –83 72 90 2.5 5000 5000 0.01 2.4 2.4 CMOS IIH = +5µA IIL = +5µA IOH = 250µA IOL = 250µA 3 0.0 3 0.0 Straight Binary +VCC 0.8 +VCC 0.4 T T T T T VCC+0.05V T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T 2.5 20 20 T T T T T T V MΩ MΩ µA µA µA DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format T T T T V V V V POWER SUPPLY REQUIREMENTS Power Supply Voltage VCC Quiescent Current, VANA tCYC ≥ 640µS, fCLK ≤ 25kHz tCYC = 90µS, fCLK = 200kHz Power Down CS = VCC TEMPERATURE RANGE Specified Performance ADS1286, K, L ADS1286A, B, C +4.50 5 200 250 5.25 400 500 3 +70 +85 T T T T T T T T T T T T T T T T T T T T V µA µA µA °C °C 0 –40 T T T T T Specifications same as grade to the left. TIMING CHARACTERISTICS fCLK = 200kHz, TA = TMIN to TMAX. SYMBOL tSMPL tSMPL (MAX) tCONV tdDO tdis ten thDO tf tr tCSD tSUCS PARAMETER Analog Input Sample Time Maximum Sampling Frequency Conversion Time Delay TIme, DCLOCK↓ to DOUT Data Valid Delay TIme, CS↑ to DOUT Hi-Z Delay TIme, DCLOCK↓ to DOUT Enable Output Data Remains Valid After DCLOCK↓ DOUT Fall Time DOUT Rise Time Delay Time, CS↓ to DCLOCK↓ Delay Time, CS↓ to DCLOCK↑ ® CONDITIONS See Operating Sequence ADS1286 See Operating Sequence See Test Circuits See Test Circuits See Test Circuits CLOAD = 100pF See Test Circuits See Test Circuits See Operating Sequence See Operating Sequence MIN 1.5 TYP MAX 2.0 20 UNITS Clk Cycles kHz Clk Cycles ns ns ns ns ns ns ns ns 15 12 85 25 50 30 70 60 150 50 100 100 100 0 30 ADS1286 2 ABSOLUTE MAXIMUM RATINGS(1) +VCC ..................................................................................................... +6V Analog Input ....................................................... –0.3V to (+VCC + 300mV) Logic Input ......................................................... –0.3V to (+VCC + 300mV) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Reference Voltage .............................................................. +5.5V NOTE: (1) Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION VREF +In –In GND 1 2 ADS1286 3 4 8-Pin Mini PDIP 8-Lead SOIC 6 5 DOUT CS/SHDN 8 7 +VCC DCLOCK PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 NAME VREF +In –In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. Non Inverting Input. Inverting Input. Connect to ground or remote ground sense point. Ground. Chip Select when low, Shutdown Mode when high. The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock synchronizes the serial data transfer and determines conversion speed. Power Supply. PACKAGE/ORDERING INFORMATION INTEGRAL LINEARITY ±2 ±2 ±1 ±2 ±2 ±1 ±2 ±2 ±1 ±2 ±2 ±1 TEMPERATURE RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C PACKAGE DRAWING NUMBER(1) 006 006 006 182 182 182 006 006 006 182 182 182 PRODUCT ADS1286P ADS1286PK ADS1286PL ADS1286U ADS1286UK ADS1286UL ADS1286PA ADS1286PB ADS1286PC ADS1286UA ADS1286UB ADS1286UC PACKAGE Plastic DIP Plastic DIP Plastic DIP SOIC SOIC SOIC Plastic DIP Plastic DIP Plastic DIP SOIC SOIC SOIC NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS1286 TYPICAL PERFORMANCE CURVES At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. REFERENCE CURRENT vs SAMPLE RATE 2.5 4.0 3.5 REFERENCE CURRENT vs TEMPERATURE Reference Current (µA) Reference Current (µA) 2.0 3.0 2.5 2.0 1.5 1.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 Sample Rate (kHz) –55 –40 –25 0 25 70 85 Temperature (°C) CHANGE IN OFFSET vs REFERENCE VOLTAGE 5 4.5 CHANGE IN OFFSET vs TEMPERATURE 0.6 0.4 Change in Offset (LSB) 3.5 3 2.5 2 1.5 1 0.5 0 1 2 3 Reference Voltage (V) 4 5 Delta from 25°C (LSB) 4 0.2 0 –0.2 –0.4 –0.6 –55 –40 –25 0 25 Temperature (°C) 70 85 CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE 0.10 4 3.5 CHANGE IN GAIN vs REFERENCE VOLTAGE Delta from +5V Reference (LSB) 0.05 0.00 –0.05 –0.10 –0.15 –0.20 1 2 3 Reference Voltage (V) 4 5 Change in Integral Linearity (LSB) Change in Differential Linearity (LSB) Change in Gain (LSB) 3 2.5 2 1.5 1 0.5 0 1 2 3 Reference Voltage (V) 4 5 ® ADS1286 4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE 12 Differential Linearity Error (LSB) Effective Number of Bits (rms) 3.0 2.0 1.0 0 –1.0 –2.0 –3.0 DIFFERENTIAL LINEARITY ERROR vs CODE 11.75 11.5 11.25 11 10.75 10.5 10.25 10 0.1 1 Reference Voltage (V) 10 0 2048 Code 4095 SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY 100 Signal-to-(Noise + Distortion) (dB) Spurious Free Dynamic Range and Signal-to-Noise Ratio (dB) SPURIOUS FREE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO vs FREQUENCY 100 90 80 70 60 50 40 30 20 10 0 Signal-to-Noise Ratio Spurious Free Dynamic Range 90 80 70 60 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 0.1 1 Frequency (kHz) 10 SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL 80 Signal-to-(Noise + Distortion) (dB) TOTAL HARMONIC DISTORTION vs FREQUENCY 0 Total Harmonic Distortion (dB) 70 60 50 40 30 20 10 0 –40 –35 –30 –25 –20 –15 Input Level (dB) –10 –5 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0.1 1 Frequency (kHz) 10 ® 5 ADS1286 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. 4096 POINT FFT 0 PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE 10 9 –25 Magnitude (dB) Peak-to-Peak Noise (LSB) 8 7 6 5 4 3 2 1 –50 –75 –100 –125 0 2 Frequency (kHz) 4 6 0 0.1 1 Reference Voltage (V) 10 POWER SUPPLY REJECTION vs RIPPLE FREQUENCY 0 –10 Power Supply Rejection (dB) Delta from 25°C (LSB) –20 –30 –40 –50 –60 –70 –80 –90 1 10 100 1000 Ripple Frequency (kHz) 10000 –0.15 –55 –40 0.15 CHANGE GAIN vs TEMPERATURE VRIPPLE = 20mV 0.1 0.05 0 –0.05 –0.1 –25 0 25 70 85 Temperature (°C) POWER DOWN SUPPLY CURRENT vs TEMPERATURE 3 2.5 Supply Current (µA) 2 1.5 1 0.5 0 –55 –40 –25 0 25 70 85 Temperature (°C) Supply Current (µA) 400 350 300 SUPPLY CURRENT vs TEMPERATURE fSAMPLE = 12.5kHz 250 200 150 100 –55 –40 –25 0 25 70 85 Temperature (°C) fSAMPLE = 1.6kHz ® ADS1286 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. INTEGRAL LINEARITY ERROR vs CODE 3.0 DIGITAL INPUT LINE THRESHOLD vs SUPPLY VOLTAGE 3 Digital Input Threshold Voltage (V) Integral Linearity Error (LSB) 2.0 1.0 0 –1.0 –2.0 –3.0 0 2048 Code 4095 2.5 2 1.5 1 0.5 0 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 Supply Voltage (V) INPUT LEAKAGE CURRENT vs TEMPERATURE 10 Leakage Current (nA) 1 0.1 0.01 –55 –40 –25 0 25 70 85 Temperature (°C) ® 7 ADS1286 TIMING DIAGRAMS AND TEST CIRCUITS 1.4V 3kΩ DOUT 100pF CLOAD Test Point DOUT tr tf VOH VOL Load Circuit for tdDO, tr, and tf Voltage Waveforms for DOUT Rise and Fall Times tr, and tf Test Point DCLOCK VIL tdDO DOUT thDO Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden VCC VOH VOL DOUT 3kΩ 100pF CLOAD tdis Waveform 2, ten tdis Waveform 1 CS/SHDN VIH CS/SHDN DOUT Waveform 1(1) tdis DOUT Waveform 2(2) Voltage Waveforms for tdis 90% DCLOCK 1 2 10% DOUT ten VOL B11 NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Voltage Waveforms for ten ® ADS1286 8 tCYC CS/SHDN tSUCS DCLOCK tCSD DOUT HI-Z NULL BIT NULL BIT POWER DOWN HI-Z B8 B7 B6 B5 B4 B3 B2 B1 B0(1) tSMPL B11 B10 B9 (MSB) B11 B10 B9 B8 tCONV tDATA Note: (1) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output LSB-First data then followed with zeroes indefinitely. tCYC CS/SHDN tSUCS DCLOCK tCSD DOUT HI-Z NULL BIT HI-Z B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 (2) POWER DOWN tSMPL B11 B10 B9 (MSB) tCONV tDATA Note: (2) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output zeroes indefinitely. tDATA: During this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes. FIGURE 1. ADS1286 Operating Sequence. SERIAL INTERFACE The ADS1286 communicates with microprocessors and other external digital systems via a synchronous 3-wire serial interface. DCLOCK synchronizes the data transfer with each bit being transmitted on the falling DCLOCK edge and captured on the rising DCLOCK edge in the receiving system. A falling CS initiates data transfer as shown in Figure 1. After CS falls, the second DCLOCK pulse enables DOUT. After one null bit, the A/D conversion result is output on the DOUT line. Bringing CS high resets the ADS1286 for the next data exchange. leaving the DCLOCK running to clock out the LSB first data or zeroes. If the CS input is not running rail-to-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CS pin to ground when it is low and to supply voltage when it is high. 1000 TA = 25°C VCC = 5V VREF = 5V fCLK = 16 • fSAMPLE Supply Current (µA) MICROPOWER OPERATION With typical operating currents of 250µA and automatic shutdown between conversions, the ADS1286 achieves extremely low power consumption over a wide range of sample rates (see Figure 2). The auto-shutdown allows the supply current to drop with sample rate. SHUTDOWN The ADS1286 is equipped with automatic shutdown features. The device draws power when the CS pin is LOW and shuts down completely when the pin is HIGH. The bias circuit and comparator powers down and the reference input becomes high impedance at the end of each conversion 100 10 1 0.1k 1k 10k 100k Sample Rate (kHz) FIGURE 2. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate. ® 9 ADS1286 MINIMIZING POWER DISSIPATION In systems that have significant time between conversions, the lowest power drain will occur with the minimum CS LOW time. Bringing CS LOW, transferring data as quickly as possible, and then bringing it back HIGH will result in the lowest current drain. This minimizes the amount of time the device draws power. After a conversion the A/D automatically shuts down even if CS is held LOW. If the clock is left running to clock out LSB-data or zero, the logic will draw a small amount of current (see Figure 3). REDUCED REFERENCE OPERATION The effective resolution of the ADS1286 can be increased by reducing the input span of the converter. The ADS1286 exhibits good linearity and gain over a wide range of reference voltages (see Typical Performance Curves “ Change in Linearity vs Reference Voltage” and “Change in Gain vs Reference Voltage”). However, care must be taken when operating at low values of VREF because of the reduced LSB size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low VREF values: 1. Offset 2. Noise 6.00 5.00 TA = 25°C VCC = +5V VREF = +5V fCLK = 16 • fSAMPLE Supply Current (µA) 4.00 3.00 2.00 1.00 0.00 0.1 CS = LOW (GND) OFFSET WITH REDUCED VREF The offset of the ADS1286 has a larger effect on the output code. When the ADC is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The Typical Performance Curve “Change in Offset vs Reference Voltage” shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 122µV which is 0.1 LSB with a 5V reference becomes 0.5LSB with a 1V reference and 2.5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the negative input of the ADS1286. NOISE WITH REDUCED VREF The total input referred noise of the ADS1286 can be reduced to approximately 200µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. For operation with a 5V reference, the 200µV noise is only 0.15LSB peak-to-peak. In this case, the ADS1286 noise will contribute virtually no uncertainty to the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 2.5V reference this same 200µV noise is 0.3LSB peak-to-peak. If the reference is further reduced to 1V, the 200µV noise becomes equal to 0.8LSBs and a stable code may be difficult to achieve. In this case averaging multiple readings may be necessary. CS HIGH (VCC) 1 10 100 Sample Rate (kHz) FIGURE 3. Shutdown Current with CS HIGH is Lower than with CS LOW. RC INPUT FILTERING It is possible to filter the inputs with an RC network as shown in Figure 4. For large values of CFILTER (e.g., 1µF), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 20pF x VIN/tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 64µs, the input current equals 1.56µA at VIN = 5V. In this case, a filter resistor of 75Ω will cause 0.1LSB of full-scale error. If a larger filter resistor must be used, errors can be eliminated by increasing the cycle time. RFILTER VIN IDC CFILTER ADS1286 FIGURE 4. RC Input Filtering. ® ADS1286 10 +5V +5V +5V R8 46kΩ R7 10Ω OPA237 0.4V R9 1kΩ 0.3V C1 10µF MUX R10 1kΩ 0.2V R11 1kΩ 0.1V R12 1kΩ D1 R1 150kΩ R3 500kΩ R2 59kΩ R6 1MΩ C3 0.1µF VREF C2 0.1µF U2 DCLOCK ADS1286 DOUT CS/SHDN U1 R5 500Ω C5 0.1µF µP 3-Wire Interface U4 A0 A1 TC1 Thermocouple TC2 TC3 C4 10µF R4 1kΩ U3 ISO Thermal Block FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the ADS1286. +VCC REF200 (100µA) VREF 1 2 RTD 3 4 ADS1286 8 0.1µF DCLOCK DOUT CS/SHDN µP FIGURE 6. ADS1286 with RTD Sensor. ® 11 ADS1286 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2006 PACKAGING INFORMATION Orderable Device ADS1286P ADS1286PA ADS1286PB ADS1286PBG4 ADS1286PC ADS1286PG4 ADS1286PK ADS1286PL ADS1286U ADS1286U/2K5 ADS1286U/2K5G4 ADS1286UA ADS1286UA/2K5 ADS1286UA/2K5G4 ADS1286UAG4 ADS1286UB ADS1286UBG4 ADS1286UC ADS1286UCG4 ADS1286UG4 ADS1286UK ADS1286UKG4 ADS1286UL ADS1286UL/2K5 ADS1286ULG4 Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing P P P P P P P P D D D D D D D D D D D D D D D D D Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 50 50 50 50 50 50 50 50 100 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Call TI Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 100 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 100 100 100 100 100 100 100 100 100 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 100 Green (RoHS & no Sb/Br) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2006 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2006, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Low Power Wireless www.ti.com/lpw