ADS1288
SBASAW0 – FEBRUARY 2024
ADS1288 32-Bit, Delta-Sigma ADC for Seismic Applications
1 Features
3 Description
•
The ADS1288 is a 32-bit, low-power, analog-todigital converter (ADC), with a programmable gain
amplifier (PGA) and a finite impulse response (FIR)
filter. The ADC is designed for the demanding
requirements of seismology equipment requiring low
power consumption to extend battery run time.
•
•
•
•
•
•
•
•
•
•
•
•
Power consumption:
– PGA operation: 5mW (typical)
– Buffer operation: 3mW (typical)
Dynamic range:
– PGA gain: 1, 500SPS (122dB, typical)
– Buffer operation: 500SPS (122dB, typical)
THD: < –120dB (typical)
CMRR: 120dB (typical)
Flexible digital filter:
– Selectable sinc + FIR + IIR
– Linear or minimum phase
– High-pass filter
Data rates: 125SPS to 2000SPS
PGA gains: 1 to 64
SYNC input
Clock error compensation
Two-channel multiplexer
Offset and gain calibration
General-purpose digital I/Os
Analog supply operation: 5V, 3.3V, or ±2.5V
The low-noise PGA extends the ADC dynamic
range through gains 1 to 64. The PGA allows
direct connection to geophones and transformercoupled hydrophones without the need of an external
amplifier. The optional unity-gain buffer reduces
power consumption.
The ADC incorporates a high-resolution, delta-sigma
(ΔΣ) modulator and a FIR filter with programmable
phase response. The high-pass filter removes dc
and low-frequency content from the signal. Clock
frequency error is compensated by the sample rate
converter with up to 7ppb frequency accuracy.
The ADC supports 3.3V operation to minimize device
power consumption. Power consumption is 3mW
(typical) in buffer mode operation and 5mW (typical)
in PGA mode operation.
2 Applications
•
•
•
•
Energy exploration
Passive seismic monitoring
Earth sciences and geology
Precision instrumentation
The ADC is available in a compact 5mm × 5mm
VQFN package and is fully specified over the –40°C
to +85°C ambient temperature range.
Package Information
PACKAGE(1)
PART NUMBER
ADS1288
(1)
(2)
AVDD1
RHB (VQFN, 32)
IOVDD
CLK
DRDY
ADS1288
AIN2P
PGA
MUX
BUF
Modulator
Sample
Rate
Converter
Digital
Filter
Serial
Interface
CS
SCLK
DOUT
DIN
Control
PWDN
RESET
SYNC
AIN2N
Noise/Offset
Test
AVSS
AGND
5mm × 5mm
For more information, see the Mechanical, Packaging, and
Orderable Information.
The package size (length × width) is a nominal value and
includes pins, where applicable.
AVDD2
AIN1P
AIN1N
PACKAGE SIZE(2)
REFP
REFN
GPIO1
GPIO0
GND
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1288
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SBASAW0 – FEBRUARY 2024
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 5
5.1 Absolute Maximum Ratings........................................ 5
5.2 ESD Ratings............................................................... 5
5.3 Recommended Operating Conditions.........................5
5.4 Thermal Information....................................................6
5.5 Electrical Characteristics.............................................7
5.6 Timing Requirements: 1.65V ≤ IOVDD ≤ 1.95V
and 2.7V ≤ IOVDD ≤ 3.6V............................................. 9
5.7 Switching Characteristics: 1.65V ≤ IOVDD ≤
1.95V and 2.7V ≤ IOVDD ≤ 3.6V...................................9
5.8 Timing Diagrams......................................................... 9
5.9 Typical Characteristics.............................................. 12
6 Parameter Measurement Information.......................... 17
6.1 Noise Performance................................................... 17
7 Detailed Description......................................................17
7.1 Overview................................................................... 17
2
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................32
7.5 Programming............................................................ 35
8 Register Map.................................................................. 40
8.1 Register Descriptions................................................40
9 Application and Implementation.................................. 45
9.1 Application Information............................................. 45
9.2 Typical Application.................................................... 45
9.3 Power Supply Recommendations.............................47
9.4 Layout....................................................................... 48
10 Device and Documentation Support..........................49
10.1 Receiving Notification of Documentation Updates..49
10.2 Support Resources................................................. 49
10.3 Trademarks............................................................. 49
10.4 Electrostatic Discharge Caution..............................49
10.5 Glossary..................................................................49
11 Revision History.......................................................... 49
12 Mechanical, Packaging, and Orderable
Information.................................................................... 49
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AVSS
CAPR
REFP
REFN
PWDN
RESET
SYNC
DRDY
32
31
30
29
28
27
26
25
4 Pin Configuration and Functions
AIN1P
1
24
DOUT
AIN1N
2
23
DIN
AIN2P
3
22
SCLK
AIN2N
4
21
CS
CAPP
5
20
CLK
CAPN
6
19
IOVDD
CAPBP
7
18
DGND
CAPBN
8
17
CAPD
9
10
11
12
13
14
15
16
CAPC
AVSS
AVDD1
AVDD2
AGND
CAPI
GPIO0
GPIO1
Thermal pad
Not to scale
Figure 4-1. RHB Package, 32-Pin, 5mm × 5mm VQFN (Top View)
Table 4-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
AIN1P
Analog input
Channel 1 positive input.
2
AIN1N
Analog input
Channel 1 negative input.
3
AIN2P
Analog input
Channel 2 positive input.
4
AIN2N
Analog input
Channel 2 negative input.
5
CAPP
Analog internal
PGA positive capacitor. Connect a 10nF C0G capacitor across CAPP and CAPN.
6
CAPN
Analog internal
PGA negative capacitor. Connect a 10nF C0G capacitor across CAPP and CAPN.
7
CAPBP
Analog internal
Buffer positive capacitor. Connect a 47nF C0G capacitor to AVSS.
8
CAPBN
Analog internal
Buffer negative capacitor. Connect a 47nF C0G capacitor to AVSS.
9
CAPC
Analog internal
Charge-pump capacitor. Connect a 4.7nF, minimum 10V rated capacitor to AGND.
10
AVSS
Analog supply
PGA negative analog supply. See the Analog Power Supplies section for details.
11
AVDD1
Analog supply
PGA positive analog supply. See the Analog Power Supplies section for details.
12
AVDD2
Analog supply
Modulator analog supply. See the Analog Power Supplies section for details.
13
AGND
Analog ground
Analog ground.
14
CAPI
Analog internal
Input bias capacitor. Connect a 100nF ceramic capacitor to AGND.
15
GPIO0
Digital I/O
General-purpose I/O.
16
GPIO1
Digital I/O
General-purpose I/O.
17
CAPD
Analog output
18
DGND
Ground
19
IOVDD
Digital supply
20
CLK
Digital input
ADC clock input.
21
CS
Digital input
Serial interface select, active low.
Digital low-dropout regulator (LDO) output. Connect a 220nF ceramic capacitor to DGND.
Digital ground.
Digital I/O power supply. See the IOVDD Power Supply section for details.
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Table 4-1. Pin Functions (continued)
PIN
TYPE
NAME
22
SCLK
Digital input
Serial interface clock.
23
DIN
Digital input
Serial interface data in.
24
DOUT
Digital output
Serial interface data out.
25
DRDY
Digital output
Data ready, active low.
26
SYNC
Digital input
ADC synchronization, active high.
27
RESET
Digital input
ADC reset, active low.
28
PWDN
Digital input
ADC power down, active low.
29
REFN
Analog input
Negative reference input. See the Voltage Reference Input section for details.
Positive reference input. See the Voltage Reference Input section for details.
30
REFP
Analog input
31
CAPR
Analog internal
Reference bias capacitor. Connect a 100nF ceramic capacitor to AVSS.
32
AVSS
Analog supply
PGA negative supply.
Thermal pad
4
DESCRIPTION
NO.
Connect the thermal pad to AVSS. Thermal vias placed in the printed circuit board (PCB) land are
optional to allow placement of bottom side components.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
AVDD1 to AVSS
–0.3
5.5
AVSS to AGND
–2.8
0.3
AVDD2 to AGND
–0.3
5.5
AVDD2 to AVSS
–0.3
5.5
IOVDD to DGND
–0.3
3.9
IOVDD to DGND (IOVDD connected to CAPD)
–0.3
2.2
Grounds
AGND to DGND
– 0.3
0.3
V
Analog input voltage
AIN1P, AIN1N, AIN2P, AIN2N, REFP, REFN
V
Digital input voltage
CLK, DIN, SCLK, CS, GPIO0, GPIO1, SYNC, RESET, PWDN
Input current
Continuous, any digital or analog pin (2)
Power-supply voltages
Temperature
(1)
(2)
AVSS – 0.3
AVDD1 + 0.3
DGND – 0.3
IOVDD + 0.3
–10
10
Junction, TJ
150
Storage, Tstg
–60
150
UNIT
V
V
mA
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional – this may affect device reliability, functionality, performance, and shorten the device
lifetime.
Analog input pins AIN1P, AIN1N, AIN2P, AIN2N, REFP and REFN are diode-clamped to AVDD1 and AVSS. Limit the input current to
10mA in the event the analog input voltage exceeds AVDD1 + 0.3V or AVSS – 0.3V. Digital input pins are clamped to IOVDD and
DGND. Limit the input current if the digital input voltage exceeds IOVDD + 0.3V or DGND – 0.3V.
5.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
2000
Charged-device model (CDM), per JEDEC JESD22-C101(2)
V
1000
JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
5.25
V
POWER SUPPLY
AVDD1 to AVSS
3
AVDD1 to AGND
Analog power supplies
AVSS to AGND
2.375
–2.625
0
2.375
5.25
AVDD2 to AGND
AVDD2 to AVSS
Digital power supply
V
5.25
IOVDD to DGND
IOVDD connected to CAPD
2.7
3.6
1.65
1.95
V
ANALOG INPUTS
VIN
Differential input voltage
Absolute input voltage
Absolute output voltage
VIN = VAINP – VAINN
±VREF / Gain
V
Buffer operation
AVSS + 0.1
AVDD1 – 0.1
PGA operation
AVSS + 1.1
AVDD1 – 0.85
Buffer operation
AVSS + 0.1
AVDD1 – 0.1
PGA operation
AVSS + 0.15
AVDD1 – 0.15
Calibration range (1)
6%
V
V
FSR
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5.3 Recommended Operating Conditions (continued)
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
2.4
2.5
2.6
UNIT
VOLTAGE REFERENCE INPUT
VREF
VREF = VREFP – VREFN
VREFN
Negative reference input
VREFP
Positive reference input
V
AVSS – 0.05
V
AVDD1 + 0.1
V
0.2 × IOVDD
V
DIGITAL INPUTS
VINL
Low-level input voltage
VINH
High-level input voltage
fCLK
Clock input frequency
0.8 × IOVDD
3
V
4.096
4.15
MHz
TEMPERATURE
TA
(1)
Ambient temperature
Operational
–50
85
Specification
–40
85
°C
Calibration range is the sum of the offset and gain error correction.
5.4 Thermal Information
ADS1288
THERMAL METRIC(1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
30
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
19.4
°C/W
Junction-to-board thermal resistance
10.9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
10.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.8
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
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5.5 Electrical Characteristics
minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD1 = 5V, AVDD2 = 2.5V to 5V, AVSS = 0V, IOVDD = 1.8V, VREFP = 2.5V, VREFN = 0V, VCM = 2.5V, PGA gain = 1, RS =
0Ω, fCLK = 4.096MHz and fDATA = 500SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Input mux on-resistance
Input 1 to input 2 cross connection
60
Ω
nA
PGA OPERATION
IB
Input current
45
IOS
Input offset current
±3
Gain
nA
1, 2, 4, 8, 16, 32, 64
V/V
en-PGA
Input voltage noise density
PGA Gain = 16
20
nV/√Hz
in-PGA
Input current noise density
Differential
2.5
pA/√Hz
30
kHz
±0.3
µA
Antialias filter frequency
BUFFER OPERATION
IB
Input current
VIN = 2.5V
DC PERFORMANCE
en
Noise
VOS
Offset error
See Noise Performance section for details
PGA operation
–350/gain - 10
±30/gain + 5
350/gain + 10
–600
±50
600
Buffer operation
After calibration
Offset error drift
PGA operation
0.5/gain
Buffer operation
PSRR
±0.02%
0.05%
2
Gain match
Relative to PGA gain = 1
Gain drift
All PGA gains
Common-mode rejection ratio
f = 60Hz
Power-supply rejection ratio
–0.05%
After calibration
Buffer operation
CMRR
µV/°C
1
PGA operation, gain = 1
Gain error
µV
±1
ppm
–0.07%
±0.05%
0.07%
–0.2%
±0.06%
0.2%
2
104
120
80
95
AVDD2
At dc
AVSS, AVDD1
At dc
85
110
IOVDD
At dc
100
120
ppm/°C
dB
dB
AC PERFORMANCE
en-MOD
Modulator voltage noise density
100
AVDD1 = 3.3V,
AVSS = 0V,
fIN = 31.25Hz,
VIN = –0.5dBFS
THD
Total harmonic distortion
AVDD1 = 5V,
AVSS = 0V,
fIN = 31.25Hz,
VIN = –0.5dBFS
SFDR
nV/√Hz
Buffer operation
–124
PGA gain = 2
–122
-117
PGA gain = 4
–124
PGA gain = 8
–125
PGA gain = 16
–123
PGA gain = 32 and 64
–124
Buffer operation
–123
-117
PGA gain = 1
–121
-115
PGA gain = 2
–124
PGA gain = 4
–125
PGA gain = 8
–122
PGA gain = 16
–121
PGA gain = 32 and 64
–123
-116
-115
dB
-115
-113
Spurious-free dynamic range
fIN = 31.25Hz, VIN = –0.5dBFS
115
dB
Crosstalk
fIN = 31.25Hz, VIN = –0.5dBFS
–140
dB
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5.5 Electrical Characteristics (continued)
minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD1 = 5V, AVDD2 = 2.5V to 5V, AVSS = 0V, IOVDD = 1.8V, VREFP = 2.5V, VREFN = 0V, VCM = 2.5V, PGA gain = 1, RS =
0Ω, fCLK = 4.096MHz and fDATA = 500SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE INPUT
Reference input current
80
µA/V
FIR DIGITAL FILTER
fDATA
Data rate
Pass-band ripple
125
2000
SPS
–0.003
0.003
dB
Pass-band (–0.01dB)
0.375 × fDATA
Hz
Bandwidth (–3dB)
0.413 × fDATA
Hz
0.5 × fDATA
Hz
Stop band
Stop-band attenuation (1)
Group delay
Settling time (latency)
135
dB
Minimum phase filter, at dc
5 / fDATA
Linear phase filter
31/ fDATA
Minimum phase filter
62 / fDATA
Linear phase filter
62 / fDATA
s
s
IIR DIGITAL FILTER
High-pass corner frequency
0.1
10
Hz
244
ppm
SAMPLE RATE CONVERTER
Frequency compensation range
–244
Resolution
7.45
ppb
DIGITAL INPUT/OUTPUT
VOH
High-level output voltage
IOH = 1mA
VOL
Low-level output voltage
IOL = –1mA
Ilkg
Input leakage
0.8 × IOVDD
V
–1
0.2 × IOVDD
V
1
μA
POWER SUPPLY
AVDD1 = 3.3V
IAVDD1,
IAVSS
AVDD1, AVSS current
AVDD1 = 5V
PGA operation
0.85
1.1
Buffer operation
0.25
0.45
PGA operation
0.85
1.1
Buffer operation
0.25
0.45
Power-down mode
IAVDD2
IIOVDD
AVDD2 current
IOVDD current
IOVDD additional current
Pd
(1)
(2)
8
Power dissipation (2)
AVDD2 = 2.5V
Power-down mode
Power-down mode
mA
1
5
µA
0.7
0.85
mA
1
5
µA
0.24
0.4
mA
1
10
Standby mode
200
Sample rate converter operation
0.6
μA
mA
AVDD1 = 3.3V
AVDD2 = 2.5V
PGA operation
5.0
6.5
Buffer operation
3.0
4.2
AVDD1 = 5V
AVDD2 = 2.5V
PGA operation
6.4
8.3
Buffer operation
3.4
5.1
mW
Input frequencies at N × 16 kHz ± fDATA / 2 (where N = 1, 2, 3, and so on) intermodulate with the chopper clock. At these frequencies
stop band attenuation = –90dBFS (typ).
Excluding current consumed by the voltage reference input or by sample rate converter operation. See voltage reference input current
and IOVDD supply current for sample rate converter operation.
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5.6 Timing Requirements: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
244.14
332
ns
CLOCK
tc(CLK)
CLK period
241
tw(CLKH)
Pulse duration, CLK high
110
ns
tw(CLKL)
Pulse duration, CLK low
110
ns
SERIAL INTERFACE
tw(CSH)
Pulse duration, CS high
20
ns
td(CSSC)
Delay time, first SCLK rising edge after CS falling edge
20
ns
tc(SCLK)
SCLK period
120
ns
tw(SCH)
Pulse duration, SCLK high
50
ns
tw(SCL)
Pulse duration, SCLK low
50
ns
tsu(DI)
Setup time, DIN valid before SCLK rising edge
10
ns
th(DI)
Hold time, DIN valid after SCLK rising edge
10
ns
tsu(SRC-W)
Setup time, SRC[1:0] register write before DRDY falling edge
256
1 / f(CLK)
2
1 / f(CLK)
SYNC
tw(SYNL)
Pulse duration, SYNC low
tw(SYNH)
Pulse duration, SYNC high
2
1 / f(CLK)
tsu(SYNCLK)
Setup time, SYNC high before CLK rising edge
10
ns
th(SYNCLK)
Hold time, SYNC high after CLK rising edge
10
ns
2
1 / f(CLK)
RESET
tw(RSTL)
Pulse duration, RESET low
tsu(RSTCLK)
Setup time, RESET high before CLK rising edge
10
ns
th(RSTCLK)
Hold time, RESET high after CLK rising edge
10
ns
5.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
over operating ambient temperature range and CLOAD = 20pF (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
SERIAL INTERFACE
tw(DRH)
Pulse duration, DRDY high
8
1 / f(CLK)
tp(CSDO)
Propagation delay time, CS falling edge to DOUT driven valid
50
ns
tp(SCDO)
Propagation delay time, SCLK falling edge to new DOUT valid
50
ns
th(SCDO)
Propagation delay time, SCLK falling edge to DOUT invalid
5
ns
SYNC
tp(SYNDR)
Propagation delay time, SYNC rising edge to valid data DRDY falling edge
62.98145 / fDATA + 930 / fCLK
s
Propagation delay time, RESET rising edge to DRDY falling edge
516,874
1/ fCLK
Propagation delay time, PWDN rising edge to DRDY falling edge
62.98145 / fDATA + 946 / f(CLK)
s
650,000
1 / fCLK
RESET
tp(RSTDR)
PWDN
tp(PDDR)
POWER UP
tp(SUPDR)
Propagation delay time, power supply and CLK applied to first DRDY pulse
5.8 Timing Diagrams
tc(CLK)
tw(CLKL)
CLK
tw(CLKH)
Figure 5-1. Clock Timing Requirements
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tw(CSH)
CS
td(CSSC)
tc(SCLK)
tw(SCH)
SCLK
tsu(DI)
tw(SCL)
DIN
th(DI)
Figure 5-2. Serial Interface Timing Requirements
tw(DRH)
DRDY
CS
SCLK
tp(CSDO)
th(SCDO)
MSB
DOUT
LSB
0
tp(SCDO)
Figure 5-3. Serial Interface Switching Characteristics
CLK
th(SYNCLK)
tsu(SYNCLK)
SYNC
tw(SYNL)
tw(SYNH)
DRDY
(settled data)
(Pulse sync mode)
tp(SYNDR)
(settled data)
DRDY
(Continuous sync mode)
Figure 5-4. SYNC Timing Requirements and Switching Characteristics
10
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CLK
th(RSTCLK)
tsu(RSTCLK)
RESET
tw(RSTL)
tp(RSTDR)
DRDY
Figure 5-5. RESET Timing Requirements and Switching Characteristics
PWDN
DRDY
tp(PDDR)
Figure 5-6. PWDN Switching Characteristics
DRDY
SPI
SRC[1:0] Register Write
tsu(SCR-W)
Figure 5-7. Sample Rate Converter Register-Write Timing Requirements
AVDD1 – AVSS
1.65 V typ.
AVDD2 – AGND
1.65 V typ.
CAPD – DGND
1.35 V typ.
+
–
+
–
+
–
CLK
DRDY
tp(SUPDR)
Figure 5-8. Power-Up Switching Characteristics
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5.9 Typical Characteristics
0
0
-20
-20
-40
-40
-60
-60
Amplitude (dB)
Amplitude (dB)
at TA = 25°C, AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 4.096MHz, VREFP = 2.5V, VREFN = 0V, PGA
gain = 1, RS = 0Ω, VCM = 2.5V, and fDATA = 500SPS (unless otherwise noted)
-80
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
25
50
75
100 125 150
Frequency (Hz)
175
200
225
0
250
25
50
75
Buffer mode
0
-20
-20
-40
-40
-60
-60
Amplitude (dB)
Amplitude (dB)
200
225
250
225
250
225
250
Figure 5-10. Shorted Input FFT
0
-80
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
25
50
75
100 125 150
Frequency (Hz)
175
200
225
250
0
25
50
75
PGA gain = 16
100 125 150
Frequency (Hz)
175
200
PGA gain = 2
Figure 5-11. Shorted Input FFT
Figure 5-12. Full-Scale Input FFT
0
0
-20
-20
-40
-40
-60
-60
Amplitude (dB)
Amplitude (dB)
175
PGA gain = 2
Figure 5-9. Shorted Input FFT
-80
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
25
50
75
100 125 150
Frequency (Hz)
175
200
PGA gain = 16
225
250
0
25
50
75
100 125 150
Frequency (Hz)
175
200
AIN2: 31.25Hz, –0.5dBFS signal, AIN1: input shorted
measured channel
Figure 5-13. Full-Scale Input FFT
12
100 125 150
Frequency (Hz)
Figure 5-14. Channel Crosstalk
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5.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 4.096MHz, VREFP = 2.5V, VREFN = 0V, PGA
gain = 1, RS = 0Ω, VCM = 2.5V, and fDATA = 500SPS (unless otherwise noted)
100
PGA gain = 1
PGA gain = 8
Buffer operation
90
80
Population (%)
70
60
50
40
30
20
10
80
100
60
40
20
0
-20
-40
-60
-80
-100
0
Offset Error (V)
30 units
Figure 5-15. Dynamic Range vs PGA Gain
Figure 5-16. Offset Error Distribution
100
100
PGA gain = 1
PGA gain = 8
Buffer operation
90
80
80
70
Population (%)
70
60
50
40
60
50
40
30
30
20
20
10
10
700
600
500
400
300
200
100
0
Gain Error (ppm)
30 units
30 units
Figure 5-17. Offset Drift Distribution
Figure 5-18. Gain Error Distribution
100
100
PGA gain = 8
PGA gain = 16, 32 and 64
Buffer operation
90
80
PGA gain = 1
PGA gain = 2
PGA gain = 4
90
80
70
50
Gain Error (ppm)
6
5.5
5
4.5
4
3.5
3
2.5
700
600
500
400
300
200
0
100
-100
-200
-300
-400
0
-500
10
0
-600
20
10
-700
30
20
2
40
30
1.5
40
60
1
50
0.5
60
0
Population (%)
70
Population (%)
-100
-200
2
-300
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Offset Drift (V/C)
-400
0
-500
-700
0
0
-600
Population (%)
PGA gain = 1
PGA gain = 2
PGA gain = 4
90
Gain Drift (ppm/C)
30 units
30 units
Figure 5-19. Gain Error Distribution
Figure 5-20. Gain Drift Distribution
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5.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 4.096MHz, VREFP = 2.5V, VREFN = 0V, PGA
gain = 1, RS = 0Ω, VCM = 2.5V, and fDATA = 500SPS (unless otherwise noted)
100
100
PGA gain = 8
PGA gain = 16, 32 and 64
Buffer operation
90
80
90
80
50
30 units
0.1
0.09
30 units
Figure 5-21. Gain Drift Distribution
-105
Figure 5-22. Gain Match Distribution
-70
TA = -40C
TA = 25C
TA = 85C
-110
PGA gain = 1
PGA gain = 4
PGA gain = 16
Buffer operation
-80
-115
-90
THD (dB)
THD (dB)
0.08
Gain Match (%)
Gain Drift (ppm/C)
-120
-100
-125
-110
-130
-120
-135
-130
1
10
Gain (value = 1 represents buffer operation)
70
0
10
20
AVDD1 = 3.3V, fIN = 31.25Hz, VIN = –0.5dBFS
-105
30
40
50
60
70
Input Frequency (Hz)
80
90
100
fIN = 31.25Hz, VIN = –0.5dBFS
Figure 5-23. THD vs PGA Gain
Figure 5-24. THD vs Input Frequency
33
RS = 0
RS = 2 x 300
RS = 2 x 660
RS = 2 x 1000
-110
30
27
24
Population (%)
-115
THD (dB)
0.07
0
6
5
5.5
4
4.5
3
3.5
2
2.5
0
1.5
10
0
1
20
10
0
30
20
0.06
40
30
0.05
40
60
0.04
50
0.03
Population (%)
70
60
0.5
Population (%)
70
-120
-125
21
18
15
12
9
6
-130
3
5
4.6
4.2
3.8
3.4
3
2.6
2.2
70
1.8
1
10
Gain (0.5 value represents buffer operation)
1.4
1
0
-135
0.5
PGA Input Current Noise Density (pA/Hz)
fIN = 31.25Hz, VIN = –0.5dBFS
Figure 5-25. THD vs Source Impedance
14
Figure 5-26. PGA Input Current Noise Distribution
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5.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 4.096MHz, VREFP = 2.5V, VREFN = 0V, PGA
gain = 1, RS = 0Ω, VCM = 2.5V, and fDATA = 500SPS (unless otherwise noted)
20
800
AINP TA = -40C
AINP TA = 25C
AINP TA = 85C
10
AINN TA = -40C
AINN TA = 25C
AINN TA = 85C
400
-10
-20
-30
-40
-50
200
0
-200
-400
-60
-600
-70
-80
-2.5
AINP TA = -40C
AINP TA = 25C
AINP TA = 85C
600
Input Current (nA)
Input Current (nA)
0
AINN TA = -40C
AINN TA = 25C
AINN TA = 85C
-2
-1.5
-1 -0.5
0
0.5
1
Differential Input Voltage (V)
1.5
2
2.5
Figure 5-27. PGA Input Current vs Input Voltage
-800
-2.5
-2
-1.5
-1 -0.5
0
0.5
1
Differential Input Voltage (V)
1.5
2
2.5
Figure 5-28. Buffer Input Current vs Input Voltage
210
50
40
35
200
Population (%)
Reference Input Current (A)
45
205
195
30
25
20
15
190
10
185
5
230
220
210
205
200
195
80
190
60
185
20
40
Temperature (C)
180
0
175
-20
170
0
180
-40
Reference Input Current (A)
30 units
Figure 5-29. Reference Input Current vs Temperature
Figure 5-30. Reference Input Current Distribution
160
100
AVDD1 buffer operation
AVDD1 PGA operation
AVDD2
90
140
80
70
Population (%)
CMRR (dB)
120
100
60
50
40
30
80
20
1
0.9
0.8
0.7
0.6
0.5
0.4
1000000
0.3
100
1000
10000
100000
Common-Mode Input Frequency (Hz)
0.2
0
0.1
40
10
10
PGA gain = 1
Buffer operation
0
60
AVDD1, AVDD2 Supply Current (mA)
30 units
Figure 5-31. CMRR vs Common-Mode Input Frequency
Figure 5-32. Power-Supply Current Distribution
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5.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 4.096MHz, VREFP = 2.5V, VREFN = 0V, PGA
gain = 1, RS = 0Ω, VCM = 2.5V, and fDATA = 500SPS (unless otherwise noted)
140
AVDD1 buffer operation
AVDD1 PGA operation
AVDD2
1
120
100
0.8
PSRR (dB)
AVDD1, AVDD2 Current (mA)
1.2
0.6
0.4
60
40
0.2
0
-40
80
AVDD1
AVDD2
IOVDD
20
-20
0
20
40
Temperature (C)
60
0
10
80
Figure 5-33. Power-Supply Current vs Temperature
100
1000
10000
100000
Power Supply Frequency (Hz)
1000000
Figure 5-34. PSRR vs Power-Supply Frequency
0.35
IOVDD Current (mA)
0.3
0.25
0.2
0.15
0.1
100
500
Data Rate (SPS)
1000
2000
Figure 5-35. IOVDD Current vs Data Rate
16
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6 Parameter Measurement Information
6.1 Noise Performance
The ADS1288 is a low-power, low-noise, delta-sigma ADC operating on the principle of oversampling.
Oversampling averages the high-frequency data of the modulator to produce the final output data. Increasing the
oversampling ratio lowers the data rate, the corresponding signal bandwidth, and total noise by averaging more
samples from the modulator to yield one conversion result.
The gain of the PGA reduces noise when the noise value is referred to the input. With increased gain, dynamic
range performance decreases because the ratio of the input voltage range to the input-referred voltage noise
also decreases.
Dynamic range and input noise are equivalent parameters that describe the available resolution of the ADC.
Equation 1 derives dynamic range from the input-referred noise data:
Dynamic Range (dB) = 20×log
1.768 V
Gain × en
(1)
where:
•
en = Input-referred voltage noise (RMS)
Table 6-1 shows dynamic range and input-referred noise performance, tested with input source resistance (RS) =
0Ω. Noise data are at TA = 25°C and are representative of typical ADC performance. The data are the standard
deviation of 4096 consecutive ADC conversion results with the ADC inputs shorted, measured over the 0.413
× fDATA bandwidth. Because of the statistical nature of noise, repeated measurements can yield varying noise
performance results.
Table 6-1. Noise Performance (AVDD1 = 3.3V or 5V, RS = 0Ω)
DYNAMIC RANGE (dB)
GAIN
(1)
MODE
en, INPUT-REFERRED NOISE (μVRMS)
fDATA (SPS)
fDATA (SPS)
125
250
500
1000
2000
125
250
500
1000
2000
1
Buffer
128
125
122
119
116
0.70
0.99
1.4
2.0
2.8
1(1)
PGA
128
125
122
119
116
0.70
0.99
1.4
2.0
2.8
2
PGA
127
124
121
118
115
0.39
0.56
0.79
1.1
1.6
4
PGA
126
123
120
117
114
0.23
0.32
0.45
0.63
0.89
8
PGA
123
120
117
114
111
0.16
0.22
0.31
0.44
0.62
16
PGA
118
115
112
109
106
0.14
0.20
0.28
0.39
0.55
32
PGA
112
109
106
103
100
0.14
0.20
0.28
0.39
0.55
64
PGA
106
103
100
97
94
0.14
0.20
0.28
0.39
0.55
PGA gain = 1 dynamic range performance specified at AVDD1 = 5V.
7 Detailed Description
7.1 Overview
The ADS1288 is a high-resolution, low-power analog-to-digital converter (ADC) designed for applications
in energy exploration, geology, and seismic monitoring where low-power consumption and high resolution
are required. The output data resolution is 32 bits spanning data rates from 125SPS to 2000SPS. The
programmable gain amplifier (PGA) expands the system dynamic range with seven input ranges of ±2.5VPP
to ±0.039VPP.
As illustrated in the Functional Block Diagram, the ADC consists of the following sections: input multiplexer
(MUX), programmable gain amplifier (PGA), unity-gain buffer, delta-sigma (ΔΣ) modulator, sample rate
converter, infinite impulse response (IIR) high-pass filter (HPF), finite impulse response (FIR) low-pass filter
(LPF), and an SPI-compatible serial interface used for both device configuration and conversion data readback.
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The input multiplexer selects between inputs 1 and 2, and internal options designed for self-test, including an
input-short connection to test device offset and noise performance.
The input multiplexer is followed by a low-noise PGA. The range of PGA gains is 1 to 16, with gains 32 and 64
implemented as digital gains. The PGA is chopper-stabilized to reduce 1/f noise and input offset voltage. The
PGA output connects to a buffer which drives the modulator. An external 10nF capacitor, connected to PGA
output pins CAPP and CAPN, provides an antialias filter for the input signal.
Disable the PGA to lower device power consumption by operating the ADC with the unity-gain buffer. External
47nF capacitors connected to each buffer output filter the modulator sampling pulses.
The ΔΣ modulator measures the differential input signal (VIN) at the PGA output against the differential reference
voltage (VREF = 2.5V). Modulator data are processed by the digital filter to provide the final conversion result.
The digital filter consists of a sinc filter followed by a programmable phase, FIR low-pass filter, and an IIR
high-pass filter. The high-pass filter removes dc and low-frequency components from the data.
The sample rate converter (SRC) compensates clock signal error by resampling the output data to correct the
output data rate. Write the desired compensation value to the SRC register for data rate correction with up to
7ppb accuracy.
User-programmable gain and offset calibration registers correct offset and gain errors.
The SYNC pin synchronizes the ADC. Synchronization has two modes of operation: pulse synchronization and
continuous synchronization. The RESET pin resets the ADC, including user-configuration settings. The pins are
noise-resistant, Schmitt-trigger inputs to increase reliability in high-noise environments.
The PWDN pin powers down the ADC when not in use. The software power-down mode (STANDBY) is available
through the serial interface
The 4-wire, SPI-compatible, serial interface reads conversion data and reads or writes device register data.
Two general-purpose digital I/Os are available to control external switches for diagnostic tests.
Power for the PGA and buffer is supplied by pins AVDD1 and AVSS. A charge pump voltage regulator increases
the buffer supply voltage to increase input voltage range. Power for the modulator is supplied by the AVDD2 pin.
The digital I/O voltage pin (IOVDD) powers the digital logic core through a 1.8V low-dropout regulator (LDO).
7.2 Functional Block Diagram
CAPC CAPBP CAPBN AVDD2
AVDD1
1.8 V
(digital core)
Charge
Pump
AIN1P
AIN1N
MUX
AIN2P
BUF
PGA
CAPD
IOVDD
LDO
CLK
DRDY
Modulator
Sample
Rate
Converter
Digital
Filter
Serial
Interface
CS
SCLK
DOUT
DIN
Control
PWDN
RESET
SYNC
AIN2N
AVSS
GPIO
2 x 400
VCM
AGND
18
AVSS
CAPP CAPN
CAPI REFP REFN CAPR GPIO1 GPIO0
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7.3 Feature Description
7.3.1 Analog Input
Figure 7-1 shows the analog input circuit and input multiplexer.
AVDD1
S1
AIN1P
ESD Diodes
S2
(+)
AIN2P
400
S3
AVSS
To PGA
To Buffer
AVDD1 + AVSS
S7
2
AVDD1
400
S4
S5
(-)
AIN1N
ESD Diodes
S6
AIN2N
AVSS
Figure 7-1. Analog Input and Multiplexer
Electrostatic discharge (ESD) diodes are incorporated to protect the ADC inputs from ESD events that occur
during device manufacturing and printed circuit board (PCB) assembly process when assembled in an ESDcontrolled environment. For system-level protection, consider using external ESD protection devices to protect
the input that are exposed to ESD events.
If the inputs are driven below AVSS – 0.3V, or above AVDD1 + 0.3V, the protection diodes can conduct. If
these conditions are possible, use external clamp diodes, series resistors, or both to limit input current to the
specified maximum value. Overdriving an unused input channel can affect the conversion results of the active
input channel. Clamp the overdriven voltage with Schottky diodes to prevent channel crosstalk.
The ADC incorporates two differential input channels. The multiplexer selects between the two differential inputs
for measurement. A test mode to measure noise and offset is also provided by the multiplexer. The shorted input
test configuration is available with or without the 400Ω resistors to simulate the thermal noise generated by an
800Ω geophone. Table 7-1 summarizes the multiplexer configurations.
Table 7-1. Input Multiplexer Modes
MUX[2:0] BITS SWITCHES
DESCRIPTION
000
S1, S5
Input AIN1P, AIN1N connection.
001
S2, S6
Input AIN2P, AIN2N connection.
010
S3, S4
400Ω input-short test mode for offset and noise test.
011
S1, S5,S2, S6
Cross-connection test mode. Inputs AIN1P, AIN2P and AIN2P, AIN2N are connected.
100
—
Reserved
101
S3,S4,S7
0Ω input-short test mode for offset and noise test.
To test geophone THD performance, apply a test signal to the test channel through series resistors. The series
resistors are typically half the value of the geophone impedance. Select the multiplexer for the cross-connection
test mode (MUX[2:0] = 011b). In cross-connection mode, the test signal is cross-fed to the geophone input.
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Geophone THD test performance can be affected by the nonlinear on-resistance of the multiplexer (RSW). Figure
7-2 shows a model of the input multiplexer resistance for the geophone THD test. Figure 7-3 shows THD
performance versus a test resistor (RLOAD) used to simulate geophone resistance. Small amplitude test signals
(such as, VIN = 0.221V), shows less THD performance degradation for geophone resistance < 500Ω.
-100
½ RLOAD
Test
Signal
PGA gain = 1, VIN = 1.77 VRMS
PGA gain = 8, VIN = 0.221 VRMS
Input2
-105
½ RLOAD
RSW
RSW
THD (dB)
PGA
RSW
-110
-115
RSW
-120
RLOAD
Input1
-125
0
2000
4000
6000
Resistive Load ()
8000
10000
Figure 7-3. THD Performance vs RLOAD
Figure 7-2. THD versus RLOAD Test Circuit
7.3.2 PGA and Buffer
Figure 7-4 shows the simplified PGA and buffer block diagram.
4.7 nF
10 nF, C0G
AVDD1
CAPP
CAPN
AVDD1
CAPC
AGND
Charge
Pump
MUX(+)
+
CAPBP
47 nF, C0G
AVSS
GAIN[2:0] bits
of register CONFIG1
(address = 02h)
Buffer mode
GAIN[2:0] = 111b
Modulator
CAPBN
MUX(-)
+
47 nF, C0G
AVSS
AVSS
AVSS
Figure 7-4. PGA and Buffer Block Diagram
The device can be operated with the PGA or the unity-gain buffer. Buffer operation disables the PGA, reducing
device power consumption. Because of the limited input headroom for PGA gain = 1 when operating AVDD1 at
3.3V, the buffer must be used in this condition.
7.3.2.1 Programmable Gain Amplifier (PGA)
The PGA is a low-noise, chopper-stabilized differential amplifier that extends the ADC dynamic range
performance. The PGA provides analog gains from 1 to 16, with gains of 32 and 64 provided by digital scaling.
The PGA output signal is routed to the CAPP and CAPN pins through 270Ω resistors. Connect an external 10nF,
C0G-dielectric capacitor across these pins. An antialias filter is formed by these components to attenuate the
signal level at the modulator aliasing frequency (fMOD).
20
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As illustrated in Figure 7-4, the buffer is used between the PGA and the modulator. Connect two 47nF, C0Gdielectric capacitors from each buffer output to AVSS (CAPBP and CAPBN). A voltage charge pump increases
the buffer input voltage headroom. Connect an external 4.7nF capacitor between CAPC and AGND for charge
pump operation.
The PGA gain is programmed by the GAIN[2:0] bits of the CONFIG1 register. Table 7-2 shows the PGA gain
settings and buffer selection.
Table 7-2. PGA Gains
GAIN[2:0] REGISTER BITS
PGA GAIN
INPUT SIGNAL RANGE (VPP)
000
1
±2.5
001
2
±1.25
010
4
±0.625
011
8
±0.3125
100
16
±0.15625
101
32
±0.078125
110
64
±0.0390625
111
Buffer mode, gain = 1
±2.5
Observe the PGA input and output voltage headroom specification. Figure 7-5 shows the input and output
voltage headroom when operating with AVDD1 = 5V, an input common-mode voltage (VCM) = 2.5V, a differential
input voltage = ±2.5VPP, and at gain = 1. The absolute minimum and maximum PGA input voltages (1.25V and
3.75V) are ±1/2 of the differential signal voltage plus the common-mode voltage. The PGA provides 0.15V input
voltage margin at the negative peak and 0.4V input voltage margin at the positive peak. The PGA provides 1.1V
output voltage margin at the positive and negative peaks.
PGA Input Headroom
PGA Output Headroom
AVDD1
AVDD1 - 0.15 V
AVDD1
AVDD1 - 0.85 V
VCM + 1.25 V
VCM + 1.25 V
VCM = 2.5 V
VCM - 1.25 V
VCM - 1.25 V
AVSS + 1.1 V
AVSS + 0.15 V
AVSS
AVSS
Figure 7-5. PGA Headroom (AVDD1 = 5V, Gain = 1)
When operating with AVDD1 = 3.3V, the PGA cannot support ±2.5VPP input signals. Use the buffer for ±2.5VPP
input signals. For ±1.25VPP input signals (PGA gain = 2), the input headroom is increased by increasing the
common-mode voltage by 0.1V to AVSS + 1.75V. Figure 7-6 shows the input and output operating headroom for
AVDD1 = 3.3V, VCM = 1.75V, input signal = ±1.25VPP, and gain = 2.
PGA Input Headroom
PGA Output Headroom
AVDD1
AVDD1 - 0.15 V
VCM + 1.25 V
AVDD1
AVDD1 - 0.85 V
VCM + 0.6125 V
VCM = 1.75 V
VCM - 0.6125 V
AVSS + 1.1 V
VCM - 1.25 V
AVSS + 0.15 V
AVSS
AVSS
Figure 7-6. PGA Headroom (AVDD1 = 3.3V, Gain = 2)
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7.3.2.2 Buffer Operation (PGA Bypass)
The ADC provides a buffer option, bypassing the PGA. The PGA is powered-down in buffer mode. Use the
buffer for ±2.5VPP input signals when operating AVDD1 at 3.3V. Buffer operation is enabled by setting the
GAIN[2:0] bits = 111b of the CONFIG1 register.
Figure 7-7 shows the buffer voltage headroom with AVDD1 = 3.3V, VCM = 1.65V, and the input signal = ±2.5VPP.
The buffer has sufficient voltage headroom for ±2.5VPP input signals when operating with AVDD1 = 3.3V.
AVDD1
AVDD1 - 0.1 V
VCM + 1.25 V
Buffer Input Headroom
Buffer Output Headroom
AVDD1
AVDD1 - 0.1 V
VCM + 1.25 V
VCM = 1.65 V
VCM - 1.25 V
AVSS + 0.1 V
AVSS
VCM - 1.25 V
AVSS + 0.1 V
AVSS
Figure 7-7. Buffer Headroom (3.3V Operation Shown)
Regardless of PGA or buffer operation, connect two 47nF, C0G-dielectric capacitors from each buffer output to
AVSS (CAPBP and CAPBN). The voltage charge pump increases the buffer input operating headroom. Connect
an external 4.7nF capacitor between CAPC and AGND for the charge pump operation.
7.3.3 Voltage Reference Input
The ADC requires a reference voltage for operation. The reference voltage input is differential, defined as the
voltage between the REFP and REFN pins: VREF = VREFP – VREFN. Because of the differential input, route
the VREFN trace to the voltage reference ground terminal to avoid ground noise pickup. Use a precision 2.5V
voltage reference with low noise, optimally less than 2μVRMS over the measurement bandwidth.
Figure 7-8 shows the simplified reference input circuit. Similar to the analog inputs, the reference inputs are
protected by ESD diodes. If the reference inputs are driven below AVSS – 0.3V or above AVDD1 + 0.3V, the
protection diodes can conduct. If these conditions are possible, use external clamp diodes, series resistors, or
both to limit the reference input current to the specified value.
AVDD1
CREF
REFP
REFN
AVSS
Figure 7-8. Simplified Voltage Reference Input Circuit
The ADC samples the reference voltage by an internal capacitor (CREF) and then discharges the capacitor at the
modulator sampling frequency (fMOD). The sampling operation results in transient current flow into the reference
inputs. The transient current is filtered by a 0.1µF ceramic capacitor placed directly at the reference pins with a
larger 10μF to 47μF capacitor at the voltage reference output. In applications where the voltage reference drives
multiple ADCs, use 0.1µF capacitors at each ADC.
22
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The external capacitors filter the current transients, resulting in 80μA/V average reference current. With VREF =
2.5V, the reference input current is 80μA / V × 2.5V = 200μA.
7.3.4 IOVDD Power Supply
The IOVDD digital supply operates in two voltage ranges: 1.65V to 1.95V and 2.7V to 3.6V. If operating IOVDD
in the 1.65V to 1.95V range, connect IOVDD directly to the CAPD pin. Figure 7-9 shows the required connection
if IOVDD is operating in the 1.65V to 1.95V range. Otherwise, if operating IOVDD in the 2.7V to 3.6V range, do
not connect these pins together.
1.65 V to 1.95 V
2.7 V to 3.6 V
IOVDD
Connect IOVDD to CAPD if IOVDD 1.65 V to 1.95 V.
Otherwise, do not connect these pins together.
CAPD
Figure 7-9. IOVDD Power-Supply Connection
7.3.5 Modulator
The modulator is a multibit delta-sigma architecture featuring low power consumption with very low levels of
spurious tones in the output. The modulator shapes the quantization noise of the internal quantizer to an out-ofband frequency range where the noise is removed by the digital filter. Noise remaining within the pass-band
region is thermal, with the characteristic of constant noise density (white noise). The total noise in the ADC
output is determined by the digital filter OSR.
7.3.5.1 Modulator Overdrive
The modulator is an inherently stable design and, therefore exhibits predictable recovery from input overdrive.
If the modulator is overdriven at the peaks of the input signal, the filter output data can clip, but not necessarily
so depending on the duration of the signal overdrive resulting from data averaging of the digital filter. If the
modulator is heavily overdriven, then the likelihood of clipped conversion data in the output increases. Be aware
the group delay of the digital filter delays the time of an input overdrive event to the output data.
7.3.6 Digital Filter
The digital filter decimates and filters the modulator data to provide high-resolution output data. By adjusting
the amount of filtering though the OSR, trade-offs can be made between output data noise and bandwidth.
Increasing the OSR reduces output data noise while decreasing the signal bandwidth.
As shown in Figure 7-10, the sample rate converter (SRC) receives data from the modulator prior to the digital
filter block. See the Sample Rate Converter section for details.
SRC
SWBypass
IIR Bypass
SW
Final Output Data
From Modulator
SRC
Sinc Filter
Variable decimation
(8 to 128)
FIR Filter
Fixed decimation
(32)
IIR Filter
No decimation
User calibration
and code clip
FILTR[1:0] bits 1,0 CONFIG0
(register address = 01h)
00: Reserved
01: Sinc filter
10: FIR filter (default)
11: FIR and IIR filter
Figure 7-10. Digital Filter Block Diagram
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The digital filter consists of three sections: a variable-decimation sinc filter; a variable-coefficient, fixeddecimation FIR filter; and a programmable high-pass filter (IIR). The desired filter sections are selected by
the FILTER[1:0] bits of the CONFIG0 register. The sinc filter provides partially filtered data, bypassing the FIR
and HPF filters and the user calibration stage. For fully filtered data, select the FIR filter option. The IIR filter
stage removes dc and low-frequency data. The FIR and the combined FIR + IIR filter are routed to the user
calibration block and output code clipping block. See the Offset and Gain Calibration section for details of user
calibration.
7.3.6.1 Sinc Filter Section
The first section of the digital filter is a variable-decimation, fifth-order sinc filter (sinx/x). Modulator data are
passed through the sample rate converter to the sinc filter at the nominal rate of fMOD = fCLK / 4 = 1.024MHz.
The sinc filter partially filters the data for the FIR filter that produces the final frequency response. The sinc filter
output data are intended to be used with post-processing filters to shape the final frequency response.
Table 7-3 shows the decimation ratio and the resulting output data rate of the sinc filter. The sinc filter data rate is
programmed by the DR[2:0] bits of the CONFIG0 register.
Table 7-3. Sinc Filter Data Rates
DR[2:0] BITS
SINC DECIMATION RATIO (N)
DATA RATE (SPS)
000
256
4,000
001
128
8,000
010
64
16,000
011
32
32,000
100
16
64,000
Equation 2 shows the Z-domain transfer function of the sinc filter.
5
1 - Z-N
H(Z) =
-1
N(1 - Z )
(2)
where:
•
N = Decimation ratio of Table 7-3
Equation 3 shows the frequency domain transfer function of the sinc filter.
5
sin
½H(f)½ =
N sin
pN ´ f
fMOD
p´f
fMOD
(3)
where:
•
•
•
24
N = Decimation ratio shown in Table 7-3
f = Input signal frequency
fMOD = Modulator sampling frequency = fCLK / 4 (sample rate converter disabled)
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The sinc filter frequency response has notches (or zeros) occurring at the output data rate and multiples thereof.
At these frequencies, the filter has zero gain. Figure 7-11 shows the wide-band frequency response of the sinc
filter and Figure 7-12 shows the –3dB response.
0
0
-20
-0.5
-40
Gain (dB)
Gain (dB)
-1.0
-60
-80
-1.5
-2.0
-100
-2.5
-120
-140
-3.0
0
1
2
3
4
Normalized Frequency (fIN/fDATA)
5
0
0.05
0.10
0.15
0.20
Normalized Frequency (fIN/fDATA)
Figure 7-11. Sinc Filter Frequency Response
Figure 7-12. Sinc Filter –3dB Response
Figure 7-13 shows the sinc filter frequency response at fDATA = 32kSPS. The tones at 1kHz and harmonics are
the result of dither added to the modulator input to suppress idle tones. The frequency of the dither signal is
fMOD divided by the combined decimation ratio from Table 7-4. The rise of the noise floor at 2kHz is resultant of
modulator noise shaping. For sinc filter decimation N = 32 (data rate = 32kSPS), the usable bandwidth through
the use of external post filtering is 500Hz.
0
-20
Amplitude (dB)
-40
-60
-80
-100
-120
-140
-160
-180
0
2
4
6
8
10
Frequency (kHz)
12
14
16
Figure 7-13. FFT Output of the Sinc Filter (fDATA = 32kSPS)
The sinc filter data bypasses the data scaling, clip stage, and user calibration stages, and as a result, the sinc
filter data are scaled differently compared to the FIR filter data. See the Conversion Data Format section for
details of sinc filter data scaling.
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7.3.6.2 FIR Filter Section
The second section of the digital filter is a multistage, FIR low-pass filter. Partially filtered data from the sinc filter
are input to the FIR filter. The FIR filter determines the final frequency and phase response of the output data.
Figure 7-14 shows that the FIR filter consists of four stages.
From sinc filter
FIR Filter 1
2
FIR Filter 2
2
FIR Filter 3
4
FIR Filter 4
2
To user calibration
PHASE bit 2 of CONFIG0
(register address = 01h)
0: Linear phase coefficients (default)
1: Minimum phase coefficients
Figure 7-14. FIR Filter
The first two FIR stages are half-band filters with decimation = 2 in each stage. The third and fourth FIR
stages determine the final frequency and phase response. Decimation is 4 and 2, in stages three and four. The
total decimation ratio of the FIR filter is 32. Different filter coefficient sets in stage 3 and 4 determine linear or
minimum phase filter response. The phase response is selected by the PHASE bit of the CONFIG0 register.
Table 7-4 lists the combined decimation ratio of the sinc and FIR filter stages and the corresponding FIR filter
data rate.
Table 7-4. FIR Filter Data Rate
DR[2:0] BITS
COMBINED DECIMATION RATIO
DATA RATE (SPS)
000
8192
125
001
4096
250
010
2048
500
011
1024
1000
100
512
2000
Table 7-5 lists the FIR filter coefficients and the data scaling for the linear and minimum phase coefficients.
Table 7-5. FIR Filter Coefficients
COEFFICIENT
26
STAGE 1
STAGE 2
STAGE 3
STAGE 4
SCALE = 1/512
SCALE = 1/8388608
SCALE = 1/134217728
SCALE = 1/134217728
LINEAR PHASE
LINEAR PHASE
LINEAR PHASE
MINIMUM PHASE
LINEAR PHASE
b0
3
–10944
0
819
–132
11767
b1
0
0
0
8211
–432
133882
b2
–25
103807
–73
44880
–75
769961
b3
0
0
–874
174712
2481
2940447
b4
150
–507903
–4648
536821
6692
8262605
b5
256
0
–16147
1372637
7419
17902757
b6
150
2512192
–41280
3012996
–266
30428735
b7
0
4194304
–80934
5788605
–10663
40215494
b8
–25
2512192
–120064
9852286
–8280
39260213
b9
0
0
–118690
14957445
10620
23325925
b10
3
–507903
–18203
20301435
22008
–1757787
b11
0
224751
24569234
348
–21028126
b12
103807
580196
26260385
–34123
–21293602
b13
0
893263
24247577
–25549
–3886901
b14
–10944
891396
18356231
33460
14396783
b15
293598
9668991
61387
16314388
b16
–987253
327749
–7546
1518875
b17
–2635779
–7171917
–94192
–12979500
b18
–3860322
–10926627
–50629
–11506007
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Table 7-5. FIR Filter Coefficients (continued)
COEFFICIENT
STAGE 1
STAGE 2
STAGE 3
STAGE 4
SCALE = 1/512
SCALE = 1/8388608
SCALE = 1/134217728
SCALE = 1/134217728
LINEAR PHASE
LINEAR PHASE
LINEAR PHASE
MINIMUM PHASE
LINEAR PHASE
b19
–3572512
–10379094
101135
MINIMUM PHASE
2769794
b20
–822573
–6505618
134826
12195551
b21
4669054
–1333678
–56626
6103823
b22
12153698
2972773
–220104
–6709466
b23
19911100
5006366
–56082
–9882714
b24
25779390
4566808
263758
–353347
b25
27966862
2505652
231231
8629331
b26
25779390
126331
–215231
5597927
b27
19911100
–1496514
–430178
–4389168
b28
12153698
–1933830
34715
–7594158
b29
4669054
–1410695
580424
–428064
b30
–822573
–502731
283878
6566217
b31
–3572512
245330
–588382
4024593
b32
–3860322
565174
–693209
–3679749
b33
–2635779
492084
366118
–5572954
b34
–987253
231656
1084786
332589
b35
293598
–9196
132893
5136333
b36
891396
–125456
–1300087
2351253
b37
893263
–122207
–878642
–3357202
b38
580196
–61813
1162189
–3767666
b39
224751
–4445
1741565
1087392
b40
–18203
22484
–522533
3847821
b41
–118690
22245
–2490395
919792
b42
–120064
10775
–688945
–2918303
b43
–80934
940
2811738
–2193542
b44
–41280
–2953
2425494
1493873
b45
–16147
–2599
–2338095
2595051
b46
–4648
–1052
–4511116
–79991
b47
–874
–43
641555
–2260106
b48
–73
214
6661730
–963855
b49
0
132
2950811
1482337
b50
0
33
–8538057
1480417
b51
0
0
–10537298
–586408
b52
9818477
–1497356
b53
41426374
–168417
b54
56835776
1166800
b55
41426374
644405
b56
9818477
–675082
b57
–10537298
–806095
b58
–8538057
211391
b59
2950811
740896
b60
6661730
141976
b61
641555
–527673
b62
–4511116
–327618
b63
–2338095
278227
b64
2425494
363809
b65
2811738
–70646
b66
–688945
–304819
b67
–2490395
–63159
b68
–522533
205798
b69
1741565
124363
b70
1162189
–107173
b71
–878642
–131357
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Table 7-5. FIR Filter Coefficients (continued)
COEFFICIENT
28
STAGE 1
STAGE 2
STAGE 3
STAGE 4
SCALE = 1/512
SCALE = 1/8388608
SCALE = 1/134217728
SCALE = 1/134217728
LINEAR PHASE
LINEAR PHASE
LINEAR PHASE
MINIMUM PHASE
LINEAR PHASE
MINIMUM PHASE
b72
–1300087
31104
b73
132893
107182
b74
1084786
15644
b75
366118
–71728
b76
–693209
–36319
b77
–588382
38331
b78
283878
38783
b79
580424
–13557
b80
34715
–31453
b81
–430178
–1230
b82
–215231
20983
b83
231231
7729
b84
263758
–11463
b85
–56082
–8791
b86
–220104
4659
b87
–56626
7126
b88
134826
–732
b89
101135
–4687
b90
–50629
–976
b91
–94192
2551
b92
–7546
1339
b93
61387
–1103
b94
33460
–1085
b95
–25549
314
b96
–34123
681
b97
348
16
b98
22008
–349
b99
10620
–96
b100
–8280
144
b101
–10663
78
b102
–266
–46
b103
7419
–42
b104
6692
9
b105
2481
16
b106
–75
0
b107
–432
–4
b108
–132
0
b109
0
0
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2.0
20
1.5
0
1.0
-20
Magnitude (dB)
Magnitude (mdB)
Figure 7-15 shows the FIR pass-band frequency response to 0.375 × fDATA with ±0.003dB pass-band ripple.
Figure 7-16 shows the pass-band, transition-band, and stop-band performance from 0Hz to fDATA. The filter is
designed for –135dB stop-band attenuation at the Nyquist frequency.
0.5
0
-0.5
-1.0
-40
-60
-80
-100
-120
-1.5
-140
-2.0
-160
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0
0.1
Normalized Input Frequency (fIN/fDATA)
Figure 7-15. FIR Filter Pass-Band Response
0.2 0.3 0.4 0.5 0.6 0.7 0.8
Normalized Input Frequency (fIN/fDATA)
0.9
1.0
Figure 7-16. FIR Filter Transition Band Response
As with many sampled systems, the filter response repeats at multiples of the modulator sample rate (fMOD). The
filter response repeats at frequencies = N × fMOD ± f0, where N = 1, 2, and so on, and f0 = filter pass-band). If
present in the signal, these frequencies fold back (or alias) into the pass-band, causing errors. A low-pass input
filter at the input removes the out-of-band signal to reduce the aliasing error. For the low-frequency output signal
typical of many geophones, a single-pole filter at the PGA output is sufficient to reduce aliasing of the geophone
thermal noise.
7.3.6.3 Group Delay and Step Response
The FIR filter offers linear and minimum phase filter options. The pass-band, transition band, and stop-band
responses of the linear and minimum phase filters are the same but differ in phase and step response behavior.
7.3.6.3.1 Linear Phase Response
A linear phase filter has the unique property that the delay from input to output is constant across all input
frequencies (that is, constant group delay). The constant delay property is independent of the nature of the input
signal (impulse or swept-tone), and therefore the phase is linear across frequency, which can be important when
analyzing multitone signals. However, as shown in Figure 7-17, the group delay is longer for the linear phase
filter compared to minimum phase. For both the linear and minimum filters, fully settled data are available 62
conversions after a step input change occurs.
1.4
Minimum Phase Filter
1.2
Amplitude (dB)
1.0
0.8
0.6
0.4
0.2
Linear Phase Filter
0
-0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Time Index (1/fDATA)
Figure 7-17. FIR Step Response
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7.3.6.3.2 Minimum Phase Response
The minimum phase filter provides a short group delay for data from filter input to filter output. Figure 7-18 shows
the group delay for minimum and linear phase filters. The group delay of the minimum phase filter is a function of
signal frequency. The PHASE bit of the CONFIG0 register programs the filter phase.
35
Linear Phase Filter
Group Delay (1/fDATA)
30
25
20
15
10
Minimum Phase Filter
5
0
20
40
60
80 100 120
Frequency (Hz)
140 160 180
200
Figure 7-18. FIR Group Delay (fDATA = 500SPS)
7.3.6.4 HPF Stage
The last stage of the digital filter is the high-pass filter (HPF). The high-pass filter is implemented as a firstorder IIR filter. The high-pass filter removes dc and low frequencies from the data. The HPF is enabled by
programming the FILTR[1:0] bits = 11b of the CONFIG0 register.
Equation 4 shows the z-domain transfer function of the filter:
H(z) =
2-a
1 - z-1
2 1 - (1 - a)z-1
(4)
where:
a=
•
•
•
•
2sin(&N)
cos(&N) + sin(&N)
ωN = π × fC / fDATA (normalized corner frequency, radians)
fC = Corner frequency (Hz)
fDATA = Output data rate (Hz)
Be aware the corner frequency programming is a function of fDATA. As shown by Equation 5, the value written to
the HPF1, HPF0 registers is value a, computed by Equation 4, × 216.
HPF[15:0] = a × 216
(5)
Table 7-6 shows examples of the high-pass filter programming.
Table 7-6. High-Pass Filter Value Examples
30
HPF[15:0]
fC (Hz)
fDATA (SPS)
0332h
0.5
250
0332h
1.0
500
019Ah
1.0
1000
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The HPF accumulates data to perform the high-pass function. Similar to the operation of an analog HPF after a
dc step change is applied to the input, the filter takes time to accumulate data to remove dc from the signal. The
lower the corner frequency, the longer the filter takes to settle.
To shorten the HPF settling time, the offset register is used as a seed value for the HPF accumulator. The
accumulator is loaded with the offset register each time the HPF state is changed from disabled to enabled. The
offset register can be preset with an estimated value, or a calibrated value if the dc level is known. To improve
accuracy, scale the offset value by the inverse value of GAIN[3:0] / 400000h. The normal offset operation is
disabled when the HPF is enabled.
To initialize the HPF accumulator with the OFFSET[2:0] registers:
1. Disable the HPF.
2. Write the desired value to the OFFSET[2:0] registers.
3. Enable the HPF. OFFSET[2:0] is loaded to the HPF data accumulator.
4. The HPF tracks the remaining dc value from the signal.
Subsequent writes to the OFFSET[2:0] registers are ignored. To reload the contents of the OFFSET[2:0]
registers to the HPF, disable and re-enable the HPF.
7.3.7 Clock Input
A clock signal is required for operation. The clock signal is applied to the CLK pin at 4.096MHz. As with many
precision data converters, a low-jitter clock is required to achieve data sheet performance. Avoid the use of R-C
clock oscillators. A crystal-based clock source is recommended. Avoid ringing on the clock signal by placing a
series resistor in the clock PCB trace to source-terminate. Keep the clock signal routed away from other clock
signals, input pins, and analog components.
7.3.8 GPIO
The ADC provides two general-purpose I/O (GPIO) pins that can be used as digital inputs or outputs. The GPIO
voltage levels are IOVDD and DGND. Figure 7-19 illustrates the GPIO block diagram.
The GPIOs are programmed by the GPIO register. The GPIOs are programmed as an input or output by the
GPIOx_DIR bits. The GPIO state is read or written by the GPIOx_DAT bits. When programmed as an output,
reading the GPIOx_DAT bits returns the register bit value previously written. If the GPIOs are unused, terminate
the GPIOs with pulldown resistors to prevent the pins from floating.
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IOVDD
GPIO0_DIR bit 1 of GPIO
(register address = 0Bh)
0: GPIO0 is an input (default)
1: GPIO0 is an output
Write
SW
GPIO0_DAT bit 3 of GPIO
(register address = 0Bh)
0: GPIO0 data is low
1: GPIO0 data is high
GPIO0
100 k
Read
GPIO1_DIR bit 2 of GPIO
(register address = 0Bh)
0: GPIO1 is an input (default)
1: GPIO1 is an output
Write
SW
GPIO1_DAT bit 4 of GPIO
(register address = 0Bh)
GPIO0
0: GPIO1 data is low
1: GPIO1 data is high
100 k
Read
Read
DGND
Figure 7-19. GPIO Operation
7.4 Device Functional Modes
7.4.1 Power-Down Mode
Power-down is engaged by taking the PWDN pin low, or by software control, by sending the STANDBY
command. To exit power-down, take PWDN high or send the WAKEUP command to exit software power-down
(with the clock running). Power-down disables the analog circuit; however, the digital LDO (CAPD pin) remains
biased, drawing a small bias current from IOVDD. In comparison, software power-down draws larger IOVDD
bias current. In both power-down modes, the ac signals of the digital outputs are stopped but remain driven
high or low. The digital inputs must not be allowed to float; otherwise, leakage current can flow from the
IOVDD supply. Reset the ADC if the clock is interrupted in power-down. Synchronization is lost in power-down;
therefore, resynchronize the ADC.
7.4.2 Reset
The ADC is reset by three methods: power-on reset (POR), the RESET pin, or the RESET command. Power-on
reset occurs when the power-supply voltages cross the respective thresholds. See the Power-Up Switching
Characteristics for details. To reset the ADC by pin, drive RESET low for at least two fCLK cycles and return high
for reset. By command, reset takes effect on the next rising fCLK edge after the eighth rising edge of SCLK of
the reset command. At reset, the filter is restarted and the user registers are reset to default. Reset timing is
illustrated in Figure 5-5.
7.4.3 Synchronization
The ADC is synchronized by the SYNC pin or by the SYNC command, resulting in restart of the digital filter
cycle. Synchronization by the pin occurs on the next rising edge of CLK after SYNC is taken high on the falling
edge of CLK. Synchronization by the SYNC command occurs on the rising edge of CLK following the eighth bit
of the command.
The following results in loss of synchronization:
•
•
•
32
When a power-up cycle or ADC reset occurs
When the hardware or software power-down modes are entered
The following register mode changes occur:
– DR[2:0] (data rate)
– PHASE (filter phase)
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– SYNC (synchronization mode)
– SRC[1:0] (sample rate converter enabled or disabled)
There are two synchronization control modes: pulse sync and continuous sync. The synchronization mode is
programmed by the SYNC bit of the ID/SYNC register.
7.4.3.1 Pulse-Sync Mode
Pulse-sync mode unconditionally synchronizes the ADC on the rising edge of SYNC. When synchronized, the
internal filter memory is reset, DRDY goes high, and the filter cycle restarts. The following 63 DRDY periods are
disabled to allow for digital filter settling. DRDY asserts low when the conversion data are ready. See Figure 5-4
for synchronization timing details.
7.4.3.2 Continuous-Sync Mode
Continuous-sync mode offers the option of accepting a continuous clock signal on the SYNC pin. The ADC
compares the period of the SYNC clock signal to N periods of the DRDY signal to qualify resynchronization.
Initially, the first SYNC positive edge synchronizes the ADC. Resynchronization occurs only when the time
period between rising edges of SYNC over N multiple DRDY periods differ by at least ± one fCLK cycle, where
N = 1, 2, 3, and so on. Otherwise, the SYNC clock period is in synchronization with the existing DRDY pulses,
so no resynchronization occurs. Be aware the continuous sync mode cannot be used when the sample rate
converter is enabled.
After synchronization, DRDY continues to pulse; however, data are held low for 63 data periods to allow for the
digital filter to settle. See Figure 5-4 for the DRDY behavior. Because of the initial delay of the digital filter, the
SYNC input signal and the DRDY pulses exhibit an offset time. The offset time is a function of the data rate.
7.4.4 Sample Rate Converter
The sample rate converter (SRC) compensates clock frequency error by resampling the modulator data at a
new rate set by a compensation factor written to the SRC registers. The compensation range is ±244ppm with
7.45ppb (1 / 227) resolution.
Clock frequency error is compensated by writing a value to the SCR0 and SRC1 registers. The register value is
in two's-complement format for positive and negative error compensation. Positive register data values decrease
the data rate frequency (increases the period). The compensated data rate frequency is observed by the
frequency of the DRDY signal.
Table 7-7 shows example values of SRC compensation. 8000h disables the sample rate converter. 0000h
passes the data through with no compensation but adds an 8 / fCLK delay to the existing time delay of SYNC
input to the DRDY pulses.
Table 7-7. Example SRC Compensation Values
SRC[15:0] VALUE
COMPENSATION FACTOR
7FFFh
(1 – 32,767 / 227) × fDATA
0001h
(1 – 1 / 227) × fDATA
0000h
1 × fDATA
7FFFh
(1 + 1 / 227) × fDATA
8001h
(1 + 32,767 / 227) × fDATA
8000h
1 × fDATA (SRC disabled)
Resynchronize the ADC after the sample rate converter is enabled or disabled.
Because the SRC is a digital function, operation is deterministic without error. When the target compensation
value is determined, the value can be immediately written to the ADC, or incrementally written up to the
determined value to reduce the effect of step changes in the output frequency. Because two bytes are used for
the SRC registers, use the multibyte command operation to write to the SRC registers and complete the write
operation 256 CLK cycles before the DRDY falling edge. This procedure simultaneously loads the high and low
bytes for compensation. See Figure 5-7 for details.
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7.4.5 Offset and Gain Calibration
The ADC integrates calibration registers to correct offset and gain errors. As shown in Equation 6 and Figure
7-20, the 24-bit offset value (OFFSET[23:0]) is subtracted from the filter data before multiplication by the 24-bit
gain value (GAIN[23:0]), divided by 400000h. The data are clipped to 32 bits to yield the final output. The offset
operation is bypassed when the high-pass filter is enabled.
Output = (Input - OFFSET[23:0])
GAIN[23:0]
400000h
(6)
offset bypassed in HPF mode
from digital filter
+
SW
output data
clipped to 32 bits
X
final output
OFFSET[23:0]
GAIN[23:0]
400000h
Figure 7-20. Calibration Block Diagram
7.4.5.1 OFFSET Register
Offset correction is by a 24-bit word consisting of three 8-bit registers (high address is the MSB). The offset
value is left-justified to align to the 32-bit data. The offset value is two's-complement coding with a maximum
positive value of 7FFFFFh and a maximum negative value of 800000h. As given in Table 7-8, OFFSET is
subtracted from the conversion data. Offset error is corrected by the offset calibration command with the
input-short multiplexer option, or by collecting shorted-input ADC data and writing the value to the registers.
Although the offset correction range is from –FS to +FS, the sum of offset and gain correction must not exceed
106% of the uncalibrated range.
When the high-pass filter is enabled, offset correction is disabled. The offset value is used instead as a starting
value to shorten the high-pass filter settling time. To reload the offset value to the HPF, disable and re-enable the
high-pass filter. See the HPF Stage section for more details.
Table 7-8. Offset Calibration Values
(1)
OFFSET[31:0]
CALIBRATED OUTPUT CODE (1)
00007Fh
FFFF8100h
000000h
00000000h
FFFF7Fh
00008100h
Ideal code value with no offset error.
7.4.5.2 GAIN Register
Gain correction is through a 24-bit word, consisting of three 8-bit registers (high address = MSB). The gain value
is 24 bits, coded in straight binary and normalized to 1.0 for GAIN[23:0] equal to 400000h. With a calibration
signal applied, gain error is calibrated by either the gain calibration command, or by collecting ADC data and
writing a computed value to the gain registers. Table 7-9 lists examples of the GAIN[23:0] register values.
Although the range of gain values can be much greater or less than 1, the sum of offset and gain correction must
not exceed 106% of the uncalibrated range.
Table 7-9. Gain Calibration Values
34
GAIN[31:0]
GAIN CORRECTION FACTOR
433333h
1.05
400000h
1.00
3CCCCCh
0.95
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7.4.5.3 Calibration Procedure
ADC calibration is performed by ADC calibration commands or manual calibration. The calibration procedure is
as follows:
1. Select the PGA or buffer operation, input channel, and PGA gain condition for calibration.
2. Preset the OFFSET register = 000000h and the GAIN register = 400000h.
3. Disable the high-pass filter for offset calibration. Short the inputs to the system, or use the input MUX to
provide the input short. A system-level input short yields more accurate calibration. After the input settles,
either send the OFSCAL command or perform a manual calibration.
a. OFSCAL command. After the command is sent, DRDY is driven low 81 conversion periods later to
indicate calibration is complete. The OFFSET register is updated with the new calibration value. As
shown in Figure 7-21, the first data output uses the new OFFSET value.
b. Manual calibration. Wait at least 64 conversions for the digital filter to settle then average a number of
data points to improve calibration accuracy. Write the value to the 24-bit OFFSET register.
4. Apply a gain calibration voltage. After the input settles, either send the GANCAL command or perform a
manual calibration.
a. GANCAL command. Apply a positive dc full-scale calibration voltage. After the command is sent, DRDY
is driven low 81 conversion periods later to indicate calibration is complete. The ADC calculates GAIN
such that the full-scale code is equal to the applied calibration signal. As shown in Figure 7-21, the first
data output uses the new GAIN value.
b. Manual calibration. Apply an ac signal coherent to the sample rate or dc calibration signal that are
slightly below full-scale (for example, 2.4V for gain = 1). Using a calibration signal less than the full-scale
range prevents clipped output codes that otherwise lead to incorrect calibration. Wait 64 conversions
for the digital filter to settle then average a number of data points to improve calibration accuracy. For
ac-signal calibration, use a number of coherent signal periods to compute the RMS value.
Equation 7 computes the value of GAIN for manual calibration.
GAIN[23:0] = 400000K Â
Expected Output Code
Actual Output Code
DRDY
(7)
81 conversion periods
CS
8
SCLK
DIN
DOUT
CAL Command
00h
Figure 7-21. Calibration Command
7.5 Programming
7.5.1 Serial Interface
Conversion data are read and ADC configuration is made through the SPI-compatible serial interface. The
interface consists of four signals: CS, SCLK, DIN, and DOUT. DRDY asserts low when conversion data are
ready. The serial interface is passive (peripheral mode), where the serial clock (SCLK) is an input. The ADC
operates in SPI mode 0, where CPOL = 0 and CPHA = 0. In mode 0, SCLK idles low and data are updated on
the SCLK falling edges and are read on the SCLK rising edges.
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7.5.1.1 Chip Select (CS)
CS is an active-low input that selects the serial interface for communication. A communication frame is started
by taking CS low and is ended by taking CS high. Because only one command per frame is permitted, toggle CS
between commands. Taking CS high before the command is completed resets the operation and blocks further
SCLK inputs. CS high forces DOUT to a high-impedance state. DRDY remains active regardless of the state of
CS.
7.5.1.2 Serial Clock (SCLK)
SCLK is the serial clock input that shifts data into and out of the ADC. The ADC latches DIN data on the rising
edge of SCLK. DOUT data are shifted out on the falling edge of SCLK. Keep SCLK low when not active. The
SCLK pin is a Schmidt-trigger input that reduces sensitivity to SCLK noise. However, keep the SCLK signal as
noise free as possible to prevent inadvertent shifting of the data.
7.5.1.3 Data Input (DIN)
DIN inputs data to the ADC. DIN data are latched on the rising edge of SCLK.
7.5.1.4 Data Output (DOUT)
DOUT is the data output pin. Data are shifted out on the falling edge of SCLK and are latched by the host on
the rising edge. Because the conversion data MSB is on DOUT when CS is driven low (DRDY low), the MSB of
the data is read on the first rising edge of SCLK. Minimize trace length to reduce load capacitance on the pin.
Place a series termination resistor close to the pin to terminate the PCB trace impedance. Taking CS high forces
DOUT to a high-impedance state.
7.5.1.5 Data Ready (DRDY)
DRDY is an active-low output that indicates conversion data are ready. DRDY is active regardless of the state of
CS. DRDY is driven high on the first falling edge of SCLK, regardless if data are being read or if a command is
input. As shown in Figure 7-22, if data are not retrieved, DRDY pulses high for eight fCLK periods.
Dara Updating
8/fCLK
DRDY
Figure 7-22. DRDY With No Data Retrieval
7.5.2 Conversion Data Format
As listed in Table 7-10, the conversion data are coded in 32-bit, two's-complement format to represent positive
and negative numbers. If desired, the data read operation can be shortened to 24 bits by taking CS high. In sinc
filter mode, data are scaled by half compared to the FIR filter mode.
Table 7-10. Output Data Format
CONVERSION CODES(1)
VIN (V)
≥ 2.5V ×
(231
– 1) /
FIR FILTER
231
/ Gain
2.5V / (Gain × (231 – 1))
(1)
(2)
36
SINC FILTER(2)
7FFFFFFFh
3FFFFFFFh
00000001h
FFFFFFFFh
≤ –2.5V / Gain
80000000h
C0000000h
Excluding the effects of reference voltage error, noise, linearity, offset, and gain errors.
Because of the low values of OSR, full 32-bit resolution is not available in sinc filter mode. When the input signal is overdriven, the sinc
filter continues to output code values beyond the nominal full-scale values until clipped when the modulator saturates.
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7.5.3 Commands
Table 7-11 lists the commands for the ADC. Most commands are one byte in length. However, the number
of bytes for the register read and write commands depend on the amount of register data specified in the
command.
Table 7-11. Command Descriptions
MNEMONIC
TYPE
BYTE 1(1)
DESCRIPTION
BYTE 2
WAKEUP
Control
Wake from standby mode or NOP
0000 000x (00h or 01h)
—
STANDBY
Control
Enter standby (software power-down mode)
0000 001x (02h or 03h)
—
SYNC
Control
Synchronize
0000 010x (04h or 5h)
—
RESET
Control
Reset
0000 011x (06h or 07h)
—
RDATA
Data
Read conversion data
0001 0010 (12h)
—
RREG
Register
Read nnnn registers beginning at address rrrr 0010 rrrr (20h +
rrrr)(2)
0000 nnnn (00h + nnnn)(3)
rrrr)(2)
0000 nnnn (00h + nnnn)(3)
WREG
Register
Write nnnn registers beginning at address rrrr 0100 rrrr (40h +
OFSCAL
Calibration
Offset calibration
0110 0000 (60h)
—
GANCAL
Calibration
Gain calibration
0110 0001 (61h)
—
(1)
(2)
(3)
x = Don't care.
rrrr = Starting address for register read and write commands.
nnnn = Number of registers to be read or written – 1. For example, to read or write three registers, nnnn = 2.
7.5.3.1 Single Byte Command
Figure 7-23 shows the general format of a single byte command. For the response bytes of the RDATA
command, see the RDATA command.
CS
8
SCLK
DIN
Command
Figure 7-23. Single Byte Command Format
7.5.3.2 WAKEUP: Wake Command
The WAKEUP command exits standby mode to resume normal operation. If the ADC is already powered, the
command is no operation (NOP). When exiting standby mode, the ADC requires resynchronization. See the
Power-Down Mode section for details of power-down mode.
7.5.3.3 STANDBY: Software Power-Down Command
The STANDBY command enters the software power-down mode. The ADC exits software power-down mode by
the WAKEUP command. See the Power-Down Mode section for details of power-down mode.
7.5.3.4 SYNC: Synchronize Command
The SYNC command synchronizes the ADC. Synchronization occurs at the eighth bit of the SYNC command
byte. When synchronized, the current conversion is stopped and restarted. To synchronize multiple ADCs by
software command, send the command simultaneously to all devices. The SYNC pin must be high when using
the command. See the Synchronization section for details of synchronization.
7.5.3.5 RESET: Reset Command
The RESET command resets the ADC. See the Reset section for details of the reset operation.
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7.5.3.6 Read Data Direct
There are two methods to read conversion data: read data direct and read data by command.
Read data direct does not require a command, instead after DRDY falls low, simply apply SCLK to read the data.
Figure 7-24 shows the read data direct operation. When DRDY falls low, take CS low to start the read operation.
CS low causes DOUT to transition from tri-state mode to the output of the data MSB. Data are read on the rising
edge of SCLK and updated on the falling edge of SCLK. DRDY returns high on the first falling edge of SCLK.
DOUT is low after 32 data bits are read. To read the same data again before new data are available, use the
RDATA command.
Keep DIN low when reading conversion data. If the RDATA (read conversion data) or RREG (read register data)
command is sent, output data are interrupted in response to the command. If DRDY falls low during the read
operation, the new data are lost unless a minimum of three bytes of the old data are read.
DRDY
CS
16
8
24
32
SCLK
DIN
00h
DOUT
00h
MSB Data
00h
00h
MSB-2 Data
MSB-1 Data
LSB Data
Figure 7-24. Read Data Direct
7.5.3.7 RDATA: Read Conversion Data Command
The RDATA command (Figure 7-25) is useful to re-read data within the same conversion period or to read data
interrupted by a read register command. In both cases, DRDY is high because DRDY is driven high on the first
SCLK of the previous operation. If DRDY is high, the first output byte is zero followed by data. If low, the first
output byte is byte 1 of the conversion data, which is restarted for output byte 2.
DRDY
CS
16
8
24
40
32
SCLK
DIN
12h
DOUT
00h
00h
MSB Data
00h
MSB-1 Data
00h
00h
MSB-2 Data
LSB Data
Figure 7-25. Read Conversion Data by Command
7.5.3.8 RREG: Read Register Command
The RREG command reads register data. The command is comprised of two bytes followed by output of the
designated number of register bytes. The ADC auto-increments the address up to the number of registers
specified in byte 2 of the command. The incrementing address does not wrap. The first byte of the command is
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the opcode added to the register starting address, and the second byte is the number of registers to read minus
one.
• First command byte: 0010 rrrr, where rrrr is the starting register address
• Second command byte: 0000 nnnn, where nnnn is the number of registers to read minus one
Figure 7-26 shows an example of a three-register read operation starting at register address 01h. The first
register data appears on DOUT at the 16th falling edge of SCLK. The data are latched on the rising edge of
SCLK.
CS
16
8
24
40
32
SCLK
DIN
DOUT
21h
00h
02h
GRQ¶W FDUH
00h
Reg 01h Data
GRQ¶W FDUH
00h
Reg 02h Data
Reg 03h Data
Figure 7-26. Read Register Data
7.5.3.9 WREG: Write Register Command
The WREG command writes register data. The command is two bytes followed by the designated number of
register bytes to be written. The ADC auto-increments the address up to the number of registers specified in the
command. The incrementing address does not wrap. The first byte of the command is the opcode added to the
register starting address, and the second byte is the number of registers to write minus one.
• First command byte: 0100 rrrr, where rrrr is the starting address of the first register
• Second command byte: 0000 nnnn, where nnnn is the number of registers to write minus one
• Data bytes: Dependent on the number of registers specified
Figure 7-27 shows an example of a three-register write operation starting at register address 01h.
CS
16
8
24
40
32
SCLK
DIN
41h
02h
Reg 01h Data
Reg 02h Data
Reg 03h Data
Figure 7-27. Write Register Data
7.5.3.10 OFSCAL: Offset Calibration Command
The OFSCAL command performs offset calibration. See the Calibration Procedure section for details of
operation.
7.5.3.11 GANCAL: Gain Calibration Command
The GANCAL command performs a gain calibration. See the Calibration Procedure section for details of
operation.
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8 Register Map
Collectively, the registers contain all the information needed to configure the device (such as data rate, filter
mode, specific reference voltage, and so on). The registers are accessed by the read and write commands
(RREG and WREG). Registers can be accessed individually, or accessed in multiples given by the number of
registers specified in the command field.
Changes made to certain register bits result in a filter reset, thus requiring resynchronization of the ADC. See the
Synchronization section for details.
Table 8-1. Register Map
ADDRESS
REG LINK
RESET
00h
ID/SYNC
xxxx0010b
01h
CONFIG0
10010010b
02h
CONFIG1
00010000b
03h
HPF0
00110010h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
REVID[3:0]
BIT 2
BIT 1
DEVID[2:0]
RESERVED
DR[2:0]
MUX[2:0]
PHASE
RESERVED
BIT 0
SYNC
FILTR[1:0]
GAIN[2:0]
HPF[7:0]
04h
HPF1
00000011b
HPF[15:8]
05h
OFFSET0
00000000b
OFFSET[7:0]
06h
OFFSET1
00000000b
OFFSET[15:8]
07h
OFFSET2
00000000b
OFFSET[23:16]
08h
GAIN0
00000000b
GAIN[7:0]
09h
GAIN1
00000000b
GAIN[15:8]
0Ah
GAIN2
01000000b
GAIN[23:16]
0Bh
GPIO
000xx000b
0Ch
SRC0
00000000b
RESERVED
GPIO1_DAT GPIO0_DAT
SRC[7:0]
0Dh
SRC1
10000000b
SRC[15:8]
GPIO1_DIR
GPIO0_DIR
RESERVED
8.1 Register Descriptions
Table 8-2 shows the register access codes for the ADS1288 registers.
Table 8-2. ADS1288 Access Codes
Access Type
Code
Description
R
R
Read
R-W
R/W
Read or write
W
W
Write
-n
40
Value after reset or the default value
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8.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0010b]
Figure 8-1. ID/SYNC Register
7
6
5
4
3
2
1
0
REVID[3:0]
DEVID[2:0]
SYNC
R-xxxxb
R-001b
R/W-0b
Table 8-3. ID/SYNC Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
REVID[3:0]
R
xxxxb
Factory-programmed die revision.
These bits identify the revision of the die. The die revision is
subject to change without notification.
3:1
DEVID[2:0]
R
001b
Factory-programmed device identification.
These bits identify the ADC.
001b = ADS1288
SYNC
R/W
0b
Synchronization mode selection.
See the Synchronization section for details.
0b = Pulse-sync mode
1b = Continuous-sync mode
0
8.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 92h]
Figure 8-2. CONFIG0 Register
7
6
5
4
3
2
1
0
RESERVED
DR[2:0]
PHASE
FILTR[1:0]
R-10b
R/W-010b
R/W-0b
R/W-10b
Table 8-4. CONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
RESERVED
R
10b
Reserved bits
5:3
DR[2:0]
R/W
010b
Data rate selection.
See the Digital Filter section for details.
000b = 125SPS
001b = 250SPS
010b = 500SPS
011b = 1000SPS
100b = 2000SPS
101b –111b = Reserved
2
PHASE
R/W
0b
FIR filter phase selection.
See the Digital Filter section for details.
0b = Linear phase
1b = Minimum phase
FILTR[1:0]
R/W
10b
Digital filter configuration.
See the Digital Filter section for details.
00b = Reserved
01b = Sinc filter output
10b = FIR filter output
11b = FIR + IIR filter output
1:0
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8.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 10h]
Figure 8-3. CONFIG1 Register
7
6
5
4
3
2
1
MUX[2:0]
RESERVED
GAIN[2:0]
R/W-000b
R-10b
R/W-000b
0
Table 8-5. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
MUX[2:0]
R/W
000b
Input MUX selection.
See the Analog Input section for details.
000b = Input 1
001b = Input 2
010b = Internal short with a 400Ω resistor
011b = Input 1 and input 2
100b = Reserved
101b = Internal short with a 0Ω resistor
110b, 111b = Reserved
4:3
RESERVED
R
10b
Reserved bits
2:0
GAIN[2:0]
R/W
000b
PGA gain selection.
See the PGA and Buffer section for details.
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = Buffer operation
8.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
Figure 8-4. HPF0 Register
7
6
5
4
3
2
1
0
2
1
0
HPF[7:0]
R/W-32h
Figure 8-5. HPF1 Register
7
6
5
4
3
HPF[15:8]
R/W-03h
Table 8-6. HPF0, HPF1 Registers Field Description
Bit
15:0
42
Field
Type
Reset
Description
HPF[15:0]
R/W
0332h
High-pass filter programming.
These registers program the corner frequency of the high-pass
filter. See the HPF Stage section for details.
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8.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers
(Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
Figure 8-6. OFFSET0 Register
7
6
5
4
3
2
1
0
2
1
0
2
1
0
OFFSET[7:0]
R/W-00h
Figure 8-7. OFFSET1 Register
7
6
5
4
3
OFFSET[15:8]
R/W-00h
Figure 8-8. OFFSET2 Register
7
6
5
4
3
OFFSET[23:16]
R/W-00h
Table 8-7. OFFSET0, OFFSET1, OFFSET2 Registers Field Description
Bit
23:0
Field
Type
Reset
Description
OFFSET[23:0]
R/W
000000h
Offset calibration.
These bits are the 24-bit offset calibration word. The format is
two's-complement coding. The ADC subtracts the value of offset
from the conversion result prior to the gain calibration operation.
See the Offset and Gain Calibration section for details.
8.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers
(Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
Figure 8-9. GAIN0 Register
7
6
5
4
3
2
1
0
2
1
0
2
1
0
GAIN[7:0]
R/W-00h
Figure 8-10. GAIN1 Register
7
6
5
4
3
GAIN[15:8]
R/W-00h
Figure 8-11. GAIN2 Register
7
6
5
4
3
GAIN[23:16]
R/W-40h
Table 8-8. GAIN0, GAIN1, GAIN2 Registers Field Description
Bit
23:0
Field
Type
Reset
Description
GAIN[23:0]
R/W
400000h
Gain calibration.
These bits are the 24-bit, gain calibration word. Gain calibration
is straight-binary coding. The register value is divided by
400000h (222) and multiplied with the conversion data. The gain
operation occurs after the offset operation. See the Offset and
Gain Calibration section for details.
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8.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
Figure 8-12. GPIO Register
7
6
5
4
3
2
1
0
RESERVED
GPIO1_DAT
GPIO0_DAT
GPIO1_DIR
GPIO0_DIR
RESERVED
R/W-000b
R/W-xb
R/W-xb
R/W-0b
R/W-0b
R/W-0b
Table 8-9. GPIO Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
RESERVED
R/W
000b
Always write 000b.
4
GPIO1_DAT
R/W
xb
GPIO1 data.
See the GPIO section for details.
0b = GPIO1 is low
1b = GPIO1 is high
3
GPIO0_DAT
R/W
xb
GPIO0 data.
0b = GPIO0 is low
1b = GPIO0 is high
2
GPIO1_DIR
R/W
0b
GPIO1 direction.
0b = GPIO1 is an input
1b = GPIO1 is an output
1
GPIO0_DIR
R/W
0b
GPIO0 direction.
0b = GPIO0 is an input
1b = GPIO0 is an output
0
RESERVED
R/W
0b
Always write 0b.
8.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
Figure 8-13. SRC0 Register
7
6
5
4
3
2
1
0
2
1
0
SRC[7:0]
R/W-00h
Figure 8-14. SRC1 Register
7
6
5
4
3
SRC[15:8]
R/W-80h
Table 8-10. SRC0, SRC1 Registers Field Description
Bit
15:0
44
Field
Type
Reset
Description
SRC[15:0]
R/W
8000h
Sample rate converter.
These registers program the sample rate converter. See the
Sample Rate Converter section for details of operation.
8000h = SRC function is disabled
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The ADS1288 is a high-resolution ADC designed for low-power seismic data acquisition equipment. Optimizing
performance requires special attention to the support circuitry and printed-circuit board (PCB) layout. As much
as possible, locate noisy circuit components (such as microcontrollers, oscillators, switching regulators, and so
forth) away from the ADC input circuit components, reference voltage, and the clock signal.
9.2 Typical Application
5V
C13
1 F
C14
0.1 F
11
12
AVDD2
3.3 V
ADS1288
19
U2
IOVDD
AVDD1
1
DAC SPI
C16
1 F
C15
0.1 F
5V
AINP1
CAPD
17
C17
0.22 F
DAC1282
2
AINN1
CLK
D3,D4
BAS70
14
5V
DIN
DOUT
R5
100
R3
100
C1
100 pF C0G
R1
20 k
Geophone
R2
20 k
R4
100
C2
100 pF C0G
D1,D2
TVS0701
Optional ESD
Protection
R6
100
SCLK
3
C4
0.1 µF
RESET
–
+
U1
OPA391
PWDN
AINN2
CAPP
GPIO1
31
CAPR
CAPBN
R7
100 k
CAPC
VIN
EN
SS
R9
120 k
U3
F
REF6225 S
FLT
C7
1 F
R8 60 m
30
C8
10 F
29
23
ADC SPI
24 R10
22
25 R11
26
27
Control
28
15
16
R13
100 k
7
R12
100 k
C18
47 nF
C0G
8
C19
47 nF
C0G
9
C20
4.7 nF
REFP
C9
0.1 F
Clock Input
21
CAPN
5V
C6
1 F
GPIO0
CAPBP
6
C10
0.1 µF
2.5 V
DRDY
SYNC
4
C11
10 nF
C0G
5V
AINP2
C3
1000 pF
C0G
5
C5
0.1 µF
CS
CAPI
C12
0.1 µF
20
THERMAL
PAD
REFN
AVSS
10
32
AGND
13
DGND
18
Figure 9-1. Geophone Input Application Example
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9.2.1 Design Requirements
Figure 9-1 depicts a typical application of a geophone input circuit. The application shows the ADC operating
with a 5V power supply and a 2.5V level-shift voltage applied to the ADC inputs. The goal of this evaluation is to
analyze the effect of noise resulting from source resistance. The source resistance is the sum of the series input
resistors and the geophone output resistance.
9.2.2 Detailed Design Procedure
Referring to Figure 9-1, Schottky diodes (BAS70 or equivalent) protect the ADC inputs from voltage overloads.
The ADC inputs are protected from ESD events by the optional ESD protection diodes (TVS0701). The
geophone signal is level-shifted to mid-supply by driving the input termination resistors (R1 and R2) common
point to 2.5V. The level-shift voltage is derived from the reference voltage and is buffered by the OPA391 op
amp. The input termination resistors also provide the input bias current return path for the ADC inputs.
The input signal is filtered to reduce out-of-band noise. The filter is comprised of common-mode and differential
sections. The common-mode section filters noise common to both inputs, consisting of R3, R4, C1, and C2. The
differential section filters differential noise, consisting of R3 through R6 and C3. The resistor values are kept low
to reduce thermal noise.
The REF6225 provides the 2.5V reference voltage.
The AVDD1 power-supply voltage is shown at 5V, with AVSS connected to AGND. The AVDD2 voltage is also
5V to simplify the power-supply requirements. IOVDD is shown at 3.3V. If IOVDD = 1.8V, connect the CAPD pin
(pin 19) to IOVDD.
Besides the power-supply pins, place additional capacitors at certain pins. Capacitors are required between
CAPP – CAPN, REFP – REFN, and at the CAPBP, CAPBN, CAPI, CAPR, CAPC, and CAPD pins with the
capacitance values given in Figure 9-1. The CAPP – CAPN, CAPBP, and CAPBN capacitors are C0G type.
The DAC1282 provides a low-distortion signal to test THD performance, and through the DAC1282 dc test
mode, test geophone impulse response. Increase the value of the DAC1282 capacitors CAPP and CAPN to
10nF to optimize the ADS1288 THD test performance. See the DAC1282 data sheet for additional circuit details.
9.2.3 Application Curves
Table 9-1 lists the effect of geophone source resistance (RS) and the effect of input current noise to total noise
performance. Geophone RS = 1000Ω, 5000Ω, and two values of input current noise taken from the input current
noise distribution of Figure 9-2. Input current noise values = 1.5pA/√Hz and 3pA/√Hz are evaluated. Geophone
RS thermal noise, current noise × RS, and ADC input-referred noise are summed to derive total noise.
33
30
27
Population (%)
24
21
18
15
12
9
6
3
5
4.6
4.2
3.8
3.4
3
2.6
2.2
1.8
1.4
1
0
PGA Input Current Noise Density (pA/Hz)
Figure 9-2. PGA Input Current Noise Distribution
46
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Table 9-1. Total Noise
RS (Ω)
GAIN
1
1000
16
1
5000
16
RS NOISE (μV)
in NOISE
(pA/√Hz)
in × RS NOISE (μV)
0.06
1.5
0.024
0.06
3
0.048
0.06
1.5
0.024
0.06
3
0.048
0.13
1.5
0.11
0.13
3
0.22
0.13
1.5
0.11
0.13
3
0.22
ADC NOISE (μV)
1.4
0.28
1.4
0.28
TOTAL NOISE (μV)
1.4
1.4
0.29
0.29
1.41
1.41
0.33
0.38
The analysis data is over a 206Hz noise bandwidth (fDATA = 500SPS). The data shows the greatest of the total
noise increase compared to ADC noise alone is with 5000Ω geophone source resistance, PGA gain = 16, and
in = 3pA/√Hz. The 1000Ω geophone source resistance shows an insignificant noise increase under the same
condition.
9.3 Power Supply Recommendations
The ADC has four power supplies: AVDD1, AVDD2, AVSS, and IOVDD. Among the power-supply options, the
number of power supplies can be reduced to a single 3.3V supply used for AVDD1, AVDD2, and IOVDD, with
AVSS connected to ground. Be aware that 3.3V operation requires using the buffer for gain = 1.
The power supplies can be sequenced in any order. The ADC is held in reset until the power supplies have
crossed the retrospective power-on voltage thresholds and the clock signal is applied (see Figure 5-8 for details
of the voltage thresholds).
9.3.1 Analog Power Supplies
The ADC has three analog power supplies, AVDD1, AVDD2, and AVSS, all of which must be well regulated
and free from switching power-supply noise (voltage ripple < 1mV). The AVDD1 power-supply voltage is relative
to AVSS and powers the PGA and buffer. AVSS is the negative power supply. The ADC can be configured
for single-supply operation with AVDD1 = 5V or 3.3V with AVSS connected to ground. Because the minimum
voltage of AVDD1 to AGND = 2.375V, dual-supply operation is only possible when AVDD1 – AVSS = ±2.5V.
Single-power supply operation requires a level-shift voltage at the geophone input through the input termination
resistors. The level-shift voltage is typically equal to AVDD1 / 2. Bypass AVDD1 with 1μF and 0.1μF parallel
capacitors to AVSS.
The AVDD2 power-supply powers the modulator. To simplify system power management, AVDD2 can be
connected to AVDD1, regardless whether AVDD1 and AVSS are configured for single- or dual-supply operation
(AVDD2 voltage range is 2.375V to 5.25V with respect to AGND). Bypass AVDD2 with 1μF and 0.1μF parallel
capacitors to AGND.
9.3.2 Digital Power Supply
IOVDD is the digital power supply. IOVDD is the digital pin I/O voltage and also powers the digital core by a
1.8V low-dropout regulator (LDO). The LDO output is the CAPD pin and is bypassed with a 0.22µF capacitor
to DGND. Do not externally load the CAPD voltage output. Bypass the IOVDD pin with 1μF and 0.1μF parallel
capacitors to DGND.
If IOVDD is in the range of 1.65V to 1.95V, tie the IOVDD and CAPD pins together. This connection forces the
internal LDO off, thereby the IOVDD voltage now directly powers the digital core. Pay close attention to the
absolute maximum voltage rating of IOVDD driving the CAPD pin to avoid damaging the device.
9.3.3 Grounds
The ADC has two ground pins, AGND and DGND. Connect the AGND and DGND pins together at the ADC to a
single ground plane using short direct connections.
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9.3.4 Thermal Pad
The thermal pad does not carry device current but must be soldered and connected to the most negative
power-supply voltage (AVSS). Because of the low power dissipation, PCB thermal vias can be omitted to provide
space for bottom layer components under the device.
9.4 Layout
9.4.1 Layout Guidelines
Figure 9-3 shows the layout of the geophone input application example of Figure 9-1. In most cases, a single
unbroken ground plane connecting the grounds of the analog and digital components is preferred. A four-layer
PCB is used, with the inner layers dedicated for ground and power-supply planes. Low resistance power-supply
planes are necessary to maintain THD performance.
Connect the REFN pin of the ADC directly to the ground terminal of the voltage reference to avoid ground noise
coupling. Similarly, avoid ground noise between the tie-points of termination resistors R1 and R2 by connecting
the resistors together first, then connect to ground (dual-supply operation).
Place the smaller of the parallel power-supply bypass capacitors closest to the device supply pins. The thermal
pad of the package connects to the most negative power-supply voltage (AVSS). Figure 9-3 shows single-supply
operation, with AVSS tied to AGND. In this case, the thermal pad connects to AGND. For dual-supply operation,
connect the thermal pad to AVSS.
9.4.2 Layout Example
DAC1282
Test Signal
5V
C7
U3
R9
REF6225
C6
5V
U1
C4
OPA391
D3
BAS70
C8
R8
R7
5V
C10
C5
C9
D1
R11
TVS0701
R1
R3 -
C1
DRDY
R10
R5
PWDN
RESET
SYNC
DOUT
Signal
Input
DIN
SCLK
CS
CLK
ADS1288
C3
U2
R2
D2
R4
C2
C11
R6
C15
TVS0701
C16
3.3 V
IOVDD
C17
C18
C14
D4
C20
BAS70
C13
C19
C12
R13
R12
5V
GPIO1
GPIO0
5V
AVDD1, AVDD2
Figure 9-3. Example Layout
48
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
February 2024
*
Initial Release
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS1288IRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
1288
Samples
ADS1288IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
1288
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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