ADS1298IPAG

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software Reference Design ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 ADS129x Low-Power, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements 1 Features 3 Description • The ADS1294, ADS1296, ADS1298 (ADS129x) and ADS1294R, ADS1296R ADS1298R (ADS129xR) are a family of multichannel, simultaneous sampling, 24-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with built-in programmable gain amplifiers (PGAs), internal reference, and an onboard oscillator. The ADS129x and ADS129xR incorporate all of the features that are commonly required in medical electrocardiogram (ECG) and electroencephalogram (EEG) applications. With high levels of integration and exceptional performance, the ADS129x and ADS129xR enables the development of scalable medical instrumentation systems at significantly reduced size, power, and overall cost. 1 • • • • • • • • • • • • • Eight Low-Noise PGAs and Eight High-Resolution ADCs (ADS1298, ADS1298R) Low Power: 0.75 mW/channel Input-Referred Noise: 4 μVPP (150 Hz BW, G = 6) Input Bias Current: 200 pA Data Rate: 250 SPS to 32 kSPS CMRR: –115 dB Programmable Gain: 1, 2, 3, 4, 6, 8, or 12 Supports systems meeting AAMI EC11, EC13, IEC60601-1, IEC60601-2-27, and IEC60601-2-51 Standards Unipolar or Bipolar Supplies: – AVDD = 2.7 V to 5.25 V – DVDD = 1.65 V to 3.6 V Built-In Right Leg Drive Amplifier, Lead-Off Detection, Wilson Center Terminal, Pace Detection, Test Signals Integrated Respiration Impedance Measurement Digital Pace Detection Capability Built-In Oscillator and Reference SPI™-Compatible Serial Interface 2 Applications • Medical Instrumentation (ECG, EMG, and EEG): Patient Monitoring; Holter, Event, Stress, and Vital Signs Including ECG, AED, Telemedicine Bispectral Index (BIS), Evoked Audio Potential (EAP), Sleep Study Monitor Simplified Schematic REF Test Signals and Monitors Reference ADS129xR A1 SPI ADC1 ADC2 A3 ADC3 A4 ADC4 A5 ADC5 A6 ADC6 A7 ADC7 INPUTS Package options include a tiny 8-mm × 8-mm, 64-ball BGA, and a TQFP-64. The ADS129x BGA version is specified over the commercial temperature range of 0°C to 70°C. The ADS129xR BGA and ADS129x TQFP versions are specified over the industrial temperature range of –40°C to +85°C. Device Information(1) CLK A2 SPI RESP DEMOD The ADS129x and ADS129xR have a flexible input multiplexer (mux) per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the right leg drive (RLD) output signal. The ADS129x and ADS129xR operate at data rates as high as 32 kSPS, thereby allowing the implementation of software pace detection. Leadoff detection can be implemented internal to the device, either with a pullup or pulldown resistor, or an excitation current sink or source. Three integrated amplifiers generate the Wilson central terminal (WCT) and the Goldberger central terminals (GCT) required for a standard 12-lead ECG. The ADS129xR versions include a fully integrated, respiration impedance measurement function. Multiple ADS129x and ADS129xR devices can be cascaded in high channel count systems in a daisy-chain configuration. Oscillator PART NUMBER ADS129x, ADS129xR MUX Control PACKAGE BODY SIZE (NOM) NFBGA (64) 8.00 mm × 8.00 mm TQFP (64) 10.00 mm × 10.00 mm GPIO AND CONTROL (1) For all available packages, see the package option addendum at the end of the data sheet. ADC8 A8 To Channel WCT RESP Wilson Terminal ¼ ¼ Resp ¼ ADS129xR RLD PACE 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 9.4 Device Functional Modes........................................ 51 9.5 Programming........................................................... 59 9.6 Register Maps ......................................................... 65 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Device Comparison ............................................... 5 Pin Configuration and Functions ......................... 6 Specifications....................................................... 12 10 Application and Implementation........................ 84 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 12 Layout................................................................... 98 Absolute Maximum Ratings .................................... ESD Ratings............................................................ Recommended Operating Conditions..................... Thermal Information ................................................ Electrical Characteristics......................................... Timing Requirements: Serial Interface.................... Switching Characteristics: Serial Interface.............. Typical Characteristics ............................................ 12 12 12 13 13 17 17 18 8 Parameter Measurement Information ................ 22 9 Detailed Description ............................................ 24 8.1 Noise Measurements .............................................. 22 9.1 Overview ................................................................. 24 9.2 Functional Block Diagram ....................................... 25 9.3 Feature Description................................................. 26 10.1 Application Information.......................................... 84 10.2 Typical Applications .............................................. 89 11 Power Supply Recommendations ..................... 96 11.1 Power-Up Sequencing .......................................... 96 11.2 Connecting to Unipolar (3 V or 1.8 V) Supplies.... 97 11.3 Connecting to Bipolar (±1.5 V or ±1.8 V) Supplies ................................................................... 97 12.1 Layout Guidelines ................................................. 98 12.2 Layout Example .................................................... 99 13 Device and Documentation Support ............... 100 13.1 13.2 13.3 13.4 13.5 Related Links ...................................................... Community Resources........................................ Trademarks ......................................................... Electrostatic Discharge Caution .......................... Glossary .............................................................. 100 100 100 100 100 14 Mechanical, Packaging, and Orderable Information ......................................................... 100 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (January 2014) to Revision K Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Changed text throughout data sheet for clarity ...................................................................................................................... 1 • Added note to DAISY_IN pin ................................................................................................................................................. 8 • Added note to DAISY_IN pin ............................................................................................................................................... 10 • Changed Equation 3 ............................................................................................................................................................ 32 Changes from Revision I (January 2012) to Revision J Page • Changed NC pin discription in Pin Assignments table ......................................................................................................... 10 • Changed NC pin discription in Pin Assignments table ......................................................................................................... 10 • Added graph of INTERNAL VREF DRIFT vs TEMPERATURE ............................................................................................. 21 • Changed order of subsections in the Theory of Operation section ...................................................................................... 26 • Changed single-ended input description to correct input range values ............................................................................... 30 • Changed Figure 27 to show correct input range for single-ended inputs ............................................................................ 30 • Changed Figure 28 to show correct input range for single-ended inputs ............................................................................ 30 • Deleted text regarding large scale signal ............................................................................................................................. 31 • Changed Figure 32 to provide a more stable external reference driver circuit .................................................................... 33 • Updated Figure 57 ............................................................................................................................................................... 51 • Added Figure 58 .................................................................................................................................................................. 52 • Added discussion of SCLK/DRDY bus behavior to Data Ready (DRDY) section................................................................ 53 • Added Figure 60 .................................................................................................................................................................. 53 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 • Added status Word section and Figure 61 to discuss the status word ................................................................................ 53 • Added Readback Length section.......................................................................................................................................... 53 • Added SCLK Clocking Methods section............................................................................................................................... 60 • Changed units in TEST_AMP bit description in CONFIG2 register ..................................................................................... 68 • Changed Figure 93 to clarify Initial Flow at Power-Up ......................................................................................................... 85 • Changed Power-Up Sequencing section text to clarify start-up timing ................................................................................ 96 • Changed Figure 105 ............................................................................................................................................................ 96 • Changed power-up reset wait time in Table 38 ................................................................................................................... 96 Changes from Revision H (October 2011) to Revision I Page • Added eighth Features bullet (list of standards supported).................................................................................................... 1 • Updated BGA pin out.............................................................................................................................................................. 6 • Deleted duplicate Digital input voltage and Digital output voltage rows from Absolute Maximum Ratings table................. 12 • Changed parameter name of Channel Performance, Common-mode rejection ratio and Power-supply rejection ratio parameters in Electrical Characteristics table ...................................................................................................................... 14 • Updated Functional Block Diagram ..................................................................................................................................... 25 • Updated description of Analog Input section........................................................................................................................ 30 • Updated Figure 30 ............................................................................................................................................................... 32 • Updated Figure 33 ............................................................................................................................................................... 34 • Updated Figure 34 ............................................................................................................................................................... 35 • Changed description of START pin in START section......................................................................................................... 51 • Changed description of Data Ready (DRDY) section .......................................................................................................... 52 • Changed conversion description in Single-Shot Mode section ............................................................................................ 54 • Changed conversion description in Continuous Mode section............................................................................................. 55 • Changed Unit column in Table 14 ........................................................................................................................................ 55 • Added power-down recommendation to bit 7 description of CHnSET: Individual Channel Settings section....................... 71 • Changed description of bit 5 in RESP: Respiration Control Register section ...................................................................... 80 • Corrected name of bit 6 in WCT2: Wilson Central Terminal Control Register section......................................................... 83 Changes from Revision G (February 2011) to Revision H Page • Changed footnote 1 of BGA Pin Assignments table .............................................................................................................. 7 • Added footnote 1 cross-reference to RLDIN, TESTP_PACE_OUT1, and TESTP_PACE_OUT in BGA Pin Assignments table .................................................................................................................................................................. 7 • Changed footnote 1 of PAG Pin Assignments table ............................................................................................................ 10 • Added footnote 1 cross-reference to TESTP_PACE_OUT1, TESTP_PACE_OUT2, and RLDIN in PAG Pin Assignments table ................................................................................................................................................................ 10 • Changed description of AVSS and AVDD in PAG Pin Assignments table .......................................................................... 11 • Added (ADS1298) to High-Resolution mode and Low-Power mode test conditions of Supply Current section in Electrical Characteristics table ............................................................................................................................................. 16 • Changed 3-V Power Dissipation, Quiescent channel power test conditions in Electrical Characteristics table .................. 16 • Changed 5-V Power Dissipation, Quiescent channel power test conditions in Electrical Characteristics table .................. 16 • Changed title of Figure 20 ................................................................................................................................................... 20 • Updated Figure 42 ............................................................................................................................................................... 41 • Added new paragraph to Respiration section ...................................................................................................................... 46 • Updated Equation 5 ............................................................................................................................................................. 49 • Changed title of Table 13 .................................................................................................................................................... 54 Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 3 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com • Updated Figure 66 ............................................................................................................................................................... 57 • Changed description of STANDBY: Enter STANDBY Mode section ................................................................................... 61 • Changed bit name for bits 5, 6, and 7 in ID register of Table 16 ........................................................................................ 65 • Changed bit name for bits 5, 6, and 7 in ID: ID Control Register section ............................................................................ 66 • Added footnote to Figure 97 ................................................................................................................................................ 89 • Changed description of solid ceramic capacitor in Power Supplies and Grounding section ............................................... 96 • Changed description of Connecting the Device to Bipolar (±1.5 V/1.8 V) Supplies section ................................................ 97 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 5 Device Comparison PRODUCT ADS1194 ADS1196 ADS1198 ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R PACKAGE OPTIONS OPERATING TEMPERATURE RANGE TQFP-64 0°C to 70°C NFBGA-64 0°C to 70°C TQFP-64 0°C to 70°C NFBGA-64 0°C to 70°C TQFP-64 0°C to 70°C NFBGA-64 0°C to 70°C TQFP-64 –40°C to +85°C NFBGA-64 0°C to 70°C NFBGA-64 –40°C to +85°C TQFP-64 –40°C to +85°C NFBGA-64 0°C to 70°C NFBGA-64 –40°C to +85°C TQFP-64 –40°C to +85°C NFBGA-64 0°C to 70°C NFBGA-64 –40°C to +85°C Copyright © 2010–2015, Texas Instruments Incorporated CHANNELS ADC RESOLUTION MAXIMUM SAMPLING RATE No 4 16 8 kSPS No 6 16 8 kSPS No 8 16 8 kSPS 4 24 32 kSPS 6 24 32 kSPS 8 24 32 kSPS RESPIRATION CIRCUITRY External Yes External Yes External Yes Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 5 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 6 Pin Configuration and Functions ZXG Package 64-Pin NFBGA Top View, Solder Bumps on Bottom Side H G F E D C B A IN1P IN2P IN3P IN4P IN5P IN6P IN7P IN8P 1 IN1N IN2N IN3N IN4N IN5N IN6N IN7N IN8N 2 VREFP VCAP4 TESTN_ PACE_OUT2 TESTP_ PACE_OUT1 WCT RLDINV RLDOUT RLDIN 3 VREFN RESP_ MODP RESP_ MODN RESV1 AVSS RLDREF AVDD AVDD 4 VCAP1 PWDN GPIO1 GPIO4 AVSS AVSS AVSS AVSS 5 VCAP2 RESET DAISY_IN GPIO3 DRDY AVDD AVDD AVDD 6 DGND START CS GPIO2 DGND DGND VCAP3 AVDD1 7 DIN CLK SCLK DOUT DVDD DVDD CLKSEL AVSS1 8 6 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Pin Function: NFBGA Package PIN TYPE DESCRIPTION NO. NAME 1A IN8P (1) Analog input Differential analog positive input 8 (ADS1298 and ADS1298R) 1B IN7P (1) Analog input Differential analog positive input 7 (ADS1298 and ADS1298R) 1C IN6P (1) Analog input Differential analog positive input 6 (ADS1296, ADS1298, ADS1296R, ADS1298R) 1D IN5P (1) Analog input Differential analog positive input 5 (ADS1296, ADS1298, ADS1296R, ADS1298R) 1E IN4P (1) Analog input Differential analog positive input 4 1F IN3P (1) Analog input Differential analog positive input 3 1G IN2P (1) Analog input Differential analog positive input 2 1H IN1P (1) Analog input Differential analog positive input 1 2A IN8N (1) Analog input Differential analog negative input 8 (ADS1298, ADS1298R) 2B IN7N (1) Analog input Differential analog negative input (ADS1298, ADS1298R) 2C IN6N (1) Analog input Differential analog negative input 6 (ADS1296, ADS1298, ADS1296R, ADS1298R) 2D IN5N (1) Analog input Differential analog negative input 5 (ADS1296, ADS1298, ADS1296R, ADS1298R) 2E IN4N (1) Analog input Differential analog negative input 4 2F IN3N (1) Analog input Differential analog negative input 3 2G IN2N (1) Analog input Differential analog negative input 2 2H IN1N (1) Analog input Differential analog negative input 1 Analog input Right leg drive input to mux (1) 3A RLDIN 3B RLDOUT Analog output 3C RLDINV Analog input/output Right leg drive inverting input 3D WCT Analog output Wilson central terminal output 3E TESTP_PACE_OUT1 (1) Analog input/buffer output Internal test signal or single-ended buffer output based on register settings 3F TESTN_PACE_OUT2 (1) Analog input/output Internal test signal or single-ended buffer output based on register settings 3G VCAP4 — 3H VREFP Analog input/output 4A AVDD Supply Analog supply Analog supply Right leg drive output Analog bypass capacitor; connect 1-μF capacitor to AVSS Positive reference input/output voltage 4B AVDD Supply 4C RLDREF Analog input 4D AVSS Supply 4E RESV1 Digital input 4F RESP_MODN Analog output ADS129xR: modulation clock for respiration measurement, negative side. ADS129x: leave floating. 4G RESP_MODP Analog output ADS129xR: modulation clock for respiration measurement, positive side. ADS129x: leave floating. 4H VREFN Analog input 5A AVSS Supply Analog ground 5B AVSS Supply Analog ground 5C AVSS Supply Analog ground 5D AVSS Supply Analog ground 5E GPIO4 Digital input/output General-purpose input/output pin 4 5F GPIO1 Digital input/output General-purpose input/output pin 1 5G PWDN Digital input Power-down pin; active low (1) Right leg drive noninverting input Analog ground Reserved for future use; must tie to logic low (DGND). Negative reference voltage Connect unused pins to AVDD. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 7 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Pin Function: NFBGA Package (continued) PIN TYPE DESCRIPTION NO. NAME 5H VCAP1 — 6A AVDD Supply Analog supply 6B AVDD Supply Analog supply Analog supply Analog bypass capacitor; connect 22-μF capacitor to AVSS 6C AVDD Supply 6D DRDY Digital output 6E GPIO3 Digital input/output General purpose input/output pin 3 6F DAISY_IN (2) Digital input Daisy-chain input; if not used, short to DGND. 6G RESET Digital input System-reset pin; active low 6H VCAP2 — 7A AVDD1 Supply 7B VCAP3 — 7C DGND Supply Digital ground 7D DGND Supply Digital ground GPIO2 Digital input/output General-purpose input/output pin 2 7F CS Digital input SPI chip select; active low 7G START Digital input Start conversion 7H DGND Supply Digital ground Analog ground for charge pump 7E Data ready; active low Analog bypass capacitor; connect 1-μF capacitor to AVSS Analog supply for charge pump Analog bypass capacitor; internally generated AVDD + 1.9 V; connect 1-μF capacitor to AVSS 8A AVSS1 Supply 8B CLKSEL Digital input Master clock select 8C DVDD Supply Digital power supply 8D DVDD Supply Digital power supply 8E DOUT Digital output SPI data output 8F SCLK Digital input SPI clock 8G CLK Digital input/output External Master clock input or internal clock output. 8H DIN Digital input SPI data input (2) 8 When DAISY_IN is not used, tie to logic 0. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 49 DGND 50 DVDD 51 DGND 52 CLKSEL 53 AVSS1 54 AVDD1 55 VCAP3 56 AVDD 57 AVSS 58 AVSS 59 AVDD 60 RLDREF 61 RLDINV 62 RLDIN 63 RLDOUT 64 WCT PAG PACKAGE 64-Pin TQFP Top View IN6N 5 44 GPIO2 IN6P 6 43 DOUT IN5N 7 42 GPIO1 IN5P 8 41 DAISY_IN IN4N 9 40 SCLK IN4P 10 39 CS IN3N 11 38 START IN3P 12 37 CLK IN2N 13 36 RESET IN2P 14 35 PWDN IN1N 15 34 DIN IN1P 16 33 DGND Copyright © 2010–2015, Texas Instruments Incorporated AVSS 32 GPIO3 RESV1 31 45 VCAP2 30 4 NC 29 IN7P VCAP1 28 GPIO4 NC 27 46 VCAP4 26 3 VREFN 25 IN7N VREFP 24 DRDY AVSS 23 47 AVDD 22 2 AVDD 21 IN8P AVSS 20 DVDD AVDD 19 48 TESTN_PACE_OUT2 18 1 TESTP_PACE_OUT1 17 IN8N Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 9 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Pin Functions: TQFP Package PIN TYPE DESCRIPTION NO. NAME 1 IN8N (1) Analog input Differential analog negative input 8 (ADS1298) 2 IN8P (1) Analog input Differential analog positive input 8 (ADS1298) 3 IN7N (1) Analog input Differential analog negative input 7 (ADS1298) 4 IN7P (1) Analog input Differential analog positive input 7 (ADS1298) 5 IN6N (1) Analog input Differential analog negative input 6 (ADS1296, ADS1298) 6 IN6P (1) Analog input Differential analog positive input 6 (ADS1296, ADS1298) 7 IN5N (1) Analog input Differential analog negative input 5 (ADS1296, ADS1298) 8 IN5P (1) Analog input Differential analog positive input 5 (ADS1296, ADS1298) 9 IN4N (1) Analog input Differential analog negative input 4 10 IN4P (1) Analog input Differential analog positive input 4 11 IN3N (1) Analog input Differential analog negative input 3 12 IN3P (1) Analog input Differential analog positive input 3 13 IN2N (1) Analog input Differential analog negative input 2 14 IN2P (1) Analog input Differential analog positive input 2 15 IN1N (1) Analog input Differential analog negative input 1 16 IN1P (1) Analog input Differential analog positive input 1 17 TESTP_PACE_OUT1 (1) Analog input/buffer output Internal test signal/single-ended buffer output based on register settings 18 TESTN_PACE_OUT2 (1) Analog input/output Internal test signal/single-ended buffer output based on register settings 19 AVDD Supply Analog supply 20 AVSS Supply Analog ground 21 AVDD Supply Analog supply 22 AVDD Supply Analog supply 23 AVSS Supply Analog ground 24 VREFP Analog input/output Positive reference input/output voltage 25 VREFN Analog input Negative reference voltage 26 VCAP4 — Analog bypass capacitor; connect 1-μF capacitor to AVSS 27 NC — No connection, can be connected to AVDD or AVSS with a 10-kΩ resistor 28 VCAP1 — Analog bypass capacitor; connect 22-μF capacitor to AVSS 29 NC — No connection, can be connected to AVDD or AVSS with a 10-kΩ resistor 30 VCAP2 — Analog bypass capacitor; connect 1-μF capacitor to AVSS 31 RESV1 Digital input 32 AVSS Supply Analog ground 33 DGND Supply Digital ground 34 DIN Digital input SPI data input 35 PWDN Digital input Power-down pin; active low 36 RESET Digital input System-reset pin; active low 37 CLK Digital input/output External Master clock input or internal clock output. 38 START Digital input Start conversion 39 CS Digital input SPI chip select; active low 40 SCLK Digital input SPI clock 41 DAISY_IN (2) Digital input Daisy-chain input; if not used, short to DGND. (1) (2) 10 Reserved for future use; must tie to logic low (DGND). Connect unused pins to AVDD. When DAISY_IN is not used, tie to logic 0. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Pin Functions: TQFP Package (continued) PIN TYPE DESCRIPTION NO. NAME 42 GPIO1 Digital input/output 43 DOUT Digital output 44 GPIO2 Digital input/output General-purpose input/output pin 2 45 GPIO3 Digital input/output General-purpose input/output pin 3 46 GPIO4 Digital input/output General-purpose input/output pin 4 47 DRDY Digital output 48 DVDD Supply Digital power supply 49 DGND Supply Digital ground 50 DVDD Supply Digital power supply 51 DGND Supply Digital ground 52 CLKSEL Digital input 53 AVSS1 Supply Analog ground 54 AVDD1 Supply Analog supply 55 VCAP3 — 56 AVDD Supply Analog supply 57 AVSS Supply Analog ground 58 AVSS Supply Analog ground 59 AVDD Supply Analog supply 60 RLDREF Analog input Right leg drive noninverting input 61 RLDINV Analog input/output Right leg drive inverting input 62 RLDIN (1) Analog input Right leg drive input to mux 63 RLDOUT Analog output Right leg drive output 64 WCT Analog output Wilson Central Terminal output Copyright © 2010–2015, Texas Instruments Incorporated General-purpose input/output pin 1 SPI data output Data ready; active low Master clock select Analog bypass capacitor; internally generated AVDD + 1.9 V; connect 1-μF capacitor to AVSS Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 11 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT AVDD to AVSS –0.3 5.5 V DVDD to DGND –0.3 3.9 V AVSS to DGND –3 0.2 V VREFP input to AVSS AVSS – 0.3 AVDD + 0.3 V Analog input voltage AVSS – 0.3 AVDD + 0.3 V Digital input voltage DGND – 0.3 DVDD + 0.3 V Digital output voltage DGND – 0.3 DVDD + 0.3 V 100 mA Input current (momentary) Input current (continuous) 10 mA Junction temperature, TJ –40 150 °C Storage temperature, Tstg –60 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY Analog power supply (AVDD – AVSS) 2.7 3 5.25 V Digital power supply (DVDD) 1.65 1.8 3.6 V AVDD – DVDD –2.1 3.6 V ANALOG INPUTS Full-scale differential input voltage range (AINP – AINN) ±VREF / Gain V See the Input Common-Mode Range subsection of the PGA Settings and Input Range section Common-mode input voltage VOLTAGE REFERENCE INPUTS Differential reference voltage 3-V supply VREF = (VREFP – VREFN) 2.5 V 5-V supply VREF = (VREFP – VREFN) 4 V AVSS V AVSS + 2.5 V Negative input (VREFN) Positive input (VREFP) CLOCK INPUT External clock input frequency CLKSEL pin = 0 1.94 2.048 2.25 MHz DIGITAL INPUTS Input Voltage DGND DVDD V 0 70 °C –40 85 °C TEMPERATURE RANGE Operating temperature range 12 Submit Documentation Feedback Commercial grade Industrial grade Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 7.4 Thermal Information ADS129x, ADS129xR THERMAL METRIC (1) PAG (TQFP) ZXG (NFBGA) 64 PINS 64 PINS UNIT 48 °C/W RθJA Junction-to-ambient thermal resistance 35 RθJC(top) Junction-to-case (top) thermal resistance 31 8 °C/W RθJB Junction-to-board thermal resistance 26 25 °C/W ψJT Junction-to-top characterization parameter 0.1 0.5 °C/W ψJB Junction-to-board characterization parameter N/A 22 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics Min and max specifications apply for all commercial grade (TA = 0°C to 70°C) devices, and from TA = –40°C to +85°C for industrial-grade devices. Typical specifications at TA = 25°C. All specifications at DVDD = 1.8 V, AVDD – AVSS = 3 V (1), VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 500 SPS, HR mode (2), and gain = 6 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±200 pA ANALOG INPUTS Input capacitance 20 TA = 25°C, input = 1.5 V Input bias current TA = 0°C to 70°C, input = 1.5 V ±1 TA = –40°C to +85°C, input = 1.5 V No lead-off DC input impedance pF nA ±1.2 nA 1000 MΩ Current source lead-off detection 500 MΩ Pullup resistor lead-off detection 10 MΩ PGA PERFORMANCE Gain settings 1, 2, 3, 4, 6, 8, 12 Bandwidth See Table 5 ADC PERFORMANCE Resolution Data rate Data rates up to 8 kSPS, no missing codes 24 Bits 16-kSPS data rate 19 Bits 32-kSPS data rate 17 Bits fCLK = 2.048 MHz, HR mode 500 32000 SPS fCLK = 2.048 MHz, LP mode 250 16000 SPS DC CHANNEL PERFORMANCE Input-referred noise Gain = 6 (3), 10 seconds of data 5 Gain = 6, 256 points, 0.5 seconds of data 4 Gain settings ≠ 6, data rates≠ 500 SPS Integral nonlinearity (4) 8 ppm Full-scale with gain = 6, best fit, ADS129xR channel 1 40 ppm –20 dBFS with gain = 6, best fit, ADS129xR channel 1 8 ppm ±500 Offset error drift µV 2 Gain error Excluding voltage reference error Gain drift Excluding voltage reference drift Gain match between channels (4) μVPP See Noise Measurements section Full-scale with gain = 6, best fit Offset error (1) (2) (3) μVPP 7 ±0.2 µV/°C ±0.5 % of FS 5 ppm/°C 0.3 % of FS Performance is applicable for 5-V operation as well. Production testing for limits is performed at 3 V. LP mode = low-power mode. Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted (without electrode resistance) over a 10-second interval. The presence of internal demodulation circuitry on channel 1 causes degradation of INL and THD. The effect is pronounced for full-scale signals and is less for small ECG-type signals. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 13 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) Min and max specifications apply for all commercial grade (TA = 0°C to 70°C) devices, and from TA = –40°C to +85°C for industrial-grade devices. Typical specifications at TA = 25°C. All specifications at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 500 SPS, HR mode(2), and gain = 6 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP –105 MAX UNIT AC CHANNEL PERFORMANCE CMRR Common-mode rejection ratio fCM = 50 Hz, 60 Hz (5) –115 dB PSRR Power-supply rejection ratio fPS = 50 Hz, 60 Hz 90 dB Crosstalk fIN = 50 Hz, 60 Hz –126 dB Signal-to-noise ratio fIN = 10 Hz input, gain = 6 112 dB 10 Hz, –0.5 dBFs –98 dB ADS129xR channel 1, 10 Hz, –0.5 dBFs –70 dB –100 dB ADS129xR channel 1, 100 Hz, –0.5 dBFs (6) –68 dB ADS129xR channel 1, 100 Hz, –20 dBFs (6) –86 dB SNR THD Total harmonic distortion (4) 100 Hz, –0.5 dBFs (6) DIGITAL FILTER –3-dB bandwidth Digital filter settling 0.262 fDR Full setting Hz 4 Conversions RIGHT LEG DRIVE (RLD) AMPLIFIER AND PACE AMPLIFIERS RLD integrated noise BW = 150 Hz 7 μVRMS Pace integrated noise BW = 8 kHz 20 µVRMS Pace-amplifier crosstalk Crosstalk between pace amplifiers 60 dB Gain bandwidth product 50 kΩ || 10 pF load, gain = 1 100 kHz Slew rate 50 kΩ || 10 pF load, gain = 1 0.25 V/μs Short circuit to GND (AVDD = 3 V) 270 μA Short circuit to supply (AVDD = 3 V) 550 μA Short circuit to GND (AVDD = 5 V) 490 μA Short circuit to supply (AVDD = 5 V) 810 μA Peak swing (AVSS + 0.3 V to AVDD + 0.3 V) at AVDD = 3 V 50 μA Peak swing (AVSS + 0.3 V to AVDD + 0.3 V) at AVDD = 5 V 75 μA Pace and RLD amplifier drive strength Pace and RLD current Pace-amplifier output resistance Total harmonic distortion fIN = 100 Hz, gain = 1 Common-mode input range 100 Ω –70 dB AVSS + 0.7 AVDD – 0.3 V Common-mode resistor matching Internal 200-kΩ resistor matching 0.1% Short-circuit current ±0.25 mA 20 μA Quiescent power consumption Either RLD or pace amplifier WILSON CENTRAL TERMINAL (WCT) AMPLIFIER Integrated noise See Table 6 nV/√Hz Gain bandwidth product BW = 150 Hz See Table 6 kHz Slew rate See Table 6 V/s Total harmonic distortion fIN = 100 Hz Common-mode input range Short-circuit current AVSS + 0.3 Through internal 30-kΩ resistor Quiescent power consumption (5) (6) 14 90 dB AVDD – 0.3 V ±0.25 mA See Table 6 μA CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the maximum of the eight channels. Harmonics above the second harmonic are attenuated by the digital filter. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Electrical Characteristics (continued) Min and max specifications apply for all commercial grade (TA = 0°C to 70°C) devices, and from TA = –40°C to +85°C for industrial-grade devices. Typical specifications at TA = 25°C. All specifications at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 500 SPS, HR mode(2), and gain = 6 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEAD-OFF DETECT Frequency See Table 16 for settings 0, fDR/4 kHz Current See Table 16 for settings 6, 12, 18, 24 nA Current accuracy ±20% Comparator threshold accuracy ±30 mV RESPIRATION (ADS129xR ONLY) Internal source Frequency External source 32, 64 32 kHz 64 22.5 90 157.5 kHz Phase shift See Table 16 for settings Degrees Impedance range IRESP = 30 μA Impedance measurement noise 0.05-Hz to 2-Hz brick wall filter, 32-kHz modulation clock, phase = 112.5, IRESP = 30 μA with 2-kΩ baseline load, gain = 4 20 mΩPP Modulator current internal reference, signal path = 82 kΩ, baseline = 2.21 kΩ 29 µA 10 kΩ Register bit CONFIG3.VREF_4V = 0, AVDD ≥ 2.7 V 2.4 V Register bit CONFIG3.VREF_4V = 1, AVDD ≥ 4.4 V 4 V 10 kΩ EXTERNAL REFERENCE Input impedance INTERNAL REFERENCE Output voltage VREF accuracy ±0.2% Internal reference drift TA = 25°C 35 ppm/°C Commercial grade, 0°C to 70°C 35 ppm Industrial grade, –40°C to 85°C 45 ppm 150 ms Start-up time SYSTEM MONITORS Analog-supply reading error 2% Digital-supply reading error 2% From power up to DRDY low Device wakeup 150 ms 9 ms 145 mV 490 μV/°C STANDBY mode Temperature-sensor reading, voltage TA = 25°C Temperature-sensor reading, coefficient Test-signal frequency See Table 16 for settings fCLK / 221, fCLK / 220 Hz Test-signal voltage See Table 16 for settings ±1, ±2 mV Test-signal accuracy ±2% CLOCK Internal-oscillator clock frequency Nominal frequency 2.048 TA = 25°C Internal clock accuracy ±0.5% 0°C ≤ TA ≤ 70°C ±2% –40°C ≤ TA ≤ 85°C, industrial grade versions only ±2.5% Internal-oscillator start-up time Internal-oscillator power consumption Copyright © 2010–2015, Texas Instruments Incorporated MHz 20 120 Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R μs μW 15 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) Min and max specifications apply for all commercial grade (TA = 0°C to 70°C) devices, and from TA = –40°C to +85°C for industrial-grade devices. Typical specifications at TA = 25°C. All specifications at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 500 SPS, HR mode(2), and gain = 6 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT (DVDD = 1.65 V to 3.6 V) VIH High-level inpout voltage VIL Low-level input voltage VOH High-level output voltage IOH = –500 μA VOL Low-level output voltage IOL = 500 μA IIN Input current 0 V < VDigitalInput < DVDD 0.8 DVDD DVDD + 0.1 V –0.1 0.2 DVDD V DVDD – 0.4 V –10 0.4 V 10 μA POWER SUPPLY (RLD, WCT, AND PACE AMPLIFIERS TURNED OFF) 2.75 mA LP mode (2) (ADS1298) 1.8 mA HR mode (ADS1298) 3.1 mA LP mode (ADS1298) 2.1 mA HR mode (ADS1298) 0.3 mA LP mode (ADS1298) 0.3 mA HR mode (ADS1298) 0.5 mA LP mode (ADS1298) 0.5 ADS1298, ADS1298R, AVDD – AVSS = 3 V HR mode 8.8 9.5 mW LP mode (250 SPS) 6.0 7.0 mW ADS1296, ADS1296R, AVDD – AVSS = 3 V HR mode 7.2 7.9 mW LP mode (250 SPS) 5.3 6.6 mW ADS1294, ADS1294R, AVDD – AVSS = 3 V HR mode 5.4 6 mW LP mode (250 SPS) 4.1 4.4 mW ADS1298, ADS1298R, AVDD – AVSS = 5 V HR mode 17.5 mW LP mode (250 SPS) 12.5 mW ADS1296, ADS1296R, AVDD – AVSS = 5 V HR mode 14.1 mW 10 mW ADS1294, ADS1294R, AVDD – AVSS = 5 V HR mode 10.1 mW 8.3 mW AVDD – AVSS = 3 V 10 μW AVDD – AVSS = 5 V 20 μW AVDD – AVSS = 3 V 2 mW 4 mW AVDD – AVSS = 3 V IAVDD AVDD current AVDD – AVSS = 5 V DVDD = 1.8 V IDVDD DVDD current DVDD = 3 V Power dissipation Power-down Standby mode LP mode (250 SPS) LP mode (250 SPS) AVDD – AVSS = 5 V Quiescent channel power 16 HR mode (ADS1298) mA AVDD – AVSS = 3 V, PGA + ADC 818 μW AVDD – AVSS = 5 V, PGA + ADC 1.5 mW Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 7.6 Timing Requirements: Serial Interface specifications apply from TA = –40°C to +85°C (unless otherwise noted); load on DOUT = 20 pF || 100 kΩ 2.7 V ≤ DVDD ≤ 3.6 V tCLK Master clock period tCSSC CS low to first SCLK, setup time tSCLK 1.65 V ≤ DVDD ≤ 2 V MIN MAX MIN MAX UNIT 414 514 414 514 ns 6 17 ns SCLK period 50 66.6 ns tSPWH, L SCLK pulse width, high and low 15 25 ns tDIST DIN valid to SCLK falling edge: setup time 10 10 ns tDIHD Valid DIN after SCLK falling edge: hold time 10 11 ns tCSH CS high pulse 2 2 tCLK tSCCS Eighth SCLK falling edge to CS high 4 4 tCLK tSDECODE Command decode time 4 4 tCLK tDISCK2ST DAISY_IN valid to SCLK rising edge: setup time 10 10 ns tDISCK2HT DAISY_IN valid after SCLK rising edge: hold time 10 10 ns 7.7 Switching Characteristics: Serial Interface specifications apply from TA = –40°C to +85°C (unless otherwise noted). Load on DOUT = 20 pF || 100 kΩ. 2.7 V ≤ DVDD ≤ 3.6 V PARAMETER MIN tDOHD SCLK falling edge to invalid DOUT: hold time tDOPD SCLK rising edge to DOUT valid: setup time tCSDOD CS low to DOUT driven tCSDOZ CS high to DOUT Hi-Z 1.65 V ≤ DVDD ≤ 2 V MAX MIN 10 MAX UNIT 10 ns 17 32 10 20 ns ns 10 20 ns tCLK CLK tCSSC tSCLK SCLK tCSH tSDECODE CS 1 tSPWL tSPWH 3 2 8 1 tDIHD tDIST tSCCS 3 2 8 tDOHD tDOPD DIN tCSDOZ tCSDOD Hi-Z Hi-Z DOUT NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing tDISCK2ST MSBD1 DAISY_IN SCLK 1 2 tDISCK2HT LSBD1 3 216 217 218 219 tDOPD DOUT LSB MSB Don’t Care MSBD1 NOTE: Daisy-chain timing shown for eight-channel ADS1298 and ADS1298R. Figure 2. Daisy-Chain Interface Timing Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 17 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 7.8 Typical Characteristics at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 500 SPS, high-resolution mode, and gain = 6 (unless otherwise noted) 1600 1400 2 1200 1 Occurrences 0 -1 1000 800 600 400 -2 200 Peak-to-Peak Over 10sec = 5mV 9 10 Time (sec) 2.18 0 8 1.68 7 1.17 6 0.67 5 0.17 4 -0.34 3 -0.84 2 -1.35 1 -1.85 0 -2.35 -3 -2.88 Input-Referred Noise (mV) 3 Input-Referred Noise (mV) Figure 4. Noise Histogram Figure 3. Input-Referred Noise 2.408 Common-Mode Rejection Ratio (dB) -130 Internal Reference (V) 2.406 2.404 2.402 2.4 2.398 2.396 -40 35 10 -15 60 -120 -115 -110 -105 -100 -95 Data Rate = 4kSPS AIN = AVDD - 0.3V to AVSS + 0.3V -90 -85 85 Gain = 1 Gain = 2 Gain = 3 Gain = 4 Gain = 6 Gain = 8 Gain = 12 -125 10 Figure 5. Internal Reference vs Temperature 0.18 Figure 6. CMRR vs Frequency 1200 AVDD - AVSS = 5V PGA = 1 1000 0.14 Leakage Current (pA) Input Leakage Current (nA) 0.16 1k 100 Frequency (Hz) Temperature (°C) 0.12 0.10 0.08 0.06 0.04 800 600 400 200 0.02 0 0 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 Input Voltage (V) Figure 7. Leakage Current vs Input Voltage 18 Submit Documentation Feedback 4.8 -40 -15 10 35 60 85 Temperature (°C) Figure 8. Leakage Current vs Temperature Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 500 SPS, high-resolution mode, and gain = 6 (unless otherwise noted) -105 Gain = 2 105 Gain = 8 Total Harmonic Distortion (dB) Power-Supply Rejection Ratio (dB) 110 Gain = 12 100 95 Gain = 4 Gain = 6 90 Gain = 3 Gain = 2 85 80 Gain = 1 75 -100 Gain = 1 -95 Gain = 3 -90 Gain = 4 -85 Gain = 6 -80 Gain = 8 -75 Data Rate = 4kSPS AIN = 0.5dBFS Data Rate = 4kSPS 10 10 1k 100 Frequency (Hz) Figure 10. THD vs Frequency 8 8 6 Integral Nonlinearity (ppm) Integral Nonlinearity (ppm) Figure 9. PSRR vs Frequency 10 6 4 2 0 Gain = 1 Gain = 2 Gain = 3 Gain = 4 Gain = 6 Gain = 8 Gain = 12 -2 -4 -6 -8 -10 -1.0 -0.8 -0.6 -0.4 -0.2 4 2 0 -2 -40°C -20°C 0°C +25°C +40°C +60°C -4 -6 -8 0 0.2 0.4 0.6 0.8 -1 1.0 Amplitude (dBFS) -60 -80 -100 -120 0 -40 -60 -80 -100 -120 -140 -140 -160 -160 0 50 100 150 200 Frequency (Hz) Figure 13. THD FFT Plot (60-Hz Signal) Copyright © 2010–2015, Texas Instruments Incorporated 1 250 PGA Gain = 6 THD = -104dB SNR = 74.5dB fDR = 32kSPS -20 Amplitude (dBFS) PGA Gain = 1 THD = -102dB SNR = 115dB fDR = 500SPS fCLK = External Clock -40 0.5 Figure 12. INL vs Temperature Figure 11. INL vs PGA Gain 0 0 -0.5 +70°C +85°C Input Range (Normalized to Full-Scale) Input (Normalized to Full-Scale) -20 1k 100 Frequency (Hz) -180 Gain = 12 -70 70 -180 0 2 4 6 8 10 12 14 16 Frequency (kHz) Figure 14. FFT Plot (60-Hz Signal) Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 19 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 500 SPS, high-resolution mode, and gain = 6 (unless otherwise noted) 800 70 700 60 Data From 31 Devices, Two Lots Number of Bins 500 400 300 50 40 30 20 200 10 100 10 12 11 PGA Gain 0.66 9 0.54 8 0.42 7 0.30 6 0.18 5 0.06 4 -0.06 3 -0.18 2 -0.53 1 -0.29 0 0 -0.41 Offset (mV) 600 Error (%) Figure 16. Test-Signal Amplitude Accuracy Figure 15. Offset vs PGA Gain (Absolute Value) 80 120 Data From 31 Devices, Two Lots Current Setting = 24nA Data From 31 Devices, Two Lots 70 100 Number of Bins Number of Bins 60 50 40 30 80 60 40 20 20 10 0 30 15.5 20 13.5 10 Power (mW) Integral Nonlinearity (ppm) 17.5 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 -20 -30 -40 2.93 2.37 1.80 1.24 0.68 0.12 -0.45 AVDD = 3V AVDD = 5V 11.5 9.5 7.5 5.5 3.5 1.5 -50 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 Input Range (Normalized to Full-Scale) Figure 19. ADS129xR Nonlinearity 20 Figure 18. Lead-Off Current-Source Accuracy Distribution 40 -10 -1.01 Error in Current Magnitude (nA) Figure 17. Lead-Off Comparator Threshold Accuracy 0 -1.57 Threshold Error (mV) -2.14 -2.70 35 30 25 20 15 10 5 0 -10 -15 -20 0 Submit Documentation Feedback 0.8 1 0 1 2 3 4 5 6 7 8 Number of Channels Disabled Figure 20. ADS1298 and ADS1298R Channel Power Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 500 SPS, high-resolution mode, and gain = 6 (unless otherwise noted) 120 105 Signal-to-Noise Ratio (dB) Total Harmonic Distortion (dBc) 110 100 95 90 85 80 75 70 110 100 90 80 Internal Master Clock, AVDD = 3V Internal Master Clock, AVDD = 5V External Master Clock, AVDD = 3V External Master Clock, AVDD = 5V 70 60 65 fIN = 10Hz, -0.5dBFS 50 60 1 2 3 4 5 6 7 8 -60 -50 -40 -30 -20 -12 -5 -2 -0.5 Input Amplitude (dBFS) Channel Figure 21. ADS129xR THD Figure 22. SNR vs Input Amplitude (10-Hz Sine Wave) 2.406 2.404 Vref (V) 2.402 2.400 2.398 2.396 2.394 2.392 ±40 ±15 10 35 60 85 Temperature (ƒC) 110 C001 Figure 23. Internal VREF Drift vs Temperature Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 21 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 8 Parameter Measurement Information 8.1 Noise Measurements NOTE The ADS129xR channel performance differs from the ADS129x in regards to respiration circuitry found on channel one. Unless otherwise noted, ADS129x refers to all specifications and functional descriptions of the ADS1294, ADS1296, ADS1298, ADS1294R, ADS1296R, and ADS1298R. ADS129xR refers to all specifications and functional descriptions of only the ADS1294R, ADS1296R, and ADS1298R. Optimize the ADS129x noise performance by adjusting the data rate and PGA setting. Reduce the data rate to increase the averaging, and the noise drops correspondingly. Increase the PGA value to reduce the inputreferred noise. This lowered noise level is particularly useful when measuring low-level biopotential signals. Table 1 and Table 2 summarize the noise performance of the ADS129x in high-resolution (HR) mode and lowpower (LP) mode, respectively, with a 3-V analog power supply. Table 3 and Table 4 summarize the noise performance of the ADS129x in HR and LP modes, respectively, with a 5-V analog power supply. The data are representative of typical noise performance at TA = 25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the RMS and peak-to-peak noise for each reading. For the two highest data rates, the noise is limited by quantization noise of the ADC and does not have a gaussian distribution. Thus, the ratio between rms noise and peak-to-peak noise is approximately 10. For the lower data rates, the ratio is approximately 6.6. Table 1 to Table 4 show measurements taken with an internal reference. The data are also representative of the ADS129x noise performance when using a low-noise external reference such as the REF5025. Table 1. Input-Referred Noise μVRMS (μVPP) in High-Resolution Mode 3-V Analog Supply and 2.4-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2 PGA GAIN = 3 000 32000 8398 335 (3553) 168 (1701) 001 16000 4193 56 (613) 28 (295) 010 8000 2096 12.4 (111) 011 4000 1048 100 2000 101 110 (1) PGA GAIN = 4 PGA GAIN = 6 PGA GAIN = 8 PGA GAIN = 12 112 (1100) 85 (823) 58 (529) 42.5 (378) 28.6 (248) 18.8 (188) 14.3 (143) 9.7 (94) 7.4 (69) 5.2 (44.3) 6.5 (54) 4.5 (37.9) 3.5 (29.7) 2.6 (21.7) 2.2 (17.8) 1.8 (13.8) 6.1 (44.8) 3.2 (23.3) 2.4 (17.1) 1.9 (14) 1.5 (11.1) 1.3 (9.7) 1.2 (8.5) 524 4.1 (27.8) 2.2 (15.4) 1.6 (11) 1.3 (9.1) 1.1 (7.3) 1 (6.5) 0.9 (6) 1000 262 2.9 (19) 1.6 (10.1) 1.2 (7.5) 1 (6.2) 0.8 (5) 0.7 (4.6) 0.6 (4.1) 500 131 2.1 (12.5) 1.1 (6.8) 0.9 (5.1) 0.7 (4.3) 0.6 (3.5) 0.5 (3.1) 0.5 (2.9) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table. Table 2. Input-Referred Noise μVRMS (μVPP) in Low-Power Mode 3-V Analog Supply and 2.4-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2 PGA GAIN = 3 000 16000 4193 333 (3481) 166 (1836) 001 8000 2096 56 (554) 28 (272) 010 4000 1048 12.5 (99) 011 2000 524 100 1000 101 500 110 250 (1) 22 PGA GAIN = 4 PGA GAIN = 6 PGA GAIN = 8 PGA GAIN = 12 111 (1168) 84 (834) 56 (576) 42 (450) 28 (284) 19 (177) 14.3 (133) 9.7 (85) 7.4 (64) 5 (42.4) 6.5 (51) 4.5 (35) 3.4 (25.9) 2.4 (18.8) 2 (14.5) 1.5 (11.3) 6.1 (41.8) 3.2 (22.2) 2.3 (15.9) 1.8 (12.1) 1.4 (9.3) 1.2 (7.8) 1 (6.7) 262 4.1 (26.3) 2.2 (14.6) 1.6 (9.9) 1.3 (8.1) 1 (6.2) 0.8 (5.4) 0.7 (4.7) 131 3 (17.9) 1.6 (9.8) 1.1 (6.8) 0.9 (5.7) 0.7 (4.2) 0.6 (3.6) 0.5 (3.4) 65 2.1 (11.9) 1.1 (6.3) 0.8 (4.6) 0.7 (4) 0.5 (3) 0.5 (2.6) 0.4 (2.4) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Table 3. Input-Referred Noise μVRMS (μVPP) in High-Resolution Mode 5-V Analog Supply and 4-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2 PGA GAIN = 3 PGA GAIN = 4 PGA GAIN = 6 PGA GAIN = 8 PGA GAIN = 12 000 32000 8398 521 (5388) 260 (2900) 173 (1946) 130 (1403) 87 (917) 65 (692) 44 (483) 001 16000 4193 86 (1252) 43 (633) 29 (402) 22 (298) 15 (206) 11 (141) 7 (91) 010 8000 2096 17 (207) 9 (112) 6 (71) 4 (57) 3 (36) 3 (29) 2 (18) 011 4000 1048 6.4 (48.2) 3.4 (25.9) 2.417.7) 1.9 (15.4) 1.5 (11.2) 1.3 (9.6) 1.1 (8.2) 100 2000 524 4.2 (29.9) 2.3 (15.9) 1.6 (11.1) 1.3 (9.3) 1 (7.5) 0.9 (6.6) 0.8 (5.8) 101 1000 262 2.9 (18.8) 1.6 (10.4) 1.1 (7.8) 0.9 (6.1) 0.7 (4.9) 0.6 (4.7) 0.6 (3.9) 110 500 131 2 (12.8) 1.1 (7.2) 0.8 (5.2) 0.7 (4) 0.5 (3.3) 0.5 (3.3) 0.4 (2.7) (1) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table. Table 4. Input-Referred Noise μVRMS (μVPP) in Low-Power Mode 5-V Analog Supply and 4-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2 PGA GAIN = 3 PGA GAIN = 4 PGA GAIN = 6 PGA GAIN = 8 PGA GAIN = 12 000 16000 4193 526 (5985) 263 (2953) 175 (1918) 132 (1410) 88 (896) 66 (681) 44 (458) 001 8000 2096 88 (1201) 44 (619) 29 (411) 22 (280) 15 (191) 11 (139) 7 (83) 010 4000 1048 17 (208) 9 (103) 6 (62) 4 (52) 3 (37) 2 (25) 2 (16) 011 2000 524 6 (41.1) 3.3 (23.3) 2.2 (15.5) 1.8 (12.3) 1.3 (9.8) 1.1 (7.8) 0.9 (6.5) 100 1000 262 4.1 (27.1) 2.3 (14.8) 1.5 (10.1) 1.2 (8.1) 0.9 (6) 0.8 (5.4) 0.7 (4.4) 101 500 131 2.9 (17.4) 1.6 (9.6) 1.1 (6.6) 0.9 (5.9) 0.7 (4.3) 0.6 (3.4) 0.5 (3.2) 110 250 65 2.1 (11.9) 1.1 (6.6) 0.8 (4.6) 0.6 (3.7) 0.5 (3) 0.4 (2.5) 0.4 (2.2) (1) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 23 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9 Detailed Description 9.1 Overview NOTE The ADS129xR channel performance differs from the ADS129x in regards to respiration circuitry found on channel one. Unless otherwise noted, ADS129x refers to all specifications and functional descriptions of the ADS1294, ADS1296, ADS1298, ADS1294R, ADS1296R, and ADS1298R. ADS129xR refers to all specifications and functional descriptions of only the ADS1294R, ADS1296R, and ADS1298R. The ADS129x are low-power, multichannel, simultaneously-sampling, 24-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices incorporate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG), electroencephalography (EEG), and electromyography (EMG) applications. These devices are also used in highperformance, multichannel data acquisition systems by powering down the ECG-specific circuitry. The ADS129x have a highly-programmable multiplexer (mux) that allows for temperature, supply, input short, and RLD measurements. Additionally, the mux allows any of the input electrodes to be programmed as the patient reference drive. The PGA gain is chosen from one of seven settings: 1, 2, 3, 4, 6, 8, or 12. The ADCs in the device offer data rates from 250 SPS to 32 kSPS. Communicate with the device by using an SPI-compatible interface. The device provides four GPIO pins for general use. Synchronize multiple devices by using the START pin. Program the internal reference to either 2.4 V or 4 V. The internal oscillator generates a 2.048-MHz clock. The versatile right-leg drive (RLD) block allows for choosing the average of any combination of electrodes to generate the patient drive signal. Lead-off detection is accomplished either by using a pullup or pulldown resistor, or a current source or sink. An internal ac lead-off detection feature is also available. These devices support both hardware pace detection and software pace detection. Use the Wilson central terminal (WCT) block to generate the WCT point of the standard 12-lead ECG. Additionally, the ADS129xR provide options for an internal respiration modulator and a demodulator circuit in the signal path of channel 1. 24 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.2 Functional Block Diagram VREFP AVDD AVDD1 RESP_MODN Internal Respiration Modulator (ADS129xR) Test Signal Temperature Sensor Input Lead-Off Excitation Source Power-Supply Signal ADS129xR ADS129xR RESP_MODP RESP_DEMOD_EN RESP DEMOD VREFN DVDD Reference DRDY IN1P EMI Filter ΔΣ ADC1 PGA1 IN1N SPI IN2P EMI Filter PGA2 ΔΣ ADC2 EMI Filter PGA3 ΔΣ ADC3 PGA4 ΔΣ ADC4 PGA5 ΔΣ ADC5 CS SCLK DIN DOUT IN2N IN3P IN3N CLKSEL IN4P EMI Filter IN4N Oscillator Control CLK MUX GPIO1 IN5P ADS1296/6R/8/8R EMI Filter GPIO4/RCLKO GPIO3/RCLKO IN5N GPIO2 IN6P EMI Filter PGA6 ΔΣ ADC6 EMI Filter PGA7 ΔΣ ADC7 EMI Filter PGA8 RESP CLK IN6N PWDN IN7P ADS1298/8R RESET IN7N START IN8P ΔΣ ADC8 IN8N WCT C From Wmuxc B From Wmuxb A From Wmuxa PACE Amplifier 2 PACE Amplifier 1 G = 0.4 RLD Amplifier G = 0.4 WCT AVSS AVSS1 RLD RLD IN RE F RLD OUT RL D INV PACE OUT2 PACE OUT1 DGND Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 25 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3 Feature Description This section discusses the details of the ADS129x internal functional elements. The analog blocks are reviewed first, followed by the digital interface. Blocks implementing ECG-specific functions are covered at the end. Throughout this document, fCLK denotes the frequency of the signal at the CLK pin, tCLK denotes the period of the signal at the CLK pin, fDR denotes the output data rate, tDR denotes the time period of the output data, and fMOD denotes the modulator input sampling frequency. 9.3.1 Analog Functionality 9.3.1.1 EMI Filter An RC filter at the input acts as an EMI filter on all channels. The –3-dB filter bandwidth is approximately 3 MHz. 9.3.1.2 Analog Input Structure The analog input of the ADS129x is shown in Figure 24. AVDD INxP, INxN 5kW 10pF AVSS Figure 24. Analog Input Protection Circuit 26 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Feature Description (continued) 9.3.1.3 Input Multiplexer The ADS129x input multiplexers are very flexible and provide many configurable signal-switching options. Figure 25 shows the multiplexer on a single channel of the device. The device has eight blocks, one for each channel. TEST_PACE_OUT1, TEST_PACE_OUT2, and RLD_IN are common to all eight blocks. VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and subsystem diagnostics, calibration, and configuration. Select the switch settings for each channel by writing 1 to the appropriate values to the CHnSET[2:0] register (see the CHnSET register for details) and the RLD_MEAS bit in the CONFIG3 register (see the CONFIG3 register for details). More details of the ECG-specific features of the multiplexer are presented in the Input Multiplexer (Rerouting The Right Leg Drive Signal) subsection of the ECG-Specific Functions section. ADS129x MUX INT_TEST TESTP_PACE_OUT1 INT_TEST MUX[2:0] = 101 TestP TempP MvddP (1) MUX[2:0] = 100 MUX[2:0] = 011 From LoffP MUX[2:0] = 000 VINP MUX[2:0] = 110 EMI Filter To PgaP MUX[2:0] = 010 AND RLD_MEAS MUX[2:0] = 001 (AVDD + AVSS) 2 MUX[2:0] = 111 MUX[2:0] = 000 VINN RLDIN From LoffN MUX[2:0] = 001 To PgaN MUX[2:0] = 010 AND RLD_MEAS RLD_REF MvddN (1) TempN MUX[2:0] = 011 MUX[2:0] = 100 MUX[2:0] = 101 TestN INT_TEST TESTN_PACE_OUT2 INT_TEST (1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section. Figure 25. Input Multiplexer Block for One Channel Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 27 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) 9.3.1.3.1 Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD – AVSS) / 2 to both inputs of the channel. Use this setting to test the inherent noise of the device. 9.3.1.3.2 Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in subsystem verification at power up. This functionality allows the entire signal chain to be tested. Although the test signals are similar to the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance testing. Use register settings to control the test signals (see the CONFIG2: Configuration Register 2 (address = 02h) (reset = 40h) section for details). The TEST_AMP bit controls the signal amplitude, and the TEST_FREQ bits control switching at the required frequency. The test signals are multiplexed and transmitted out of the device at the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins. A bit register (CONFIG2.INT_TEST = 0) deactivates the internal test signals so that the test signal can be driven externally. This feature allows the calibration of multiple devices with the same signal. The test signal feature cannot be used in conjunction with the external hardware pace feature (see the External Hardware Approach section for details). 9.3.1.3.3 Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2) When hardware pace detection is not used, the TESTP_PACE_OUT1 and TESPN_PACE_OUT2 signals can be used as a multiplexed differential input channel. These inputs can be multiplexed to any of the eight channels. The performance of the differential input signal fed through these pins is identical to the normal channel performance. 9.3.1.3.4 Temperature Sensor (TempP, TempN) The ADS129x contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in Figure 26. The difference in current densities of the diodes yields a difference in voltage that is proportional to absolute temperature. Temperature Sensor Monitor AVDD 1x 2x To MUX TempP To MUX TempN 8x 1x AVSS Figure 26. Measurement of the Temperature Sensor in the Input As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal sensor tracks the PCB temperature closely. Self-heating of the ADS129x causes a higher reading than the temperature of the surrounding PCB. The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, scale the the temperature reading code to μV. Temperature (°C) = 28 Temperature Reading (mV) - 145,300 mV Submit Documentation Feedback 490 mV/°C + 25°C (1) Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Feature Description (continued) 9.3.1.3.5 Supply Measurements (MVDDP, MVDDN) Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) = [0.5 × (AVDD – AVSS)] For channels 3 and 4, (MVDDP – MVDDN) = DVDD / 4. To avoid saturating the PGA while measuring power supplies, set the gain to 1. For example, if AVDD = 2.5 V and AVSS = –2.5 V, then the measurement result is 2.5 V. 9.3.1.3.6 Lead-Off Excitation Signals (LoffP, LoffN) The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of the lead-off block, refer to the Lead-Off Detection section. 9.3.1.3.7 Auxiliary Single-Ended Input The RLD_IN pin is primarily used for routing the right leg drive (RLD) signal to any of the electrodes in case the RLD electrode falls off. However, the RLD_IN pin can be used as a multiple single-ended input channel. The signal at the RLD_IN pin can be measured with respect to the voltage at the RLD_REF pin using any of the eight channels. This measurement is done by setting the channel multiplexer setting to 010, and the RLD_MEAS bit of the CONFIG3 register to 1. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 29 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) 9.3.1.4 Analog Input The analog input to the ADS129x is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span between –VREF to VREF. The absolute range for INP and INN must be between AVSS – 0.3 V and AVDD + 0.3 V. See Table 13 for an explanation of the correlation between the analog input and the digital codes. As shown in Figure 27 and Figure 28, there are two general methods of driving the analog input of the ADS129x: single-ended or differential. INP and INN are 180° out-of-phase in the differential input method. When the input is single-ended, the INN input is held at the common-mode voltage (CM), preferably at midsupply. The INP input swings around the same common-mode voltage and the peak-to-peak amplitude swings from CM – VREF to CM + VREF. When the input is differential, the common-mode is given by (INP + INN) / 2. Both the INP and INN inputs swing from CM + ½ VREF to CM – ½ VREF. For optimal performance, use the ADS129x devices in a differential configuration. ±VREF to +VREF Device VREF Peak-to-Peak Device VREF Peak-to-Peak Common Voltage Common Voltage a) Single-Ended Input b) Differential Input Figure 27. Methods of Driving the ADS129x: Single-Ended or Differential CM + VREF +VREF INP CM Voltage ±VREF CM ± VREF INN = CM Voltage t Single-Ended Inputs CM + 1/2 VREF INP +VREF CM Voltage CM ± 1/2 VREF INN ±VREF t Differential Inputs Common-Mode Voltage (Differential Mode) = (INP) + (INN) , Common-Mode Voltage (Single-Ended Mode) = INN 2 Input Range (Differential Mode) = (AINP ± AINN) = 2 VREF Figure 28. Using the ADS129x in Single-Ended and Differential Input Modes 30 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.1.5 PGA Settings and Input Range The PGA is a differential input and differential output amplifier, as shown in Figure 29. The PGA has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that are set by writing to the CHnSET register (see the CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 00h) section). The ADS129x have CMOS inputs, and therefore have negligible current noise. Table 5 shows the typical values of bandwidths for various gain settings. Table 5 shows the small-signal bandwidth. From MuxP PGAp R2 50kΩ R1 20kΩ (for Gain = 6) To ADC R2 50kΩ PGAn From MuxN Figure 29. PGA Implementation Table 5. PGA Gain versus Small-Signal Bandwidth GAIN NOMINAL BANDWIDTH AT ROOM TEMPERATURE (kHz) 1 237 2 146 3 127 4 96 6 64 8 48 12 32 The resistor string of the PGA that implements the gain has 120 kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 31 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.1.5.1 Input Common-Mode Range The usable input common-mode range of the front end depends on various parameters, including the maximum differential input signal, supply voltage, PGA gain, and more. This range is described in Equation 2: æ Gain ´ VMAX _ DIFF ö æ Gain ´ VMAX _ DIFF ö AVDD - 0.2 V - çç ÷÷ > CM > AVSS + 0.2 V + çç ÷÷ 2 2 è ø è ø where • • VMAX_DIFF = maximum differential signal at the input of the PGA CM = common-mode range (2) For example, If VDD = 3 V, gain = 6, and VMAX_DIFF = 350 mV, then 1.25 V < CM < 1.75 V. 9.3.1.5.2 Input Differential Dynamic Range The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This range is shown in Equation 3. 2VREF ± VREF Full-Scale Range = = Gain Gain (3) The 3-V supply, with a reference of 2.4 V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300 mV. For higher dynamic range, use a 5-V supply with a reference of 4 V (set by the VREF_4V bit of the CONFIG3 register) to increase the differential dynamic range. 9.3.1.5.3 ADC Delta-Sigma Modulator Power Spectral Density (dB) Each channel of the ADS129x has a 24-bit, delta-sigma ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK / 4 for high-resolution (HR) mode and fMOD = fCLK / 8 for low-power (LP) mode. As in the case of any delta-sigma modulator, the noise of the ADS129x is shaped until fMOD / 2, as shown in Figure 30. Use the on-chip digital decimation filters, explained in the Digital Decimation Filter section, to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the delta-sigma converters drastically reduces the complexity of the analog antialiasing filters that are typically needed with Nyquist ADCs. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 0.001 0.01 0.1 Normalized Frequency (fIN/fMOD) 1 G001 Figure 30. Modulator Noise Spectrum up to 0.5 × fMOD 32 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.1.6 Reference Figure 31 shows a simplified block diagram of the ADS129x internal reference. The reference voltage is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS. 22mF VCAP1 R1 (1) Bandgap 2.4V or 4V R3 VREFP (1) 10mF R2 (1) VREFN AVSS To ADC Reference Inputs (1) For VREF = 2.4 V: R1 = 12.5 kΩ, R2 = 25 kΩ, and R3 = 25 kΩ. For VREF = 4 V: R1 = 10.5 kΩ, R2 = 15 kΩ, and R3 = 35 kΩ. Figure 31. Internal Reference The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG systems, choose capacitor values with a bandwidth that is limited to less than 10Hz, so that the reference noise does not dominate the system noise. When using a 3-V analog supply, set the internal reference to 2.4 V. For a 5-V analog supply, set the internal reference to 4 V by setting the VREF_4V bit in the CONFIG2 register. Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 32 shows a typical external reference drive circuitry. Power down is controlled by the PD_REFBUF bit in the CONFIG3 register. By default, the device wakes up in external reference mode. 100 k 22 nF +5 V 0.1 F 10 OPA350 100 5V VIN 10 F OUT 10 F 0.1 F To VREFP Pin 100 F REF5025 1 F TRIM Figure 32. External Reference Driver Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 33 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.1.7 ECG-Specific Functions 9.3.1.7.1 Input Multiplexer (Rerouting The Right Leg Drive Signal) The input multiplexer has ECG-specific functions for the right leg drive (RLD) signal. The RLD signal is available at the RLDOUT pin after the appropriate channels are selected for the RLD derivation, feedback elements are installed external to the chip, and the loop is closed. This signal can be fed after filtering, or fed directly into the RLDIN pin as shown in Figure 33. Multiplex the RLDIN signal into any one of the input electrodes by setting the mux bits of the appropriate channel set registers to 110 for P-side or 111 for N-side. Figure 33 shows the RLD signal generated from channels 1, 2, and 3 routed to the N-side of channel 8. Use this feature to dynamically change the electrode that is used as the reference signal to drive the patient body. The corresponding channel cannot be used and can be powered down. RLD_SENSP[0] = 1 IN1P EMI Filter PGA1 RLD_SENSN[0] = 1 MUX1[2:0] = 000 IN1N RLD_SENSP[1] = 1 IN2P EMI Filter PGA2 RLD_SENSN[1] = 1 MUX2[2:0] = 000 IN2N RLD_SENSP[2] = 1 IN3P EMI Filter PGA3 RLD_SENSN[2] = 1 MUX3[2:0] = 000 ¼ ¼ ¼ IN3N RLD_SENSP[7] = 0 IN8P EMI Filter PGA8 MUX8[2:0] = 111 RLD_SENSN[7] = 0 IN8N MUX (AVDD + AVSS)/2 ADS1298 RLDIN RLDREF_INT RLDREF_INT RLDREF Filter or Feedthrough RLD_AMP RLDOUT 1MW 1.5nF (1) RLDINV (1) (1) Typical values for example only. Figure 33. Example of RLDOUT Signal Configured to be Routed to IN8N 34 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.1.7.2 Input Multiplexer (Measuring The Right Leg Drive Signal) The RLDOUT signal can also be routed to a channel (that is not used for the calculation of RLD) for measurement. Figure 34 shows the register settings to route the RLDIN signal to channel 8. The measurement is done with respect to the voltage on the RLDREF pin. If RLDREF is set to internal, it is at (AVDD + AVSS) / 2. This feature is useful for debugging purposes during product development. RLD_SENSP[0] = 1 IN1P EMI Filter PGA1 RLD_SENSN[0] = 1 MUX1[2:0] = 000 IN1N RLD_SENSP[1] = 1 IN2P EMI Filter PGA2 RLD_SENSN[1] = 1 MUX2[2:0] = 000 IN2N RLD_SENSP[2] = 1 IN3P EMI Filter PGA3 RLD_SENSN[2] = 1 MUX3[2:0] = 000 ¼ ¼ ¼ IN3N RLD_SENSP[7] = 0 IN8P EMI Filter PGA8 MUX8[2:0] = 010 RLD_SENSN[7] = 0 IN8N MUX RLDREF_INT (AVDD + AVSS)/2 RLDREF_INT MUX8[2:0] = 010 AND RLD_MEAS = 1 RLD_AMP ADS1298 RLD_IN RLD_REF Filter or Feedthrough RLD_OUT 1MW 1.5nF (1) RLD_INV (1) (1) Typical values for example only. Figure 34. RLDOUT Signal Configured to be Read Back by Channel 8 Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 35 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.1.7.3 Wilson Central Terminal (WCT) and Chest Leads In the standard 12-lead ECG, WCT voltage is defined as the average of right arm (RA), left arm (LA), and left leg (LL) electrodes. This voltage is used as the reference voltage for the measurement of the chest leads. The ADS129x has three integrated low-noise amplifiers that generate the WCT voltage. Figure 35 shows the block diagram of the implementation. IN1P IN1N IN2P IN2N IN3P IN3N IN4P IN4N To Channel PGAs 8:1 MUX 8:1 MUX 30kΩ WCT2[2:0] WCT2[5:3] WCT1[2:0] WCTa 8:1 MUX WCTb WCTc 30kΩ 30kΩ WCT 80pF ADS1294/6/8 AVSS Figure 35. WCT Voltage These devices provide the flexibility to route any one of the eight signals (IN1P to IN4N) to each of the amplifiers to generate the average. This flexibility allows the RA, LA, and LL electrodes to be connected to any input of the first four channels, depending on the lead configuration. Each of the three amplifiers in the WCT circuitry can be powered down individually with register settings. By powering up two amplifiers, the average of any two electrodes is generated at the WCT pin. Powering up one amplifier provides the buffered electrode voltage at the WCT pin. The WCT amplifiers have limited drive strength, and thus, should be buffered if used to drive a low-impedance load. Table 6 shows the typical WCT performance when using any 1, 2, or 3 of the WCT buffers. Table 6. Typical WCT Performance 36 PARAMETER ANY ONE (A, B, or C) ANY TWO (A+B, A+C, or B+C) ALL THREE (A+B+C) UNIT Integrated noise 540 382 312 nVRMS Power 53 59 65 μW –3-dB BW 30 59 89 kHz Slew rate BW limited BW limited BW limited V/μs Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 As shown in Table 6, the overall noise reduces when more than one WCT amplifier is powered up. This noise reduction is a result of the fact that noise is averaged by the passive summing network at the output of the amplifiers. Powering down individual buffers gives negligible power savings because a significant portion of the circuitry is shared between the three amplifiers. The bandwidth of the WCT node is limited by the RC network. The internal summing network consists of three 30-kΩ resistors and a 80-pF capacitor. For optimal performance, add an external 100-pF capacitor. The effective bandwidth depends on the number of amplifiers that are powered up, as shown in Table 6. Only use the WCT node to drive very high input impedances (typically greater than 500 MΩ). A typical application connects this WCT signal to the negative inputs of a ADS129x for use as a reference signal for the chest leads. As mentioned, all three WCT amplifiers can be connected to one of eight analog input pins. The inputs of the amplifiers are chopped, and the chop frequency varies with the data rates of the ADS129x. The chop frequency for the three highest data rates scale 1:1. For example, at a 32-kSPS data rate, the chop frequency is 32 kHz in HR mode with WCT_CHOP = 0. The chop frequency of the four lower data rates is fixed at 4 kHz. When WCT_CHOP = 1, the chop frequency is fixed to highest data rate frequency (that is, fMOD / 16), as shown in Table 7. The chop frequency appears at the output of the WCT amplifiers as a small square wave riding on dc. The amplitude of the square wave is the offset of the amplifier and is typically 5 mVPP. As a result of out-of-band chopping, this artifact does not interfere with ECG-related measurements. As a result of the chopping function, the input current leakage on the pins with the connected WCT amplifiers increases at higher data rates and as the input common voltage swings closer to 0 V (AVSS), as described in Figure 36. If the output of a channel connected to the WCT amplifier (for example, the V-lead channels) is connected to one of the pace amplifiers for external pace detection, the chopping artifact appears at the pace amplifier output. 200 DR = 0.5kSPS, 0.25kSPS DR = 1kSPS DR = 2kSPS DR = 4kSPS DR = 8kSPS DR = 16kSPS DR = 32kSPS 180 160 140 120 100 WCT Input Leakage Current (pA) WCT Input Leakage Current (pA) 200 80 60 40 20 TA = +25°C 0 0.3 0.8 1.3 1.8 2.3 LP Mode HR Mode 180 160 140 120 100 80 60 40 20 TA = +25°C 0 0.3 2.8 Input Common-Mode Voltage (V) 0.8 1.3 1.8 2.3 2.8 Input Common-Mode Voltage (V) Figure 36. WCT Input Leakage Current vs Input Voltage (WCT_CHOP = 0) Figure 37. WCT Input Leakage Current vs Input Voltage (WCT_CHOP = 1) Table 7. WCT Amplifiers Chop Frequency CONFIG1.DR[2:0] BIT CONFIG2.WCT_CHOP = 0 000 fMOD/16 fMOD/16 001 fMOD / 32 fMOD / 16 010 fMOD / 64 fMOD / 16 011 fMOD / 128 fMOD / 16 100 fMOD / 128 fMOD / 16 101 fMOD / 128 fMOD / 16 110 fMOD / 128 fMOD / 16 Copyright © 2010–2015, Texas Instruments Incorporated CONFIG2.WCT_CHOP = 1 Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 37 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.1.7.3.1 Augmented Leads In a typical implementation of the 12-lead ECG with eight channels, the augmented leads are calculated digitally. In certain applications, it may be required that all leads are derived in analog rather than digital. The ADS1298 and ADS1298R provide the option to generate the augmented leads by routing appropriate averages to channels 5, 6, and 7. The same three amplifiers that are used to generate the WCT signal are also used to generate the Goldberger central terminal (GCT) signals. Figure 38 shows an example of generating the augmented leads in analog domain. In this implementation, more than eight channels are used to generate the standard 12 leads. This feature is not available in the ADS1294, ADS1294R, ADS1296 and ADS1296R. IN1P IN1N IN2P IN2N IN3P IN3N IN4P IN4N To Channel PGAs 8:1 MUX WCTb 8:1 MUX WCT2[2:0] WCT2[5:3] WCT1[2:0] WCTa 8:1 MUX WCTc avF_ch4 ADS1298 avF_ch6 avF_ch5 avF_ch7 IN5P IN5N IN6P IN6N IN7P IN7N To Channel PGAs Figure 38. Analog Domain Augmented Leads 9.3.1.7.3.2 Right Leg Drive with the WCT Point In certain applications, the out-of-phase version of the WCT is used as the RLD reference. The ADS1298 provides the option to have a buffered version of the WCT terminal at the RLD_OUT pin. This signal can be inverted in phase using an external amplifier and then used as the right leg drive. Refer to the Right Leg Drive (RLD DC Bias Circuit) section for more details. 38 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.1.7.4 Lead-Off Detection Patient electrode impedances decay over time; therefore, these electrode connections must be continuously monitored to verify that a suitable connection is present. The ADS129x lead-off detection functional block provides significant flexibility to choose from various lead-off detection strategies. Although called lead-off detection, this feature is in fact electrode-off detection. The basic principle is to inject an excitation signal and measure the response to determine if the electrode is off. As shown in the lead-off detection functional block diagram in Figure 39, this circuit provides two different methods of determining the state of the patient electrode. The methods differ in the frequency content of the excitation signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENSP and LOFF_SENSN registers. The internal excitation circuitry can be disabled while the sensing circuitry is enabled. AVDD AVSS FLEAD_OFF[1:0] Vx FLEAD_OFF[1:0] 10pF 10pF 7MΩ 7MΩ (AVDD + AVSS)/2 3.3MΩ Patient Skin, Electrode Contact Model Patient Protection Resistor 12pF 3.3MΩ 12pF 3.3MΩ 3.3MΩ 3.3MΩ Anti-Aliasing Filter < 512kHz 3.3MΩ 47nF 51kΩ LOFF_STATP 100kΩ LOFF_SENSP AND VLEAD_OFF_EN LOFF_SENSN AND VLEAD_OFF_EN VINP 51kΩ 100kΩ EMI Filter LOFF_SENSP AND VLEAD_OFF_EN 47nF 47nF 51kΩ VINN AVDD PGA LOFF_SENSN AND VLEAD_OFF_EN AVSS To ADC LOFF_STATN 4-Bit DAC COMP_TH[2:0] 100kΩ RLD OUT Figure 39. Lead-Off Detection Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 39 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.1.7.4.1 DC Lead-Off In this approach, the lead-off excitation is accomplished with a dc signal. Choose a dc excitation signal from either a pullup or pulldown resistor, or from a current source or sink system, as shown in Figure 40. Select by setting the VLEAD_OFF_EN bit in the LOFF register. One side of the channel is pulled to supply, and the other side is pulled to ground. Swap the pullup resistor and pulldown resistor by setting the bits in the LOFF_FLIP register, as shown in Figure 41. If using a current source or sink, set the magnitude of the current by using the ILEAD_OFF[1:0] bits in the LOFF register. The current source or sink gives larger input impedance compared to the 10-MΩ pullup or pulldown resistor. AVDD AVDD AVDD ADS129x AVDD ADS129x ADS129x ADS129x 10MW 10MW INP INP INP PGA INN 10MW INP PGA PGA INN INN PGA INN 10MW 10MW a) Pull-Up/Pull-Down Resistors b) Current Source Figure 40. DC Lead-Off Excitation Options a) LOFF_FLIP = 0 10MW a) LOFF_FLIP = 1 Figure 41. LOFF_FLIP Usage Response sensing is achieved either by looking at the digital output code from the device, or by monitoring the input voltages with on-chip comparators. If either of the electrodes is off, the pullup or pulldown resistors saturate the channel. Look at the output code to determine if either the P-side or the N-side is off. To pinpoint which side is off, check the comparator outputs. During conversion, the input voltage is simultaneously monitored by using a comparator and a 4-bit DAC with levels that are set by the COMP_TH[2:0] bits in the LOFF register. The comparator outputs are stored in the LOFF_STATP and LOFF_STATN registers. These two registers are available as a part of the output data stream (see the Data Output Pin (DOUT) section). If dc lead-off is not used, the lead-off comparators can be powered down by setting the PD_LOFF_COMP bit in the CONFIG4 register. An example procedure to turn on dc lead-off is given in the Lead-Off section. 9.3.1.7.4.2 AC Lead-Off This method uses an out-of-band ac signal for excitation. The ac signal is generated by providing pullup and pulldown resistors at the input with a fixed frequency. The ac signal is passed through an antialiasing filter to prevent aliasing. Select the frequency with the FLEAD_OFF[1:0] bits in the LOFF register. The excitation frequency is a function of the output data rate and is fDR / 4. This out-of-band excitation signal is passed through the channel and measured at the output. AC signal sensing is achieved by passing the signal through the channel to digitize the signal, and measuring the output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of the excitation signal at the output spectrum, the lead-off status is calculated. Therefore, the ac lead-off detection is accomplished simultaneously with the ECG signal acquisition. 40 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.1.7.5 RLD Lead-Off Determine if the RLD electrode is connected in the ADS129x by powering down the RLD amplifier. After power down, there are two measurement procedures to determine the RLD electrode connect status: a pullup or pulldown resistor, or a sink or source current source, as shown in Figure 42. Set the reference level of the comparator to determine the acceptable RLD impedance threshold. Patient Skin, Electrode Contact Model Patient Protection Resistor To ADC input (through VREF connection to any of the channels). 47nF 51kW RLD_STAT 100kW RLD_SENS AND RLD_SENS AND VLEAD_OFF_EN VLEAD_OFF_EN ILGND_OFF[1:0] AVSS AVSS Figure 42. RLD Lead-Off Detection at Power Up The current source, or pullup or pulldown resistor method has no function when the RLD amplifier is powered on. Use the comparator to sense the voltage at the output of the RLD amplifier. The comparator threshold is set by the same LOFF[7:5] bits that are used to set the thresholds for the other negative inputs. 9.3.1.7.6 Right Leg Drive (RLD) DC Bias Circuit Use the right leg drive (RLD) circuitry to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode voltage of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted commonmode signal. The negative feedback loop restricts the common-mode movement to a narrow range, depending on the loop gain. Stabilizing the entire loop is specific to the individual system, based on the various poles in the loop. The ADS129x incorporate muxes that are used to select the channel to the operational amplifier. All the amplifier terminals are available at the pins, allowing selection of the components for the feedback loop. The circuit shown in Figure 43 shows the overall functional connectivity for the RLD bias circuit. Set the reference voltage for the RLD to be generated internally ([AVDD + AVSS] / 2), or provided externally with a resistive divider. The selection of an internal versus external reference voltage for the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the CONFIG3 register. If the RLD function is not used, power down the amplifier using the PD_RLD bit (see the CONFIG3: Configuration Register 3 (address = 03h) (reset = 40h) section for details). This bit is also used in daisy-chain mode to power down all but one of the RLD amplifiers. The functionality of the RLDIN pin is explained in the Input Multiplexer section. An example procedure to use the RLD amplifier is shown in the Right Leg Drive section of the Power-Supply Recommendations. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 41 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 From MUX1P www.ti.com RLD1P 220kW PGA1P 50kW 220kW RLD2P PGA2P 20kW 50kW From MUX2P 50kW 20kW 220kW PGA1N From MUX1N RLD1N From MUX3P RLD3P 50kW 220kW PGA2N From MUX2N RLD2N 220kW PGA3P 50kW 220kW RLD4P PGA4P 20kW 50kW From MUX4P 50kW 20kW 220kW PGA3N From MUX3N RLD3N From MUX5P RLD5P 50kW 220kW PGA4N RLD4N From MUX4N RLD6P From MUX6P 220kW PGA5P 50kW 220kW PGA6P 20kW 50kW 50kW 20kW 220kW PGA5N From MUX5N RLD5N From MUX7P RLD7P 50kW 220kW PGA6N From MUX6N RLD6N 220kW PGA7P 50kW 220kW RLD8P PGA8P 20kW 50kW From MUX8P 50kW 20kW 220kW PGA7N From MUX7N RLD7N PGA8N RLDINV (1) CEXT 1.5nF RLD8N (1) REXT 1MW RLDOUT 50kW 220kW RLD Amp From MUX8N (AVDD + AVSS)/2 RLDREF_INT RLDREF RLDREF_INT (1) Typical values. (2) When CONFIG3 bit RLDREF_INT = 0, the RLDREF_INT switch is closed and the RLDREF_INT switch is open. When CONFIG3 bit RLDREF_INT = 1, the RLDREF_INT switch is open and the RLDREF_INT switch is closed. Figure 43. RLD Channel Selection 42 Submit Documentation Feedback (2) Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.1.7.6.1 WCT as RLD In certain applications, the RLD is derived as the average of RA, LA, and LL. This level is the same as the WCT voltage. The WCT amplifier has limited drive strength; therefore, only use the WCT to drive very high impedances directly. The ADS129x provide an option to internally buffer the WCT signal by setting the WCT_TO_RLD bit in the CONFIG4 register. Short the RLD_OUT and RLD_INV pins external to the device. Before the RLD_OUT signal is connected to the RLD electrode, use an external amplifier to invert the phase of the signal for negative feedback. ADS129x RLD_INV RLD_OUT RLD Amp RLD (AVDD + AVSS)/2 RLDREF_INT RLD_REF From WCT Amplifiers WCT_TO_RLD RLD_REF RLDREF_INT WCT Figure 44. Using the WCT as the Right Leg Drive (RLD) 9.3.1.7.6.2 RLD Configuration with Multiple Devices Figure 45 shows multiple devices connected to an RLD. RLDIN RLD REF VA1-8 VA1-8 RLD OUT RLDINV Device 1 Power-Down RLDIN RLD REF VA1-8 VA1-8 RLD OUT RLDINV To Input MUX Device 2 To Input MUX To Input MUX Device N Power-Down VA1-8 VA1-8 RLDIN RLD REF RLD OUT RLDINV Figure 45. RLD Connection for Multiple Devices Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 43 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.1.7.7 Pace Detect The ADS129x provide flexibility for pace detection by using either software or external hardware. The software approach is made possible by providing sampling rates up to 32 kSPS. The external hardware approach is made possible by bringing out the output of the PGA at two pins: TESTP_PACE_OUT1 and TESTN_PACE_OUT2. If the WCT amplifier is connected to the signal path, switching noise occurs as a result of chopping; see the Wilson Central Terminal (WCT) and Chest Leads section for details. 9.3.1.7.7.1 Software Approach To use the software approach, operate the device at 8 kSPS or more to capture the fastest pulse. Afterwards, digital signal processing is used to identify the presence of the pacemaker pulse. The software approach gives the utmost flexibility to program the pace detect threshold on-the-fly (dynamically) using software. This flexibility is increasingly important as pacemakers evolve over time. Two parameters must be considered while measuring fast pace pulses: 1. PGA bandwidth: determines the gain setting that can be used; shown in Table 5. 2. Settling time: determines the operating data rate for the device. For a step change in input, the digital decimation filter takes 3 × tDR to settle. 9.3.1.7.7.2 External Hardware Approach One of the drawbacks of using the software approach is that all channels on a single device must operate at higher data rates. For systems where high data rates are a problem, the ADS129x provide the option of connecting external hardware to the output of the PGA to detect the presence of the pulse. The output of the pace detection logic is then fed into the device through one of the GPIO pins. The GPIO data are transmitted through the SPI port and loaded 2 tCLKs before DRDY goes low. Two of the eight channels are selected using register bits in the PACE register: one from the odd-numbered channels, and the other from the even-numbered channels. During the differential to single-ended conversion, there is an attenuation of 0.4; therefore, the total gain in the pace path is equal to (0.4 × PGA_GAIN). The pace output signals are multiplexed with the TESTP and TESTN signals through the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins, respectively. Channel selection is achieved by setting bits[4:1] of the PACE register. If the pace circuitry is not used, turn off the pace amplifiers by using the PD_PACE bit in the PACE register. If the output of a channel connected to the WCT amplifier (for example, the V-lead channels) is connected to one of the pace amplifiers for external pace detection, chopping artifacts appear at the pace amplifier output. See the Wilson Central Terminal (WCT) and Chest Leads section for more details. 44 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 PACE[4:3] PACE[2:1] From MUX1P 00 PGA1P 50kΩ 00 PGA2P 20kΩ From MUX2P 50kΩ 50kΩ 20kΩ PGA1N From MUX1N 00 From MUX3P 01 50kΩ PGA2N 00 From MUX2N 01 From MUX4P PGA3P 50kΩ PGA4P 20kΩ 50kΩ 50kΩ 20kΩ PGA3N From MUX3N 01 From MUX5P 10 50kΩ PGA4N 01 From MUX4N 10 From MUX6P PGA5P 50kΩ PGA6P 20kΩ 50kΩ 50kΩ 20kΩ PGA5N From MUX5N 10 From MUX7P 11 50kΩ PGA6N From MUX6N 10 PGA7P 50kΩ 11 PGA8P 20kΩ From MUX8P 50kΩ 50kΩ 20kΩ PGA7N From MUX7N 11 50kΩ (AVDD + AVSS) PGA8N 2 From MUX8N 11 200kΩ 500kΩ PDB_PACE TESTN_PACE_OUT2 PACE Amp 500kΩ GPIO1 (1) PACE_IN (GPIO1) 200kΩ (AVDD + AVSS) 2 200kΩ 500kΩ PDB_PACE TESTP_PACE_OUT1 PACE Amp 500kΩ 200kΩ (1) GPIO1 can be used as the PACE_IN signal. Figure 46. Hardware Pace Detection Option Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 45 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.1.7.8 Respiration As shown in Table 8, the ADS129xR provide three options for respiration impedance measurement: external respiration, internal respiration using on-chip modulation signals, and internal respiration using user-generated modulation signals. The ADS129x provides only external respiration impedance measurement. Table 8. Respiration Control RESP.RESP_CTRL[1] RESP.RESP_CTRL[0] 0 0 Respiration disabled ADS129x, ADS129xR 0 1 Generates modulation and demodulation signals for external respiration circuitry. RESP_CLK signals on GPIO2, GPIO3, and GPIO4. ADS129x, ADS129xR 1 0 Respiration measurement using internally-generated RESP_MOD signals. 1 1 Respiration measurement using user-generated modulation and blocking signal. (1) DESCRIPTION MODE AVAILABLE ADS129xR ADS129xR (1) Do not set RESP_CTRL[1:0] = 11 if CLKSEL = 1 (internal master clock). For more information on respiration impedance measurement, see Respiration Rate Measurement Using Impedance Pneumography, SBAA181. 9.3.1.7.8.1 External Respiration Circuitry (RESP_CTRL = 01b) With this option, GPIO2, GPIO3, and GPIO4 are automatically configured as outputs. The phase relationship between the signals is shown in Figure 47. GPIO2 is the exclusive-OR of GPIO3 and GPIO4, as shown in Figure 48. GPIO3 is the modulation signal, and GPIO4 is the demodulation signal. While using this option, the general-purpose pin functions of GPIO2, GPIO3, and GPIO4 are not available. The modulation frequency is set to either 64 kHz or 32 kHz by using the RESP_FREQ[2:0] bits in the CONFIG4 register. The remaining bit options of RESP_FREQ[2:0] generate square waves on GPIO3 and GPIO4. The exclusive-OR out on GPIO2 is only available in 64-kHz or 32-kHz. The phase of GPIO4, relative to GPIO3, is set by RESP_PH[2:0] bits in the RESP register. Use this option to implement custom respiration impedance circuitry external to the ADS129x. CLK (2.048MHz) (Modulation Clock) GPIO3 tPHASE Modulation Clock GPIO4 (Demodulation Clock) GPIO4 Respiration Modulation Generator tBLKDLY (Blocking Signal) GPIO2 Demodulation Clock GPIO3 GPIO2 RESP_PH[2:0] Figure 47. External Respiration (RESP_CTRL = 01b) Timing Figure 48. External Respiration (RESP_CTRL = 01b) Block Diagram Table 9. Switching Characteristics for Figure 47 (1) 2.7 V ≤ DVDD ≤ 3.6 V PARAMETER tPHASE Respiration phase delay, set by RESP.RESP_PH[2:0] tBLKDLY Modulation clock rising edge to XOR signal (1) Specifications apply from –40°C to 85°C. 46 Submit Documentation Feedback MIN TYP 22.5 1.65 V ≤ DVDD ≤ 2 V MAX MIN 157.5 22.5 TYP 1 5 MAX UNIT 157.5 Degrees ns Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.1.7.8.2 Internal Respiration Circuitry with Internal Clock (RESP_CTRL = 10b, ADS129xR Only) Figure 49 shows a block diagram of the internal respiration circuitry. The internal modulation and demodulator circuitry can be selectively used. The modulation block is controlled by the RESP_MOD_EN bit and the demodulation block is controlled by the RESP_DEMOD_EN bit. The modulation signal is a square wave of magnitude VREFP – AVSS. Using this option, the output of the modulation circuitry is available at the RESP_MODP and RESP_MODN pins of the device. This availability allows custom filtering to be added to the square-wave modulation signal. Using this option, GPIO2, GPIO3, and GPIO4 can be used for other purposes. The modulation frequency is either 64 kHz or 32 kHz, as set by the RESP_FREQ[2:0] bits in the CONFIG4 register. The phase of the internal demodulation signal is set by the RESP_PH[2:0] bits in the RESP register. When this respiration option is enabled, ADS129xR channel 1 cannot be used to acquire ECG signals. If the RA and LA leads are intended to measure respiration and ECG signals, wire the two leads into channel 1 for respiration and channel 2 for ECG signals. CLK Demodulation Clock Modulation Block RESP_CTRL[1:0] RESP_CTRL[1:0] Blocking Mod. Clock RESP_MODN Modulation Clock Respiration Clock Generator RESP_MODP I/O GPIO3 I/O GPIO4 I/O GPIO2 IN1P EMI Filter MUX Ch1 PGA Demodulation Block Ch1 ADC IN1N Figure 49. Internal Respiration Block Diagram 9.3.1.7.8.3 Internal Respiration Circuitry With User-Generated Signals (RESP_CTRL = 11b, ADS129xR Only) In this mode GPIO2, GPIO3, and GPIO4 are automatically configured as inputs and cannot be used for other purposes. The signals must be provided as described in Figure 50. Do not use the internal master clock in this mode. (Modulation Clock) GPIO4 tPHASE tBLKDLY GPIO2 (Blocking Signal) Figure 50. Internal Respiration (RESP_CTRL = 11b) Timing Diagram Table 10. Swtiching Characteristics for Figure 50 (1) 1.65 V ≤ DVDD ≤ 3.6V PARAMETER tPHASE Respiration phase delay tBLKDLY Modulation clock rising edge to XOR signal (1) MIN TYP 0 MAX 157.5 0 UNIT Degrees 5 ns Specifications apply from –40°C to 85°C. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 47 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.3.2 Digital Functionality 9.3.2.1 GPIO Pins (GPIO[4:1]) The ADS129x have a total of four general-purpose digital input/output (GPIO) pins available in normal operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits of the GPIO register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the GPIOD bit sets the output value. If configured as inputs, these pins must be driven; do not float these pins. The GPIO pins are set as inputs after power-on or after a reset. Figure 51 shows the GPIO port structure. If not used, short these pins to DGND. For example, one configuration is to use GPIO1 as the PACEIN signal, multiplex GPIO2 with RESP_BLK signal, multiplex GPIO3 with the RESP signal, and multiplex GPIO4 with the RESP_PH signal. GPIO Data (read) GPIO Pin GPIO Data (write) GPIO Control Figure 51. GPIO Port Pin 9.3.2.2 Power-Down Pin (PWDN) When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wakeup. During power down, shut down the external clock to save power. 9.3.2.3 Reset (RESET Pin and Reset Command) There are two methods to reset the ADS129x: pull the RESET pin low, or send the RESET opcode command (see the RESET: Reset Registers to Default Values section). Take the RESET pin low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. At reset, 18 tCLK cycles are required to complete initialization of the configuration registers to the default states and start the conversion cycle. For more information, see the RESET: Reset Registers to Default Values section. An internal reset is automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to new values with a WREG command. 48 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.3.2.4 Digital Decimation Filter The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs are made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in ECG applications to implement software pace detection and ac lead-off detection. The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters is adjusted by the DR bits in the CONFIG1 register (see Table 16 for details). This setting is a global setting that affects all channels; therefore, in these devices, all channels operate at the same data rate. 9.3.2.4.1 Sinc Filter Stage (sinx / x) The sinc filter is a variable-decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter. Equation 4 shows the scaled Z-domain transfer function of the sinc filter. ½H(z)½ = 3 1 - Z-N 1 - Z-1 (4) The frequency-domain transfer function of the sinc filter is shown in Equation 5. 3 Npf fMOD sin ½H(f)½ = N ´ sin pf fMOD where • N = decimation ratio (5) 0 0 -20 -0.5 -40 -1 Gain (dB) Gain (dB) The sinc filter has notches (or zeroes) that occur at the output data rate multiples. At these frequencies, the filter has infinite attenuation. Figure 52 shows the frequency response of the sinc filter and Figure 53 shows the rolloff of the sinc filter. With a step change at input, the filter requires 3 × tDR conversion cycles to settle. After a rising edge of the START pin or completion of the START command, the filter takes tSETTLE periods to give the first data output. The settling time of the filters at various data rates are discussed in the Start Mode subsection of the SPI Interface section. Figure 54 and Figure 55 show the filter transfer function to fMOD / 2 and fMOD / 16, respectively, at different data rates. Figure 56 shows the transfer function extended out to 4 × fMOD. As shown in the figures, the passband of the ADS129x repeats itself at every fMOD muiltple. Choose input R-C antialiasing filters for the system that sufficiently attenuate any interference in frequencies around multiples of fMOD. -60 -80 -1.5 -2 -100 -2.5 -120 -3 -140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Normalized Frequency (fIN / fDR) Figure 52. Sinc Filter Frequency Response Copyright © 2010–2015, Texas Instruments Incorporated 5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Normalized Frequency (fIN / fDR) Figure 53. Sinc Filter Roll-Off Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 49 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 0 0 DR[2:0] = 110 DR[2:0] = 110 -20 -20 DR[2:0] = 000 DR[2:0] = 000 -40 Gain (dB) Gain (dB) -40 -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 0.01 Normalized Frequency (fIN/fMOD) Figure 54. Transfer Function of On-Chip Decimation Filters to fMOD / 2 10 0.02 0.03 0.04 0.05 0.06 0.07 Normalized Frequency (fIN/fMOD) DR[2:0] = 000 Figure 55. Transfer Function of On-Chip Decimation Filters to fMOD / 16 DR[2:0] = 110 -10 Gain (dB) -30 -50 -70 -90 -110 -130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (fIN/fMOD) Figure 56. Transfer Function of On-Chip Decimation Filters to 4 × fMOD for DR[2:0] = 000 and DR[2:0] = 110 9.3.2.5 Clock The ADS129x provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. The accuracy varies over the specified temperature range; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit. Use the CLKSEL pin to select either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 11. Use the CLK_EN bit is when multiple devices are connected in a daisy-chain configuration. During power down, shut down the external clock to save power. Table 11. CLKSEL Pin and CLK_EN Bit 50 CLKSEL PIN CONFIG1.CLK_EN BIT CLOCK SOURCE CLK PIN STATUS 0 X External clock Input: external clock 1 0 Internal clock oscillator Tri-state 1 1 Internal clock oscillator Output: internal clock oscillator Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.4 Device Functional Modes 9.4.1 Data Acquisition This section describes the data acquisition process in relation to the START and DRDY pins, settled data, and data readback. 9.4.1.1 Start Mode Pull the START pin high for at least 2 tCLK periods, or send the START command to begin conversions. When the START pin is low, or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to begin conversions, hold the START pin low. The ADS129x feature two modes to control conversion: continous and single-shot. The mode is selected by SINGLE_SHOT (bit 3 of the CONFIG4 register). In multiple device configurations, the START pin is used to synchronize devices (see the MultipleDevice Configuration section for more details). 9.4.1.1.1 Settling Time The settling time (tSETTLE) is the time it takes for the converter to output fully-settled data when the START signal is pulled high. When the START pin is pulled high, or when the START command is sent, the device ADCs convert the input signals and DRDY is pulled high. The next falling edge of DRDY indicates that data are ready. Figure 57 shows the timing diagram and Table 12 shows the settling time for different data rates as a function of tCLK. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). START § § § § DIN START DRDY tSETTLE Figure 57. Settling Time for Initial Conversion Table 12. Settling Times for Different Data Rates (tSETTLE) DR[2:0] SETTLING TIME (tCLK Periods) HIGH-RESOLUTION MODE LOW-POWER MODE 000 296 584 001 584 1160 010 1160 2312 011 2312 4616 100 4616 9224 101 9224 18440 110 18440 36872 Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 51 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com When the START pin is held high and there is a step change in the input signal, 3 × tDR conversion cycles are required for the filter to settle to the new value, as shown in Figure 58. Settled data are available on the fourth DRDY pulse. This settling time must be considered when trying to measure narrow pace pulses for pace detection. Data are available to read at each DRDY high-to-low transition, but can be ignored. START Input Transient § Analog Input DRDY 4 x tDR Figure 58. Settling Time for Input Transient 9.4.1.2 Data Ready Pin (DRDY) DRDY is an output. When DRDY transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. Regardless of the status of the CS signal, a rising edge on SCLK pulls DRDY high. Thus, when using multiple devices in the SPI bus, gate SCLK with CS. The behavior of DRDY depends on if the device is in RDATAC mode or if the RDATA command is being used to read data on demand. See the RDATAC: Read Data Continuous and RDATA: Read Data sections for further details. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. Use the START pin or the START command to place the device either in normal data capture mode or pulse data capture mode. Figure 59 shows the relationship among DRDY, DOUT, and SCLK during data retrieval (in the case of an ADS129x with a selected data rate that gives 24-bit resolution). DOUT latches at the rising edge of SCLK. The device pulls DRDY high at the first falling edge of SCLK, regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. The data starts from the MSB of the status word and then proceeds to the ADC channel data in sequential order (that is, channel 1, channel 2, ..., channel x). Channels that are powered down still have a position in the data stream; however, the data are not valid and can be ignored. CS DRDY SCLK DOUT MSB MSB-1 MSB-2 Figure 59. DRDY with Data Retrieval (CS = 0) 52 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 The DRDY signal is cleared on the first SCLK falling edge, regardless of the state of CS. Even if no data are clocked out, the DRDY signal is still cleared. Take this condition into consideration if the SPI bus is used to communicate with other devices on the same bus. Figure 60 shows a timing diagram for this multiplexing. CS DRDY SCLK Figure 60. DRDY and SCLK Behavior for SPI Bus Multiplexing 9.4.1.3 Data Retrieval Data retrieval is accomplished in one of two methods: 1. RDATAC: the read data continuous command sets the device mode that reads data continuously without sending opcodes. See the RDATAC: Read Data Continuous section for more details. 2. RDATA: the read data command reads just one data output from the device. See the RDATA: Read Data section for more details. See the SPI Command Definitions section for more details. The conversion data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. Keep DIN low for the entire read operation. 9.4.1.3.1 Status Word The ADS129x data readback is preceded by a status word that provides information on the state of the ADC. The status word is 24 bits long and contains the values for LOFF_STATP, LOFF_STATN, and part of the GPIO registers. The content alignment is shown in Figure 61. LOFF_STATP[7:0] GPIO[7:4] LOFF_STATN[7:0] § § 0 § 0 § § 1 § 1 § § DOUT § SCLK Figure 61. Status Word Content 9.4.1.3.2 Readback Length The number of bits in the data output depends on the number of channels and the number of bits per channel. The data format for each channel data is twos complement and MSB first. For the ADS129x with 32-kSPS and 64-kSPS data rates, the number of data bits is 24 status bits + 16 bits per channel × 8 channels = 152 bits. For all other data rates, the number of data bits is 24 status bits + 24 bits per channel × 8 channels = 216 bits. When channels are powered down using the user-register setting, the corresponding channel output is set to 0. However, the sequence of channel outputs remains the same. The ADS1294 outputs four channels of datam and the ADS1296 outputs six channels of data. The ADS129x also provide a multiple-readback feature. Set the DAISY_IN bit in the CONFIG1 register to 1 for multiple readbacks. Simply provide additional SCLKs to read data multiple times; the MSB data byte repeats after reading the last byte. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 53 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.4.1.3.3 Data Format The ADS129x output 24 bits of data per channel in binary twos complement format, MSB first. The LSB has a weight of VREF / (223 – 1). A positive full-scale input produces an output code of 7FFFFFh and the negative fullscale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 13 summarizes the ideal output codes for different input signals. For DR[2:0] = 000 and 001, the device has only 17 and 19 bits of resolution, respectively. The last seven (in 17-bit mode) or five (in 19-bit mode) bits can be ignored. Table 13. Ideal Output Code versus Input Signal (1) INPUT SIGNAL, VIN (INxP – INxN) IDEAL OUTPUT CODE (2) ≥ VREF 7FFFFFh VREF / (223 – 1) 000001h 0 000000h 23 –VREF / (2 – 1) ≤ –VREF (223 / (223 – 1)) (1) (2) FFFFFFh 800000h Only valid for 24-bit resolution data rates, with gain = 1. Excludes effects of noise, linearity, offset, and gain error. 9.4.1.4 Single-Shot Mode Enable single-shot mode by setting the SINGLE_SHOT bit in CONFIG4 register to 1. In single-shot mode, the ADS129x perform a single conversion when the START pin is taken high, or when the START opcode command is sent. As seen in Figure 62, when a conversion completes, DRDY goes low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To begin a new conversion, take the START pin low and then back high for at least two tCLKs, or transmit the START opcode again. When switching from continous conversion mode to single-shot mode, make sure the START signal is pulsed, or issue a STOP command followed by a START command. START tSETTLE 4 / fCLK Data Updating 4 / fCLK DRDY Figure 62. DRDY With No Data Retrieval in Single-Shot Mode Single-shot conversion mode is provided for applications that require nonstandard or noncontinuous data rates. Issue a START command or toggle the START pin high to reset the digital filter, effectively dropping the data rate by a factor of four. This mode leaves the system more susceptible to aliasing effects, thus requiring more complex analog or digital filtering. Loading on the host processor increases because it must toggle the START pin or send a START command to initiate a new conversion cycle. 54 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.4.1.5 Continuous Conversion Mode Conversions begin when the START pin is taken high for at least two tCLKs, or when the START opcode command is sent. As seen in Figure 63, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete. Figure 64 and Table 14 show the required timing of DRDY to the START pin and the START and STOP opcode commands when controlling conversions in this mode. To keep the converter running continuously, permanently tie the START pin high. When switching from single-shot mode to continousconversion mode, pulse the START signal or a issue a STOP command followed by a START command. This conversion mode is ideal for applications that require a continuous stream of conversions results. START Pin or or (1) DIN (1) START Opcode STOP Opcode tDR tSETTLE DRDY (1) START and STOP opcode commands take effect on the seventh SCLK falling edge. Figure 63. Continuous Conversion Mode tSDSU DRDY and DOUT tDSHD START Pin or STOP Opcode (1) STOP(1) STOP(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission. Figure 64. START to DRDY Timing Table 14. Timing Requirements for Figure 64 (1) MIN MAX UNIT tSDSU START pin low or STOP opcode to DRDY setup time to halt further conversions 16 tCLK tDSHD START pin low or STOP opcode to complete current conversion 16 tCLK (1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 55 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.4.2 Multiple-Device Configuration The ADS129x provide configuration flexibility when multiple devices are connected in a system. The serial interface typically requires four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal per device, multiple devices can be connected together. The number of signals required to interface n devices is 3 + n. Daisy-chain the RLD amplifiers as explained in the RLD Configuration with Multiple Devices section. To use the internal oscillator in a daisy-chain configuration, set one of the devices as the master for the clock source with the internal oscillator enabled (CLKSEL pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit to 1. Use this master device clock as the external clock source for the other devices. When using multiple devices, synchronize the devices with the START signal. The delay from the START signal to the DRDY signal is fixed for a fixed data rate (see the Start Mode section for more details on the settling times). As an example, Figure 65 shows the behavior of two devices when synchronized with the START signal. There are two configurations used to connect multiple devices with a optimal number of interface pins: cascade or daisy-chain. ADS12981 START CLK START1 DRDY DRDY1 CLK ADS12982 START2 DRDY DRDY2 CLK CLK START DRDY1 DRDY2 Figure 65. Synchronizing Multiple Converters 56 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.4.2.1 Cascade Configuration Figure 66(a) shows a configuration with two devices cascaded together. One of the devices is an ADS1298 (eight channels) and the other is an ADS1294 (four channels). Together, they create a system with 12 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the majority of applications. 9.4.2.2 Daisy-Chain Configuration Enable daisy-chain mode by setting the DAISY_EN bit in the CONFIG1 register. Figure 66(b) shows the daisychain configuration. In this configuration, SCLK, DIN, and CS are shared across multiple devices. Connect the DOUT pin of the first device to the DAISY_IN pin of the next device, thereby creating a chain. Issue one extra SCLK between each data set. Note that when using daisy-chain mode, the multiple readback feature is not available. Short the DAISY_IN pin to digital ground if not used. Figure 2 describes the required timing for the ADS1298 shown in Figure 67. Data from the ADS1298 appear first on DOUT, followed by a don’t care bit, and finally by the status and data words from the ADS1294. START (1) CLK START CLK START INT DRDY CS (1) START CLK GPO0 DRDY CLK INT CS GPO GPO1 ADS1298 (Device 1) SCLK SCLK MOSI ADS1298 (Device 1) SCLK DIN DIN SCLK MOSI DOUT MISO DAISY_IN1 DOUT1 MISO Host Processor START Host Processor DOUT2 DRDY CLK CS SCLK SCLK CLK DIN ADS1294 (Device 2) DRDY CS START DIN ADS1294 (Device 2) DOUT DAISY_IN2 b) Daisy-Chain Configuration a) Cascaded Configuration (1) 0 To reduce pin count, set the START pin low and use the START opcode command to synchronize and start conversions. Figure 66. Multiple Device Configurations DOUT1 DAISY_IN0 1 SCLK DOUT LSB1 MSB1 0 2 3 216 LSB0 MSB0 Data from first device (ADS1298) 219 218 217 XX MSB1 338 LSB1 Data from second device (ADS1294) Figure 67. Daisy-Chain Timing for Figure 66(b) Important reminders when using daisy-chain mode: 1. Issue one extra SCLK between each data set (see Figure 67). 2. All devices are configured to the same register values because CS is shared. 3. Device register readback (RREG) is only valid for device 0 in the daisy chain. Only conversion data can be read from device 1 to device N, where N is the last device in the chain; register data cannot be read. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 57 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com If all devices in the chain operate in the same register setting, DIN can be shared, thereby reducing the SPI communication signals to four, regardless of the number of devices. However, the individual devices cannot be programmed; therefore, the RLD driver cannot be shared among the multiple devices. Furthermore, an external clock must be used. As shown in Figure 2, the SCLK rising edge shifts data out of the ADS129x on DOUT. The SCLK rising edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK rate speed, but it also makes the interface sensitive to board-level signal delays. The more devices in the chain, the more challenging it becomes to adhere to setup and hold times. A star-pattern connection of SCLK to all devices, minimizing length of DOUT, and other PCB layout techniques help. Placing delay circuits such as buffers between DOUT and DAISY_IN is another way to mitigate this challenge. One other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. In addition, note that daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries. The maximum number of daisy-chained devices depends on the data rate at which the device is operated. The maximum number of devices can be estimated with Equation 6: fSCLK NDEVICES = fDR (NBITS)(NCHANNELS) + 24 where • • NBITS = device resolution (depends on data rate) NCHANNELS = number of channels in the device (4, 6, or 8) (6) For example, when the ADS1298 (eight-channel, 24-bit version) is operated at a 2-kSPS data rate with a 4-MHz fSCLK, up to ten devices can be daisy-chained. 58 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.5 Programming 9.5.1 SPI Interface The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls the ADS129x operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available. 9.5.1.1 Chip Select Pin (CS) Chip select (CS) selects the ADS129x devices for SPI communication. While CS is low, the serial interface is active. CS must remain low for the entire duration of the serial communication. After the serial communication is finished, always wait four or more tCLK periods before taking CS high. When CS is taken high, the serial interface resets, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low. While ADS129x is selected, the device attempts to decode and execute commands every eight serial clocks. If the device ceases to execute serial commands, it is possible extra clock pulses were presented that placed the serial interface into an unknown state. To reset the serial interface to a known state, take CS high and back low again. 9.5.1.2 Serial Clock (SCLK) SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from the device. The serial clock (SCLK) features a Schmitt-triggered input, and clocks data on the DIN and DOUT pins into and out of the ADS129x. Even though the input has hysteresis, keep SCLK as clean as possible to prevent glitches from accidentally forcing a clock event. The absolute maximum limit for SCLK is specified in the Timing Requirements: Serial Interface table. While ADS129x is selected (CS = low), the device attempts to decode and execute commands every eight serial clocks. Therefore, present multiples of eight SCLKs every serial transfer to keep the interface in a normal operating mode. If the interface ceases to function because of extra serial clocks, reset by toggling CS high and back low. For a single device, the minimum speed required for SCLK depends on the number of channels, number of bits of resolution, and output data rate. For multiple cascaded devices, see the Cascade Configuration section. Equation 7 shows the calculation for minimum SCLK speed. tSCLK < (tDR – 4tCLK) / (NBITS × NCHANNELS + 24) (7) For example, if the ADS1298 is used at 500-SPS (eight channels, 24-bit resolution), the minimum SCLK speed is 110 kHz. Retrieve data either by putting the device in RDATAC mode or by issuing a RDATA command for data on demand. The SCLK rate limitation of Equation 7 also applies to RDATAC. For the RDATA command, the limitation applies if data must be read between two consecutive DRDY signals. Equation 7 assumes that there are no other commands issued between data captures. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 59 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Programming (continued) 9.5.1.2.1 SCLK Clocking Methods As shown in Figure 68, there are two different SCLK clocking methods to satisfy the decode timing specification shown in Figure 1 for multiple-byte commands. For SCLK speeds that meet the tSDECODE timing requirement shown in Figure 1, transmit SCLK in a continuous stream when CS is low. This method is not to be confused with a free-running SCLK, where SCLK operates when CS is high. Free-running SCLK operation is not supported by this device. For faster SCLK speeds that do not meet the tSDECODE timing requirement, SCLK is transmitted in 8-bit bursts with a delay between bursts. The absolute maximum SCLK limit is specified in the Timing Requirements: Serial Interface table. Figure 68 shows the difference between the two SCLK clocking methods for this device. CS Continuous Stream Method SCLK CS Burst Method SCLK Figure 68. SCLK Clocking Methods 9.5.1.3 Data Input Pin (DIN) The data input pin (DIN) is used along with SCLK to communicate with the ADS129x (opcode commands and register data). The device latches data on DIN on the falling edge of SCLK. 9.5.1.4 Data Output Pin (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS129x. Data on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available. Use this feature to minimize the number of connections between the device and the system controller. Figure 69 shows the data output protocol for ADS1298. DRDY CS SCLK 216 SCLKs DOUT STAT CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 24-Bit 24-Bit 24-Bit 24-Bit 24-Bit 24-Bit 24-Bit 24-Bit 24-Bit DIN Figure 69. SPI Bus Data Output for the ADS1298 (Eight Channels) 60 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Programming (continued) 9.5.2 SPI Command Definitions The ADS129x provide flexible configuration control. The opcode commands, summarized in Table 15, control and configure the operation of the ADS129x. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data. CS can be taken high or held low between opcode commands, but must stay low for the entire command operation (especially for multibyte commands). System opcode commands and the RDATA command are decoded by the ADS129x on the seventh falling edge of SCLK. The register read and write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing requirements when pulling CS high after issuing a command. Table 15. Opcode Command Definitions COMMAND DESCRIPTION FIRST BYTE SECOND BYTE SYSTEM COMMANDS WAKEUP Wakeup from standby mode 0000 0010 (02h) — STANDBY Enter standby mode 0000 0100 (04h) — RESET Reset the device 0000 0110 (06h) — START Start/restart (synchronize) conversions 0000 1000 (08h) — STOP Stop conversion 0000 1010 (0Ah) — DATA READ COMMANDS RDATAC Enable Read Data Continuous mode. This mode is the default mode at power up. (1) 0001 0000 (10h) — SDATAC Stop Read Data Continuously mode 0001 0001 (11h) — RDATA Read data by command; supports multiple read back. 0001 0010 (12h) — REGISTER READ COMMANDS RREG WREG (1) (2) Read n nnnn registers starting at address r rrrr 001r rrrr (2xh) (2) 000n nnnn (2) Write n nnnn registers starting at address r rrrr (2) 000n nnnn (2) 010r rrrr (4xh) When in RDATAC mode, the RREG command is ignored. n nnnn = number of registers to be read/written – 1. For example, to read/write three registers, set n nnnn = 0 (0010). r rrrr = starting register address for read/write opcodes. 9.5.2.1 WAKEUP: Exit Standby Mode The WAKEUP opcode exits low-power standby mode; see the STANDBY: Enter Standby Mode section. Time is required when exiting standby mode (see the Electrical Characteristics for details). There are no restrictions on the SCLK rate for this command; issue this command at any time. Any subsequent command must be sent after 4 tCLK cycles. 9.5.2.2 STANDBY: Enter Standby Mode The STANDBY opcode command enters low-power standby mode. All parts of the circuit are shut down except for the reference section. Standby mode power consumption is specified in the Electrical Characteristics. There are no restrictions on the SCLK rate for this command; issue this command at any time. Send a WAKEUP command to return device to normal operation. Serial interface is active; therefore, register read and write commands are permitted while in this mode. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 61 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.5.2.3 RESET: Reset Registers to Default Values The RESET command resets the digital filter cycle and returns all register settings to the respective default values. See the Reset (RESET Pin and Reset Command) section for more details. There are no restrictions on the SCLK rate for this command; issue this command at any time. 18 tCLK cycles are required to execute the RESET command. Do not send any commands during this time. 9.5.2.4 START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command, there must be a gap of 4 tCLK cycles between the two commands. When the START opcode is sent to the device, keep the START pin low until the STOP command is issued. (See the Start Mode subsection of the SPI Interface section for more details.) There are no restrictions on the SCLK rate for this command and it can be issued any time. 9.5.2.5 STOP: Stop Conversions The STOP opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command; issue this command at any time. 9.5.2.6 RDATAC: Read Data Continuous The RDATAC opcode enables the output of conversion data on each DRDY without the need to issue subsequent read data opcodes. This opcode places the conversion data in the output register where it may be shifted out directly. The read data continuous mode is the default mode of the device and the device defaults to this mode on power up and reset. RDATAC mode is cancelled by the stop read data continuous command (SDATAC). If the device is in RDATAC mode, an SDATAC command must be issued before any other commands can be sent to the device. There is no restriction on the SCLK rate for this command. However, subsequent data retrieval SCLKs or the SDATAC opcode command must wait at least 4 tCLK cycles. As shown in Figure 70, the timing for RDATAC illustrates the keep-out zone of 4 tCLK periods around the DRDY pulse when this command cannot be issued. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from the device after RDATAC command is issued, make sure that either the START pin is high or the START command is issued. Figure 70 shows the recommended way to use the RDATAC command. RDATAC is ideally suited for applications such as data loggers or recorders, where registers are set once and do not need to be reconfigured. START DRDY CS SCLK tUPDATE RDATAC Opcode DIN Hi-Z DOUT Status Register + 8-Channel Data (216 Bits) (1) Next Data tUPDATE = 4 / fCLK (where fCLK = 1 / tCLK). Do not read data during this time. Figure 70. RDATAC Usage 62 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.5.2.7 SDATAC: Stop Read Data Continuous This SDATAC opcode command cancels read data continuous (RDATAC) mode. There is no restriction on the SCLK rate for this command, but the next command must wait for 4 tCLK cycles. 9.5.2.8 RDATA: Read Data Issue the RDATA command after DRDY goes low to read the conversion result (in SDATAC mode). There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make sure that either the START pin is high or the START command is issued. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 71 shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type systems, where register settings must be read or changed often between conversion cycles. START DRDY CS SCLK RDATA Opcode DIN RDATA Opcode Hi-Z DOUT Status Register+ 8-Channel Data (216 Bits) Figure 71. RDATA Usage 9.5.2.9 Sending Multibyte Commands The ADS129x serial interface decodes commands in bytes, and requires 4 tCLK periods to decode and execute. Therefore, when sending multibyte commands, a 4 tCLK period must separate the end of one byte (or opcode) and the next. For example, if CLK is 2.048 MHz, then tSDECODE (4 × tCLK) is 1.96 µs. When SCLK is 16 MHz, the maximum transfer speed for one byte is 500 ns. This byte transfer time does not meet the tSDECODE specification; therefore, a delay must be inserted so that the end of the second byte arrives 1.46 µs later. However, if SCLK is 4 MHz, one byte is transferred in 2 µs. Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without delay. In the second scenario, the serial port can be programmed to use multiplebyte transfers instead of the single-byte transfers required to meet the timing of the first scenario . Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 63 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.5.2.10 RREG: Read From Register The RREG opcode command reads register data. The RREG command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1. First opcode byte: 001r rrrr, where r rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1. The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 72. When the device is in read data continuous mode, it is necessary to issue a SDATAC command before a RREG command can be issued. An RREG command can be issued any time. However, because this command is a multibyte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) section for more details. CS must be low for the entire command. CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA DOUT REG DATA + 1 Figure 72. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register) (OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001) 9.5.2.11 WREG: Write to Register The WREG opcode command writes register data. The WREG command is a two-byte opcode followed by the input of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to write – 1. First opcode byte: 010r rrrr, where r rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1. After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 73. The WREG command can be issued any time. However, because this command is a multibyte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) section for more details. CS must be low for the entire command. CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2 DOUT Figure 73. WREG Command Example: Write Two Registers Starting from 00h (ID Register) (OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001) 64 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6 Register Maps Table 16 lists the various ADS129x registers. Table 16. Register Assignments ADDRESS RESET VALUE (Hex) REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DEV_ID7 DEV_ID6 DEV_ID5 1 0 DEV_ID2 DEV_ID1 DEV_ID0 DEVICE SETTINGS (READ-ONLY REGISTERS) 00h ID xx GLOBAL SETTINGS ACROSS CHANNELS 01h CONFIG1 06 HR DAISY_EN CLK_EN 0 0 DR2 DR1 DR0 02h CONFIG2 40 0 0 WCT_CHOP INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 03h CONFIG3 40 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_ SENS RLD_STAT 04h LOFF 00 COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_ EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 CHANNEL-SPECIFIC SETTINGS 05h CH1SET 00 PD1 GAIN12 GAIN11 GAIN10 0 MUX12 MUX11 MUX10 06h CH2SET 00 PD2 GAIN22 GAIN21 GAIN20 0 MUX22 MUX21 MUX20 07h CH3SET 00 PD3 GAIN32 GAIN31 GAIN30 0 MUX32 MUX31 MUX30 08h CH4SET 00 PD4 GAIN42 GAIN41 GAIN40 0 MUX42 MUX41 MUX40 09h CH5SET (1) 00 PD5 GAIN52 GAIN51 GAIN50 0 MUX52 MUX51 MUX50 0Ah CH6SET (1) 00 PD6 GAIN62 GAIN61 GAIN60 0 MUX62 MUX61 MUX60 0Bh CH7SET (1) 00 PD7 GAIN72 GAIN71 GAIN70 0 MUX72 MUX71 MUX70 0Ch CH8SET (1) 00 PD8 GAIN82 GAIN81 GAIN80 0 MUX82 MUX81 MUX80 0Dh RLD_SENSP (2) 00 RLD8P (1) RLD7P (1) RLD6P (1) RLD5P (1) RLD4P RLD3P RLD2P RLD1P 0Eh RLD_SENSN (2) 00 RLD8N (1) RLD7N (1) RLD6N (1) RLD5N (1) RLD4N RLD3N RLD2N RLD1N 0Fh LOFF_SENSP (2) 00 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P 10h LOFF_SENSN (2) 00 LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N 11h LOFF_FLIP 00 LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1 LEAD-OFF STATUS REGISTERS (READ-ONLY REGISTERS) 12h LOFF_STATP 00 IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF 13h LOFF_STATN 00 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF GPIO AND OTHER REGISTERS (1) (2) 14h GPIO 0F GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 15h PACE 00 0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE 16h RESP 00 RESP_ DEMOD_EN1 RESP_MOD_ EN1 1 RESP_PH2 RESP_PH1 RESP_PH0 RESP_CTRL1 RESP_CTRL0 17h CONFIG4 00 RESP_FREQ2 RESP_FREQ1 RESP_FREQ0 0 SINGLE_ SHOT WCT_TO_ RLD PD_LOFF_ COMP 0 18h WCT1 00 aVF_CH6 aVL_CH5 aVR_CH7 avR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0 19h WCT2 00 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0 CH5SET and CH6SET are not available for the ADS1294 and ADS1294R. CH7SET and CH8SET registers are not available for the ADS1294, ADS1294R, ADS1296, and ADS1296R. The RLD_SENSP, PACE_SENSP, LOFF_SENSP, LOFF_SENSN, and LOFF_FLIP registers bits[5:4] are not available for the ADS1294 and ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1296, ADS1294R, and ADS1296R. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 65 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1 Register Descriptions The read-only ID control register is programmed during device manufacture to indicate device characteristics. 9.6.1.1 ID: ID Control Register (address = 00h) (reset = xxh) Figure 74. ID Control Register 7 6 DEV_ID[7:5] R-x 5 4 1 3 0 2 R-2h 1 DEV_ID[2:0] R-x 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17. ID Control Register Field Descriptions 66 Bit Field Type Reset Description 7:5 DEV_ID[7:5] R xh Device ID These bits indicate the device family. 000 = Reserved 011 = Reserved 100 = ADS129x device family 101 = Reserved 110 = ADS129xR device family 111 = Reserved 4:3 RESERVED R 2h Reserved Always read back 2h 2:0 DEV_ID[2:0] R xh Channel ID These bits indicates number of channels. 000 = 4-channel ADS1294 or ADS1294R 001 = 6-channel ADS1296 or ADS1296R 010 = 8-channel ADS1298 or ADS1298R 011 = Reserved 111 = Reserved Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) (reset = 06h) Figure 75. CONFIG1: Configuration Register 1 7 HR R/W-0h 6 DAISY_EN R/W-0h 5 CLK_EN R/W-0h 4 0 3 0 2 1 DR[2:0] R/W-6h R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. Configuration Register 1 Field Descriptions Bit (1) Field Type Reset Description 7 HR R/W 0h High-resolution or low-power mode This bit determines whether the device runs in low-power or high-resolution mode. 0 = LP mode 1 = HR mode 6 DAISY_EN R/W 0h Daisy-chain or multiple readback mode This bit determines which mode is enabled. 0 = Daisy-chain mode 1 = Multiple readback mode 5 CLK_EN R/W 0h CLK connection (1) This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1. 0 = Oscillator clock output disabled 1 = Oscillator clock output enabled 4:3 RESERVED R/W 0h Reserved Always write 0h 2:0 DR[2:0] R/W 6h Output data rate For High-Resolution mode, fMOD = fCLK / 4. For low power mode, fMOD = fCLK / 8. These bits determine the output data rate of the device. 000: fMOD / 16 (HR Mode: 32 kSPS, LP Mode: 16 kSPS) 001: fMOD / 32 (HR Mode: 16 kSPS, LP Mode: 8 kSPS) 010: fMOD / 64 (HR Mode: 8 kSPS, LP Mode: 4 kSPS) 011: fMOD / 128 (HR Mode: 4 kSPS, LP Mode: 2 kSPS) 100: fMOD / 256 (HR Mode: 2 kSPS, LP Mode: 1 kSPS) 101: fMOD / 512 (HR Mode: 1 kSPS, LP Mode: 500 SPS) 110: fMOD / 1024 (HR Mode: 500 SPS, LP Mode: 250 SPS) 111: Reserved (do not use) Additional power is consumed when driving external devices. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 67 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) (reset = 40h) Configuration register 2 configures the test signal generation. See the Input Multiplexer section for more details. Figure 76. CONFIG2: Configuration Register 2 7 0 6 0 R/W-1h 5 WCT_CHOP R/W-0h 4 INT_TEST R/W-0h 3 0 R/W-0h 2 TEST_AMP R/W-0h 1 0 TEST_FREQ[1:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19. Configuration Register 2 Field Descriptions Bit Field Type Reset Description 7:6 RESERVED R/W 1h Reserved Always write 0h 5 WCT_CHOP R/W 0h WCT chopping scheme This bit determines whether the chopping frequency of WCT amplifiers is variable or fixed. 0 = Chopping frequency varies, see Table 7 1 = Chopping frequency constant at fMOD / 16 4 INT_TEST R/W 0h TEST source This bit determines the source for the test signal. 0 = Test signals are driven externally 1 = Test signals are generated internally 3 RESERVED R/W 0h Reserved Always write 0h 2 TEST_AMP R/W 0h Test signal amplitude These bits determine the calibration signal amplitude. 0 = 1 × –(VREFP – VREFN) / 2400 V 1 = 2 × –(VREFP – VREFN) / 2400 V TEST_FREQ[1:0] R/W 0h Test signal frequency These bits determine the calibration signal frequency. 00 = Pulsed at fCLK / 221 01 = Pulsed at fCLK / 220 10 = Not used 11 = At dc 1:0 68 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) (reset = 40h) Configuration register 3 configures multireference and RLD operation. Figure 77. CONFIG3: Configuration Register 3 7 PD_REFBUF 6 1 5 VREF_4V 4 RLD_MEAS 3 RLDREF_INT 2 PD_RLD R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h 1 RLD_LOFF_SE NS R/W-0h 0 RLD_STAT R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20. Configuration Register 3 Field Descriptions Bit Field Type Reset Description 7 PD_REFBUF R/W 0h Power-down reference buffer This bit determines the power-down reference buffer state. 0 = Power-down internal reference buffer 1 = Enable internal reference buffer 6 RESERVED R/W 1h Reserved Always write 1h 5 VREF_4V R/W 0h Reference voltage This bit determines the reference voltage, VREFP. 0 = VREFP is set to 2.4 V 1 = VREFP is set to 4 V (use only with a 5-V analog supply) 4 RLD_MEAS R/W 0h RLD measurement This bit enables RLD measurement. The RLD signal may be measured with any channel. 0 = Open 1 = RLD_IN signal is routed to the channel that has the MUX_Setting 010 (VREF) 3 RLDREF_INT R/W 0h RLDREF signal This bit determines the RLDREF signal source. 0 = RLDREF signal fed externally 1 = RLDREF signal (AVDD – AVSS) / 2 generated internally 2 PD_RLD R/W 0h RLD buffer power This bit determines the RLD buffer power state. 0 = RLD buffer is powered down 1 = RLD buffer is enabled 1 RLD_LOFF_SENS R/W 0h RLD sense function This bit enables the RLD sense function. 0 = RLD sense is disabled 1 = RLD sense is enabled 0 RLD_STAT R 0h RLD lead-off status This bit determines the RLD status. 0 = RLD is connected 1 = RLD is not connected Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 69 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.5 LOFF: Lead-Off Control Register (address = 04h) (reset = 00h) The lead-off control register configures the lead-off detection operation. Figure 78. LOFF: Lead-Off Control Register 7 6 COMP_TH2[2:0] R/W-0h 5 4 VLEAD_OFF_E N R/W-0h 3 2 ILEAD_OFF[1:0] 1 0 FLEAD_OFF[1:0] R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21. Lead-Off Control Register Field Descriptions 70 Bit Field Type Reset Description 7:5 COMP_TH[2:0] R/W 0h Lead-off comparator threshold Comparator positive side 000 = 95% 001 = 92.5% 010 = 90% 011 = 87.5% 100 = 85% 101 = 80% 110 = 75% 111 = 70% Comparator negative side 000 = 5% 001 = 7.5% 010 = 10% 011 = 12.5% 100 = 15% 101 = 20% 110 = 25% 111 = 30% 4 VLEAD_OFF_EN R/W 0h Lead-off detection mode This bit determines the lead-off detection mode. 0 = Current source mode lead-off 1 = pullup or pulldown resistor mode lead-off 3:2 ILEAD_OFF[1:0] R/W 0h Lead-off current magnitude These bits determine the magnitude of current for the current lead-off mode. 00 = 6 nA 01 = 12 nA 10 = 18 nA 11 = 24 nA 1:0 FLEAD_OFF[1:0] R/W 0h Lead-off frequency These bits determine the frequency of lead-off detect for each channel. 00 = When any bits of the LOFF_SENSP or LOFF_SENSN registers are turned on, make sure that FLEAD[1:0] are either set to 01 or 11 01 = AC lead-off detection at fDR / 4 10 = Do not use 11 = DC lead-off detection turned on Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.6 CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 00h) The CH[1:8]SET control register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels. Figure 79. CHnSET: Individual Channel Settings Register 7 PDn R/W-0h 6 5 GAINn[2:0] R/W-0h 4 3 0 R/W-0h 2 1 MUXn[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22. Individual Channel Settings (n = 1 to 8) Field Descriptions Bit Field Type Reset Description 7 PDn R/W 0h Power-down This bit determines the channel power mode for the corresponding channel. 0 = Normal operation 1 = Channel power-down. When powering down a channel, TI recommends that the channel be set to input short by setting the appropriate MUXn[2:0] = 001 of the CHnSET register. 6:4 GAINn[2:0] R/W 0h PGA gain These bits determine the PGA gain setting. 000 = 6 001 = 1 010 = 2 011 = 3 100 = 4 101 = 8 110 = 12 3 RESERVED R/W 0h Reserved Always write 0h MUXn[2:0] R/W 0h Channel input These bits determine the channel input selection. 000 = Normal electrode input 001 = Input shorted (for offset or noise measurements) 010 = Used in conjunction with RLD_MEAS bit for RLD measurements. See the Right Leg Drive (RLD) DC Bias Circuit subsection of the ECG-Specific Functions section for more details. 011 = MVDD for supply measurement 100 = Temperature sensor 101 = Test signal 110 = RLD_DRP (positive electrode is the driver) 111 = RLD_DRN (negative electrode is the driver) 2:0 Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 71 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.7 RLD_SENSP: RLD Positive Signal Derivation Register (address = 0Dh) (reset = 00h) This register controls the selection of the positive signals from each channel for right leg drive (RLD) derivation. See the Right Leg Drive (RLD) DC Bias Circuit section for details. Registers bits[5:4] are not available for the ADS1294 or ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R. Figure 80. RLD_SENSP: RLD Positive Signal Derivation Register 7 RLD8P R/W-0h 6 RLD7P R/W-0h 5 RLD6P R/W-0h 4 RLD5P R/W-0h 3 RLD4P R/W-0h 2 RLD3P R/W-0h 1 RLD2P R/W-0h 0 RLD1P R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23. RLD Positive Signal Derivation Field Descriptions Bit 72 Field Type Reset Description 7 RLD8P R/W 0h IN8P to RLD Route channel 8 positive signal into RLD derivation 0: Disabled 1: Enabled 6 RLD7P R/W 0h IN7P to RLD Route channel 7 positive signal into RLD derivation 0: Disabled 1: Enabled 5 RLD6P R/W 0h IN6P to RLD Route channel 6 positive signal into RLD derivation 0: Disabled 1: Enabled 4 RLD5P R/W 0h IN5P to RLD Route channel 5 positive signal into RLD derivation 0: Disabled 1: Enabled 3 RLD4P R/W 0h IN4P to RLD Route channel 4 positive signal into RLD derivation 0: Disabled 1: Enabled 2 RLD3P R/W 0h IN3P to RLD Route channel 3 positive signal into RLD derivation 0: Disabled 1: Enabled 1 RLD2P R/W 0h IN2P to RLD Route channel 2 positive signal into RLD channel 0: Disabled 1: Enabled 0 RLD1P R/W 0h IN1P to RLD Route channel 1 positive signal into RLD channel 0: Disabled 1: Enabled Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.8 RLD_SENSN: RLD Negative Signal Derivation Register (address = 0Eh) (reset = 00h) This register controls the selection of the negative signals from each channel for right leg drive derivation. See the Right Leg Drive (RLD) DC Bias Circuit section for details. Registers bits[5:4] are not available for the ADS1294 and ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R. Figure 81. RLD_SENSN: RLD Negative Signal Derivation Register 7 RLD8N R/W-0h 6 RLD7N R/W-0h 5 RLD6N R/W-0h 4 RLD5N R/W-0h 3 RLD4N R/W-0h 2 RLD3N R/W-0h 1 RLD2N R/W-0h 0 RLD1N R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24. RLD Negative Signal Derivation Field Descriptions Bit Field Type Reset Description 7 RLD8N R/W 0h IN8N to RLD Route channel 8 negative signal into RLD derivation 0: Disabled 1: Enabled 6 RLD7N R/W 0h IN7N to RLD Route channel 7 negative signal into RLD derivation 0: Disabled 1: Enabled 5 RLD6N R/W 0h IN6N to RLD Route channel 6 negative signal into RLD derivation 0: Disabled 1: Enabled 4 RLD5N R/W 0h IN5N to RLD Route channel 5 negative signal into RLD derivation 0: Disabled 1: Enabled 3 RLD4N R/W 0h IN4N to RLD Route channel 4 negative signal into RLD derivation 0: Disabled 1: Enabled 2 RLD3N R/W 0h IN3N to RLD Route channel 3 negative signal into RLD derivation 0: Disabled 1: Enabled 1 RLD2N R/W 0h IN2N to RLD Route channel 2 negative signal into RLD derivation 0: Disabled 1: Enabled 0 RLD1N R/W 0h IN1N to RLD Route channel 1 negative signal into RLD derivation 0: Disabled 1: Enabled Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 73 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.9 LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h) This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection section for details. The LOFF_STATP register bits are only valid if the corresponding LOFF_SENSP bits are set to 1. Registers bits[5:4] are not available for the ADS1294 or ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R. Figure 82. LOFF_SENSP: Positive Signal Lead-Off Detection Register 7 LOFF8P R/W-0h 6 LOFF7P R/W-0h 5 LOFF6P R/W-0h 4 LOFF5P R/W-0h 3 LOFF4P R/W-0h 2 LOFF3P R/W-0h 1 LOFF2P R/W-0h 0 LOFF1P R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25. Positive Signal Lead-Off Detection Field Descriptions Bit 74 Field Type Reset Description 7 LOFF8P R/W 0h IN8P lead off Enable lead-off detection on IN8P 0: Disabled 1: Enabled 6 LOFF7P R/W 0h IN7P lead off Enable lead-off detection on IN7P 0: Disabled 1: Enabled 5 LOFF6P R/W 0h IN6P lead off Enable lead-off detection on IN6P 0: Disabled 1: Enabled 4 LOFF5P R/W 0h IN5P lead off Enable lead-off detection on IN5P 0: Disabled 1: Enabled 3 LOFF4P R/W 0h IN4P lead off Enable lead-off detection on IN4P 0: Disabled 1: Enabled 2 LOFF3P R/W 0h IN3P lead off Enable lead-off detection on IN3P 0: Disabled 1: Enabled 1 LOFF2P R/W 0h IN2P lead off Enable lead-off detection on IN2P 0: Disabled 1: Enabled 0 LOFF1P R/W 0h IN1P lead off Enable lead-off detection on IN1P 0: Disabled 1: Enabled Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h) This register selects the negative side from each channel for lead-off detection. See the Lead-Off Detection section for details. The LOFF_STATN register bits are only valid if the corresponding LOFF_SENSN bits are set to 1. Registers bits[5:4] are not available for the ADS1294 or ADS1294R. Bits[7:6] are not available for the ADS1294, ADS1294R, ADS1296, or ADS1296R. Figure 83. LOFF_SENSN: Negative Signal Lead-Off Detection Register 7 LOFF8N R/W-0h 6 LOFF7N R/W-0h 5 LOFF6N R/W-0h 4 LOFF5N R/W-0h 3 LOFF4N R/W-0h 2 LOFF3N R/W-0h 1 LOFF2N R/W-0h 0 LOFF1N R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26. Negative Signal Lead-Off Detection Field Descriptions Bit Field Type Reset Description 7 LOFF8N R/W 0h IN8N lead off Enable lead-off detection on IN8N 0: Disabled 1: Enabled 6 LOFF7N R/W 0h IN7N lead off Enable lead-off detection on IN7N 0: Disabled 1: Enabled 5 LOFF6N R/W 0h IN6N lead off Enable lead-off detection on IN6N 0: Disabled 1: Enabled 4 LOFF5N R/W 0h IN5N lead off Enable lead-off detection on IN5N 0: Disabled 1: Enabled 3 LOFF4N R/W 0h IN4N lead off Enable lead-off detectionn on IN4N 0: Disabled 1: Enabled 2 LOFF3N R/W 0h IN3N lead off Enable lead-off detectionion on IN3N 0: Disabled 1: Enabled 1 LOFF2N R/W 0h IN2N lead off Enable lead-off detectionction on IN2N 0: Disabled 1: Enabled 0 LOFF1N R/W 0h IN1N lead off Enable lead-off detectionction on IN1N 0: Disabled 1: Enabled Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 75 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h) This register controls the direction of the current used for lead-off derivation. See the Lead-Off Detection section for details. Figure 84. LOFF_FLIP: Lead-Off Flip Register 7 LOFF_FLIP8 R/W-0h 6 LOFF_FLIP7 R/W-0h 5 LOFF_FLIP6 R/W-0h 4 LOFF_FLIP5 R/W-0h 3 LOFF_FLIP4 R/W-0h 2 LOFF_FLIP3 R/W-0h 1 LOFF_FLIP2 R/W-0h 0 LOFF_FLIP1 R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27. Lead-Off Flip Register Field Descriptions Bit 76 Field Type Reset Description 7 LOFF_FLIP8 R/W 0h Channel 8 LOFF polarity flip Flip the pullup/pulldown polarity of the current source or resistor on channel 8 for lead-off derivation. 0: No Flip: IN8P is pulled to AVDD and IN8N pulled to AVSS 1: Flipped: IN8P is pulled to AVSS and IN8N pulled to AVDD 6 LOFF_FLIP7 R/W 0h Channel 7 LOFF polarity flip Flip the pullup/pulldown polarity of the current source or resistor on channel 7 for lead-off derivation. 0: No Flip: IN7P is pulled to AVDD and IN7N pulled to AVSS 1: Flipped: IN7P is pulled to AVSS and IN7N pulled to AVDD 5 LOFF_FLIP6 R/W 0h Channel 6 LOFF polarity flip Flip the pullup/pulldown polarity of the current source or resistor on channel 6 for lead-off derivation. 0: No Flip: IN6P is pulled to AVDD and IN6N pulled to AVSS 1: Flipped: IN6P is pulled to AVSS and IN6N pulled to AVDD 4 LOFF_FLIP5 R/W 0h Channel 5 LOFF polarity flip Flip the pullup/pulldown polarity of the current source or resistor on channel 5 for lead-off derivation. 0: No Flip: IN5P is pulled to AVDD and IN5N pulled to AVSS 1: Flipped: IN5P is pulled to AVSS and IN5N pulled to AVDD 3 LOFF_FLIP4 R/W 0h Channel 4 LOFF polarity flip Flip the pullup/pulldown polarity of the current source or resistor on channel 4 for lead-off derivation. 0: No Flip: IN4P is pulled to AVDD and IN4N pulled to AVSS 1: Flipped: IN4P is pulled to AVSS and IN4N pulled to AVDD 2 LOFF_FLIP3 R/W 0h Channel 3 LOFF polarity flip Flip the pullup/pulldown polarity of the current source or resistor on channel 3 for lead-off derivation. 0: No Flip: IN3P is pulled to AVDD and IN3N pulled to AVSS 1: Flipped: IN3P is pulled to AVSS and IN3N pulled to AVDD 1 LOFF_FLIP2 R/W 0h Channel 2 LOFF Polarity Flip Flip the pullup/pulldown polarity of the current source or resistor on channel 2 for lead-off derivation. 0: No Flip: IN2P is pulled to AVDD and IN2N pulled to AVSS 1: Flipped: IN2P is pulled to AVSS and IN2N pulled to AVDD 0 LOFF_FLIP1 R/W 0h Channel 1 LOFF Polarity Flip Flip the pullup/pulldown polarity of the current source or resistor on channel 1 for lead-off derivation. 0: No Flip: IN1P is pulled to AVDD and IN1N pulled to AVSS 1: Flipped: IN1P is pulled to AVSS and IN1N pulled to AVDD Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h) This register stores the status of whether the positive electrode on each channel is on or off. See the Lead-Off Detection section for details. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits are not set to 1. When the LOFF_SENSEP bits are 0, the LOFF_STATP bits should be ignored. Figure 85. LOFF_STATP: Lead-Off Positive Signal Status Register (Read-Only) 7 IN8P_OFF R-0h 6 IN7P_OFF R-0h 5 IN6P_OFF R-0h 4 IN5P_OFF R-0h 3 IN4P_OFF R-0h 2 IN3P_OFF R-0h 1 IN2P_OFF R-0h 0 IN1P_OFF R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28. Lead-Off Positive Signal Status Field Descriptions Bit Field Type Reset Description 7 IN8P_OFF R 0h Channel 8 positive channel lead-off status Status of whether IN8P electrode is on or off 0: Electrode is on 1: Electrode is off 6 IN7P_OFF R 0h Channel 7 positive channel lead-off status Status of whether IN7P electrode is on or off 0: Electrode is on 1: Electrode is off 5 IN6P_OFF R 0h Channel 6 positive channel lead-off status Status of whether IN6P electrode is on or off 0: Electrode is on 1: Electrode is off 4 IN5P_OFF R 0h Channel 5 positive channel lead-off status Status of whether IN5P electrode is on or off 0: Electrode is on 1: Electrode is off 3 IN4P_OFF R 0h Channel 4 positive channel lead-off status Status of whether IN4P electrode is on or off 0: Electrode is on 1: Electrode is off 2 IN3P_OFF R 0h Channel 3 positive channel lead-off status Status of whether IN3P electrode is on or off 0: Electrode is on 1: Electrode is off 1 IN2P_OFF R 0h Channel 2 positive channel lead-off status Status of whether IN2P electrode is on or off 0: Electrode is on 1: Electrode is off 0 IN1P_OFF R 0h Channel 1 positive channel lead-off status Status of whether IN1P electrode is on or off 0: Electrode is on 1: Electrode is off Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 77 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h) This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off Detection section for details. Ignore the LOFF_STATN values if the corresponding LOFF_SENSN bits are not set to 1. When the LOFF_SENSEN bits are 0, the LOFF_STATP bits should be ignored. Figure 86. LOFF_STATN: Lead-Off Negative Signal Status Register (Read-Only) 7 IN8N_OFF R-0h 6 IN7N_OFF R-0h 5 IN6N_OFF R-0h 4 IN5N_OFF R-0h 3 IN4N_OFF R-0h 2 IN3N_OFF R-0h 1 IN2N_OFF R-0h 0 IN1N_OFF R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29. Lead-Off Negative Signal Status Field Descriptions Bit 78 Field Type Reset Description 7 IN8N_OFF R 0h Channel 8 negative channel lead-off status Status of whether IN8N electrode is on or off 0: Electrode is on 1: Electrode is off 6 IN7N_OFF R 0h Channel 7 negative channel lead-off status Status of whether IN7N electrode is on or off 0: Electrode is on 1: Electrode is off 5 IN6N_OFF R 0h Channel 6 negative channel lead-off status Status of whether IN6N electrode is on or off 0: Electrode is on 1: Electrode is off 4 IN5N_OFF R 0h Channel 5 negative channel lead-off status Status of whether IN5N electrode is on or off 0: Electrode is on 1: Electrode is off 3 IN4N_OFF R 0h Channel 4 negative channel lead-off status Status of whether IN4N electrode is on or off 0: Electrode is on 1: Electrode is off 2 IN3N_OFF R 0h Channel 3 negative channel lead-off status Status of whether IN3N electrode is on or off 0: Electrode is on 1: Electrode is off 1 IN2N_OFF R 0h Channel 2 negative channel lead-off status Status of whether IN2N electrode is on or off 0: Electrode is on 1: Electrode is off 0 IN1N_OFF R 0h Channel 1 negative channel lead-off status Status of whether IN1N electrode is on or off 0: Electrode is on 1: Electrode is off Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh) The general-purpose I/O register controls the action of the three GPIO pins. When RESP_CTRL[1:0] is in mode 01 and 11, the GPIO2, GPIO3, and GPIO4 pins are not available for use. Figure 87. GPIO: General-Purpose I/O Register 7 6 5 4 3 2 GPIOD[4:1] R/W-0h 1 0 GPIOC[4:1] R/W-Fh LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30. General-Purpose I/O Field Descriptions Bit Field Type Reset Description 7:4 GPIOD[4:1] R/W 0h GPIO data These bits are used to read and write data to the GPIO ports. When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. GPIO is not available in certain respiration modes. 3:0 GPIOC[4:1] R/W Fh GPIO control (corresponding GPIOD) These bits determine if the corresponding GPIOD pin is an input or output. 0 = Output 1 = Input 9.6.1.15 PACE: Pace Detect Register (address = 15h) (reset = 00h) This register provides the pace controls that configure the channel signal used to feed the external pace detect circuitry. See the Pace Detect section for details. Figure 88. PACE: Pace Detect Register 7 0 R/W-0h 6 0 R/W-0h 5 0 R/W-0h 4 3 PACEE[1:0] R/W-0h 2 1 PACEO[1:0] R/W-0h 0 PD_PACE R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31. (For example, CONTROL_REVISION Register) Field Descriptions Bit Field Type Reset Description 7:5 RESERVED R/W 0h Reserved Always write 0h 4:3 PACEE[1:0] R/W 0h Pace even channels These bits control the selection of the even number channels available on TEST_PACE_OUT1. Only one channel may be selected at any time. 00 = Channel 2 01 = Channel 4 10 = Channel 6 (ADS1296, ADS1296R, ADS1298, ADS1298R) 11 = Channel 8 (ADS1298 and ADS1298R) 2:1 PACEO[1:0] R/W 0h Pace odd channels These bits control the selection of the odd number channels available on TEST_PACE_OUT2. Only one channel may be selected at any time. 00 = Channel 1 01 = Channel 3 10 = Channel 5 (ADS1296, ADS1296R, ADS1298, ADS1298R) 11 = Channel 7 (ADS1298, ADS1298R) PD_PACE R/W 0h Pace detect buffer This bit is used to enable/disable the pace detect buffer. 0 = Pace detect buffer turned off 1 = Pace detect buffer turned on 0 Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 79 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.16 RESP: Respiration Control Register (address = 16h) (reset = 00h) This register provides the controls for the respiration circuitry; see the Respiration section for details. Figure 89. RESP: Respiration Control Register 7 RESP_ DEMOD_EN1 R/W-0h 6 RESP_MOD_ EN1 R/W-0h 5 1 R/W-0h 4 3 RESP_PH[2:0] R/W-0h 2 1 0 RESP_CTRL[1:0] R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32. Respiration Control Register Field Descriptions Bit (1) 80 Field Type Reset Description 7 RESP_DEMOD_EN1 R/W 0h Enables respiration demodulation circuitry (ADS129xR only; for ADS129x always write 0) This bit enables and disables the demodulation circuitry on channel 1. 0 = RESP demodulation circuitry turned off 1 = RESP demodulation circuitry turned on 6 RESP_MOD_EN1 R/W 0h RESP_MOD_EN1: Enables respiration modulation circuitry (ADS129xR only; for ADS129x always write 0) This bit enables and disables the modulation circuitry on channel 1. 0 = RESP modulation circuitry turned off 1 = RESP modulation circuitry turned on 5 RESERVED R/W 0h Reserved Always write 1h 4:2 RESP_PH[2:0] R/W 0h Respiration phase (1) 000 = 22.5° 001 = 45° 010 = 67.5° 011 = 90° 100 = 112.5° 101 = 135° 110 = 157.5° 111 = N/A 1:0 RESP_CTRL[1:0] R/W 0h Respiration control These bits set the mode of the respiration circuitry. 00 = No respiration 01= External respiration 10 = Internal respiration with internal signals 11 = Internal respiration with user-generated signals RESP_PH[2:0] phase control bits only for internal respiration (RESP_CTRL = 10) and external respiration (RESP_CTRL = 01) modes when the CONFIG4.RESP_FREQ[2:0] register bits are 000b or 001b. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h) Figure 90. CONFIG4: Configuration Register 4 7 6 RESP_FREQ[2:0] 5 4 0 R/W-0h 3 2 SINGLE_SHOT WCT_TO_RLD R/W-0h R/W-0h R/W-0h 1 PD_LOFF_CO MP R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33. Configuration Register 4 Field Descriptions (1) Bit Field Type Reset Description 7:5 RESP_FREQ[2:0] R/W 0h Respiration modulation frequency These bits control the respiration control frequency when RESP_CTRL[1:0] = 10 or RESP_CTRL[1:0] = 10 (1). 000 = 64 kHz modulation clock 001 = 32 kHz modulation clock 010 = 16kHz square wave on GPIO3 and GPIO04. Output on GPIO4 is 180 degree out of phase with GPIO3. 011 = 8kHz square wave on GPIO3 and GPIO04. Output on GPIO4 is 180 degree out of phase with GPIO3. 100 = 4kHz square wave on GPIO3 and GPIO04. Output on GPIO4 is 180 degree out of phase with GPIO3. 101 = 2kHz square wave on GPIO3 and GPIO04. Output on GPIO4 is 180 degree out of phase with GPIO3. 110 = 1kHz square wave on GPIO3 and GPIO04. Output on GPIO4 is 180 degree out of phase with GPIO3. 111 = 500Hz square wave on GPIO3 and GPIO04. Output on GPIO4 is 180 degree out of phase with GPIO3. Modes 000 and 001 are modulation frequencies in internal and external respiration modes. In internal respiration mode, the control signals appear at the RESP_MODP and RESP_MODN terminals. All other bit settings generate square waves as described above on GPIO4 and GPIO3. 4 RESERVED R/W 0h Reserved Always write 0h 3 SINGLE_SHOT R/W 0h Single-shot conversion This bit sets the conversion mode. 0 = Continuous conversion mode 1 = Single-shot mode 2 WCT_TO_RLD R/W 0h Connects the WCT to the RLD This bit connects WCT to RLD. 0 = WCT to RLD connection off 1 = WCT to RLD connection on 1 PD_LOFF_COMP R/W 0h Lead-off comparator power-down This bit powers down the lead-off comparators. 0 = Lead-off comparators disabled 1 = Lead-off comparators enabled 0 RESERVED R/W 0h Reserved Always write 0h These frequencies assume fCLK = 2.048 MHz. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 81 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 9.6.1.18 WCT1: Wilson Central Terminal and Augmented Lead Control Register (address = 18h) (reset = 00h) The WCT1 control register configures the device WCT circuit channel selection and the augmented leads. Figure 91. WCT1: Wilson Central Terminal and Augmented Lead Control Register 7 aVF_CH6 R/W-0h 6 aVL_CH5 R/W-0h 5 aVR_CH7 R/W-0h 4 aVR_CH4 R/W-0h 3 PD_WCTA R/W-0h 2 1 WCTA[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34. Wilson Central Terminal and Augmented Lead Control Field Descriptions Bit 82 Field Type Reset Description 7 aVF_CH6 R/W 0h Enable (WCTA + WCTB)/2 to the negative input of channel 6 (ADS1296, ADS1296R, ADS1298, and ADS1298R) 0 = Disabled 1 = Enabled 6 aVL_CH5 R/W 0h Enable (WCTA + WCTC)/2 to the negative input of channel 5 (ADS1296, ADS1296R, ADS1298, and ADS1298R) 0 = Disabled 1 = Enabled 5 aVR_CH7 R/W 0h Enable (WCTB + WCTC)/2 to the negative input of channel 7 (ADS1298 and ADS1298R) 0 = Disabled 1 = Enabled 4 aVR_CH4 R/W 0h Enable (WCTB + WCTC)/2 to the negative input of channel 4 0 = Disabled 1 = Enabled 3 PD_WCTA R/W 0h Power-down WCTA 0 = Powered down 1 = Powered on 2:0 WCTA[2:0] R/W 0h WCT Amplifier A channel selection, typically connected to RA electrode These bits select one of the eight electrode inputs of channels 1 to 4. 000 = Channel 1 positive input connected to WCTA amplifier 001 = Channel 1 negative input connected to WCTA amplifier 010 = Channel 2 positive input connected to WCTA amplifier 011 = Channel 2 negative input connected to WCTA amplifier 100 = Channel 3 positive input connected to WCTA amplifier 101 = Channel 3 negative input connected to WCTA amplifier 110 = Channel 4 positive input connected to WCTA amplifier 111 = Channel 4 negative input connected to WCTA amplifier Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.19 WCT2: Wilson Central Terminal Control Register (address = 18h) (reset = 00h) The WCT2 configuration register configures the device WCT circuit channel selection. Figure 92. WCT2: Wilson Central Terminal Control Register 7 PD_WCTC R/W-0h 6 PD_WCTB R/W-0h 5 4 WCTB[2:0] R/W-0h 3 2 1 WCTC[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 35. Wilson Central Terminal Control Field Descriptions Bit Field Type Reset Description 7 PD_WCTC R/W 0h Power-down WCTC 0 = Powered down 1 = Powered on 6 PD_WCTB R/W 0h Power-down WCTB 0 = Powered down 1 = Powered on 5:3 WCTB[2:0] R/W 0h WCT amplifier B channel selection, typically connected to LA electrode. These bits select one of the eight electrode inputs of channels 1 to 4. 000 = Channel 1 positive input connected to WCTB amplifier 001 = Channel 1 negative input connected to WCTB amplifier 010 = Channel 2 positive input connected to WCTB amplifier 011 = Channel 2 negative input connected to WCTB amplifier 100 = Channel 3 positive input connected to WCTB amplifier 101 = Channel 3 negative input connected to WCTB amplifier 110 = Channel 4 positive input connected to WCTB amplifier 111 = Channel 4 negative input connected to WCTB amplifier 2:0 WCTC[2:0] R/W 0h WCT amplifier C channel selection, typically connected to LL electrode. These bits select one of the eight electrode inputs of channels 1 to 4. 000 = Channel 1 positive input connected to WCTC amplifier 001 = Channel 1 negative input connected to WCTC amplifier 010 = Channel 2 positive input connected to WCTC amplifier 011 = Channel 2 negative input connected to WCTC amplifier 100 = Channel 3 positive input connected to WCTC amplifier 101 = Channel 3 negative input connected to WCTC amplifier 110 = Channel 4 positive input connected to WCTC amplifier 111 = Channel 4 negative input connected to WCTC amplifier Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 83 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information 10.1.1 Setting the Device for Basic Data Capture Figure 93 outlines the procedure to configure the device in a basic state and capture data. This procedure puts the device into a configuration that matches the parameters listed in the Specifications section, in order to check if the device is working properly in the user system. Follow this procedure initially until familiar with the device settings. After this procedure has been verified, the device can be configured as needed. For details on the timings for commands, refer to the appropriate sections in the data sheet. Sample programming codes are added for the ECG-specific functions. 84 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Application Information (continued) Analog/Digital Power-Up Set CLKSEL Pin = 0 and Provide External Clock fCLK = 2.048MHz Yes // Follow Power-Up Sequencing External Clock No Set CLKSEL Pin = 1 and Wait for Oscillator to Wake Up Set PDWN = 1 Set RESET = 1 Wait at least tPOR for Power-On Reset // If START is Tied High, After This Step // DRDY Toggles at fCLK/8192 // (LP Mode with DR = fMOD/1024) // Delay for Power-On Reset and Oscillator Start-Up No VCAP1 ³ 1.1V // If VCAP1 < 1.1V at tPOR, continue waiting until VCAP1 ³ 1.1V Yes Issue Reset Pulse, Wait for 18 tCLKs Set PDB_REFBUF = 1 and Wait for Internal Reference to Settle // Activate DUT // CS can be Either Tied Permanently Low // Or Selectively Pulled Low Before Sending // Commands or Reading/Sending Data from/to Device Send SDATAC Command // Device Wakes Up in RDATAC Mode, so Send // SDATAC Command so Registers can be Written SDATAC External Reference // If Using Internal Reference, Send This Command WREG CONFIG3 0xC0 No Yes Write Certain Registers, Including Input Short // Set Device in HR Mode and DR = fMOD/1024 WREG CONFIG1 0x86 WREG CONFIG2 0x00 // Set All Channels to Input Short WREG CHnSET 0x01 Set START = 1 // Activate Conversion // After This Point DRDY Should Toggle at // fCLK/4096 RDATAC // Put the Device Back in RDATAC Mode RDATAC Capture Data and Check Noise // Look for DRDY and Issue 24 + n ´ 24 SCLKs Set Test Signals // Activate a (1mV ´ VREF/2.4) Square-Wave Test Signal // On All Channels SDATAC WREG CONFIG2 0x10 WREG CHnSET 0x05 RDATAC Capture Data and Test Signal // Look for DRDY and Issue 24 + n ´ 24 SCLKs Figure 93. Initial Flow at Power Up Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 85 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Application Information (continued) 10.1.1.1 Lead-Off Sample code to set dc lead-off with pullup or pulldown resistors on all channels: WREG LOFF 0x13 // // WREG CONFIG4 0x02 // WREG LOFF_SENSP 0xFF // WREG LOFF_SENSN 0xFF // Comparator threshold at 95% and 5%, pullup or pulldown resistor dc lead-off Turn on dc lead-off comparators Turn on the P-side of all channels for lead-off sensing Turn on the N-side of all channels for lead-off sensing Observe the status bits of the output data stream to monitor lead-off status. 10.1.1.2 Right Leg Drive Sample code to choose RLD as an average of the first three channels. WREG RLD_SENSP 0x07 // Select channel 1-3 P-side for RLD sensing WREG RLD_SENSN 0x07 // Select channel 1-3 N-side for RLD sensing WREG CONFIG3 b’x1xx 1100 // Turn on RLD amplifier, set internal RLDREF voltage Sample code to route the RLD_OUT signal through channel 4 N-side and measure RLD with channel 5. Make sure the external side to the chip RLDOUT is connected to RLDIN. WREG CONFIG3 b’xxx1 1100 WREG CH4SET b’1xxx 0111 WREG CH5SET b’1xxx 0010 // Turn on RLD amp, set internal RLDREF voltage, set RLD measurement bit // Route RLDIN to channel 4 N-side // Route RLDIN to be measured at channel 5 w.r.t RLDREF 10.1.1.3 Pace Detection Sample code to select channel 5 and 6 outputs for pace: WREG PACE b’0001 0101 // Power-up pace amplifier and select channel 5 and 6 for pace out 10.1.2 Establishing the Input Common-Mode The ADS129x measures fully-differential signals where the common-mode voltage point is the midpoint of the positive and negative analog input. The internal PGA restricts the common-mode input range because of the headroom required for operation. The human body is prone to common-mode drifts because noise easily couples onto the human body, similar to an antenna. These common-mode drifts may push the ADS129x input commonmode voltage out of the measurable range of the ADC. If a patient-drive electrode is used by the system, the ADS129x includes an on-chip right leg drive (RLD) amplifier that connects to the patient drive electrode. The RLD amplifier function is to bias the patient to maintain the other electrode common-mode voltages within the valid range. When powered on, the amplifier uses either the analog midsupply voltage, or the voltage present at the RLDREF pin, as a reference input to stabilize the output near that voltage. 86 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Application Information (continued) The ADS129x provide the option to use input electrode voltages as feedback to the amplifier to more effectively stabilize the output to the amplifier reference voltage by setting corresponding bits in the RLD_SENSP and RLD_SENSN registers. See to Figure 94 for an example of a three-electrode system that leverages this technique. RA Anti-aliasing/ Protection INxP LA Anti-aliasing/ Protection INxN ADS129x RLDINV 1.5 nF RL 1 M  RLDOUT Protection Figure 94. Setting Common-Mode Using RLD Electrode A second strategy for maintaining a valid common-mode voltage is to ac-couple the analog inputs, which is especially useful when a patient-drive electrode is not in use. A dc blocking capacitor combined with a voltage divider between the analog power supplies, or a pullup resistor to set the DC bias to a known point, effectively makes sure that the dc common-mode voltage never drifts. Applications that do not use a patient-drive electrode may still use the RLD amplifier on the ADS129x as a buffered midsupply voltage to bias the inputs. Take care when choosing the passive components because the capacitor and the resistors form an RC high-pass filter. If passive components are chosen poorly, the filter undesirably attenuates frequencies at the lower end of the signal band. Figure 95 shows an example of this configuration. CBlock RA Anti-aliasing/ Protection LA Anti-aliasing/ Protection INxP CBlock INxN ADS129x RPull-up RPull-up RLDINV RLDOUT Figure 95. Setting Common-Mode Without Using RLD Electrode Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 87 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Application Information (continued) 10.1.3 Antialiasing As with all analog-to-digital systems, take care to prevent undesired aliasing effects. The ADS129x modulator samples the input at either 256 kHz or 512 kHz, depending on whether the device is in low-power (LP) mode or high-resolution (HR) mode, respectively. As is the case with all digital filters, the response of the on-chip digital decimation filter on the ADS129x repeats at integer multiples of the modulator frequency. A benefit to using the delta-sigma architecture is that the digital decimation filter significantly attenuates frequencies between the signal band and the alias of the signal band near the modulator frequency. This attenuation, combined with the limited bandwidth of the PGA (see Table 5), makes the requirement on the steepness of the response of the analog antialiasing filter much less stringent. In many cases, acceptable attenuation at the modulator frequency is provided by either a single or double-pole RC low pass filter. Also take care when choosing components for antialiasing. Common-mode to differential-mode conversion as a result of component mismatch, including antialiasing components, causes common-mode rejection degradation. Figure 96 shows a typical front-end configuration. R INxP C ADS129x R + /R VP INxN C + /C Figure 96. Typical Front-End Configuration VP is the common-mode signal to the system. If the values of R and C modeled in the differential signal are perfectly matched, then the system exhibits a very large CMR. If δR and δC in resistor R and capacitor C, respectively, are mismatched, the CMR of the entire system is approximated to Equation 8. f /5 /&  )  20 log ( ) CMR 20 log ( fc R C where • fC is the –3-dB frequency of the RC filter. (8) If 1%-precision external components are used and the bandwidth of the RC filter is approximately 6 kHz, the system then has only 74 dB of CMR at 60 Hz. In the real world, the front-end of the ECG does not contain only first-order RC filters; electrodes, cables, and second- or third-order RC filters are also included. Considering all of these components, mismatch can easily accumulate, and thus contribute up to 20% or more of the signal. This degree of mismatch degrades the CMR of the system to less than 60 dB at 60 Hz. Therefore, it is necessary to consider different techniques to improve CMR. There is a tradeoff when placing the bandwidth of the antialiasing filter in front of the modulator. Considering the mismatch between the discrete components, it is better to select the large bandwidth; the upper limit of the bandwidth is determined by the sampling frequency of the modulator. For more information on ways to prevent common-mode rejection, see Improving Common-Mode Rejection Using the Right-Leg Drive Amplifier, SBAA188. 88 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 10.2 Typical Applications 10.2.1 ADS129xR Respiration Measurement Using Internal Modulation Circuitry The respiration measurement circuitry on the ADS129xR employs out-of-band amplitude modulation and demodulation to measure changes in thoracic impedance that correspond to breathing. When respiration mode is enabled, channel 1 cannot be used to acquire ECG signals because the internal demodulation circuitry is unique to that channel. ECG signals can still be acquired with the same electrodes used for respiration measurement if they are also connected to another channel. Note the configuration shown in Figure 97. R6 10MΩ AVDD R5 10MΩ AVSS IN1P C1 470pF C2 0.1µF C3 2.2nF ADS1294R/6R/8R R2 40.2kΩ RESP_MODP Left Arm Lead IN2P IN2N RESP_MODN Right Arm Lead C6 0.1µF R4 10MΩ C4 2.2nF R1 40.2kΩ C5 470pF AVDD R3 10MΩ IN1N AVSS NOTE: Patient and input protection circuitry not shown. Figure 97. Typical Respiration Circuitry 10.2.1.1 Design Requirements Table 36 shows the design requirements for the components shown in Figure 97. Table 36. Respiration Design Requirements DESIGN PARAMETER VALUE Modulation frequency 32 kHz or 64 kHz Input high-pass filter cutoff ≈ 68 Hz ADC reference voltage 2.4 V Maximum ac body current 100 μA Minimum resistance R1 + R2 24 kΩ 10.2.1.2 Detailed Design Procedure To configure the ADS129xR to use its internal modulation circuitry, set RESP register bits[6:7] to enable both the internal modulation and demodulation circuitry. RESP register bits[4:2] determine the phase of the demodulation blocking signal. To configure the device to use the internally generated signals for internal respiration measurement, configure RESP register bits[1:0] to 10b. The RESP_MODP and RESP_MODN pins produce a 32 kHz or 64 kHz square wave depending on the CONFIG4 regsiter bits[7:5] when configured to use the internal circuitry. The REP_MODP and RESP_MODN pin voltages toggle between VREFP and VREFN at opposite phases at the specified frequency. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 89 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com Choosing R1 and R2 involves first recognizing the ideal behavior of this circuit. Ideally, all of the series capacitors appear as short-circuits to the high-frequency modulation signal, and there is no nonideal shunt capacitance anywhere in the circuit. Figure 98 shows an equivalent circuit representing these assumptions. R2 Rpp RElectrode IMOD IN1P RBaseline VREF IN1N R1 ûR Rpp RElectrode Figure 98. Ideal Behavior of the Respiration Modulation Circuit. The voltage appearing at the channel 1 input is set by the voltage divider formed by the resistors in the circuit. Resistor RPP represents any patient protection resistance in the cable; RElectrode represents the electrode-to-body interface resistance; RBaseline represents the baseline body impedance; and ΔR is the change in thoracic impedance due to respiration. Assume that R1 and R2 are significantly larger than all the other resistors in the circuit, and then approximate the RESP_MOD pins as the terminals of an ac current source with magnitude IMOD according to Equation 9: VREF IMOD | R1  R2 where • VREF is the square wave with the amplitude VREFP – VREFN that is produced at the RESP_MOD pins. (9) According to IEC60601, patient current at a frequency of 32 kHz must be limited to less than 100 μA; this limitation places a minimum value on the combination of R1 and R2. For best performance, the inputs to the ADS129xR must be ac coupled and biased to midsupply. The components that perform this function correspond to C1, C5, R3, R4, R5, and R6 in Figure 97. It is possible for ECG interference to couple into channel 1. As a result of this possibility, it is advisable to make the high-pass filter cutoff of those components large enough to attenuate the ECG bandwidth significantly. Conversely, if the cutoff is set to high, the carrier signal may attenuate. The signal that appears at the channel 1 input is amplified by the PGA, and then fed to the internal demodulation block. The demodulation block removes the square wave from the input leaving only the very low-frequency waveform corresponding to the ΔR due to respiration, and the offset due to RPP, RElectrode, and RBaseline. Equation 10 describes the modulator output voltage corresponding to the change in body impedance. VRESP IMOD u 'R u GPGA (10) Measure the rate of respiration by using the period at which VRESP oscillates as a result of ΔR. Make sure that the magnitude of VRESP remains greater than the noise-free resolution of the ADS129x. This magnitude imposes upper limits on the sizes of R1 and R2, as well as the cable impedance RPP, and demands that the quality of the electrode-to-body connection is high. Parasitic shunt capacitance tends to attenuate high frequencies and the outputs from the PGA are limited by the bandwidth of the amplifiers. The result is that the square edges of the carrier are rounded. To account for this error, the ADS129xR allows configuration of the RESP_PH[2:0] bits in the RESP regsiter. Those bits control the demodulation phase that introduces a phase delay between the modulation and demodulation clocks to account for the delay introduced by low-pass elements in the circuit. Choosing the optimal phase depends on the system characteristics. The time constant introduced by the resistance in the path of the input and the cable capacitance is an example of a system level characteristic that influences the amount of phase required for optimal respiration rate measurement. 90 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 Figure 99 shows a respiration test circuit. Figure 100 and Figure 101 plot noise on channel 1 for the ADS129xR as baseline impedance, gain, and phase are swept. The x-axis is the baseline impedance, normalized to a 29-μA modulation current (see Equation 11). ADS129xR IN1P R2 40.2 kW RESP_MODP RBASELINE 2.21 kW RESP_MODN R2 40.2 kW IN1N Figure 99. Respiration-Noise Test Circuit 10 20 Phase = 112.5, PGA = 4 Phase = 112.5, PGA = 3 Phase = 135, PGA = 4 Phase = 135, PGA = 3 9 18 Channel 1 Noise (mVPP) Channel 1 Noise (mVPP) 9.5 8.5 8 7.5 7 16 Phase = 135, PGA = 3 Phase = 135, PGA = 2 Phase = 157, PGA = 3 Phase = 157, PGA = 2 14 12 10 8 6.5 6 2214 3690 4845 8076 9155 15258 Normalized Baseline Respiration Impedance (W) 6 2214 3690 4845 8076 9155 15258 Normalized Baseline Respiration Impedance (W) BW = 150 Hz, respiration modulation clock = 32 kHz BW = 150 Hz, respiration modulation clock = 64 kHz Figure 100. Channel-1 Noise vs Impedance for 32-kHz Modulation Clock and Phase Figure 101. Channel-1 Noise vs Impedance for 64-kHz Modulation Clock and Phase RNORMALIZED = RACTUAL ´ IACTUAL 29mA where • • RACTUAL is the baseline body impedance. IACTUAL is the modulation current, as calculated by (VREFP – VREFN) divided by the impedance of the modulation circuit. (11) For example, assume that: • Modulation frequency = 32 kHz • RACTUAL = 3 kΩ • IACTUAL = 50 μA • RNORMALIZED = (3 kΩ × 50 μA) / 29 μA = 5.1 kΩ Referring to Figure 100 and Figure 101, gain = 4 and phase = 112.5° yield the best performance at 6.4 μVPP. Low-pass filtering this signal with a high-order, 2-Hz cutoff reduces the noise to less than 600 nVPP. The impedance resolution is 600 nVPP / 29 μA = 20 mΩ. When the modulation frequency is 32 kHz, use gains of 3 and 4, and a phase of 112.5° and 135° for best performance. When the modulation frequency is 64 kHz, use gains of 2 and 3 and phase of 135° and 157° for best performance. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 91 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 10.2.1.3 Application Curve Figure 102 shows respiration data taken with the ADS1298RECGFE-PDK using the Fluke medSim 300b. The data was then low-pass filtered to attenuate noise outside of the band of interest. A modulation frequency of 32 kHz was used along with a PGA gain of 3 and a RESP_PH setting of 112.5°. 15.9 15.89 15.88 15.87 Voltage (mV) 15.86 15.85 15.84 15.83 15.82 15.81 15.8 15.79 15.78 15.77 15.76 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Time (s) Figure 102. Respiration Impedance Taken With ADS1298R 92 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 10.2.2 Software-Based Artificial Pacemaker Detection Using the PACEOUT Pins on the ADS129x The electrical pulses produced by an artificial pacemaker are used to regulate the beating of the heart, and have a very small duration (width) when measured on the scale of other biopotential signals. According to the standard listed in AAMI EC11, medical instrumentation must be capable of capturing pacemaker pulses with durations as narrow as 0.5 ms. The ADS129x is capable of capturing data at 32 kSPS; ideally, fast enough to capture even the narrowest pulse. However, the data rate setting on the ADS129x is global for all channels. Using the ADS129x to digitize an input channel fast enough for robust pacemaker detection dictates that all channels must be converted as quickly; a condition that may be undesirable. An alternative topology is to use the ADS129x internal pace buffers to route a single-ended version of any particular channel input out to a fast-sampling SAR ADC to digitize the detection channel signal separately. Detection of a pacemaker pulse is then performed in the digital domain. Refer to Figure 103 for the basic block diagram for this architecture. The example features the combination of the OPA320 and the ADS7042. The OPA320 is used to drive the input sampling structure of the ADS7042, but provides corollary flexibility to add another gain stage and active antialias filtering before the pace output is digitized. VCC AVDD IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 RESPMOD VCAP2 ADS129x PACEOUT SPI SPI 1 CLK GPIO AVSS Microcontroller C1 VCC VCC R1 R2 R3 + C2 C3 R6 R7 AVDD OPA320 AINP C4 í C5 ADS7042 SPI SPI 2 AINN AVSS R5 R4 Figure 103. Block Diagram of the Software Pacemaker Detection Topology 10.2.2.1 Design Requirements Table 37 shows the design requirements for the components shown in Figure 103. Table 37. Software Pace Design Requirements DESIGN PARAMETER VALUE Analog supply voltage 3.3 V Minimum pacemaker signal bandwidth 0.5 ms Minimum pacemaker signal amplitude 2 mV Feedback network R4 + R5 (nonunity gain) ≈ 100 kΩ Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 93 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 10.2.2.2 Detailed Design Procedure The pace amplifiers on the ADS129x provides differential to single-ended conversion and amplification of 0.4 V/V to whatever voltage appears at the output of the PGA of the channel from which the pace amplifier is routed. Selecting which channels are routed to the pace amplifiers is performed in the pace detect register of the ADS129x. The voltage that appears at the output of the pace amplifier is to be taken with respect to analog midsupply. Before the signal is converted by the ADS7042, the signal must be buffered by a high-speed op amp because the inputs of the ADS7042 represent a switch-capacitor type load. The OPA320 is ideal to perform this function because of the low input bias current and 20-MHz unity gain bandwidth. The op amp also provides the flexibility to provide an extra gain stage before the SAR ADC, isolate filter stages, or to provide simple buffering. The purpose of C1 and R1 are to provide ac coupling to the pacemaker detection signal. This coupling may be necessary because electrode offset and the pacemaker pulse can both be, in some cases, up to a few hundred millivolts. An actively-driven signal ground is required to set the dc bias of the op amp at midsupply. It is possible to use the voltage provided at VCAP2 on the ADS129x as a buffered midsupply voltage. The voltage at the VCAP2 pin may be noisy, but using it to drive the common-mode voltage for both inverting and noninverting inputs to the op amp causes the op amp to cancel that noise significantly because it is common to both inputs. Op amp feedback resistors R4 and R5 set the gain for the OPA320. The transfer function for this configuration is that of the noninverting op amp configuration shown in Equation 12. vo v i (1  R3 ) R2 (12) Resistors R4 and R5 are chosen to set the desired gain. The series combination is approximately 100 kΩ, so that both the feedback current is limited to within the ADS129x VCAP2 internal regulator drive strength, and the Johnson-Nyquist noise of the resistors remains negligible. If the OPA320 is to be used only as a buffer, remove R4 removed to provide unity gain. If ac coupling is not desired, for best performance, replace C1 with a 0-Ω resistor and depopulate R1. The RC network of R2, C2, R3, C3, R6, C4, R7, and C5 form isolated two-pole RC antialiasing filters for the SAR ADC. The component values of the filter are set to provide significant attenuation at the ADC sampling frequency, but still provide enough bandwidth to detect a pacemaker pulse. A bandwidth of greater than 2 kHz is enough to capture a narrow 0.5-ms pacemaker pulse. In a real-time system, data must be collected and analyzed for a pacemaker with each incoming sample. Digitally filter data that are collected from the ADS7042 to remove out-of-band noise. Unlike a delta-sigma converter, a SAR converter does not apply a filter to the data before it is sent to the host. There are a number of factors that drive a decision on digital-filter implementation. Some of those factors include steepness of the response, phase linearity, and the number of taps. When using this topology with an ADS129xR device simultaneously with the respiration measurement circuitry, take special care to remove noise generated by the respiration modulation circuitry. The key to detecting a pacemaker pulse is the detection of a steep transition in the input voltage. To measure the magnitude of the transitions in input voltages, apply a digital differentiator algorithm. The algorithm measures the change in voltage magnitude over the span of a few samples and compares the change to a threshold required to trigger detection. The following pseudocode exemplifies some of the processing steps required to use this topology: newDataPoint = collectFromADS7042( ); // Collect data from the ADS7042 // Apply combined low-pass filter and differentiator inputRateOfChange = LPFandDifferentiator( newDataPoint ); if( abs( inputRateOfChange ) > thresholdValue ) // Check if a quick edge occurred { pacemakerFlag = true; // Edge detected } 94 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 10.2.2.3 Application Curve Figure 104 shows data that was collected from the PACEOUT pin of the ADS1298R (using the OPA320 and the ADS7042), and then filtered. The pacemaker pulse can be clearly identified. 0.12 0.1 0.08 Voltage (V) 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 0.33 0.36 0.39 0.42 0.45 0.48 0.51 0.54 0.57 0.6 0.63 0.66 Time (s) D001 NOTE: For illustration purposes, plot data were not processed in real time. As a result of the lack of shielding in this particular configuration, data were also high-pass filtered to attenuate the utility noise. Figure 104. Filtered ADS7042 Output Data With Pacemaker Pulse Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 95 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 11 Power Supply Recommendations The ADS129x have three power supplies: AVDD, AVDD1, and DVDD. For best performance, both AVDD and AVDD1 must be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, star connect AVDD1 and AVSS1 to AVDD and AVSS. It is important to eliminate noise from AVDD and AVDD1 that is nonsynchronous with ADS129x operation. Bypass each ADS129x supply with 1-μF and 0.1-μF solid ceramic capacitors. For best performance, place the digital circuits (DSP, microcontrollers, FPGAs, and so forth) in the system so that the return currents on those devices do not cross the analog return path of the ADS129x. Power the ADS129x from unipolar or bipolar supplies. Use surface-mount, low-cost, low-profile, multilayer ceramic-type capacitors for decoupling. In most cases, the VCAP1 capacitor is also a multilayer ceramic; however, in systems where the board is subjected to high- or lowfrequency vibration, install a nonferroelectric capacitor, such as a tantalum or class 1 capacitor (C0G or NPO). EIA class 2 and class 3 dielectrics such as (X7R, X5R, X8R, and so forth) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming from the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation. 11.1 Power-Up Sequencing Before device power up, all digital and analog inputs must be low. At the time of power up, keep all of these signals low until the power supplies have stabilized, as shown in Figure 105. Allow time for the supply voltages to reach their final value, and then begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a reset pulse using either the RESET pin or RESET command to initialize the digital portion of the chip. Issue the reset after tPOR or after the VCAP1 voltage is greater than 1.1 V, whichever time is longer. Note that: • tPOR is described in Table 38. • The VCAP1 pin charge time is set by the RC time constant; see Figure 31. After releasing the RESET pin, program the configuration registers; see the CONFIG1: Configuration Register 1 (address = 01h) (reset = 06h) section for details. The power-up sequence timing is shown in Table 38. tPOR(1)(2) Supplies tBG(1) 1.1V VCAP1 VCAP = 1.1V Start using device 18 × tCLK RESET tRST (1) Timing to reset pulse is tPOR or after tBG, whichever is longer. (2) When using an external clock, tPOR timing does not start until CLK is valid. Figure 105. Power-Up Timing Diagram Table 38. Timing Requirements for Figure 105 MIN tPOR Wait after power up until reset tRST Reset low duration 96 Submit Documentation Feedback MAX UNIT 218 tCLK 2 tCLK Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 11.2 Connecting to Unipolar (3 V or 1.8 V) Supplies Figure 106 illustrates the ADS129x connected to a unipolar supply. In this example, analog supply (AVDD) is referenced to analog ground (AVSS) and digital supplies (DVDD) are referenced to digital ground (DGND). +3V +1.8V 0.1mF 1 mF 1mF 0.1mF AVDD AVDD1 DVDD VREFP VREFN 10mF 0.1mF VCAP1 VCAP2 ADS1298 RESV1 VCAP3 VCAP4 WCT AVSS1 AVSS 1nF DGND 1mF 1mF 0.1mF 1mF 22mF NOTE: Place the capacitors for supply, reference, WCT, and VCAP1 to VCAP4 as close to the package as possible. Figure 106. Single-Supply Operation 11.3 Connecting to Bipolar (±1.5 V or ±1.8 V) Supplies Figure 107 illustrates the ADS129x connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND). +1.5V +1.8V 1mF 0.1mF 0.1mF 1 mF AVDD AVDD1 DVDD VREFP VREFN 10mF 0.1mF -1.5V VCAP1 RESV1 ADS1298 VCAP2 VCAP3 VCAP4 WCT AVSS1 AVSS DGND 1nF 1mF 1mF 1 mF 0.1mF 1mF 22mF 0.1mF -1.5V NOTE: Place the capacitors for supply, reference, WCT, and VCAP1 to VCAP4 as close to the package as possible. Figure 107. Bipolar Supply Operation Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 97 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 12 Layout 12.1 Layout Guidelines Use a a low-impedance connection for ground, so that return currents flow undisturbed back to their respective sources. For best performance, dedicate an entire PCB layer to a ground plane and route no other signal traces on this layer. Keep connections to the ground plane as short and direct as possible. When using vias to connect to the ground layer, use multiple vias in parallel to reduce impedance to ground. A mixed signal layout sometimes incorporates separate analog and digital ground planes that are tied together at one location; however, separating the ground planes is not necessary when analog, digital and power supply components are properly placed. Proper placement of components partitions the analog, digital and power supply circuitry into different PCB regions to prevent digital return currents from coupling into sensitive analog circuitry. If ground plane separation is necessary, then make the connection at the ADC. Connecting individual ground planes at multiple locations creates ground loops, and is not recommended. A single ground plane for analog and digital avoids ground loops. Bypass supply pins with a low-ESR ceramic capacitor. The placement of the bypass capacitors must be as close as possible to the supply pins using short, direct traces. For optimum performance, the ground-side connections of the bypass capacitors must also be low-impedance connections. The supply current flows through the bypass capacitor pin first and then to the supply pin to make the bypassing most effective (also known as a Kelvin connection). If multiple ADCs are on the same PCB, use wide power-supply traces or dedicated power-supply planes to minimize the potential of crosstalk between ADCs. If external filtering is used for the analog inputs, use C0G-type ceramic capacitors when possible. C0G capacitors have stable properties and low-noise characteristics. Ideally, route differential signals as pairs to minimize the loop area between the traces. Route digital circuit traces (such as clock signals) away from all analog pins. Note the internal reference output return shares the same pin as the AVSS power supply. To minimize coupling between the power-supply trace and reference return trace, route the two traces separately; ideally, as a star connection at the AVSS pin. It is essential to make short, direct interconnections on analog input lines and avoid stray wiring capacitance, particularly between the analog input pins and AVSS. These analog input pins are high-impedance and extremely sensitive to extraneous noise. Treat the AVSS pin as a sensitive analog signal and connect directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the input bias current of the ADS129x if shielding is not implemented. Keep digital signals as far as possible from the analog input signals on the PCB. It is important the SCLK input of the serial interface is free from noise and glitches. Even with relatively slow SCLK frequencies, short digital signal rise and fall times may cause excessive ringing and noise. For best performance, keep the digital signal traces short, using termination resistors as needed, and make sure all digital signals are routed directly above the ground plane with minimal use of vias. Ground Fill or Ground Plane Supply Generation Microcontroller Device Optional: Split Ground Cut Signal Conditioning (RC Filters and Amplifiers) Ground Fill or Ground Plane Optional: Split Ground Cut Ground Fill or Ground Plane Interface Transceiver Connector or Antenna Ground Fill or Ground Plane Figure 108. System Component Placement 98 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 12.2 Layout Example Figure 109 is an example layout of the ADS129x requiring a minimum of two PCB layers. The example circuit is shown for either a single analog supply or a bipolar-supply connection. In this example, polygon pours are used as supply connections around the device. If a three- or four-layer PCB is used, the additional inner layers can be dedicated to route power traces. The PCB is partitioned with analog signals routed from the left, digital signals routed to the right, and power routed above and below the device. Via to AVSS pour or plane 49: DGND 50: DVDD 51: DGND 52: CLKSEL 53: AVSS1 54: AVDD1 57: AVSS 58: AVSS 55: VCAP3 59: AVDD 56: AVDD 60: RLDREF 61: RLDINV 62: RLDIN 64: WCT 1: IN8N 48: DVDD 2: IN8P 47: DRDY 3: IN7N 46: GPIO4 4: IN7P 45: GPIO3 5: IN6N 44: GPIO2 6: IN6P 43: DOUT 7: IN5N 42: GPIO1 8: IN5P 41: DAISY_ IN ADS129x 9: IN4N 40: SCLK 32: AVSS 31: RESV1 30: VCAP2 29: NC 28: VCAP1 27: NC 26: VCAP4 24: VREFP 33: DGND 25: VREFN 34: DIN 16: IN1P 22: AVDD 35:PWDN 15: IN1N 21: AVDD 36: RESET 14: IN2P 20: AVSS 37: CLK 13: IN2N 19: AVDD 38: START 12: IN3P 18: TESTN_ PACE_OUT2 39: CS 11: IN3N 17: TESTP_ PACE_OUT1 10: IN4P 23: AVSS Input filtered with differential and common-mode capacitors 63: RLDOUT Via to digital ground pour or plane Long digital input lines terminated with resistors to prevent reflection Reference, VCAP, and power supply decoupling capacitors close to pins Figure 109. ADS129x Layout Example Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R 99 ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 www.ti.com 13 Device and Documentation Support 13.1 Related Links Table 39 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 39. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS1294 Click here Click here Click here Click here Click here ADS1294R Click here Click here Click here Click here Click here ADS1296 Click here Click here Click here Click here Click here ADS1296R Click here Click here Click here Click here Click here ADS1298 Click here Click here Click here Click here Click here ADS1298R Click here Click here Click here Click here Click here 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 100 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1294CZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1294 ADS1294CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1294 ADS1294IPAG ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS1294 ADS1294IPAGR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS1294 ADS1294RIZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS1294R ADS1294RIZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS1294R ADS1296CZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1296 ADS1296CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1296 ADS1296IPAG ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS1296 ADS1296IPAGR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS1296 ADS1296RIZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS1296R ADS1296RIZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS1296R ADS1298CZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1298 ADS1298CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 ADS1298 ADS1298IPAG ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS1298 ADS1298IPAGR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS1298 ADS1298RIZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS1298R ADS1298RIZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS1298R (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of