ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
12-/14-Bit, 160/250MSPS, Ultralow-Power ADC
Check for Samples: ADS4126, ADS4129, ADS4146, ADS4149
FEATURES
DESCRIPTION
•
•
The ADS412x/4x are a family of 12-bit/14-bit
analog-to-digital converters (ADCs) with sampling
rates up to 250MSPS. These devices use innovative
design techniques to achieve high dynamic
performance, while consuming extremely low power
at 1.8V supply. The devices are well-suited for
multi-carrier,
wide
bandwidth
communications
applications.
1
23
•
•
•
•
•
•
•
Maximum Sample Rate: 250MSPS
Ultralow Power with 1.8V Single Supply:
– 201mW Total Power at 160MSPS
– 265mW Total Power at 250MSPS
High Dynamic Performance:
– SNR: 70.6dBFS at 170MHz
– SFDR: 84dBc at 170MHz
Dynamic Power Scaling with Sample Rate
Output Interface:
– Double Data Rate (DDR) LVDS with
Programmable Swing and Strength
– Standard Swing: 350mV
– Low Swing: 200mV
– Default Strength: 100Ω Termination
– 2x Strength: 50Ω Termination
– 1.8V Parallel CMOS Interface Also
Supported
Programmable Gain up to 6dB for SNR/SFDR
Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude Down To
200mVPP
Package: QFN-48 (7mm × 7mm)
The ADS412x/4x have fine gain options that can be
used to improve SFDR performance at lower
full-scale input ranges, especially at high input
frequencies. They include a dc offset correction loop
that can be used to cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled down power with no loss in performance.
The ADS412x/4x are available in a compact QFN-48
package and are specified over the industrial
temperature range (–40°C to +85°C)
ADS412x/ADS414x Family Comparison
SAMPLING RATE
WITH ANALOG INPUT BUFFERS
FAMILY
65MSPS
125MSPS
160MSPS
250MSPS
200MSPS
250MSPS
ADS412x
12-bit family
ADS4122
ADS4125
ADS4126
ADS4129
—
ADS41B29
ADS414x
14-bit family
ADS4142
ADS4145
ADS4146
ADS4149
—
ADS41B49
9-bit
—
—
—
—
—
ADS58B19
11-bit
—
—
—
—
ADS58B18
—
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
ADS4126, ADS4129
ADS4146, ADS4149
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
ADS4126
QFN-48
RGZ
–40°C to +85°C
ADS4129
ADS4146
ADS4149
(1)
(2)
QFN-48
QFN-48
QFN-48
RGZ
RGZ
RGZ
ECO PLAN (2)
GREEN (RoHS, no
Sb/Br)
–40°C to +85°C
GREEN (RoHS, no
Sb/Br)
–40°C to +85°C
GREEN (RoHS, no
Sb/Br)
–40°C to +85°C
GREEN (RoHS, no
Sb/Br)
LEAD/BALL
FINISH
PACKAGE
MARKING
Cu/NiPdAu
AZ4126
Cu/NiPdAu
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
ADS4126IRGZR
Tape and reel, 2500
ADS4126IRGZT
Tape and reel, 250
ADS4129IRGZR
Tape and reel, 2500
AZ4129
Cu/NiPdAu
ADS4129IRGZT
Tape and reel, 250
ADS4146IRGZR
Tape and reel, 2500
AZ4146
Cu/NiPdAu
ADS4146IRGZT
Tape and reel, 250
ADS4149IRGZR
Tape and reel, 2500
ADS4149IRGZT
Tape and reel, 250
AZ4149
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
The ADS412x/4x family is pin-compatible with the previous generation ADS6149 family; this architecture enables
easy migration. However, there are some important differences between the generations, summarized in Table 1.
Table 1. MIGRATING FROM THE ADS6149 FAMILY
ADS6149 FAMILY
ADS4149 FAMILY
PINS
Pin 21 is NC (not connected)
Pin 21 is NC (not connected)
Pin 23 is MODE
Pin 23 is RESERVED in the ADS4149 family. It is reserved as a digital control pin for an (as yet) undefined function in the
next-generation ADC series.
SUPPLY
AVDD is 3.3V
AVDD is 1.8V
DRVDD is 1.8V
No change
INPUT COMMON-MODE VOLTAGE
VCM is 1.5V
VCM is 0.95V
SERIAL INTERFACE
Protocol: 8-bit register address and 8-bit register data
No change in protocol
New serial register map
EXTERNAL REFERENCE MODE
Supported
Not supported
ADS61B49 FAMILY
ADS41B29/B49/ADS58B18 FAMILY
PINS
Pin 21 is NC (not connected)
Pin 21 is 3.3V AVDD_BUF (supply for the analog input buffers)
Pin 23 is MODE
Pin 23 is a digital control pin for the RESERVED function.
Pin 23 functions as SNR Boost enable (B18 only).
SUPPLY
AVDD is 3.3V
AVDD is 1.8V, AVDD_BUF is 3.3V
DRVDD is 1.8V
No change
INPUT COMMON-MODE VOLTAGE
VCM is 1.5V
VCM is 1.7V
SERIAL INTERFACE
Protocol: 8-bit register address and 8-bit register data
No change in protocol
New serial register map
EXTERNAL REFERENCE MODE
Supported
2
Not supported
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Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
Supply voltage range, AVDD
–0.3 to 2.1
V
Supply voltage range, DRVDD
–0.3 to 2.1
V
Voltage between AGND and DRGND
–0.3 to 0.3
V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
0 to 2.1
V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
0 to 2.1
V
–0.3 to minimum (1.9, AVDD + 0.3)
V
–0.3 to AVDD + 0.3
V
–0.3 to 3.9
V
Operating free-air temperature range, TA
–40 to +85
°C
Operating junction temperature range, TJ
+125
°C
Storage temperature range, Tstg
–65 to +150
°C
ESD, human body model (HBM)
2
kV
INP, INM
Voltage applied to input pins
CLKP, CLKM (2), DFS, OE
RESET, SCLK, SDATA, SEN
(1)
(2)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.
This prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS4126,
ADS4129,
ADS4146,
ADS4149
THERMAL METRIC (1)
UNITS
RGZ
48 PINS
qJA
Junction-to-ambient thermal resistance
qJCtop
Junction-to-case (top) thermal resistance
qJB
Junction-to-board thermal resistance
10
yJT
Junction-to-top characterization parameter
0.3
yJB
Junction-to-board characterization parameter
9
qJCbot
Junction-to-case (bottom) thermal resistance
1.13
(1)
29
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2009–2011, Texas Instruments Incorporated
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3
ADS4126, ADS4129
ADS4146, ADS4149
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
ADS412x, ADS414x
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
1.7
1.8
1.9
V
DRVDD
Digital supply voltage
1.7
1.8
1.9
V
ANALOG INPUTS
Differential input voltage range (1)
2
Input common-mode voltage
VPP
VCM ± 0.05
V
Maximum analog input frequency with 2VPP input amplitude (2)
400
MHz
Maximum analog input frequency with 1VPP input amplitude (2)
800
MHz
CLOCK INPUT
Input clock sample rate
ADS4129/ADS4149
Low-speed mode enabled (3)
20
80
MSPS
Low-speed mode disabled (3)
> 80
250
MSPS
ADS4126/ADS4146
Low-speed mode enabled (3)
20
80
MSPS
Low-speed mode disabled (3)
> 80
160
MSPS
Input clock amplitude differential (VCLKP – VCLKM)
Sine wave, ac-coupled
1.5
VPP
LVPECL, ac-coupled
0.2
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
1.8
V
Input clock duty cycle
Low-speed mode enabled
40
50
60
%
Low-speed mode disabled
35
50
65
%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
RLOAD
Differential load resistance between the LVDS output pairs (LVDS
mode)
TA
Operating free-air temperature
–40
5
pF
100
Ω
+85
°C
HIGH PERFORMANCE MODES (4) (5) (6)
Mode 1
Set the MODE 1 register bits to get best performance across sample
clock and input signal frequencies.
Register address = 03h, register data = 03h
Mode 2
Set the MODE 2 register bit to get best performance at high input
signal frequencies.
Register address = 4Ah, register data = 01h
(1)
(2)
(3)
(4)
(5)
(6)
4
With 0dB gain. See the Fine Gain section in the Application Information for relation between input voltage range and gain.
See the Theory of Operation section in the Application Information.
See the Serial Interface section for details on low-speed mode.
It is recommended to use these modes to get best performance. These modes can be set using the serial interface only.
See the Serial Interface section for details on register programming.
Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device
Configuration section.
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Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS: ADS4126/ADS4129
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain,
and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. Note that after reset, the device is in 0dB gain mode.
ADS4126 (160MSPS)
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
SNR (signal-to-noise ratio), LVDS
SINAD (signal-to-noise and distortion ratio),
LVDS
SFDR
THD
70
69.7
dBFS
69.6
dBFS
69
dBFS
IMD
Input overload recovery
66.5
69
65.8
fIN = 300MHz
68
68
dBFS
fIN = 10MHz
70.1
69.7
dBFS
fIN = 70MHz
70
69.4
dBFS
fIN = 100MHz
69.5
69.3
dBFS
68.7
dBFS
65.5
68.7
65.5
fIN = 300MHz
67.3
66.8
dBFS
fIN = 10MHz
88
87
dBc
fIN = 70MHz
87
82
dBc
fIN = 100MHz
86.3
81
dBc
80
dBc
72.5
82
70
fIN = 300MHz
77.5
75
dBc
fIN = 10MHz
87
85
dBc
fIN = 70MHz
85
80
dBc
fIN = 100MHz
84
79
dBc
79
dBc
fIN = 300MHz
74.5
71.5
dBc
fIN = 10MHz
92
90
dBc
fIN = 70MHz
90
85
dBc
fIN = 100MHz
88
84
dBc
84
70
dBc
72.5
81
69
88
70
fIN = 300MHz
78
74
dBc
fIN = 10MHz
88
87
dBc
fIN = 70MHz
87
82
dBc
fIN = 100MHz
86
81
dBc
80
dBc
72.5
82
70
fIN = 300MHz
77
75
dBc
fIN = 10MHz
92
90
dBc
fIN = 70MHz
91
88
dBc
fIN = 100MHz
90
90
dBc
88
dBc
fIN = 170MHz
Two-tone intermodulation
distortion
Bits
69.7
fIN = 170MHz
Worst spur
(other than second and third harmonics)
UNIT
fIN = 70MHz
fIN = 170MHz
HD3
12
fIN = 100MHz
fIN = 170MHz
HD2
MAX
dBFS
fIN = 170MHz
Third-harmonic distortion
TYP
69.8
fIN = 170MHz
Second-harmonic distortion
MIN
70.2
fIN = 170MHz
Total harmonic distortion
MAX
12
fIN = 10MHz
Spurious-free dynamic range
ADS4129 (250MSPS)
76
90
75
fIN = 300MHz
88
88
dBc
f1 = 46MHz, f2 = 50MHz,
each tone at –7dBFS
–88
–88
dBFS
f1 = 185MHz, f2 = 190MHz,
each tone at –7dBFS
–86
–86
dBFS
Recovery to within 1% (of final
value) for 6dB overload with
sine-wave input
1
1
Clock
cycles
> 30
> 30
dB
AC power-supply rejection ratio
PSRR
For 100mVPP signal on AVDD
supply, up to 10MHz
Effective number of bits
ENOB
fIN = 170MHz
Differential nonlinearity
DNL
fIN = 170MHz
Integrated nonlinearity
INL
fIN = 170MHz
Copyright © 2009–2011, Texas Instruments Incorporated
11.2
–0.85
11.2
±0.2
2.5
±0.25
3.5
–0.95
LSBs
±0.2
2.5
LSBs
±0.5
5
LSBs
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ADS4126, ADS4129
ADS4146, ADS4149
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS4146/ADS4149
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain,
and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. Note that after reset, the device is in 0dB gain mode.
ADS4146 (160MSPS)
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
SNR (signal-to-noise ratio), LVDS
SINAD (signal-to-noise and distortion ratio),
LVDS
SFDR
HD3
72
71.4
dBFS
71.5
71.4
dBFS
70.6
dBFS
IMD
Input overload recovery
dBFS
fIN = 10MHz
72
71.6
dBFS
fIN = 70MHz
71.8
71
dBFS
fIN = 100MHz
71.4
70.9
dBFS
69.4
dBFS
67.5
70.4
66
fIN = 300MHz
68.2
67.4
dBFS
fIN = 10MHz
88
87
dBc
fIN = 70MHz
87
82
dBc
fIN = 100MHz
86
81
dBc
84
dBc
74.5
82
72
fIN = 300MHz
77
75
dBc
fIN = 10MHz
86.5
85
dBc
fIN = 70MHz
85
80
dBc
fIN = 100MHz
84
79
dBc
80.5
dBc
fIN = 300MHz
74.5
71.5
dBc
fIN = 10MHz
91
89
dBc
fIN = 70MHz
90
85
dBc
fIN = 100MHz
88
84
dBc
84
72
dBc
74.5
81
71
88
72
fIN = 300MHz
79
75
dBc
fIN = 10MHz
88
87
dBc
fIN = 70MHz
87
82
dBc
fIN = 100MHz
86
81
dBc
82
dBc
74.5
82
72
fIN = 300MHz
77
75
dBc
fIN = 10MHz
91
90
dBc
fIN = 70MHz
90
88
dBc
fIN = 100MHz
90
90
dBc
88
dBc
78
90
77
fIN = 300MHz
88
88
dBc
f1 = 46MHz, f2 = 50MHz,
each tone at –7dBFS
–88
–88
dBFS
f1 = 185MHz, f2 = 190MHz,
each tone at –7dBFS
–86
–86
dBFS
Recovery to within 1% (of final
value) for 6dB overload with
sine-wave input
1
1
Clock
cycles
> 30
> 30
dB
11.3
LSBs
PSRR
For 100mVPP signal on AVDD
supply, up to 10MHz
Effective number of bits
ENOB
fIN = 170MHz
Differential nonlinearity
DNL
fIN = 170MHz
Integrated nonlinearity
INL
fIN = 170MHz
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67.5
69
AC power-supply rejection ratio
6
70.8
69
fIN = 170MHz
Two-tone intermodulation
distortion
68.5
fIN = 300MHz
fIN = 170MHz
Worst spur
(other than second and third harmonics)
Bits
fIN = 70MHz
fIN = 170MHz
Third-harmonic distortion
UNIT
fIN = 100MHz
fIN = 170MHz
HD2
14
dBFS
fIN = 170MHz
THD
MAX
71.9
fIN = 170MHz
Second-harmonic distortion
TYP
72.2
fIN = 170MHz
Total harmonic distortion
MIN
14
fIN = 10MHz
Spurious-free dynamic range
MAX
ADS4149 (250MSPS)
11.5
–0.95
±0.5
±2
–0.95
±4.5
±0.5
±2
LSBs
±5
LSBs
Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and
DRVDD = 1.8V.
PARAMETER
ADS4126/ADS4146 (160MSPS)
ADS4129/ADS4149 (250MSPS)
MIN
MIN
TYP
MAX
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range
Differential input resistance (at dc); see Figure 114
Differential input capacitance; see Figure 115
Analog input bandwidth
Analog input common-mode current (per input pin)
Common-mode output voltage
VCM
VCM output current capability
2
2
VPP
>1
>1
MΩ
4
4
pF
550
550
MHz
µA/MSPS
0.6
0.6
0.95
0.95
V
4
4
mA
DC ACCURACY
Offset error
–15
Temperature coefficient of offset error
2.5
15
–15
2.5
0.003
Gain error as a result of internal reference
inaccuracy alone
EGREF
Gain error of channel alone
EGCHAN
Temperature coefficient of EGCHAN
–2
15
0.003
2
–2
2
–0.2
–0.2
0.001
0.001
mV
mV/°C
–1
%FS
%FS
Δ%/°C
POWER SUPPLY
IAVDD
Analog supply current
72
83
99
IDRVDD (1)
Output buffer supply current
LVDS interface with 100Ω external termination
Low LVDS swing (200mV)
39.5
51
47
IDRVDD
Output buffer supply current
LVDS interface with 100Ω external termination
Standard LVDS swing (350mV)
51
63
59
IDRVDD output buffer supply current (1) (2)
CMOS interface (2)
8pF external load capacitance
fIN = 2.5MHz
26
113
mA
mA
72
mA
35
mA
Analog power
130
179
mW
LVDS interface, low LVDS swing
71.1
84.6
mW
47
63
mW
Digital power
CMOS interface (2)
8pF external load capacitance
fIN = 2.5MHz
Global power-down
10
Standby
185
(1)
(2)
25
10
25
185
mW
mW
The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the
maximum recommended load capacitance on each digital output line is 10pF.
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
Copyright © 2009–2011, Texas Instruments Incorporated
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
DIGITAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise noted. Minimum and
maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4126, ADS4129, ADS4146, ADS4149
PARAMETER
TEST CONDITIONS
MIN
RESET, SCLK, SDATA, and
SEN support 1.8V and 3.3V
CMOS logic levels
1.3
OE only supports 1.8V CMOS
logic levels
1.3
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE)
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
V
0.4
V
V
0.4
V
High-level input current: SDATA, SCLK (1)
VHIGH = 1.8V
10
µA
High-level input current: SEN
VHIGH = 1.8V
0
µA
Low-level input current: SDATA, SCLK
VLOW = 0V
0
µA
Low-level input current: SEN
VLOW = 0V
10
µA
DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT)
High-level output voltage
DRVDD – 0.1
DRVDD
Low-level output voltage
0
V
0.1
V
DIGITAL OUTPUTS (LVDS INTERFACE: DA0P/M TO DA13P/M, DB0P/M TO DB13P/M, CLKOUTP/M)
High-level output voltage (2)
VODH
Standard swing LVDS
270
+350
430
mV
Low-level output voltage (2)
VODL
Standard swing LVDS
–430
–350
–270
mV
High-level output voltage
(2)
VODH
Low swing LVDS
+200
Low-level output voltage (2)
VODL
Low swing LVDS
–200
Output common-mode voltage
VOCM
(1)
(2)
8
0.85
1.05
mV
mV
1.25
V
SDATA and SCLK have an internal 180kΩ pull-down resistor.
With an external 100Ω termination.
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PIN CONFIGURATION (LVDS MODE)
D10_D11_P
D10_D11_M
D8_D9_P
D8_D9_M
D6_D7_P
D6_D7_M
D4_D5_P
D4_D5_M
D2_D3_P
D2_D3_M
D0_D1_P
D0_D1_M
RGZ PACKAGE(1)
QFN-48
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
NC
CLKOUTP
5
32
NC
DFS
6
31
NC
OE
7
30
RESET
AVDD
8
29
SCLK
AGND
9
28
SDATA
CLKP 10
27
SEN
CLKM 11
26
AVDD
AGND 12
25
AGND
13
14
15
16
17
18
19
20
21
22
23
24
AVDD
NC
33
RESERVED
34
4
AVDD
3
CLKOUTM
NC
OVR_SDOUT
AVDD
DRVDD
AVDD
35
AGND
2
AGND
DRVDD
INP
DRGND
INM
36
AGND
1
VCM
DRGND
(1) The PowerPAD is connected to DRGND.
Figure 1. ADS412x LVDS Pinout
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D8_D9_M
D6_D7_P
D6_D7_M
45
44
43
42
41
D2_D3_M
D8_D9_P
46
D2_D3_P
D10_D11_M
47
D4_D5_P
D10_D11_P
48
D4_D5_M
D12_D13_P
D12_D13_M
RGZ PACKAGE(2)
QFN-48
(TOP VIEW)
40
39
38
37
DRGND
1
36
DRGND
32
NC
6
31
NC
OE
7
30
RESET
AVDD
8
29
SCLK
AGND
9
28
SDATA
CLKP 10
27
SEN
CLKM 11
26
AVDD
AGND 12
25
AGND
14
15
16
17
AGND
13
18
19
20
21
22
23
24
AVDD
5
DFS
RESERVED
CLKOUTP
NC
D0_D1_M
AVDD
33
AVDD
4
AVDD
CLKOUTM
AGND
D0_D1_P
INM
DRVDD
34
INP
35
3
VCM
2
AGND
DRVDD
OVR_SDOUT
(2) The PowerPAD™ is connected to DRGND.
Figure 2. ADS414x LVDS Pinout
ADS412x, ADS414x Pin Assignments (LVDS Mode)
10
PIN NAME
PIN NUMBER
# OF
PINS
FUNCTION
AVDD
8, 18, 20, 22, 24, 26
6
I
1.8V analog power supply
AGND
9, 12, 14, 17, 19, 25
6
I
Analog ground
CLKP
10
1
I
Differential clock input, positive
CLKM
11
1
I
Differential clock input, negative
INP
15
1
I
Differential analog input, positive
INM
16
1
I
Differential analog input, negative
VCM
13
1
O
Outputs the common-mode voltage (0.95V) that can be used externally to bias the
analog input pins.
DESCRIPTION
RESET
30
1
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through
hardware RESET by applying a high pulse on this pin or by using the software reset
option; refer to the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this
condition, SEN can be used as an analog control pin.
RESET has an internal 180kΩ pull-down resistor.
SCLK
29
1
I
This pin functions as a serial interface clock input when RESET is low. When RESET is
high, SCLK has no function and should be tied to ground. This pin has an internal
180kΩ pull-down resistor.
SDATA
28
1
I
This pin functions as a serial interface data input when RESET is low. When RESET is
high, SDATA functions as a STANDBY control pin (see Table 9). This pin has an
internal 180kΩ pull-down resistor.
SEN
27
1
I
This pin functions as a serial interface enable input when RESET is low. When RESET
is high, SEN has no function and should be tied to AVDD. This pin has an internal
180kΩ pull-up resistor to AVDD.
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ADS412x, ADS414x Pin Assignments (LVDS Mode) (continued)
PIN NAME
PIN NUMBER
# OF
PINS
FUNCTION
DESCRIPTION
OE
7
1
I
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to
DRVDD.
DFS
6
1
I
Data format select input. This pin sets the DATA FORMAT (twos complement or offset
binary) and the LVDS/CMOS output interface type. See Table 7 for detailed information.
RESERVED
23
1
I
Digital control pin, reserved for future use
CLKOUTP
5
1
O
Differential output clock, true
CLKOUTM
4
1
O
Differential output clock, complement
D0_D1_P
Refer to Figure 1 and
Figure 2
1
O
Differential output data D0 and D1 multiplexed, true
D0_D1_M
Refer to Figure 1 and
Figure 2
1
O
Differential output data D0 and D1 multiplexed, complement
D2_D3_P
Refer to Figure 1 and
Figure 2
1
O
Differential output data D2 and D3 multiplexed, true
D2_D3_M
Refer to Figure 1 and
Figure 2
1
O
Differential output data D2 and D3 multiplexed, complement
D4_D5_P
Refer to Figure 1 and
Figure 2
1
O
Differential output data D4 and D5 multiplexed, true
D4_D5_M
Refer to Figure 1 and
Figure 2
1
O
Differential output data D4 and D5 multiplexed, complement
D6_D7_P
Refer to Figure 1 and
Figure 2
1
O
Differential output data D6 and D7 multiplexed, true
D6_D7_M
Refer to Figure 1 and
Figure 2
1
O
Differential output data D6 and D7 multiplexed, complement
D8_D9_P
Refer to Figure 1 and
Figure 2
1
O
Differential output data D8 and D9 multiplexed, true
D8_D9_M
Refer to Figure 1 and
Figure 2
1
O
Differential output data D8 and D9 multiplexed, complement
D10_D11_P
Refer to Figure 1 and
Figure 2
1
O
Differential output data D10 and D11 multiplexed, true
D10_D11_M
Refer to Figure 1 and
Figure 2
1
O
Differential output data D10 and D11 multiplexed, complement
D12_D13_P
Refer to Figure 1 and
Figure 2
1
O
Differential output data D12 and D13 multiplexed, true
D12_D13_M
Refer to Figure 1 and
Figure 2
1
O
Differential output data D12 and D13 multiplexed, complement
OVR_SDOUT
3
1
O
This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
DRVDD
2, 35
2
I
1.8V digital and output buffer supply
DRGND
1, 36, PAD
2
I
Digital and output buffer ground
NC
Refer to Figure 1 and
Figure 2
—
—
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PIN CONFIGURATION (CMOS MODE)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RGZ PACKAGE(3)
QFN-48
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
DRGND
1
36
DRGND
NC
31
NC
OE
7
30
RESET
AVDD
8
29
SCLK
AGND
9
28
SDATA
CLKP 10
27
SEN
CLKM 11
26
AVDD
AGND 12
25
AGND
13
14
15
16
17
18
19
20
21
22
23
24
AVDD
32
6
RESERVED
5
DFS
AVDD
CLKOUT
NC
NC
AVDD
33
AVDD
4
AGND
UNUSED
AGND
NC
INP
DRVDD
34
INM
35
3
AGND
2
VCM
DRVDD
OVR_SDOUT
(3) The PowerPAD is connected to DRGND.
Figure 3. ADS412x CMOS Pinout
12
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
RGZ PACKAGE(4)
QFN-48
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
DRGND
1
36
DRGND
NC
31
NC
OE
7
30
RESET
AVDD
8
29
SCLK
AGND
9
28
SDATA
CLKP 10
27
SEN
CLKM 11
26
AVDD
AGND 12
25
AGND
13
14
15
16
17
18
19
20
21
22
23
24
AVDD
32
6
RESERVED
5
DFS
AVDD
CLKOUT
NC
D0
AVDD
33
AVDD
4
AGND
UNUSED
AGND
D1
INP
DRVDD
34
INM
35
3
AGND
2
VCM
DRVDD
OVR_SDOUT
(4) The PowerPAD is connected to DRGND.
Figure 4. ADS414x CMOS Pinout
ADS412x, ADS414x Pin Assignments (CMOS Mode)
PIN NAME
PIN NUMBER
# OF
PINS
FUNCTION
AVDD
8, 18, 20, 22, 24, 26
6
I
1.8V analog power supply
AGND
9, 12, 14, 17, 19, 25
6
I
Analog ground
CLKP
10
1
I
Differential clock input, positive
CLKM
11
1
I
Differential clock input, negative
INP
15
1
I
Differential analog input, positive
INM
16
1
I
Differential analog input, negative
VCM
13
1
O
Outputs the common-mode voltage (0.95V) that can be used externally to bias the
analog input pins.
DESCRIPTION
RESET
30
1
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through
hardware RESET by applying a high pulse on this pin or by using the software reset
option; refer to the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this
condition, SEN can be used as an analog control pin.
RESET has an internal 180kΩ pull-down resistor.
SCLK
29
1
I
This pin functions as a serial interface clock input when RESET is low. When RESET is
high, SCLK has no function and should be tied to ground. This pin has an internal
180kΩ pull-down resistor.
SDATA
28
1
I
This pin functions as a serial interface data input when RESET is low. When RESET is
high, SDATA functions as a STANDBY control pin (see Table 9). This pin has an
internal 180kΩ pull-down resistor.
SEN
27
1
I
This pin functions as a serial interface enable input when RESET is low. When RESET
is high, SEN has no function and should be tied to AVDD. This pin has an internal
180kΩ pull-up resistor to AVDD.
OE
7
1
I
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to
DRVDD.
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ADS412x, ADS414x Pin Assignments (CMOS Mode) (continued)
PIN NAME
PIN NUMBER
# OF
PINS
FUNCTION
DESCRIPTION
I
Data format select input. This pin sets the DATA FORMAT (twos complement or offset
binary) and the LVDS/CMOS output interface type. See Table 7 for detailed information.
DFS
6
1
RESERVED
23
1
I
Digital control pin, reserved for future use
CLKOUT
5
1
O
CMOS output clock
D0
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D1
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D2
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D3
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D4
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D5
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D6
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D7
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D8
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D9
Refer to Figure 3 and
Figure 4
1
O
D10
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D11
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D12
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
D13
Refer to Figure 3 and
Figure 4
1
O
12-bit/14-bit CMOS output data
OVR_SDOUT
3
1
O
This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
14
12-bit/14-bit CMOS output data
DRVDD
2, 35
2
I
1.8V digital and output buffer supply
DRGND
1, 36, PAD
2
I
Digital and output buffer ground
UNUSED
4
1
—
Unused pin in CMOS mode
NC
Refer to Figure 3 and
Figure 4
—
—
Do not connect
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
DDR LVDS
Interface
DRGND
CLKP
CLKOUTP
CLOCKGEN
CLKOUTM
CLKM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
Low-Latency Mode
(Default After Reset)
INP
INM
12-Bit
ADC
Sampling
Circuit
Common
Digital Functions
D4_D5_P
DDR
Serializer
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
Control
Interface
Reference
VCM
D10_D11_P
D10_D11_M
OVR_SDOUT
DFS
SEN
SDATA
SCLK
RESET
ADS4129
OE
Figure 5. ADS412x Block Diagram
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AVDD
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AGND
DRVDD
DDR LVDS
Interface
DRGND
CLKOUTP
CLKP
CLOCKGEN
CLKOUTM
CLKM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Low-Latency Mode
(Default After Reset)
INP
INM
14-Bit
ADC
Sampling
Circuit
Common
Digital Functions
D6_D7_P
DDR
Serializer
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
Interface
Reference
VCM
D12_D13_P
D12_D13_M
OVR_SDOUT
DFS
SEN
SDATA
SCLK
RESET
ADS4149
OE
Figure 6. ADS414x Block Diagram
16
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TIMING CHARACTERISTICS
Dn_Dn + 1_P
Logic 0
VODL
Logic 1
VODH
Dn_Dn + 1_M
VOCM
GND
(1) With external 100Ω termination.
Figure 7. LVDS Output Voltage Levels
TIMING REQUIREMENTS: LVDS and CMOS Modes (1)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,
CLOAD = 5pF (2), and RLOAD = 100Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature
range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER
tA
CONDITIONS
Aperture delay
Variation of aperture
delay
tJ
MIN
TYP
MAX
UNIT
0.6
0.8
1.2
ns
Between two devices at the same temperature and
DRVDD supply
Aperture jitter
Wakeup time
ADC latency (4)
±100
ps
100
fS rms
Time to valid data after coming out of STANDBY
mode
5
25
µs
Time to valid data after coming out of PDN GLOBAL
mode
100
500
µs
Low-latency mode (default after reset)
10
Clock
cycles
Low-latency mode disabled (gain enabled, offset
correction disabled)
16
Clock
cycles
Low-latency mode disabled (gain and offset
correction enabled)
17
Clock
cycles
DDR LVDS MODE (5) (6)
tSU
Data setup time (3)
(3)
tH
Data hold time
tPDI
Clock propagation
delay
Variation of tPDI
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Data valid (7) to zero-crossing of CLKOUTP
0.75
1.1
ns
Zero-crossing of CLKOUTP to data becoming
invalid (7)
0.35
0.6
ns
Input clock rising edge cross-over to output clock
rising edge cross-over
1MSPS ≤ sampling frequency ≤ 250MSPS
3
4.2
Between two devices at the same temperature and
DRVDD supply
5.4
±0.6
ns
ns
Timing parameters are ensured by design and characterization but are not production tested.
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
RLOAD is the differential load resistance between the LVDS output pair.
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
The LVDS timings are unchanged for low latency disabled and enabled.
Data valid refers to a logic high of 1.26V and a logic low of 0.54V.
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TIMING REQUIREMENTS: LVDS and CMOS Modes(1) (continued)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,
CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature
range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Duty cycle of differential clock, (CLKOUTP –
CLKOUTM)
1MSPS ≤ sampling frequency ≤ 250MSPS
42
48
54
%
DDR LVDS MODE (continued)
LVDS bit clock duty
cycle
tRISE, tFALL
Data rise time,
Data fall time
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ sampling frequency ≤ 250MSPS
0.14
ns
tCLKRISE,
tCLKFALL
Output clock rise
time,
Output clock fall time
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ sampling frequency ≤ 250MSPS
0.14
ns
tOE
Output enable (OE) to
data delay
Time to valid data after OE becomes active
50
PARALLEL CMOS MODE
tSTART
Input clock to data
delay
tDV
Data valid time
tPDI
100
ns
1.1
ns
(8) (9)
Input clock rising edge cross-over to start of data
valid (10)
Time interval of valid data (10)
2.5
3.2
Clock propagation
delay
Input clock rising edge cross-over to output clock
rising edge cross-over
1MSPS ≤ sampling frequency ≤ 200MSPS
4
5.5
Output clock duty
cycle
Duty cycle of output clock, CLKOUT
1MSPS ≤ sampling frequency ≤ 200MSPS
47
%
ns
7
ns
tRISE, tFALL
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ sampling frequency ≤ 250MSPS
0.35
ns
tCLKRISE,
tCLKFALL
Output clock rise
time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ sampling frequency ≤ 200MSPS
0.35
ns
tOE
Output enable (OE) to
data delay
Time to valid data after OE becomes active
20
40
ns
(8) For fS > 200MSPS, it is recommended to use an external clock for data capture instead of the device output clock signal (CLKOUT).
(9) Low latency mode enabled.
(10) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.
18
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Table 2. LVDS Timing Across Sampling Frequencies
SAMPLING
FREQUENCY
(MSPS)
SETUP TIME (ns)
MIN
TYP
230
0.85
200
1.05
185
HOLD TIME (ns)
MAX
MIN
TYP
1.25
0.35
0.6
1.55
0.35
0.6
1.1
1.7
0.35
0.6
160
1.6
2.1
0.35
0.6
125
2.3
3
0.35
0.6
80
4.5
5.2
0.35
0.6
MAX
Table 3. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
200
1.6
185
160
tSETUP (ns)
tHOLD (ns)
MAX
MIN
TYP
2.2
1.8
1.8
2.4
2.3
2.9
125
3.1
80
5.4
tPDI (ns)
MAX
MIN
TYP
MAX
2.5
4
5.5
7
1.9
2.7
4
5.5
7
2.2
3
4
5.5
7
3.7
3.2
4
4
5.5
7
6
5.4
6
4
5.5
7
Table 4. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
MIN
TYP
MIN
TYP
MAX
200
1
1.6
2
2.8
4
5.5
7
185
1.3
2
2.2
3
4
5.5
7
160
1.8
2.5
2.5
3.3
4
5.5
7
125
2.5
3.2
3.5
4.3
4
5.5
7
80
4.8
5.5
5.7
6.5
4
5.5
7
tSETUP (ns)
tHOLD (ns)
MAX
tPDI (ns)
MAX
Table 5. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)
TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK
SAMPLING FREQUENCY
(MSPS)
tSTART (ns)
MIN
tDV (ns)
MAX
MIN
TYP
1.1
2.5
3.2
230
0.7
2.9
3.5
200
–0.3
3.5
4.2
185
–1
3.9
4.5
170
–1.5
4.3
5
250
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TYP
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Table 6. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)
TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK
SAMPLING FREQUENCY
(MSPS)
tSTART (ns)
MIN
tDV (ns)
MAX
MIN
TYP
250
TYP
1.6
2.5
3.2
230
1.1
2.9
3.5
200
0.3
3.5
4.2
185
0
3.9
4.5
170
–1.3
4.3
5
Sample N
N+3
N+2
N+1
N+4
MAX
N + 12
N + 11
N + 10
Input Signal
tA
CLKP
Input Clock
CLKM
CLKOUTM
CLKOUTP
tPDI
tH
10 Clock Cycles
DDR LVDS
(1)
tSU
(2)
Output Data
(DXP, DXM)
E
O
N - 10
E
O
N-9
E
O
E
N-8
O
N-7
O
E
E
O
O
E
N-6
E
O
N+1
N
E
O
E
O
N+2
tPDI
CLKOUT
tSU
Parallel CMOS
10 Clock Cycles
Output Data
N - 10
N-9
N-8
(1)
N-7
tH
N-1
N
N+1
(1) ADC latency in low-latency mode. At higher sampling frequencies, tDPI is greater than one clock cycle which then makes the overall
latency = ADC latency + 1.
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).
Figure 8. Latency Diagram
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CLKM
Input
Clock
CLKP
tPDI
CLKOUTP
Output
Clock
CLKOUTM
tSU
Output Dn_Dn + 1_P
Data Pair Dn_Dn + 1_M
tSU
tH
Dn
(1)
Dn + 1
tH
(1)
(1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc.
Figure 9. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
Output
Data
Dn
tH
Dn
(1)
CLKM
Input
Clock
CLKP
tSTART
tDV
Output
Data
Dn
Dn
(1)
Dn = bits D0, D1, D2, etc.
Figure 10. CMOS Mode Timing
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DEVICE CONFIGURATION
The ADS412x/4x have several modes that can be configured using a serial programming interface, as described
in Table 7, Table 8, and Table 9. In addition, the devices have two dedicated parallel pins for quickly configuring
commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The
analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).
Table 7. DFS: Analog Control Pin
VOLTAGE APPLIED ON DFS
DESCRIPTION
(Data Format/Output Interface)
0, +100mV/–0mV
Twos complement/DDR LVDS
(3/8) AVDD ± 100mV
Twos complement/parallel CMOS
(5/8) AVDD ± 100mV
Offset binary/parallel CMOS
AVDD, +0mV/–100mV
Offset binary/DDR LVDS
Table 8. OE: Digital Control Pin
VOLTAGE APPLIED ON OE
DESCRIPTION
0
Output data buffers disabled
AVDD
Output data buffers enabled
When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device
in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have
any alternative functions. Keep SEN tied high and SCLK tied low on the board.
Table 9. SDATA: Digital Control Pin
VOLTAGE APPLIED ON SDATA
DESCRIPTION
0
Normal operation
Logic high
Device enters standby
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
(3/8) AVDD
3R
(3/8) AVDD
To Parallel Pin
Figure 11. Simplified Diagram to Configure DFS Pin
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SERIAL INTERFACE
The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface
formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data)
pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every
falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK
falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the
register address and the remaining eight bits are the register data. The interface can work with SCLK frequency
from 20MHz down to very low speeds (a few Hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10ns), as shown
in Figure 12; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin is kept low.
Register Address
SDATA
A7
A6
A5
A3
A4
Register Data
A2
A1
A0
D7
D6
D5
tSCLK
D4
tDSU
D3
D2
D1
D0
tDH
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 12. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at +25°C, minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
PARAMETER
MIN
TYP
UNIT
20
MHz
SCLK frequency (equal to 1/tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
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MAX
fSCLK
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Serial Register Readout
The serial register readout function allows the contents of the internal registers to be read back on the
OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface
communication between the external controller and the ADC.
After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When
the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:
1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any
further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is
also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of
the register at address 0 cannot be read in the register readout mode.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.
4. The external controller can latch the contents at the falling edge of SCLK.
5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the
device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.
Register Address A[7:0] = 0x00
SDATA
0
0
0
0
0
0
Register Data D[7:0] = 0x01
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
OVR_SDOUT
(1)
a) Enable Serial Readout (READOUT = 1)
Register Address A[7:0] = 0x43
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
0
SCLK
SEN
OVR_SDOUT
(2)
b) Read Contents of Register 0x43. This Register Has Been Initialized with 0x40 (device is put in global power-down mode).
(1) The OVR_SDOUT pin functions as OVR (READOUT = 0).
(2) The OVR_SDOUT pin functions as a serial readout (READOUT = 1).
Figure 13. Serial Readout Timing Diagram
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RESET TIMING CHARACTERISTICS
Power Supply
AVDD, DRVDD
t1
RESET
t3
t2
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 14. Reset Timing Diagram
RESET TIMING REQUIREMENTS
Typical values at +25°C and minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
unless otherwise noted.
PARAMETER
t1
Power-on delay
t2
Reset pulse width
t3
(1)
TEST CONDITIONS
MIN
Delay from power-up of AVDD and DRVDD to RESET
pulse active
1
Pulse width of active RESET signal that resets the
serial registers
10
Delay from RESET disable to SEN active
100
TYP
MAX
UNIT
ms
ns
1
(1)
µs
ns
The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could
enter the parallel configuration mode briefly and then return back to serial interface mode.
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SERIAL REGISTER MAP
Table 10 summarizes the functions supported by the serial interface.
Table 10. Serial Interface Register Map (1)
(1)
REGISTER
ADDRESS
DEFAULT VALUE
AFTER RESET
A[7:0] (Hex)
D[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00
00
0
0
0
0
0
0
RESET
READOUT
01
00
0
0
03
00
0
0
0
0
0
HIGH PERF MODE 1
25
00
26
00
0
3D
00
DATA FORMAT
3F
00
40
00
REGISTER DATA
LVDS SWING
0
DISABLE
GAIN
GAIN
0
TEST PATTERNS
0
0
0
0
EN
OFFSET
CORR
0
0
0
LVDS
LVDS DATA
CLKOUT
STRENGTH
STRENGTH
0
0
CUSTOM PATTERN HIGH D[13:6]
CUSTOM PATTERN D[5:0]
0
CMOS CLKOUT
STRENGTH
EN
CLKOUT
RISE
CLKOUT FALL POSN
0
0
DIS LOW
LATENCY
STBY
0
PDN
GLOBAL
0
PDN OBUF
0
0
0
0
0
0
0
0
41
00
LVDS CMOS
42
00
43
00
4A
00
BF
00
CLKOUT RISE POSN
0
CF
00
DF
00
0
0
0
OFFSET CORR TIME CONSTANT
LOW SPEED
0
0
EN LVDS SWING
OFFSET PEDESTAL
FREEZE
OFFSET
CORR
0
EN
CLKOUT
FALL
0
0
HIGH PERF
MODE 2
0
0
0
0
0
0
Multiple functions in a register can be programmed in a single write operation.
DESCRIPTION OF SERIAL REGISTERS
For best performance, two special mode register bits must be enabled: HI PERF MODE 1 and HI PERF MODE
2.
Register Address 00h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
RESET
READOUT
Bits[7:2]
Always write '0'
Bit 1
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit 0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage
indicator.
1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout.
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Register Address 01h (Default = 00h)
7
6
5
4
3
2
LVDS SWING
Bits[7:2]
(1)
0
0
0
0
LVDS SWING: LVDS swing programmability (1)
000000 =
011011 =
110010 =
010100 =
111110 =
001111 =
Bits[1:0]
1
Default LVDS swing; ±350mV with external 100Ω termination
LVDS swing increases to ±410mV
LVDS swing increases to ±465mV
LVDS swing increases to ±570mV
LVDS swing decreases to ±200mV
LVDS swing decreases to ±125mV
Always write '0'
The EN LVDS SWING register bits must be set to enable LVDS swing control.
Register Address 03h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
HI PERF MODE 1
Bits[7:2]
Always write '0'
Bits[1:0]
HI PERF MODE 1: High performance mode 1
00 = Default performance after reset
01 = Do not use
10 = Do not use
11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF
MODE 1 bits
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Register Address 25h (Default = 00h)
7
6
5
4
GAIN
Bits[7:4]
3
2
DISABLE GAIN
1
0
TEST PATTERNS
GAIN: Gain programmability
These bits set the gain programmability in 0.5dB steps.
0000
0001
0010
0011
0100
0101
0110
Bit 3
=
=
=
=
=
=
=
0dB gain (default after reset)
0.5dB gain
1.0dB gain
1.5dB gain
2.0dB gain
2.5dB gain
3.0dB gain
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
3.5dB gain
4.0dB gain
4.5dB gain
5.0dB gain
5.5dB gain
6dB gain
DISABLE GAIN: Gain setting
This bit sets the gain.
0 = Gain enabled; gain is set by the GAIN bits only if low-latency mode is disabled
1 = Gain disabled
Bits[2:0]
TEST PATTERNS: Data capture
These bits verify data capture.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In the ADS4146/49, output data D[13:0] is an alternating sequence of 01010101010101 and
10101010101010.
In the ADS4126/29, output data D[11:0] is an alternating sequence of 010101010101 and
101010101010.
100 = Outputs digital ramp
In ADS4149/46, output data increments by one LSB (14-bit) every clock cycle from code 0 to
code 16383
In ADS4129/26, output data increments by one LSB (12-bit) every 4th clock cycle from code 0 to
code 4095
101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern)
110 = Unused
111 = Unused
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Register Address 26h (Default = 00h)
7
6
0
5
0
4
0
3
0
0
2
1
0
0
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
Bits[7:2]
Always write '0'
Bit 1
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength
This bit determines the external termination to be used with the LVDS output clock buffer.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Bit 0
LVDS DATA STRENGTH: LVDS data buffer strength
This bit determines the external termination to be used with all of the LVDS data buffers.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Register Address 3Dh (Default = 00h)
7
6
DATA FORMAT
Bits[7:6]
5
4
3
2
1
0
EN OFFSET
CORR
0
0
0
0
0
DATA FORMAT: Data format selection
These bits selects the data format.
00 = The DFS pin controls data format selection
10 = Twos complement
11 = Offset binary
Bit 5
ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
PATTERN D13
CUSTOM
PATTERN D12
CUSTOM
PATTERN D11
CUSTOM
PATTERN D10
CUSTOM
PATTERN D9
CUSTOM
PATTERN D8
CUSTOM
PATTERN D7
CUSTOM
PATTERN D6
Bits[7:0]
CUSTOM PATTERN (1)
These bits set the custom pattern.
(1)
For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
Register Address 40h (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
PATTERN D5
CUSTOM
PATTERN D4
CUSTOM
PATTERN D3
CUSTOM
PATTERN D2
CUSTOM
PATTERN D1
CUSTOM
PATTERN D0
0
0
Bits[7:2]
CUSTOM PATTERN (1)
These bits set the custom pattern.
Bits[1:0]
(1)
Always write '0'
For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
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Register Address 41h (Default = 00h)
7
6
LVDS CMOS
Bits[7:6]
5
4
CMOS CLKOUT STRENGTH
3
EN CLKOUT
RISE
2
1
CLKOUT RISE POSN
0
EN CLKOUT
FALL
LVDS CMOS: Interface selection
These bits select the interface.
00 = The DFS pin controls the selection of either LVDS or CMOS interface
10 = The DFS pin controls the selection of either LVDS or CMOS interface
01 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
Controls strength of CMOS output clock only.
00 = Maximum strength (recommended and used for specified timings)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bit 3
ENABLE CLKOUT RISE
0 = Disables control of output clock rising edge
1 = Enables control of output clock rising edge
Bits[2:1]
CLKOUT RISE POSN: CLKOUT rise control
Controls position of output clock rising edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 500ps, hold increases by 500ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 100ps, hold increases by 100ps
10 = Setup reduces by 200ps, hold increases by 200ps
11 = Setup reduces by 1.5ns, hold increases by 1.5ns
Bit 0
ENABLE CLKOUT FALL
0 = Disables control of output clock fall edge
1 = Enables control of output clock fall edge
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Register Address 42h (Default = 00h)
7
6
CLKOUT FALL CTRL
Bits[7:6]
5
0
4
3
2
1
0
0
DIS LOW
LATENCY
STBY
0
0
CLKOUT FALL CTRL
Controls position of output clock falling edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 400ps, hold increases by 400ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Falling edge is advanced by 100ps
10 = Falling edge is advanced by 200ps
11 = Falling edge is advanced by 1.5ns
Bits[5:4]
Always write '0'
Bit 3
DIS LOW LATENCY: Disable low latency
This bit disables low-latency mode,
0 = Low latency mode is enabled. Digital functions such as gain, test patterns and offset correction
are disabled
1 = Low-latency mode is disabled. This setting enables the digital functions. See the Digital
Functions and Low Latency Mode section.
Bit 2
STBY: Standby mode
This bit sets the standby mode.
0 = Normal operation
1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time
from standby is fast
Bits[1:0]
Always write '0'
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Register Address 43h (Default = 00h)
7
6
5
4
3
2
1
0
PDN GLOBAL
0
PDN OBUF
0
0
EN LVDS SWING
Bit 0
Always write '0'
Bit 6
PDN GLOBAL: Power-down
0
This bit sets the state of operation.
0 = Normal operation
1 = Total power down; the ADC, internal references, and output buffers are powered down; slow
wake-up time.
Bit 5
Always write '0'
Bit 4
PDN OBUF: Power-down output buffer
This bit set the output data and clock pins.
0 = Output data and clock pins enabled
1 = Output data and clock pins powered down and put in high- impedance state
Bits[3:2]
Always write '0'
Bits[1:0]
EN LVDS SWING: LVDS swing control
00
01
10
11
=
=
=
=
LVDS swing control using LVDS SWING register bits is disabled
Do not use
Do not use
LVDS swing control using LVDS SWING register bits is enabled
Register Address 4Ah (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
HI PERF
MODE 2
Bits[7:1]
Always write '0'
Bit[0]
HI PERF MODE 2: High performance mode 2
This bit is recommended for high input signal frequencies greater than 230MHz.
0 = Default performance after reset
1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit
32
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
Register Address BFh (Default = 00h)
7
6
5
4
3
2
OFFSET PEDESTAL
Bits[7:2]
1
0
0
0
OFFSET PEDESTAL
These bits set the offset pedestal.
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC mid-code value. A pedestal can be added to the final converged value by programming these
bits.
Bits[1:0]
ADS414x VALUE
PEDESTAL
011111
011110
011101
—
000000
—
111111
111110
—
100000
31LSB
30LSB
29LSB
—
0LSB
—
–1LSB
–2LSB
—
–32LSB
Always write '0'
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Register Address CFh (Default = 00h)
7
6
FREEZE
OFFSET
CORR
BYPASS
OFFSET
CORR
Bit 7
5
4
3
2
OFFSET CORR TIME CONSTANT
1
0
0
0
FREEZE OFFSET CORR
This bit sets the freeze offset correction.
0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set)
1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the
last estimated value is used for offset correction every clock cycle. See OFFSET CORRECTION,
Offset Correction.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
These bits set the offset correction time constant for the correction loop time constant in number of
clock cycles.
Bits[1:0]
VALUE
TIME CONSTANT (Number of Clock Cycles)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1M
2M
4M
8M
16M
32M
64M
128M
256M
512M
1G
2G
Always write '0'
Register Address DFh (Default = 00h)
7
6
0
0
5
4
LOW SPEED
Bits[7:1]
Always write '0'
Bit 0
LOW SPEED: Low-speed mode
3
2
1
0
0
0
0
0
00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for
sampling rates greater than 80MSPS.
11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal
to 80MSPS.
34
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4126
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
FFT FOR 10MHz INPUT SIGNAL
0
SFDR = 94dBc
SNR = 70dBFS
SINAD = 70dBFS
THD = 93dBc
-20
SFDR = 82.5dBc
SNR = 69.2dBFS
SINAD = 68.9dBFS
THD = 80.7dBc
-20
-40
Amplitude (dB)
Amplitude (dB)
FFT FOR 170MHz INPUT SIGNAL
0
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
10
20
30
40
60
50
70
80
0
50
-40
-60
-80
-100
-120
30
40
50
60
60
70
80
FFT FOR TWO-TONE INPUT SIGNAL
Amplitude (dB)
Amplitude (dB)
-20
70
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
80
Each Tone at -7dBFS Amplitude
fIN1 = 185MHz
fIN2 = 190MHz
Two-Tone IMD = 89dBFS
SFDR = 93dBFS
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 17.
Figure 18.
SFDR vs INPUT FREQUENCY
60
70
80
SNR vs INPUT FREQUENCY
71.0
95
70.5
90
-2dBFS Input, 0dB Gain
70.0
69.5
SNR (dBFS)
85
SFDR (dBc)
40
Figure 16.
SFDR = 78.3dBc
SNR = 67.6dBFS
SINAD = 67dBFS
THD = 75.3dBc
20
30
Figure 15.
FFT FOR 300MHz INPUT SIGNAL
10
20
Frequency (MHz)
0
0
10
Frequency (MHz)
80
75
70
69.0
68.5
68.0
-1dBFS Input, 1dB Gain
67.5
67.0
66.5
-1dBFS Input, 1dB Gain
-2dBFS Input, 0dB Gain
65
60
66.0
65.5
65.0
0
50
100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50
100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 19.
Copyright © 2009–2011, Texas Instruments Incorporated
Figure 20.
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TYPICAL CHARACTERISTICS: ADS4126 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR vs INPUT FREQUENCY (CMOS)
SNR vs INPUT FREQUENCY (CMOS)
90
71.5
88
71.0
86
70.5
82
70.0
SNR (dBFS)
SFDR (dBc)
84
80
78
76
69.5
69.0
68.5
74
68.0
72
67.5
70
68
67.0
0
50
100
150
200
250
350
300
0
50
100
Input Frequency (MHz)
150
Figure 21.
170MHz
250
350
300
Figure 22.
SFDR ACROSS GAIN AND INPUT FREQUENCY
88
200
Input Frequency (MHz)
SINAD ACROSS GAIN AND INPUT FREQUENCY
71
150MHz
170MHz
70
84
69
SINAD (dBFS)
SFDR (dBc)
80
220MHz
300MHz
76
72
400MHz
150MHz
68
67
220MHz
66
400MHz
300MHz
65
64
68
63
500MHz
64
500MHz
62
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Gain (dB)
Gain (dB)
Figure 23.
Figure 24.
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
105
105
74
74
SFDR (dBFS)
73
85
72
65
71
SNR (dBFS)
55
70
69
SFDR (dBc)
95
73
85
72
75
71
65
70
SNR (dBFS)
55
69
SFDR (dBc)
45
68
45
68
Input Frequency = 40.1MHz
35
-50
Input Frequency = 170.1MHz
67
-40
-30
-20
Input Amplitude (dBFS)
-10
0
35
-50
67
-40
-30
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-20
-10
0
Input Amplitude (dBFS)
Figure 25.
36
SNR (dBFS)
75
SFDR (dBc, dBFS)
95
SNR (dBFS)
SFDR (dBc, dBFS)
SFDR (dBFS)
Figure 26.
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Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
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ADS4146, ADS4149
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4126 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
71.0
90
88
SNR
88
70.5
86
70.0
87
69.5
82
69.0
SFDR (dBc)
SFDR
84
SNR (dBFS)
SFDR (dBc)
86
AVDD = 1.8V
84
83
AVDD = 1.75V
AVDD = 1.7V
82
68.5
80
81
Input Frequency = 40MHz
78
0.80
0.90
0.85
0.95
1.00
1.05
AVDD = 1.85V
AVDD = 1.9V
85
68.0
1.10
80
fIN = 40MHz
-40
35
10
-15
Input Common-Mode Voltage (V)
85
60
Temperature (°C)
Figure 27.
Figure 28.
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
73.0
87
72.0
fIN = 40MHz
72.5
86
71.5
SFDR
SFDR (dBc)
70.5
AVDD = 1.75V, 1.8V, 1.9V
70.0
85
72.0
84
71.5
SNR (dBFS)
SNR (dBFS)
AVDD = 1.7V, 1.85V
71.0
71.0
83
SNR
70.5
82
69.5
fIN = 40MHz
-40
35
10
-15
60
70.0
81
1.70
69.0
85
1.75
1.80
DRVDD Supply (V)
Temperature (°C)
Figure 29.
Figure 30.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
(CMOS)
87
73.0
86
72.5
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
78
86
76
71.0
83
SNR
70.5
82
SFDR (dBc)
71.5
84
78
72
74
70
70
68
SNR (dBFS)
66
66
62
64
58
1.75
1.80
1.85
DRVDD Supply (V)
70.0
1.90
54
0.1
Input Frequency = 170MHz
62
60
0.3
0.5
0.7
0.9
1.1 1.3
1.5
1.7
1.9
2.1
2.3
Differential Clock Amplitude (VPP)
Figure 31.
Copyright © 2009–2011, Texas Instruments Incorporated
74
SFDR (dBc)
SNR (dBFS)
72.0
85
SNR (dBFS)
SFDR (dBc)
90
82
SFDR
81
1.70
1.90
1.85
Figure 32.
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www.ti.com
TYPICAL CHARACTERISTICS: ADS4126 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
85
71.5
0.2
71.0
0.1
SNR
70.5
83
THD
70.0
82
81
INL (LSB)
0.3
SNR (dBFS)
72.0
84
THD (dBc)
INTEGRAL NONLINEARITY
86
0
-0.1
69.5
-0.2
69.0
-0.3
Input Frequency = 10MHz
80
25
30
35
40
45
50
55
60
65
70
75
0
500
1000
Input Clock Duty Cycle (%)
1500
2000
2500
3000
3500
4000
Output Code (LSB)
Figure 33.
Figure 34.
DIFFERENTIAL NONLINEARITY
0.20
0.15
DNL (LSB)
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
0
500
1000
1500
2000
2500
3000
3500
4000
Output Code (LSB)
Figure 35.
38
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4129
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
FFT FOR 10MHz INPUT SIGNAL
0
SFDR = 87.7dBc
SNR = 70.3dBFS
SINAD = 70.2dBFS
THD = 83.5dBc
-20
-40
-60
-80
SFDR = 87.2dBc
SNR = 69.6dBFS
SINAD = 69.4dBFS
THD = 83.9dBc
-20
Amplitude (dB)
Amplitude (dB)
FFT FOR 170MHz INPUT SIGNAL
0
-100
-40
-60
-80
-100
-120
-120
0
25
100
75
50
125
0
25
Frequency (MHz)
50
Figure 36.
FFT FOR 300MHz INPUT SIGNAL
-40
Amplitude (dB)
Amplitude (dB)
-20
-60
-80
-100
-120
75
50
100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
125
Each Tone at
-7dBFS Amplitude
fIN1 = 185MHz
fIN2 = 190MHz
Two-Tone IMD = 90dBFS
SFDR = 94dBFS
0
25
Frequency (MHz)
50
75
100
125
Frequency (GHz)
Figure 38.
Figure 39.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
71.0
95
70.5
90
-2dBFS Input, 0dB Gain
70.0
-1dBFS Input, 1dB Gain
69.5
SNR (dBFS)
85
SFDR (dBc)
125
FFT FOR TWO-TONE INPUT SIGNAL
SFDR = 79.3dBc
SNR = 68dBFS
SINAD = 67.5dBFS
THD = 76.3dBc
25
100
Figure 37.
0
0
75
Frequency (MHz)
80
-2dBFS Input, 0dB Gain
75
70
69.0
68.5
-1dBFS Input, 1dB Gain
68.0
67.5
67.0
66.5
65
66.0
60
65.5
0
50
100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50
100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 40.
Copyright © 2009–2011, Texas Instruments Incorporated
Figure 41.
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www.ti.com
TYPICAL CHARACTERISTICS: ADS4129 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR vs INPUT FREQUENCY (CMOS)
SNR vs INPUT FREQUENCY (CMOS)
71.0
90
70.5
70.0
SNR (dBFS)
SFDR (dBc)
86
82
78
69.5
69.0
68.5
68.0
74
67.5
67.0
70
0
50
100
150
200
250
350
300
0
50
100
150
250
200
350
300
Input Frequency (MHz)
Input Frequency (MHz)
Figure 42.
Figure 43.
SFDR ACROSS GAIN AND INPUT FREQUENCY
SINAD ACROSS GAIN AND INPUT FREQUENCY
90
71
170MHz
150MHz
70
86
150MHz
82
SINAD (dBFS)
SFDR (dBc)
69
220MHz
78
300MHz
74
68
300MHz
66
65
400MHz
400MHz
70
64
500MHz
500MHz
66
63
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Gain (dB)
Gain (dB)
Figure 44.
Figure 45.
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
105
105
72.0
74
SFDR (dBFS)
SFDR (dBFS)
85
71.0
75
70.5
65
70.0
55
69.5
95
73
85
72
75
71
65
70
SFDR (dBc)
55
69
SNR (dBFS)
SFDR (dBc)
45
69.0
45
68
Input Frequency = 170.1MHz
Input Frequency = 40.1MHz
35
-50
68.5
-40
-30
SNR (dBFS)
SNR (dBFS)
SFDR (dBc, dBFS)
71.5
SNR (dBFS)
SFDR (dBc, dBFS)
95
-20
Input Amplitude (dBFS)
-10
0
35
-50
67
-40
-30
Submit Documentation Feedback
-20
-10
0
Input Amplitude (dBFS)
Figure 46.
40
170MHz
220MHz
67
Figure 47.
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Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4129 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
72.0
87
92
71.5
86
90
71.0
88
70.5
94
AVDD = 1.8V
86
70.0
84
69.5
SFDR
82
0.90
0.85
0.95
1.00
1.05
AVDD = 1.9V
84
AVDD = 1.85V
83
AVDD = 1.75V
82
69.0
80
78
0.80
SFDR (dBc)
SNR
85
SNR (dBFS)
SFDR (dBc)
Input Frequency = 40MHz
68.5
81
68.0
1.10
80
AVDD = 1.7V
fIN = 40MHz
-40
Figure 49.
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
72.0
88
72.0
fIN = 40MHz
71.5
87
SFDR
SFDR (dBc)
70.5
70.0
69.5
AVDD = 1.7V
AVDD = 1.75V
AVDD = 1.8V
AVDD = 1.85V
AVDD = 1.9V
69.0
68.5
-15
SNR
85
70.5
84
70.0
69.5
83
fIN = 40MHz
35
10
60
69.0
82
1.70
68.0
-40
71.0
86
85
1.75
1.80
Figure 50.
Figure 51.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
(CMOS)
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
90
72.0
88
74
88
70.5
85
SNR
70.0
84
69.5
83
72
84
71
82
70
80
69
78
68
SNR (dBFS)
76
67
74
66
72
1.80
1.85
DRVDD Supply (V)
69.0
1.90
70
0.15
Input Frequency = 170MHz
0.37
0.75
1.00
1.25
1.60
1.90
2.20
2.40
65
64
2.60
Differential Clock Amplitude (VPP)
Figure 52.
Copyright © 2009–2011, Texas Instruments Incorporated
73
SFDR (dBc)
86
SNR (dBFS)
71.0
86
SFDR (dBc)
SFDR
SNR (dBFS)
SFDR (dBc)
71.5
1.75
1.90
1.85
DRVDD Supply (V)
Temperature (°C)
82
1.70
SNR (dBFS)
SNR (dBFS)
71.0
87
85
60
Temperature (°C)
Figure 48.
71.5
35
10
-15
Input Common-Mode Voltage (V)
Figure 53.
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ADS4126, ADS4129
ADS4146, ADS4149
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4129 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
85
72.5
84
72.0
83
71.5
THD
82
71.0
70.5
81
SNR
80
INTEGRAL NONLINEARITY
0.3
0.2
0.1
INL (LSB)
73.0
SNR (dBFS)
THD (dBc)
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
86
0
-0.1
70.0
-0.2
69.5
79
Input Frequency = 10MHz
-0.3
69.0
78
25
30
35
40
45
50
55
60
65
70
75
0
500
1000
Input Clock Duty Cycle (%)
1500
2000
2500
3000
3500
4000
Output Code (LSB)
Figure 54.
Figure 55.
DIFFERENTIAL NONLINEARITY
0.3
DNL (LSB)
0.2
0.1
0
-0.1
-0.2
-0.3
0
500
1000
1500
2000
2500
3000
3500
4000
Output Code (LSB)
Figure 56.
42
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ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4146
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
FFT FOR 10MHz INPUT SIGNAL
0
SFDR = 94dBc
SNR = 72.25dBFS
SINAD = 72.20dBFS
THD = 91.29dBc
-10
-20
-40
-50
-60
-70
-80
SFDR = 82.5dBc
SNR = 70.8dBFS
SINAD = 70.4dBFS
THD = 80.6dBc
-10
-20
-30
Amplitude (dB)
-30
Amplitude (dB)
FFT FOR 170MHz INPUT SIGNAL
0
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
10
20
30
40
60
50
70
80
0
-20
Amplitude (dB)
Amplitude (dB)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
30
40
50
60
70
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
60
80
70
80
Each Tone at
-7dBFS Amplitude
fIN1 = 185MHz
fIN2 = 190MHz
Two-Tone IMD = 89.5dBFS
SFDR = 95dBFS
0
25
50
Figure 59.
SNR vs INPUT FREQUENCY
-2dBFS Input, 0dB Gain
73
-1dBFS Input, 1dB Gain
-2dBFS Input, 0dB Gain
72
SNR (dBFS)
85
70
125
74
90
75
100
Figure 60.
SFDR vs INPUT FREQUENCY
80
75
Frequency (MHz)
Frequency (MHz)
SFDR (dBc)
50
FFT FOR TWO-TONE INPUT SIGNAL
SFDR = 78.1dBc
SNR = 68.4dBFS
SINAD = 67.8dBFS
THD = 75.2dBc
95
40
Figure 58.
-10
20
30
Figure 57.
FFT FOR 300MHz INPUT SIGNAL
10
20
Frequency (MHz)
0
0
10
Frequency (MHz)
71
70
-1dBFS Input, 1dB Gain
69
68
67
65
66
60
65
0
50
100 150 200 250 300 350 400 450 500
0
100
200
300
400
Input Frequency (MHz)
Input Frequency (MHz)
Figure 61.
Figure 62.
Copyright © 2009–2011, Texas Instruments Incorporated
500
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600
43
ADS4126, ADS4129
ADS4146, ADS4149
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4146 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR vs INPUT FREQUENCY (CMOS)
SNR vs INPUT FREQUENCY (CMOS)
74
90
88
73
86
SNR (dBFS)
84
SFDR (dBc)
82
80
78
76
72
71
70
74
72
69
70
68
68
0
50
100
150
200
250
350
300
0
50
100
150
250
200
Input Frequency (MHz)
Input Frequency (MHz)
Figure 63.
Figure 64.
SFDR ACROSS GAIN AND INPUT FREQUENCY
88
170MHz
SINAD ACROSS GAIN AND INPUT FREQUENCY
73
150MHz
170MHz
84
71
80
69
SINAD (dBFS)
SFDR (dBc)
220MHz
220MHz
300MHz
350
300
76
72
150MHz
300MHz
67
400MHz
65
400MHz
68
63
500MHz
500MHz
64
61
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Gain (dB)
Figure 65.
Figure 66.
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
100
76
SFDR (dBFS)
76
105
SFDR (dBFS)
95
75
80
74
85
74
70
73
75
73
60
72
SNR (dBFS)
50
71
40
70
SFDR (dBc, dBFS)
75
65
72
SFDR (dBc)
55
71
SNR (dBFS)
SNR (dBFS)
90
SNR (dBFS)
SFDR (dBc, dBFS)
0
Gain (dB)
70
45
SFDR (dBc)
69
30
69
35
Input Frequency = 40.1MHz
20
-60
Input Frequency = 170.1MHz
68
-50
-40
-30
-20
Input Amplitude (dBFS)
-10
0
25
-60
68
-50
-40
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-20
-10
0
Input Amplitude (dBFS)
Figure 67.
44
-30
Figure 68.
Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4146 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
90
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
75.5
88
75.0
87
74.5
86
Input Frequency = 40MHz
88
84
74.0
82
73.5
80
73.0
SNR
SNR (dBFS)
SFDR (dBc)
SFDR
SFDR (dBc)
AVDD = 1.85V
86
84
83
AVDD = 1.75V
72.5
82
76
72.0
81
71.5
1.10
80
0.90
0.85
0.95
AVDD = 1.9V
85
78
74
0.80
AVDD = 1.8V
1.00
1.05
AVDD = 1.7V
fIN = 40MHz
-40
Figure 70.
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
75.5
88
75.0
74.5
SFDR
SFDR (dBc)
AVDD = 1.75V, 1.85V
73.5
73.0
75.0
87
AVDD = 1.8V
AVDD = 1.7V
AVDD = 1.9V
72.5
74.5
86
SNR (dBFS)
SNR (dBFS)
85
60
Temperature (°C)
Figure 69.
74.0
35
10
-15
Input Common-Mode Voltage (V)
74.0
85
SNR
73.5
84
72.0
71.0
73.0
83
71.5
fIN = 40MHz
fIN = 40MHz
-40
-15
35
10
60
72.5
82
1.70
85
1.75
1.80
DRVDD Supply (V)
Temperature (°C)
Figure 71.
Figure 72.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
(CMOS)
89
75.0
88
74.5
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
90
85
73.0
SNR
72.5
SFDR (dBc)
SFDR (dBc)
73.5
74
78
72
74
70
70
68
SNR (dBFS)
66
66
62
64
58
83
1.70
1.75
1.80
1.85
DRVDD Supply (V)
72.0
1.90
Input Frequency = 170MHz
54
62
60
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1 2.3
Differential Clock Amplitude (VPP)
Figure 73.
Copyright © 2009–2011, Texas Instruments Incorporated
76
SFDR (dBc)
82
SNR (dBFS)
86
SNR (dBFS)
74.0
87
78
86
SFDR
84
1.90
1.85
Figure 74.
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ADS4126, ADS4129
ADS4146, ADS4149
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4146 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
INTEGRAL NONLINEARITY
75.0
1.0
87
74.5
0.8
86
74.0
85
73.5
73.0
72.5
83
0.4
INL (LSB)
SNR
84
0.6
SNR (dBFS)
THD (dBc)
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
88
THD
82
72.0
81
71.5
0.2
0
-0.2
-0.4
-0.6
-0.8
Input Frequency = 10MHz
71.0
80
60
65
70
-1.0
75
0
2k
6k
4k
Input Clock Duty Cycle (%)
Figure 75.
10k
36
0.4
32
Code Occurrence (%)
0.3
0.2
0.1
0
-0.1
-0.2
31.1
27.5
23.1
24
20
16
12.2
12
8
-0.4
4
-0.5
0
4.8
1.0
8230
8228
16k
8226
14k
8227
12k
8224
10k
8225
8k
8222
6k
Output Code (LSB)
8223
0.3
4k
16k
RMS = 1.137LSB
28
-0.3
2k
14k
OUTPUT HISTOGRAM WITH INPUTS SHORTED
0.5
0
12k
Figure 76.
DIFFERENTIAL NONLINEARITY
DNL (LSB)
8k
Output Code (LSB)
8236
55
8234
50
8235
45
8232
40
8233
35
8231
30
8229
25
Output Code (LSB)
Figure 77.
46
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Figure 78.
Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4149
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
FFT FOR 10MHz INPUT SIGNAL
0
SFDR = 88.3dBc
SNR = 72.4dBFS
SINAD = 72.2dBFS
THD = 84dBc
-20
-40
-60
-80
SFDR = 87.2dBc
SNR = 71.3dBFS
SINAD = 71.2dBFS
THD = 84.7dBc
-20
Amplitude (dB)
Amplitude (dB)
FFT FOR 170MHz INPUT SIGNAL
0
-100
-40
-60
-80
-100
-120
-120
0
25
100
75
50
125
0
25
Frequency (MHz)
Figure 79.
FFT FOR 300MHz INPUT SIGNAL
-20
Amplitude (dB)
Amplitude (dB)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
75
50
125
FFT FOR TWO-TONE INPUT SIGNAL
SFDR = 78.9dBc
SNR = 68.8dBFS
SINAD = 68.3dBFS
THD = 76.6dBc
-10
25
100
Figure 80.
0
0
75
50
Frequency (MHz)
100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
125
Each Tone at
-7dBFS Amplitude
fIN1 = 185MHz
fIN2 = 190MHz
Two-Tone IMD = 89.5dBFS
SFDR = 95dBFS
0
25
Frequency (MHz)
50
75
100
125
Frequency (MHz)
Figure 81.
Figure 82.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
74
90
73
86
SNR (dBFS)
SFDR (dBc)
72
82
78
74
-2dBFS Input, 0dB Gain
71
70
69
-1dBFS Input, 1dB Gain
68
70
-1dBFS Input, 1dB Gain
-2dBFS Input, 0dB Gain
66
0
50
100 150 200 250 300 350 400 450 500
67
66
0
50
100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Input Frequency (MHz)
Figure 83.
Figure 84.
Copyright © 2009–2011, Texas Instruments Incorporated
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47
ADS4126, ADS4129
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4149 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR vs INPUT FREQUENCY (CMOS)
SNR vs INPUT FREQUENCY (CMOS)
74
90
73
86
SNR (dBFS)
SFDR (dBc)
72
82
78
71
70
69
74
68
67
70
0
50
100
150
200
250
350
300
0
150
250
Figure 86.
170MHz
150MHz
150MHz
72
170MHz
71
SINAD (dBFS)
82
220MHz
78
350
300
SINAD ACROSS GAIN AND INPUT FREQUENCY
73
86
300MHz
74
70
220MHz
69
68
300MHz
67
66
400MHz
400MHz
65
70
64
500MHz
66
500MHz
63
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Gain (dB)
Gain (dB)
Figure 87.
Figure 88.
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone)
90
75
90
80
74
80
70
73
60
72
SNR (dBFS)
50
71
SFDR (dBc)
30
68
20
-60
-20
Input Amplitude (dBFS)
-10
0
71
SFDR (dBc)
40
-30
72
50
69
-40
73
60
70
-50
74
SNR (dBFS)
30
20
-60
70
69
Input Frequency = 170.1MHz
68
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Figure 89.
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75
SFDR (dBFS)
70
40
Input Frequency = 40.1MHz
76
SNR (dBFS)
100
SNR (dBFS)
76
SFDR (dBFS)
SFDR (dBc, dBFS)
100
48
200
Figure 85.
SFDR ACROSS GAIN AND INPUT FREQUENCY
SFDR (dBc)
100
Input Frequency (MHz)
90
SFDR (dBc, dBFS)
50
Input Frequency (MHz)
Figure 90.
Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149
ADS4126, ADS4129
ADS4146, ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4149 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
92
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
75.0
88
74.5
87
74.0
86
Input Frequency = 40MHz
AVDD = 1.8V
90
86
73.5
84
73.0
82
72.5
SNR
80
SNR (dBFS)
SFDR (dBc)
SFDR
SFDR (dBc)
AVDD = 1.9V
88
85
AVDD = 1.75V
84
AVDD = 1.85V
83
72.0
82
71.5
81
71.0
1.10
80
AVDD = 1.7V
78
76
0.80
0.90
0.85
0.95
1.00
1.05
fIN = 40MHz
-40
35
10
-15
Input Common-Mode Voltage (V)
85
60
Temperature (°C)
Figure 91.
Figure 92.
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
74.0
73.5
89
75.0
88
74.5
SFDR (dBc)
73.0
AVDD = 1.8V, 1.9V
72.5
AVDD = 1.75V
72.0
AVDD = 1.7V
SFDR
73.5
86
SNR
73.0
85
72.5
84
71.5
71.0
74.0
87
fIN = 40MHz
fIN = 40MHz
-40
-15
35
10
60
72.0
83
1.70
85
1.75
1.80
Figure 93.
Figure 94.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
(CMOS)
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
90
75.0
89
74
88
74.5
88
73.0
85
SNR
72.5
84
SFDR (dBc)
73.5
86
72
84
71
82
70
SNR (dBFS)
80
69
78
68
76
67
74
66
72
1.80
1.85
DRVDD Supply (V)
72.0
1.90
70
0.15
Input Frequency = 170MHz
0.37
0.75
1.00
1.25
1.60
1.90
2.20
2.40
65
64
2.60
Differential Clock Amplitude (VPP)
Figure 95.
Copyright © 2009–2011, Texas Instruments Incorporated
73
SFDR (dBc)
86
SNR (dBFS)
74.0
87
SNR (dBFS)
SFDR (dBc)
SFDR
1.75
1.90
1.85
DRVDD Supply (V)
Temperature (°C)
83
1.70
SNR (dBFS)
SNR (dBFS)
AVDD = 1.85V
Figure 96.
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49
ADS4126, ADS4129
ADS4146, ADS4149
SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4149 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
88
74.0
87
73.5
86
73.0
INTEGRAL NONLINEARITY
1.5
1.0
72.0
84
THD
83
71.5
0.5
INL (LSB)
72.5
SNR (dBFS)
THD (dBc)
SNR
85
0
-0.5
71.0
82
-1.0
70.5
81
Input Frequency = 10MHz
-1.5
70.0
80
60
65
70
75
0
2k
4k
Input Clock Duty Cycle (%)
6k
Figure 97.
DIFFERENTIAL NONLINEARITY
40
0.3
36
20
16
-0.5
0
10k
12k
14k
16k
6.0
3.8
0.2 1.4
0.7
8239
4
8237
8
-0.4
8229
-0.3
Output Code (LSB)
12.6
12
8230
-0.2
24
8227
-0.1
39.7
28
8228
0
8k
16k
32
8225
0.1
6k
14k
35.7
8226
DNL (LSB)
0.2
RMS = 0.999LSB
8224
Code Occurrence (%)
0.4
4k
12k
OUTPUT HISTOGRAM WITH INPUTS SHORTED
44
2k
10k
Figure 98.
0.5
0
8k
Output Code (LSB)
8238
55
8235
50
8236
45
8233
40
8234
35
8231
30
8232
25
Output Code (LSB)
Figure 99.
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Figure 100.
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TYPICAL CHARACTERISTICS: COMMON
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
CMRR ACROSS FREQUENCY
-20
Input Frequency = 70MHz
50mVPP Signal Superimposed
on Input Common-Mode Voltage
(0.95V)
-25
fIN = 70MHz
fCM = 10MHz, 100mVPP
SFDR = 81dBc
Amplitude (fIN) = -1dBFS
Amplitude (fCM) = -74dBFS
Amplitude (fIN + fCM) = -87dBFS
Amplitude (fIN - fCM) = -86dBFS
-20
Amplitude (dB)
-30
CMRR (dB)
CMRR SPECTRUM
0
-35
-40
-45
-40
-60
-80
fIN + fCM = 80MHz
fCM = 10MHz
-120
-55
-140
-60
50
0
100
150
200
250
300
0
25
75
50
Frequency of Input Common-Mode Signal (MHz)
125
100
Frequency (MHz)
Figure 101.
Figure 102.
PSRR ACROSS FREQUENCY
ZOOMED VIEW OF SPECTRUM WITH PSRR SIGNAL
0
-20
Input Frequency = 10MHz
50mVPP Signal Applied on AVDD
-25
-35
-40
PSRR (dB) on AVDD Supply
fIN = 10MHz
fPSRR = 1MHz
Amplitude (fIN) = -1dBFS
Amplitude (fPSRR) = -81dBFS
Amplitude (fIN + fPSRR) = -67.7dBFS
Amplitude (fIN - fPSRR) = -68.8dBFS
fIN
-20
Amplitude (dB)
-30
PSRR (dB)
fIN - fCM = 60MHz
-100
-50
-40
fIN - fPSRR
-60
fIN + fPSRR
-80
-45
-100
-50
-120
fPSRR
-140
-55
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
Frequency of Signal on AVDD (MHz)
20
25
30
35
40
45
50
Frequency (MHz)
Figure 103.
Figure 104.
POWER ACROSS SAMPLING FREQUENCY
DRVDD CURRENT ACROSS SAMPLING FREQUENCY
70
200
180
AVDD Power (mW)
140
120
100
80
DRVDD Power
200mV LVDS
60
40
DRVDD Power
350mV LVDS
20
60
DRVDD Current (mA)
160
Power (mW)
fIN = 70MHz
LVDS, 350mV Swing
50
LVDS, 200mV Swing
40
30
20
CMOS, 8pF Load Capacitor
10
CMOS, 6pF Load Capacitor
0
0
0
25
50
75
100 125 150 175 200 225 250
0
25
50
75
100 125 150 175 200 225 250
Sampling Frequency (MSPS)
Sampling Frequency (MSPS)
Figure 105.
Figure 106.
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TYPICAL CHARACTERISTICS: CONTOUR
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (1dB Gain)
Applies to ADS412x and ADS414x
250
240
88
86
fS - Sampling Frequency - MSPS
220
78
82
84
84
200
180
84
82
82
84
70
74
86
84
84
86
66
78
88
160
82
140
82
86
88
74
70
78
84
120
100
74
88
88
80
74
50
100
70
78
86
10
70
82
88
65
66
84
150
62
66
200
250
300
350
400
450
500
fIN - Input Frequency - MHz
60
65
70
75
80
85
90
SFDR - dBFS
Figure 107.
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain)
Applies to ADS412x and ADS414x
250
240
86
84
72
82
86
fS - Sampling Frequency - MSPS
220
76
80
84
84
68
200
82
84
72
82
82
180
80
84
86
88
160
140
86
86
120
76
84
82
86
76
80
72
88
88
100
72
84
88
80
76
86
82
84
65
10
50
100
150
64
80
72
200
250
300
350
400
450
500
fIN - Input Frequency - MHz
60
65
70
75
80
85
90
SFDR - dBFS
Figure 108.
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES
(1dB Gain)
250
240
69.5
68.5
67
69
fS - Sampling Frequency - MSPS
220
200
68
180
68.5
69.5
70
160
66
69
67
140
68
120
68.5
100
66
69.5
70
67
69
80
68.5
68
10
50
100
66
67
65
150
200
250
300
350
65
400
64
450
500
fIN - Input Frequency - MHz
62
63
64
65
66
67
68
69
70
71
SNR - dBFS
Figure 109.
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES
(6dB Gain)
250
240
66
65
65.5
64.5
fS - Sampling Frequency - MSPS
220
200
180
66
66.5
65.5
65
160
64.5
66
140
66.5
67
120
65.5
100
65
66
65.5
80
67
65
65
10
50
100
64
63.5
64.5
66
150
200
250
63
300
350
400
450
500
fIN - Input Frequency - MHz
62
63
64
65
66
67
68
SNR - dBFS
Figure 110.
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES
(1dB Gain)
250
240
68
71
69
70
71.5
fS - Sampling Frequency - MSPS
220
70.5
200
67
180
71
160
72
68
70
71.5
69
140
70.5
67
120
70
66
68
100
71
72
80
69
71.5
70
72.5
70.5
10
50
100
67
150
200
250
300
65
66
68
65
64
350
400
450
500
70
71
72
73
fIN - Input Frequency - MHz
63
64
65
66
67
68
69
SNR - dBFS
Figure 111.
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SBAS483G – NOVEMBER 2009 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES
(6dB Gain)
250
240
66
67
65
66.5
65.5
fS - Sampling Frequency - MSPS
220
200
66.5
180
67
65
66
67.5
160
65.5
67
140
66.5
120
65
66.5
100
66
67.5
65.5
67
80
66
10
50
100
150
200
64.5
65
65.5
65
250
300
350
64
400
63.5
450
500
fIN - Input Frequency - MHz
62
63
64
65
66
67
68
SNR - dBFS
Figure 112.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS412x/4x is a family of high-performance and low-power 12-bit and 14-bit ADCs with maximum sampling
rates up to 250MSPS. The conversion process is initiated by a rising edge of the external input clock and the
analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates
through the pipeline, resulting in a data latency of 10 clock cycles. The output is available as 14-bit data or 12-bit
data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement
format.
ANALOG INPUT
The analog input consists of a switched-capacitor-based, differential, sample-and-hold architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 0.95V, available on the
VCM pin. For a full-scale differential input, each input INP and INM pin must swing symmetrically between (VCM
+ 0.5V) and (VCM – 0.5V), resulting in a 2VPP differential input swing. The input sampling circuit has a high 3dB
bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage). Figure 113 shows
an equivalent circuit for the analog input.
Sampling
Switch
LPKG
2nH
INP
10W
CBOND
1pF
RESR
200W
100W
INM
CPAR2
1pF
RESR
200W
CSAMP
2pF
CPAR1
0.5pF
RON
15W
100W
CBOND
1pF
RON
15W
3pF
3pF
LPKG
2nH
Sampling
Capacitor
RCR Filter
RON
15W
CPAR2
1pF
CSAMP
2pF
Sampling
Capacitor
Sampling
Switch
Figure 113. Analog Input Equivalent Circuit
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the
common-mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input
pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low
impedance (less than 50Ω) for the common-mode switching currents. This impedance can be achieved by using
two resistors from each input terminated to the common-mode voltage (VCM).
Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to
absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the
R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the
input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal
R-C filter, high input frequency can be supported but now the sampling glitches must be supplied by the external
driving circuit. The inductance of the package bond wires limits the ability of the external driving circuit to support
the sampling glitches.
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In the ADS412x/4x, the R-C component values have been optimized while supporting high input bandwidth
(550MHz). However, in applications where very high input frequency support is not required, filtering of the
glitches can be improved further with an external R-C-R filter; see Figure 116 and Figure 117).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. While designing the drive circuit, the ADC impedance must be
considered. Figure 114 and Figure 115 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.
Differential Input Resistance (kW)
100.00
10.00
1.00
0.10
0.01
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (GHz)
Figure 114. ADC Analog Input Resistance (RIN) Across Frequency
Differential Input Capacitance (pF)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (GHz)
Figure 115. ADC Analog Input Capacitance (CIN) Across Frequency
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Driving Circuit
Two example driving circuit configurations are shown in Figure 116 and Figure 117—one optimized for low
bandwidth and the other one for high bandwidth to support higher input frequencies. In Figure 116, an external
R-C-R filter with 3.3pF is used to help absorb sampling glitches. The R-C-R filter limits the bandwidth of the drive
circuit, making it suitable for low input frequencies (up to 250MHz). Transformers such as ADT1-1WT or WBC1-1
can be used up to 250MHz.
For higher input frequencies, the R-C-R filter can be dropped. Together with the lower series resistors (5Ω to
10Ω), this drive circuit provides higher bandwidth to support frequencies up to 500MHz (as shown in Figure 117).
A transmission line transformer such as ADTL2-18 can be used.
Note that both the drive circuits have been terminated by 50Ω near the ADC side. The termination is
accomplished by a 25Ω resistor from each input to the 0.95V common-mode (VCM) from the device. This
termination allows the analog inputs to be biased around the required common-mode voltage.
10W to 15W
T2
3.6nH
INP
T1
0.1mF
0.1mF
25W
50W
RIN
3.3pF
25W
CIN
50W
INM
1:1
1:1
10W to 15W
3.6nH
VCM
ADS41xx
Figure 116. Drive Circuit with Low Bandwidth (for Low Input Frequencies)
5W to 10W
T2
T1
INP
0.1mF
0.1mF
25W
RIN
CIN
25W
INM
1:1
1:1
5W to 10W
VCM
ADS41xx
Figure 117. Drive Circuit with High Bandwidth (for High Input Frequencies)
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The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 116 and Figure 117. The center point of this
termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The
values of the terminations between the transformers and on the secondary side must be chosen to obtain an
effective 50Ω (for a 50Ω source impedance).
Figure 116 and Figure 117 use 1:1 transformers with a 50Ω source. As explained in the Drive Circuit
Requirements section, this architecture helps to present a low source impedance to absorb sampling glitches.
With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to absorb the
sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers).
In almost all cases, either a bandpass or low-pass filter is needed to get the desired dynamic performance, as
shown in Figure 118. Such a filter presents low source impedance at the high frequencies corresponding to the
sampling glitch and helps avoid the performance loss with the high source impedance.
10W
Bandpass or
Low-Pass
Filter
Differential
Input Signal
0.1mF
INP
100W
ADS41xx
100W
INM
10W
VCM
Figure 118. Drive Circuit with 1:4 Transformer
Input Common-Mode
To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each ADC input pin sinks a
common-mode current of approximately 0.6µA per MSPS of clock frequency.
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CLOCK INPUT
The ADS412x/4x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources. Figure 119 shows an equivalent circuit for the input
clock.
Clock Buffer
LPKG
1nH
20W
CLKP
CBOND
1pF
RESR
100W
LPKG
1nH
5kW
2pF
20W
CEQ
CEQ
VCM
5kW
CLKM
CBOND
1pF
RESR
100W
NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 119. Input Clock Equivalent Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1mF
capacitor, as shown in Figure 120. For best performance, the clock inputs must be driven differentially, reducing
susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock
source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no
change in performance with a non-50% duty cycle clock input. Figure 121 shows a differential circuit.
CMOS
Clock Input
0.1mF
0.1mF
CLKP
CLKP
VCM
0.1mF
Differential Sine-Wave,
PECL, or LVDS
Clock Input
0.1mF
CLKM
CLKM
Figure 120. Single-Ended Clock Driving Circuit
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Figure 121. Differential Clock Driving Circuit
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DIGITAL FUNCTIONS AND LOW LATENCY MODE
The device has several useful digital functions such as test patterns, gain, and offset correction. All of these
functions require extra clock cycles for operation and increase the overall latency and power of the device.
Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with
a latency of 10 clock cycles. In this mode, the digital functions are bypassed. Figure 122 shows more details of
the processing after the ADC.
The device is in low-latency mode after reset. In order to use any of the digital functions, first the low-latency
mode must be disabled by setting the DIS LOW LATENCY register bit to '1'. After this, the respective register bits
must be programmed as described in the following sections and in the Serial Register Map section.
Output
Interface
14-Bit
ADC
14b
14b
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
DIS LOW LATENCY Pin
Figure 122. Digital Processing Block Diagram
GAIN FOR SFDR/SNR TRADE-OFF
The ADS412x/4x include gain settings that can be used to get improved SFDR performance. The gain is
programmable from 0dB to 6dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog
input full-scale range scales proportionally, as shown in Table 11.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR.
After a reset, the device is in low-latency mode and gain function is disabled. To use gain:
• First, disable the low-latency mode (DIS LOW LATENCY = 1).
• This setting enables the gain and puts the device in a 0dB gain mode.
• For other gain settings, program the GAIN bits.
Table 11. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
Default after reset
2
1
Programmable gain
1.78
2
Programmable gain
1.59
3
Programmable gain
1.42
4
Programmable gain
1.26
5
Programmable gain
1.12
6
Programmable gain
1.00
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OFFSET CORRECTION
The ADS412x/4x has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV.
The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 12.
Table 12. Time Constant of Offset Correction Loop
(1)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
TIME CONSTANT, TCCLK × 1/fS (sec) (1)
0000
1M
4ms
0001
2M
8ms
0010
4M
16.7ms
0011
8M
33.5ms
0100
16M
67ms
0101
32M
134ms
0110
64M
268ms
0111
128M
537ms
1000
256M
1.1s
1001
512M
2.15s
1010
1G
4.3s
1011
2G
8.6s
1100
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
Sampling frequency, fS = 250MSPS.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by a default after reset.
After a reset, the device is in low-latency mode and offset correction is disabled. To use offset correction:
• First, disable the low-latency mode (DIS LOW LATENCY = 1).
• Then set EN OFFSET CORR to '1' and program the required time constant.
Figure 123 shows the time response of the offset correction algorithm after it is enabled.
Output Code (LSB)
OFFSET CORRECTION
Time Response
8200
8190
8180
8170
8160
8150
8140
8130
8120
8110
8100
8090
8080
8070
8060
8050
8181
Offset of
10 LSBs
8192
Final converged value
Offset correction
converges to output
code of 8192
Offset correction
begins
-5
5
15
25
35
45
55
65
75
85
95
105
Time (ms)
Figure 123. Time Response of Offset Correction
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POWER DOWN
The ADS412x/4x has three power-down modes: power-down global, standby, and output buffer disable.
Power-Down Global
In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down,
resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state.
The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To
enter the global power-down mode, set the PDN GLOBAL register bit.
Standby
In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up
time of 5µs. The total power dissipation in standby mode is approximately 185mW. To enter the standby mode,
set the STBY register bit.
Output Buffer Disable
The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast,
approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin.
Input Clock Stop
In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The
power dissipation is approximately 80mW.
POWER-SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device. Externally, they can be driven from separate supplies or from a single supply.
DIGITAL OUTPUT INFORMATION
The ADS412x/4x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the
data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit or using the DFS pin.
DDR LVDS Outputs
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 124 and Figure 125.
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Pins
Pins
CLKOUTP
Output Clock
CLKOUTP
CLKOUTM
Output Clock
CLKOUTM
D0_D1_P
Data Bits D0, D1
D0_D1_P
Data Bits D0, D1
D0_D1_M
LVDS Buffers
LVDS Buffers
D0_D1_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D4_D5_P
12-Bit
ADC Data
Data Bits D4, D5
D4_D5_M
D4_D5_P
Data Bits D4, D5
14-Bit
ADC Data
D4_D5_M
D6_D7_P
Data Bits D6, D7
D6_D7_P
Data Bits D6, D7
D6_D7_M
D6_D7_M
D8_D9_P
Data Bits D8, D9
D8_D9_P
Data Bits D8, D9
D8_D9_M
D8_D9_M
D10_D11_P
D10_D11_P
Data Bits D10, D11
Data Bits D10, D11
D10_D11_M
D10_D11_M
ADS4129
D12_D13_P
Data Bits D12, D13
Figure 124. ADS412x LVDS Data Outputs
D12_D13_M
ADS4149
Figure 125. ADS414x LVDS Data Outputs
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Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5,
etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to
capture all 14 data bits, as shown in Figure 126.
CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
D12_D13_P,
D12_D13_M
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 126. DDR LVDS Interface
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LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 127. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
VDIFF
High
Low
OUTP
External
100W Load
OUTM
1.1V
ROUT
VDIFF
Low
High
NOTE: Use the default buffer strength to match 100Ω external termination (ROUT = 100Ω). To match with a 50Ω external termination, set the
LVDS STRENGTH bit (ROUT = 50Ω).
Figure 127. LVDS Buffer Equivalent Circuit
Parallel CMOS Interface
In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The
rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 128 depicts the CMOS
output interface.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this
degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength
ensures a wide data stable window (even at 250MSPS) is provided so the data outputs have minimal load
capacitance. It is recommended to use short traces (one to two inches or 2,54cm to 5,08cm) terminated with less
than 5pF load capacitance, as shown in Figure 129.
For sampling frequencies greater than 200MSPS, it is recommended to use an external clock to capture data.
The delay from input clock to output data and the data valid times are specified for higher sampling frequencies.
These timings can be used to delay the input clock appropriately and use it to capture data.
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Pins
OVR
CLKOUT
CMOS Output Buffers
D0
D1
D2
D3
¼
¼
14-Bit
ADC Data
D11
D12
D13
ADS4149
Figure 128. CMOS Output Interface
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Use External Clock Buffer
(> 200MSPS)
Input Clock
Receiver (FPGA, ASIC, etc.)
Flip-Flops
CLKOUT
CMOS Output Buffers
D0
D1
D2
CLKIN
D0_In
D1_In
D2_In
14-Bit ADC Data
D12
D13
D12_In
D13_In
ADS4149
Use short traces between
ADC output and receiver pins (1 to 2 inches).
Figure 129. Using the CMOS Data Outputs
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG)
where:
CL = load capacitance,
N × FAVG = average number of output bits switching.
(1)
Figure 106 shows the current across sampling frequencies at 2 MHz analog input frequency.
Input Over-Voltage Indication (OVR Pin)
The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the
sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR
remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off
DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS).
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For a positive overload, the D[13:0] output data bits are 3FFFh in offset binary output format and 1FFFh in twos
complement output format. For a negative input overload, the output code is 0000h in offset binary output format
and 2000h in twos complement output format.
Output Data Format
Two output data formats are supported: twos complement and offset binary. They can be selected using the
DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event
of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout
and grounding.
Supply Decoupling
Because the ADS412x/4x already include internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum
number of capacitors depends on the actual application. The decoupling capacitors should be placed very close
to the converter supply pins.
Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as
EGREF and EGCHAN.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(2)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
SINAD = 10Log10
PS
PN + PD
(3)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
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Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
ENOB =
SINAD - 1.76
6.02
(4)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
THD = 10Log10
PS
PN
(5)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(6)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(7)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2010) to Revision G
Page
•
Updated document to current standards .............................................................................................................................. 1
•
Added 125MSPS and 65MSPS columns to ADS412x/ADS414x Family Comparison table ................................................ 1
•
Changed Clock Input, Low-speed mode enabled minimum specification for both ADS4129/49 and ADS4126/46
rows in Electrical Characteristics table ................................................................................................................................. 4
•
Changed DF register address and register data in Table 10 ............................................................................................. 26
•
Changed DFh register in Description of Serial Registers section ...................................................................................... 34
•
Changed titles of Figure 21 and Figure 22 ......................................................................................................................... 36
•
Changed titles of Figure 42 and Figure 43 ......................................................................................................................... 40
•
Changed titles of Figure 63 and Figure 64 ......................................................................................................................... 44
•
Changed titles of Figure 85 and Figure 86 ......................................................................................................................... 48
•
Updated Figure 105 and Figure 106 ................................................................................................................................... 51
•
Updated Table 11 ............................................................................................................................................................... 63
Changes from Revision E (September 2010) to Revision F
Page
•
Changed status of ADS4129 throughout document ............................................................................................................. 1
•
Changed ADS4129 SNR, SINAD, SFDR, THD, and HD3 fIN = 170MHz typical specifications in Electrical
Characteristics table ............................................................................................................................................................. 5
•
Added ADS4129 SNR, SINAD, SFDR, THD, HD2, HD3, and Worst spur fIN = 170MHz minimum specifications in
Electrical Characteristics table .............................................................................................................................................. 5
•
Added ADS4129 DNL minimum and maximum specifications in Electrical Characteristics table ........................................ 5
•
Added ADS4129 INL maximum specification in Electrical Characteristics table .................................................................. 5
•
Changed ADS4129 INL typical specification in Electrical Characteristics table ................................................................... 5
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PACKAGE OPTION ADDENDUM
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21-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
TBD
Call TI
Call TI
-40 to 85
AZ4126
(4/5)
ADS4126IRGZ25
ACTIVE
VQFN
RGZ
48
ADS4126IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4126
ADS4126IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4126
ADS4129IRGZ25
ACTIVE
VQFN
RGZ
48
TBD
Call TI
Call TI
-40 to 85
AZ4129
ADS4129IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4129
ADS4129IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4129
ADS4146IRGZ25
ACTIVE
VQFN
RGZ
48
TBD
Call TI
Call TI
-40 to 85
AZ4146
ADS4146IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4146
ADS4146IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4146
ADS4149IRGZ25
ACTIVE
VQFN
RGZ
48
TBD
Call TI
Call TI
-40 to 85
AZ4149
ADS4149IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4149
ADS4149IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4149
ADS58B18IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ58B18
ADS58B18IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ58B18
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS4126IRGZR
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS4126IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS4129IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS4129IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS4146IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS4146IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS4149IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS4149IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS58B18IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS58B18IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS4126IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
ADS4126IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADS4129IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
ADS4129IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADS4146IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
ADS4146IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADS4149IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
ADS4149IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADS58B18IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
ADS58B18IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
Pack Materials-Page 2
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