ADS41B25IRGZR

ADS41B25 SBAS548 – JUNE 2011 www.ti.com 12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer Check for Samples: ADS41B25 FEATURES DESCRIPTION • • The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. 1 23 • • • • • • • • Resolution: 12-Bit, 125MSPS Integrated High-Impedance Analog Input Buffer: – Input Capacitance at dc: 3.5pF – Input Resistance at dc: 10kΩ Maximum Sample Rate: 125MSPS Ultralow Power: – 1.8V Analog Power: 114mW – 3.3V Buffer Power: 96mW – I/O Power: 100mW (DDR LVDS) High Dynamic Performance: – SNR: 68.3dBFS at 170MHz – SFDR: 87dBc at 170MHz Output Interface: – Double Data Rate (DDR) LVDS with Programmable Swing and Strength: – Standard Swing: 350mV – Low Swing: 200mV – Default Strength: 100Ω Termination – 2x Strength: 50Ω Termination – 1.8V Parallel CMOS Interface Also Supported Programmable Gain for SNR/SFDR Trade-Off DC Offset Correction Supports Low Input Clock Amplitude Package: QFN-48 (7mm × 7mm) The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C). 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated ADS41B25 SBAS548 – JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ADS41B25 QFN-48 RGZ –40°C to +85°C (1) (2) ECO PLAN (2) LEAD/BALL FINISH PACKAGE MARKING GREEN (RoHS, no Sb/Br) Cu/NiPdAu AZ41B25 ORDERING NUMBER TRANSPORT MEDIA ADS41B25IRGZR Tape and reel ADS41B25IRGZT Tape and reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. ABSOLUTE MAXIMUM RATINGS (1) ADS41B25 MIN MAX Supply voltage range, AVDD –0.3 2.1 V Supply voltage range, AVDD_BUF –0.3 3.9 V Supply voltage range, DRVDD –0.3 2.1 V Voltage between AGND and DRGND –0.3 0.3 V Voltage between AVDD to DRVDD (when AVDD leads DRVDD) –2.4 2.4 V Voltage between DRVDD to AVDD (when DRVDD leads AVDD) –2.4 2.4 V Voltage between AVDD_BUF to DRVDD/AVDD –4.2 4.2 V –0.3 Minimum (1.9, AVDD + 0.3) V –0.3 AVDD + 0.3 V INP, INM Voltage applied to input pins (2) CLKP, CLKM , RESET, SCLK, SDATA, SEN, DFS –40 Operating free-air temperature range, TA Operating junction temperature range, TJ –65 Storage temperature range, Tstg +85 °C +125 °C +150 °C 2 kV ESD, human body model (HBM) (1) (2) UNIT Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|. Doing so prevents the ESD protection diodes at the clock input pins from turning on. THERMAL INFORMATION ADS41B25 THERMAL METRIC (1) RGZ UNITS 48 PINS θJA Junction-to-ambient thermal resistance 27.9 θJCtop Junction-to-case (top) thermal resistance 15.1 θJB Junction-to-board thermal resistance 5.4 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 5.4 θJCbot Junction-to-case (bottom) thermal resistance 1.7 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS ADS41B25 MIN TYP MAX UNIT 1.7 1.8 1.9 V 3 3.3 3.6 V 1.7 1.8 1.9 V SUPPLIES AVDD Analog supply voltage AVDD_BUF Analog buffer supply voltage DRVDD Digital supply voltage ANALOG INPUTS Differential input voltage range (1) 1.5 VPP 1.7 ± 0.05 Input common-mode voltage V Maximum analog input frequency with 1.5VPP input amplitude (2) 400 MHz Maximum analog input frequency with 1VPP input amplitude (2) 600 MHz CLOCK INPUT Low-speed mode enabled (3) 20 80 MSPS Low-speed mode disabled (3) 80 125 MSPS Input clock amplitude differential (VCLKP – VCLKM) Sine wave, ac-coupled 1.5 VPP LVPECL, ac-coupled 0.2 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 1.8 Input clock duty Low-speed mode enabled cycle Low-speed mode disabled V 40 50 60 % 35 50 65 % DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) TA Operating free-air temperature (1) (2) (3) –40 5 pF 100 Ω +85 °C With 0dB gain. See the Gain for SFDR/SNR Trade-Off section in Application Information for the relationship between input voltage range and gain. See the Theory of Operation section in the Application Information. See the Serial Interface section for details on the low-speed mode. HIGH-PERFORMANCE MODES (1) (2) (3) PARAMETER DESCRIPTION MODE 1 Set the MODE 1 register bits to get the best performance across sample clock and input signal frequencies. Register address = 03h, register data = 03h. MODE 2 Set the MODE 2 register bit to get the best performance at high input signal frequencies greater than 230MHz. Register address = 4Ah, register data = 01h. (1) (2) (3) It is recommended to use these modes to get best performance. These modes can only be set with the serial interface. See the Serial Interface section for details on register programming. Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device Configuration section. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 3 ADS41B25 SBAS548 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS41B25 Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 1.5VPP clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V. ADS41B25 PARAMETER TEST CONDITIONS MIN TYP Resolution 12 fIN = 20MHz fIN = 70MHz SNR (signal-to-noise ratio), LVDS SINAD (signal-to-noise and distortion ratio), LVDS SFDR THD dBFS dBFS fIN = 170MHz 68.3 dBFS fIN = 300MHz 67 dBFS fIN = 20MHz 68.8 dBFS 68.6 dBFS fIN = 100MHz 68.5 dBFS fIN = 170MHz 68.2 dBFS fIN = 300MHz 65.4 dBFS fIN = 20MHz 89 dBc 88 dBc fIN = 100MHz 89 dBc fIN = 170MHz 87 dBc fIN = 300MHz 71 dBc fIN = 20MHz 86 dBc 86 dBc fIN = 100MHz 85 dBc fIN = 170MHz 83 dBc fIN = 300MHz 69 dBc fIN = 20MHz 89 dBc 88 dBc fIN = 100MHz 89 dBc fIN = 170MHz 90 dBc fIN = 300MHz 78 dBc fIN = 20MHz 100 dBc 93 dBc fIN = 100MHz 91 dBc fIN = 170MHz 87 dBc fIN = 300MHz 71 dBc fIN = 20MHz 93 dBc 94 dBc fIN = 100MHz 94 dBc fIN = 170MHz 95 dBc fIN = 300MHz 91 dBc f1 = 185MHz, f2 = 190MHz, each tone at –7dBFS –86 dBFS fIN = 70MHz Second-harmonic distortion HD2 fIN = 70MHz Third-harmonic distortion HD3 fIN = 70MHz Worst spur (other than second and third harmonics) Two-tone intermodulation distortion IMD Input overload recovery dBFS 68.6 fIN = 70MHz Total harmonic distortion 65.5 78 77 78 78 82.5 Recovery to within 1% (of final value) for 6dB overload with sine-wave input 1 Clock cycle 30 dB AC power-supply rejection ratio PSRR For 100mVPP signal on AVDD supply, up to 10MHz Effective number of bits ENOB fIN = 70MHz 11.1 INL fIN = 70MHz ±1.5 Integrated nonlinearity 4 Bits 68.8 68.7 fIN = 70MHz 66.5 UNIT fIN = 100MHz fIN = 70MHz Spurious-free dynamic range MAX Submit Documentation Feedback LSBs ±3.5 LSBs Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V. ADS41B25 PARAMETER MIN TYP MAX UNIT ANALOG INPUTS Differential input voltage range 1.5 VPP Differential input resistance, at dc (see Figure 42) 10 kΩ Differential input capacitance, at dc (see Figure 43) 3.5 pF Analog input bandwidth 800 MHz 0.04 µA Analog input common-mode current (per input pin) Common-mode output voltage VCM 1.7 VCM output current capability V 4 mA DC ACCURACY –15 Offset error Temperature coefficient of offset error Gain error as a result of internal reference inaccuracy alone Gain error of channel alone 2.5 15 0.003 EGREF –2 EGCHAN mV mV/°C 2 2.5 %FS %FS POWER SUPPLY IAVDD Analog supply current 64 73 mA IAVDD_BUF Analog input buffer supply current 29 42 mA IDRVDD (1) Output buffer supply current LVDS interface with 100Ω external termination Low LVDS swing (200mV) 42 IDRVDD Output buffer supply current LVDS interface with 100Ω external termination Standard LVDS swing (350mV) 55 IDRVDD output buffer supply current (1) (2) CMOS interface (2) fIN = 2.5MHz 32 Global power-down 10 Standby (1) (2) 145 mA 65 mA mA 25 mW mW The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10pF. In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information). Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 5 ADS41B25 SBAS548 – JUNE 2011 www.ti.com DIGITAL CHARACTERISTICS Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V. ADS41B25 PARAMETER TEST CONDITIONS MIN RESET, SCLK, SDATA, and SEN support 1.8V and 3.3V CMOS logic levels 1.3 OE only supports 1.8V CMOS logic levels 1.3 TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE) High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage V 0.4 V V 0.4 V High-level input current: SDATA, SCLK (1) VHIGH = 1.8V 10 µA High-level input current: SEN (2) VHIGH = 1.8V 0 µA Low-level input current: SDATA, SCLK VLOW = 0V 0 µA Low-level input current: SEN VLOW = 0V –10 µA DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT) DRVDD – 0.1 High-level output voltage Low-level output voltage DRVDD 0 V 0.1 V DIGITAL OUTPUTS (LVDS INTERFACE: D0_D1_P/M to D12_D13_P/M, CLKOUTP/M) High-level output voltage (3) VODH Standard swing LVDS 270 +350 430 mV Low-level output voltage (3) VODL Standard swing LVDS –430 –350 –270 mV High-level output voltage (3) VODH Low swing LVDS +200 Low-level output voltage (3) VODL Low swing LVDS –200 Output common-mode voltage VOCM (1) (2) (3) 6 0.85 1.05 mV mV 1.25 V SDATA and SCLK have an internal 180kΩ pull-down resistor. SEN has an internal 180kΩ pull-up resistor to AVDD. With an external 100Ω termination. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com PIN CONFIGURATION (CMOS MODE) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RGZ PACKAGE QFN-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC UNUSED 4 33 NC CLKOUT 5 32 NC DFS 6 31 NC PowerPAD SEN 26 AVDD AGND 12 25 AGND 14 15 16 17 INP 13 18 19 20 21 22 23 24 AVDD 27 CLKM 11 RESERVED CLKP 10 AVDD SDATA AVDD SCLK 28 AVDD_BUF 29 9 AVDD 8 AGND AVDD AGND AGND RESET INM 30 AGND 7 VCM OE NOTE: The PowerPAD™ is connected to DRGND. Figure 1. CMOS Pinout Pin Descriptions (CMOS Mode) PIN NAME PIN NUMBER # OF PINS AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply AVDD_BUF 21 1 I 3.3V input buffer supply AGND 9, 12, 14, 17, 19, 25 6 I Analog ground CLKP 10 1 I Differential clock input, positive CLKM 11 1 I Differential clock input, negative INP 15 1 I Differential analog input, positive INM 16 1 I Differential analog input, negative VCM 13 1 O Outputs the common-mode voltage that can be used externally to bias the analog input pins. FUNCTION DESCRIPTION RESET 30 1 I Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as a control pin. RESET has an internal 180kΩ pull-down resistor. SCLK 29 1 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground. This pin has an internal 180kΩ pull-down resistor SDATA 28 1 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 5). This pin has an internal 180kΩ pull-down resistor. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 7 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Pin Descriptions (CMOS Mode) (continued) PIN NAME PIN NUMBER # OF PINS FUNCTION DESCRIPTION SEN 27 1 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD. This pin has an internal 180kΩ pull-up resistor to AVDD. DFS 6 1 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS/CMOS output interface type. See Table 3 for detailed information. CLKOUT 5 1 O CMOS output clock OE 7 1 I Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to AVDD. RESERVED 23 1 I Digital control pin, reserved for future use D0 to D11 Refer to Figure 1 12 O 12-bit CMOS output data OVR_SDOUT 3 1 O This pin functions as an out-of-range indicator after reset, when register bit SERIAL READOUT = 0, and functions as a serial register readout pin when SERIAL READOUT = 1. This pin is a CMOS output level pin (powered from DRVDD). 8 DRVDD 2, 35 2 I 1.8V digital and output buffer supply DRGND 1, 36, PAD 2 I Digital and output buffer ground UNUSED 4 1 — Not used NC Refer to Figure 1 4 — Do not connect Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com PIN CONFIGURATION (LVDS MODE) D10_D11_P D10_D11_M D8_D9_P D8_D9_M D6_D7_P D6_D7_M D4_D5_P D4_D5_M D2_D3_P D2_D3_M D0_D1_P D0_D1_M RGZ PACKAGE QFN-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC CLKOUTM 4 33 NC CLKOUTP 5 32 NC DFS 6 31 NC PowerPAD SEN 26 AVDD AGND 12 25 AGND 14 15 16 17 INP 13 18 19 20 21 22 23 24 AVDD 27 CLKM 11 RESERVED CLKP 10 AVDD SDATA AVDD SCLK 28 AVDD_BUF 29 9 AVDD 8 AGND AVDD AGND AGND RESET INM 30 AGND 7 VCM OE NOTE: The PowerPAD is connected to DRGND. Figure 2. LVDS Pinout Pin Descriptions (LVDS Mode) PIN NAME PIN NUMBER # OF PINS AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply AVDD_BUF 21 1 I 3.3V input buffer supply AGND 9, 12, 14, 17, 19, 25 6 I Analog ground CLKP 10 1 I Differential clock input, positive CLKM 11 1 I Differential clock input, negative INP 15 1 I Differential analog input, positive INM 16 1 I Differential analog input, negative VCM 13 1 O Outputs the common-mode voltage that can be used externally to bias the analog input pins. FUNCTION DESCRIPTION RESET 30 1 I Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SDATA can be used as a control pin. RESET has an internal 180kΩ pull-down resistor. SCLK 29 1 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground. This pin has an internal 180kΩ pull-down resistor SDATA 28 1 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 6). This pin has an internal 180kΩ pull-down resistor. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 9 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Pin Descriptions (LVDS Mode) (continued) PIN NAME PIN NUMBER # OF PINS FUNCTION DESCRIPTION SEN 27 1 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD. This pin has an internal 180kΩ pull-up resistor to AVDD. OE 7 1 I Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to AVDD. DFS 6 1 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS/CMOS output interface type (see Table 3). RESERVED 23 1 I Digital control pin, reserved for future use CLKOUTP 5 1 O Differential output clock, true CLKOUTM 4 1 O Differential output clock, complement D0_D1_P Refer to Figure 2 1 O Differential output data D0 and D1 multiplexed, true D0_D1_M Refer to Figure 2 1 O Differential output data D0 and D1 multiplexed, complement D2_D3_P Refer to Figure 2 1 O Differential output data D2 and D3 multiplexed, true D2_D3_M Refer to Figure 2 1 O Differential output data D2 and D3 multiplexed, complement D4_D5_P Refer to Figure 2 1 O Differential output data D4 and D5 multiplexed, true D4_D5_M Refer to Figure 2 1 O Differential output data D4 and D5 multiplexed, complement D6_D7_P Refer to Figure 2 1 O Differential output data D6 and D7 multiplexed, true D6_D7_M Refer to Figure 2 1 O Differential output data D6 and D7 multiplexed, complement D8_D9_P Refer to Figure 2 1 O Differential output data D8 and D9 multiplexed, true D8_D9_M Refer to Figure 2 1 O Differential output data D8 and D9 multiplexed, complement D10_D11_P Refer to Figure 2 1 O Differential output data D10 and D11 multiplexed, true D10_D11_M Refer to Figure 2 1 O Differential output data D10 and D11 multiplexed, complement OVR_SDOUT 3 1 O This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. This pin is a 1.8V CMOS output pin (powered from DRVDD). 10 DRVDD 2, 35 2 I 1.8V digital and output buffer supply DRGND 1, 36, PAD 2 I Digital and output buffer ground NC Refer to Figure 2 4 — Do not connect Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DDR LVDS Interface DRGND CLKP CLKOUTP CLOCKGEN CLKOUTM CLKM D0_D1_P D0_D1_M D2_D3_P AVDD_BUF D2_D3_M D4_D5_P INP Common Digital Functions 12-Bit ADC Sampling Circuit DDR Serializer D4_D5_M D6_D7_P INM D6_D7_M D8_D9_P Analog Buffers D8_D9_M Control Interface Reference VCM D10_D11_P D10_D11_M OVR_SDOUT DFS SEN SDATA SCLK RESET ADS41B25 OE Figure 3. Block Diagram TIMING CHARACTERISTICS Dn_Dn + 1_P Logic 0 VODL Logic 1 VODH Dn_Dn + 1_M VOCM GND (1) With external 100Ω termination. Figure 4. LVDS Output Voltage Levels Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 11 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TIMING REQUIREMENTS: LVDS and CMOS Modes (1) Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, sampling frequency = 125MSPS, sine wave input clock, CLOAD = 5pF (2), and RLOAD = 100Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.7V to 1.9V. PARAMETER tA CONDITIONS Aperture delay Variation of aperture delay tJ MIN TYP MAX 0.6 0.8 1.2 Between two devices at the same temperature and DRVDD supply ±100 Aperture jitter Wakeup time Time to valid data after coming out of PDN GLOBAL mode ns ps 100 Time to valid data after coming out of STANDBY mode UNIT fS rms 5 25 100 500 µs µs Gain enabled (default after reset) 21 Clock cycles Gain and offset correction enabled 22 Clock cycles ADC latency (4) DDR LVDS MODE Data setup time (3) tSU tH Data hold time (3) Data valid (5) to zero-crossing of CLKOUTP 2.3 3.0 ns Zero-crossing of CLKOUTP to data becoming invalid (5) 0.35 0.6 ns 3 4.2 Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 1MSPS ≤ sampling frequency ≤ 125MSPS Variation of tPDI Between two devices at the same temperature and DRVDD supply LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP – CLKOUTM) 1MSPS ≤ sampling frequency ≤ 125MSPS tRISE, tFALL Data rise time, Data fall time Rise time measured from –100mV to +100mV Fall time measured from +100mV to –100mV 1MSPS ≤ sampling frequency ≤ 125MSPS 0.14 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from –100mV to +100mV Fall time measured from +100mV to –100mV 1MSPS ≤ sampling frequency ≤ 125MSPS 0.14 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active tPDI 5.4 ±0.6 42 48 50 ns ns 54 100 % ns PARALLEL CMOS MODE (6) tSETUP Data setup time Data valid (5) to 50% of CLKOUT rising edge 2.5 3.2 ns tHOLD Data hold time Time interval of valid data (5) 3.5 4.3 ns 4 5.5 tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 1MSPS ≤ sampling frequency ≤ 125MSPS Output clock duty cycle Duty cycle of output clock, CLKOUT 1MSPS ≤ sampling frequency ≤ 125MSPS 7 ns 47 % tRISE, tFALL Data rise time, Data fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1MSPS ≤ sampling frequency ≤ 125MSPS 0.35 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1MSPS ≤ sampling frequency ≤ 125MSPS 0.35 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active (1) (2) (3) (4) (5) (6) 12 20 40 ns Timing parameters are ensured by design and characterization but are not production tested. CLOAD is the effective external single-ended load capacitance between each output pin and ground. RLOAD is the differential load resistance between the LVDS output pair. At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. Data valid refers to a logic high of 1.26V and a logic low of 0.54V. For fS > 200MSPS, it is recommended to use an external clock for data capture instead of the device output clock signal (CLKOUT). Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Table 1. LVDS Timing Across Sampling Frequencies SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) MIN TYP 80 4.5 65 5.5 HOLD TIME (ns) MAX MIN TYP 5.2 0.35 0.6 6.5 0.35 0.6 MAX Table 2. CMOS Timing Across Sampling Frequencies TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK SAMPLING FREQUENCY (MSPS) MIN TYP 80 4.8 65 6.0 tSETUP (ns) tHOLD (ns) MAX MIN TYP 5.5 5.7 7.0 7.0 MIN TYP MAX 6.5 4 5.5 7 8.0 4 5.5 7 N+3 N+2 N+1 Sample N tPDI (ns) MAX N+4 N + 23 N + 22 N + 21 Input Signal tA CLKP Input Clock CLKM CLKOUTM CLKOUTP tPDI tH 21 Clock Cycles DDR LVDS (1) tSU (2) Output Data (DXP, DXM) E O N - 21 E O N - 21 E O E N - 19 O N - 18 O E E N - 17 O O E E O N+1 N E O E O N+2 tPDI CLKOUT tSU Parallel CMOS 21 Clock Cycles Output Data N - 21 N - 20 N - 19 (1) N - 18 tH N-1 N N+1 (1) At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency = ADC latency + 1. (2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc). Figure 5. Latency Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 13 ADS41B25 SBAS548 – JUNE 2011 www.ti.com CLKM Input Clock CLKP tPDI CLKOUTP Output Clock CLKOUTM tSU Output Dn_Dn + 1_P Data Pair Dn_Dn + 1_M tSU tH Dn (1) Dn + 1 tH (1) (1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc. Figure 6. LVDS Mode Timing CLKM Input Clock CLKP tPDI Output Clock CLKOUT tSU Output Data Dn tH Dn (1) CLKM Input Clock CLKP tSTART tDV Output Data Dn Dn (1) Dn = bits D0, D1, D2, etc. Figure 7. CMOS Mode Timing 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com DEVICE CONFIGURATION The ADS41B25 has several modes that can be configured using a serial programming interface, as described in Table 3, Table 4, and Table 5. In addition, the device has two dedicated parallel pins to quickly configure commonly-used functions. The parallel pins are DFS (analog four-level control pin) and OE (digital control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors). Table 3. DFS: Analog Control Pin VOLTAGE APPLIED ON DFS DESCRIPTION (Data Format/Output Interface) 0, +100mV/0mV Twos complement/DDR LVDS (3/8) AVDD ± 100mV Twos complement/parallel CMOS (5/8) AVDD ± 100mV Offset binary/parallel CMOS AVDD, 0mV/–100mV Offset binary/DDR LVDS Table 4. OE: Digital Control Pin VOLTAGE APPLIED ON OE DESCRIPTION 0 Output data buffers disabled AVDD Output data buffers enabled When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have any alternative functions. Keep SEN tied high and SCLK tied low on the board. Table 5. SDATA: Digital Control Pin VOLTAGE APPLIED ON SDATA DESCRIPTION 0 Normal operation Logic high Device enters standby AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD 3R (3/8) AVDD To Parallel Pin Figure 8. Simplified Diagram to Configure DFS Pin Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 15 ADS41B25 SBAS548 – JUNE 2011 www.ti.com SERIAL INTERFACE The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from 20MHz down to very low speeds (a few Hertz) and also with non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways: 1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10ns), as shown in Figure 9; or 2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. Register Address SDATA A7 A6 A5 A4 A3 Register Data A2 A1 A0 D7 D6 D5 tSCLK D4 tDSU D3 D2 D1 D0 tDH SCLK tSLOADS tSLOADH SEN RESET Figure 9. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at +25°C, minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted. PARAMETER MIN > dc TYP MAX UNIT 20 MHz fSCLK SCLK frequency (equal to 1/tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDATA setup time 25 ns tDH SDATA hold time 25 ns 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Serial Register Readout The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially, as shown in Figure 10: 1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of the register at address 0 cannot be read in the register readout mode. 2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read. 3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin. 4. The external controller can latch the contents at the falling edge of SCLK. 5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin. Register Address A[7:0] = 00h SDATA 0 0 0 0 0 0 Register Data D[7:0] = 01h 0 0 0 0 0 0 0 0 0 1 SCLK SEN OVR_SDOUT (1) a) Enable Serial Readout (READOUT = 1) Register Address A[7:0] = 43h SDATA A7 A6 A5 A4 A3 A2 Register Data D[7:0] = XX (don’t care) A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 SCLK SEN OVR_SDOUT (2) b) Read Contents of Register 43h. This Register Has Been Initialized with 40h (device is put in global power-down mode). (1) The OVR_SDOUT pin functions as OVR (READOUT = 0). (2) The OVR_SDOUT pin functions as a serial readout (READOUT = 1). Figure 10. Serial Readout Timing Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 17 ADS41B25 SBAS548 – JUNE 2011 www.ti.com RESET TIMING CHARACTERISTICS Power Supply AVDD, DRVDD t1 RESET t3 t2 SEN NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET must be permanently tied high. Figure 11. Reset Timing Diagram RESET TIMING REQUIREMENTS Typical values at +25°C and minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless otherwise noted. PARAMETER t1 Power-on delay t2 Reset pulse width t3 (1) 18 TEST CONDITIONS MIN Delay from power-up of AVDD and DRVDD to RESET pulse active 1 Pulse width of active RESET signal that resets the serial registers 10 Delay from RESET disable to SEN active 100 TYP MAX UNIT ms ns 1 (1) µs ns The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could enter the parallel configuration mode briefly and then return back to serial interface mode. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com SERIAL REGISTER MAP Table 6 summarizes the functions supported by the serial interface. Table 6. Serial Interface Register Map (1) (1) REGISTER ADDRESS DEFAULT VALUE AFTER RESET A[7:0] (Hex) D[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00 00 0 0 0 0 0 0 RESET READOUT 01 00 0 0 03 00 0 0 0 0 0 HIGH PERF MODE 1 25 50 26 00 0 3D 00 DATA FORMAT 3F 00 0 40 00 REGISTER DATA LVDS SWING 0 GAIN 0 0 TEST PATTERNS 0 0 0 0 EN OFFSET CORR 0 0 0 0 LVDS LVDS DATA CLKOUT STRENGTH STRENGTH 0 0 CUSTOM PATTERN D[11:6] CUSTOM PATTERN D[5:0] CMOS CLKOUT STRENGTH 0 EN CLKOUT RISE 0 EN CLKOUT FALL 41 00 LVDS CMOS 42 08 CLKOUT FALL POSN 0 0 1 STBY 43 00 0 PDN GLOBAL 0 PDN OBUF 0 0 4A 00 0 0 0 0 0 0 0 HIGH PERF MODE 2 BF 00 0 0 0 0 0 0 0 0 OFFSET PEDESTAL CF 00 FREEZE OFFSET CORR DF 00 0 0 0 CLKOUT RISE POSN 0 EN LVDS SWING OFFSET CORR TIME CONSTANT LOW SPEED 0 0 0 Multiple functions in a register can be programmed in a single write operation. DESCRIPTION OF SERIAL REGISTERS For best performance, two special mode register bits must be enabled: • HI PERF MODE 1 and • HI PERF MODE 2 Register Address 00h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RESET READOUT Bits[7:2] Always write '0' Bit 1 RESET: Software reset applied This bit resets all internal registers to the default values and self-clears to 0 (default = 1). Bit 0 READOUT: Serial readout This bit sets the serial readout of the registers. 0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage indicator. 1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 19 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address 01h (Default = 00h) 7 6 5 4 3 2 LVDS SWING Bits[7:2] (1) 0 0 0 0 LVDS SWING: LVDS swing programmability (1) 000000 = 011011 = 110010 = 010100 = 111110 = 001111 = Bits[1:0] 1 Default LVDS swing; ±350mV with external 100Ω termination LVDS swing increases to ±410mV LVDS swing increases to ±465mV LVDS swing increases to ±570mV LVDS swing decreases to ±200mV LVDS swing decreases to ±125mV Always write '0' The EN LVDS SWING register bits must be set to enable LVDS swing control. Register Address 03h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 HI PERF MODE 1 Bits[7:2] Always write '0' Bits[1:0] HI PERF MODE 1: High performance mode 1 00 = Default performance after reset 01 = Do not use 10 = Do not use 11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF MODE 1 bits 20 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address 25h (Default = 50h) 7 6 5 4 GAIN Bits[7:4] 3 0 2 1 0 TEST PATTERNS GAIN: Gain programmability These bits set the gain programmability in 0.5dB steps. 0000, 0001, 0010, 0011, 0100 = Do not use 0101 = 0dB gain (default after reset) 0110 = 0.5dB gain 0111 = 1dB gain 1000 = 1.5dB gain 1001 = 2dB gain 1010 = 2.5dB gain 1011 = 3dB gain 1100 = 3.5dB gain Bit 3 Always write '0' Bits[2:0] TEST PATTERNS: Data capture These bits verify data capture. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern Output data D[11:0] is an alternating sequence of 010101010101 and 101010101010. 100 = Outputs digital ramp Output data increments by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095 101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern) 110 = Unused 111 = Unused Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 21 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address 26h (Default = 00h) 7 6 0 5 0 4 0 3 0 0 2 1 0 0 LVDS CLKOUT STRENGTH LVDS DATA STRENGTH Bits[7:2] Always write '0' Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength This bit determines the external termination to be used with the LVDS output clock buffer. 0 = 100Ω external termination (default strength) 1 = 50Ω external termination (2x strength) Bit 0 LVDS DATA STRENGTH: LVDS data buffer strength This bit determines the external termination to be used with all of the LVDS data buffers. 0 = 100Ω external termination (default strength) 1 = 50Ω external termination (2x strength) Register Address 3Dh (Default = 00h) 7 6 DATA FORMAT Bits[7:6] 5 4 3 2 1 0 EN OFFSET CORR 0 0 0 0 0 DATA FORMAT: Data format selection These bits selects the data format. 00 = The DFS pin controls data format selection 10 = Twos complement 11 = Offset binary Bit 5 ENABLE OFFSET CORR: Offset correction setting This bit sets the offset correction. 0 = Offset correction disabled 1 = Offset correction enabled Bits[4:0] Always write '0' Register Address 3Fh (Default = 00h) 7 0 6 5 4 3 2 1 0 0 CUSTOM PATTERN D11 CUSTOM PATTERN D10 CUSTOM PATTERN D9 CUSTOM PATTERN D8 CUSTOM PATTERN D7 CUSTOM PATTERN D6 Bits[7:6] Always write '0' Bits[5:0] CUSTOM PATTERN These bits set the custom pattern. Register Address 40h (Default = 00h) 7 6 5 4 3 2 1 0 CUSTOM PATTERN D5 CUSTOM PATTERN D4 CUSTOM PATTERN D3 CUSTOM PATTERN D2 CUSTOM PATTERN D1 CUSTOM PATTERN D0 0 0 Bits[7:2] CUSTOM PATTERN These bits set the custom pattern. Bits[1:0] 22 Always write '0' Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address 41h (Default = 00h) 7 6 LVDS CMOS Bits[7:6] 5 4 CMOS CLKOUT STRENGTH 3 EN CLKOUT RISE 2 1 CLKOUT RISE POSN 0 EN CLKOUT FALL LVDS CMOS: Interface selection These bits select the interface. 00, 10 = The DFS pin controls the selection of either LVDS or CMOS interface 01 = DDR LVDS interface 11 = Parallel CMOS interface Bits[5:4] CMOS CLKOUT STRENGTH Controls strength of CMOS output clock only. 00 = Maximum strength (recommended and used for specified timings) 01 = Medium strength 10 = Low strength 11 = Very low strength Bit 3 ENABLE CLKOUT RISE 0 = Disables control of output clock rising edge 1 = Enables control of output clock rising edge Bits[2:1] CLKOUT RISE POSN: CLKOUT rise control Controls position of output clock rising edge LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 500ps, hold increases by 500ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200ps, hold increases by 200ps CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 100ps, hold increases by 100ps 10 = Setup reduces by 200ps, hold increases by 200ps 11 = Setup reduces by 1.5ns, hold increases by 1.5ns Bit 0 ENABLE CLKOUT FALL 0 = Disables control of output clock fall edge 1 = Enables control of output clock fall edge Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 23 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address 42h (Default = 08h) 7 6 CLKOUT FALL POSN Bits[7:6] 5 4 3 2 1 0 0 0 1 STBY 0 0 CLKOUT FALL POSN Controls position of output clock falling edge LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 400ps, hold increases by 400ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200ps, hold increases by 200ps CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Falling edge is advanced by 100ps 10 = Falling edge is advanced by 200ps 11 = Falling edge is advanced by 1.5ns Bits[5:4] Always write '0' Bit 3 Always write '1' Bit 2 STBY: Standby mode This bit sets the standby mode. 0 = Normal operation 1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time from standby is fast Bits[1:0] 24 Always write '0' Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address 43h (Default = 00h) 7 6 5 4 3 2 1 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING Bit 0 Always write '0' Bit 6 PDN GLOBAL: Power-down 0 This bit sets the state of operation. 0 = Normal operation 1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time. Bit 5 Always write '0' Bit 4 PDN OBUF: Power-down output buffer This bit set the output data and clock pins. 0 = Output data and clock pins enabled 1 = Output data and clock pins powered down and put in high- impedance state Bits[3:2] Always write '0' Bits[1:0] EN LVDS SWING: LVDS swing control 00 = LVDS swing control using LVDS SWING register bits is disabled 01, 10 = Do not use 11 = LVDS swing control using LVDS SWING register bits is enabled Register Address 4Ah (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 HI PERF MODE 2 Bits[7:1] Always write '0' Bit[0] HI PERF MODE 2: High performance mode 2 This bit is recommended for high input signal frequencies greater than 230MHz. 0 = Default performance after reset 1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address BFh (Default = 00h) 7 6 5 OFFSET PEDESTAL Bits[7:4] 4 3 2 1 0 0 0 0 0 OFFSET PEDESTAL These bits set the offset pedestal. When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. Bits[3:0] 26 VALUE PEDESTAL 0111 0110 0101 — 0000 — 1111 1110 — 1000 7LSB 6LSB 5LSB — 0LSB — –1LSB –2LSB — –8LSB Always write '0' Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Register Address CFh (Default = 00h) 7 6 FREEZE OFFSET CORR 0 Bit 7 5 4 3 2 OFFSET CORR TIME CONSTANT 1 0 0 0 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set) 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the last estimated value is used for offset correction every clock cycle; see the OFFSET CORRECTION section. Bit 6 Always write '0' Bits[5:2] OFFSET CORR TIME CONSTANT These bits set the offset correction time constant for the correction loop time constant in number of clock cycles. Bits[1:0] VALUE TIME CONSTANT (Number of Clock Cycles) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1M 2M 4M 8M 16M 32M 64M 128M 256M 512M 1G 2G Always write '0' Register Address DFh (Default = 00h) 7 6 0 0 5 4 LOW SPEED Bits[7:6] Always write '0' Bits[5:4] LOW SPEED: Low-speed mode 3 2 1 0 0 0 0 0 00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for sampling rates greater than 80MSPS. 11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal to 80MSPS. Bits[3:0] Always write '0' Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 27 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 10MHz INPUT SIGNAL FFT FOR 70MHz INPUT SIGNAL 0 0 SFDR = 94.3dBc SINAD = 68.8dBFS SNR = 68.9dBFS THD = 89.7dBc −20 −20 −40 Amplitude (dB) Amplitude (dB) −40 −60 −60 −80 −80 −100 −100 −120 SFDR = 93.5dBc SINAD = 68.7dBFS SNR = 68.7dBFS THD = 89.3dBc 0 10 20 30 40 Frequency (MHz) 50 −120 60 0 10 20 Figure 12. FFT FOR 170MHz INPUT SIGNAL FFT FOR 300MHz INPUT SIGNAL SFDR = 93.7dBc SINAD = 68.2dBFS SNR = 68.3dBFS THD = 88.9dBc SFDR = 71.2dBc SINAD = 66dBFS SNR = 67.2dBFS THD = 70.9dBc −20 −40 Amplitude (dB) −40 Amplitude (dB) 60 0 −20 −60 −60 −80 −80 −100 −100 0 10 20 30 40 Frequency (MHz) 50 60 −120 0 Figure 14. 28 50 Figure 13. 0 −120 30 40 Frequency (MHz) 10 20 30 40 Frequency (MHz) 50 60 Figure 15. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR TWO-TONE INPUT SIGNAL FFT FOR TWO-TONE INPUT SIGNAL 0 0 Each Tone at −7dBFS Amplitude fIN1=100.1MHz fIN2=105.1MHz TwoTone IMD = 97.7dBFS SFDR = 105.7dBFS −20 −20 −40 Amplitude (dB) Amplitude (dB) −40 −60 −80 −100 −100 0 10 20 30 40 Frequency (MHz) 50 −120 60 10 20 30 40 Frequency (MHz) 50 Figure 17. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 95 69 90 68 60 68 68 SNR (dBFS) 80 75 70 65 67 66 66 66 60 65 55 50 0 Figure 16. 85 SFDR (dBc) −60 −80 −120 Each Tone at −36dBFS Amplitude fIN1=100.1MHz fIN2=105.1MHz TwoTone IMD = 94.9dBFS SFDR = 100.4dBFS 64 0 50 100 150 200 250 300 350 400 450 500 64 0 Input Frequency (MHz) 50 100 150 200 250 300 350 400 450 500 Input Frequency (MHz) Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 29 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR vs GAIN AND INPUT FREQUENCY SINAD vs GAIN AND INPUT FREQUENCY 105 72 150MHz 170MHz 220MHz 100 300MHz 400MHz 150MHz 170MHz 220MHz 70 300MHz 400MHz 95 68 SINAD (dBFS) SFDR (dBc) 90 85 80 66 64 75 62 70 60 65 0 0.5 1 1.5 2 Digital Gain (dB) 2.5 3 58 3.5 0 0.5 1 3 Figure 21. PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs INPUT AMPLITUDE 71 3.5 71 110 Input Frequency = 70MHz Input Frequency = 170MHz 70.5 100 70.5 100 70 90 70 80 69.5 80 69.5 70 69 70 69 60 68.5 60 68.5 50 68 50 68 40 67.5 40 67.5 67 30 66.5 20 −50 SFDR(dBc) SFDR(dBFS) SNR 30 20 −50 −45 −40 −35 −30 −25 −20 −15 Amplitude (dBFS) −10 −5 0 SFDR (dBc,dBFS) 90 SNR (dBFS) SFDR(dBc,dBFS) 2.5 Figure 20. 110 SFDR(dBc) SFDR(dBFS) SNR −45 Figure 22. 30 1.5 2 Digital Gain (dB) −40 −35 −30 −25 −20 −15 Amplitude (dBFS) −10 −5 SNR (dBFS) 60 67 0 66.5 Figure 23. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR ACROSS TEMPERATURE vs AVDD SUPPLY 70 94 100 Input Frequency = 70MHz AVDD = 1.65 AVDD = 1.7 AVDD = 1.75 AVDD = 1.8 98 69.5 92 69 88 68.5 94 SFDR (dBc) 90 SNR (dBFS) SFDR (dBc) 96 68 86 AVDD = 1.85 AVDD = 1.9 AVDD = 1.95 92 90 88 86 67.5 84 SFDR SNR 82 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 Input Common−Mode Voltage (V) 2 82 67 Input Frequency = 70MHz 80 −40 10 35 Temperature (°C) 60 85 Figure 24. Figure 25. SNR ACROSS TEMPERATURE vs AVDD SUPPLY PERFORMANCE vs DRVDD SUPPLY VOLTAGE 70.5 92 70 AVDD = 1.65 AVDD = 1.7 AVDD = 1.75 AVDD = 1.8 69.8 69.6 SFDR SNR AVDD = 1.85 AVDD = 1.9 AVDD = 1.95 SFDR (dBc) 69.4 SNR (dBFS) −15 69.2 69 68.8 91 70 90 69.5 89 69 88 68.5 87 68 SNR (dBFS) 84 68.6 68.4 Input Frequency = 70MHz 68.2 Input Frequency = 70MHz 68 −40 −15 10 35 Temperature (°C) 60 86 1.65 85 Figure 26. 1.7 1.75 1.8 1.85 DRVDD Supply (V) 1.9 67.5 1.95 Figure 27. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 31 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE vs INPUT CLOCK AMPLITUDE PERFORMANCE vs INPUT CLOCK AMPLITUDE 70 70 95 SFDR SNR 69.5 93 69.5 91 69 91 69 89 68.5 89 68.5 87 68 87 68 85 67.5 85 67.5 SFDR (dBc) 93 SNR (dBFS) SFDR (dBc) SFDR SNR Input Frequency = 70MHz 67 83 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Input Frequency = 70MHz 67 83 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Differential Clock Amplitude (VPP) Differential Clock Amplitude (VPP) Figure 28. Figure 29. PERFORMANCE vs INPUT CLOCK DUTY CYCLE CMRR vs FREQUENCY 70 96 0 92 69 90 68.5 −10 −20 CMRR (dB) 69.5 Input Frequency = 170MHz 50mVPP Signal Superimposed on Input Common−Mode Voltage (1.7V) SNR (dBFS) THD (dBc) SNR THD 94 SNR (dBFS) 95 −30 68 88 −40 67.5 86 −50 Input Frequency = 10MHz 84 10 20 30 40 50 60 70 Input Clock Duty Cycle (%) 80 90 67 −60 0 50 100 150 200 250 300 Frequency of Input Common−Mode Signal (MHz) Figure 30. 32 Figure 31. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. CMRR SPECTRUM PSRR vs FREQUENCY 0 fIN = 70MHz fCM = 10MHz, 50mVPP SFDR = 85.3dBc Amplitude (fIN) = -1dBFS Amplitude (fCM) = -94.9 Amplitude (fIN + fCM) = -86.3 Amplitude (fIN - fCM) = -87.4 Amplitude (dB) -40 PSRR on AVDD Supply 50mVPP PSRR on AVDD_BUF Supply 100mVPP −10 −20 −30 PSRR (dB) -20 0 fIN = 70MHz fIN - fCM = 60MHz -60 −40 fIN + fCM = 80MHz -80 −50 fCM = 10MHz −60 -100 −70 -120 0 12.5 25 37.5 50 −80 62.5 0 Frequency (MHz) 20 30 40 50 60 70 80 Figure 32. Figure 33. ZOOMED VIEW OF SPECTRUM WITH PSRR SIGNAL POWER vs SAMPLING FREQUENCY -20 -40 Analog Power (AVDD Power + BUF Power) DRVDD Power 230 210 190 Power (mW) fPSRR -60 fIN - fPSRR 100 250 fIN = 10MHz fPSRR = 10MHz, 50mVPP Amplitude (fIN) = -1dBFS Amplitude (fPSRR) = -65.6 Amplitude (fIN + fPSRR) = -67.5 Amplitude (fIN - fPSRR) = -68.3 fIN 90 Frequency of Signal on Supply (MHz) 0 Amplitude (dB) 10 fIN + fPSRR 170 150 130 -80 110 90 -100 70 -120 0 5 10 15 20 25 30 50 0 Frequency (MHz) Figure 34. 25 50 75 Sampling Speed (MSPS) 100 125 Figure 35. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 33 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. DRVDD CURRENT vs SAMPLING FREQUENCY 60 LVDS 350mV Swing LVDS 200mV Swing CMOS Default DRVDD Current (mA) 50 40 30 20 10 0 0 25 50 75 Sampling Speed (MSPS) 100 125 Figure 36. 34 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR CONTOUR (0dB Gain) 125 89 120 89 75 70 80 65 Sampling Frequency (MSPS) 83 86 110 100 80 89 89 75 70 90 83 65 86 80 89 89 70 80 70 86 75 65 83 65 10 50 100 150 200 250 300 350 400 Input Frequency (MHz) 65 70 75 80 85 SFDR (dBc) Figure 37. SFDR CONTOUR (3.5dB Gain) 125 89 89 120 82 88 74 78 70 Sampling Frequency (MSPS) 87 110 89 88 86 100 89 88 82 88 89 90 88 89 78 74 87 70 88 80 88 86 88 88 87 70 87 86 82 70 74 78 65 10 50 100 150 200 250 300 350 400 Input Frequency (MHz) 70 75 80 85 SFDR (dBc) Figure 38. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 35 ADS41B25 SBAS548 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SNR CONTOUR (0dB Gain) 125 68.8 Sampling Frequency (MSPS) 120 68.6 68.4 68.2 68 67.5 67 66.5 66 110 65.5 100 66.5 68.8 68.6 68.4 68.2 65 90 66 67.5 68 65.5 67 66.5 80 68.8 70 68.4 68.2 68.6 66 67.5 68 65.5 65 67 64.5 65 64 65 10 50 100 150 200 250 300 350 400 Input Frequency (MHz) 64 65 66 67 68 SNR (dBFS) Figure 39. SNR CONTOUR (3.5dB Gain) 125 Sampling Frequency (MSPS) 120 66.4 66.2 66.4 66.2 66 65.8 65.3 64.8 64.3 110 100 66 65.8 64.8 90 65.3 64.3 80 64.8 65.8 70 66.2 66.4 66 65.3 63.8 64.3 63.3 63.8 65 10 50 100 150 200 250 300 350 400 Input Frequency (MHz) 62.5 63 63.5 64 64.5 65 65.5 66 SNR (dBFS) Figure 40. 36 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS41B25 is a buffered analog input and ultralow power ADC with maximum sampling rates up to 125MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 21 clock cycles. The output is available as 12-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement format. ANALOG INPUT The analog input pins have analog buffers (powered from the AVDD_BUF supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (10kΩ dc resistance and 3.5pF input capacitance). The buffer helps to isolate the external driving source from the switching currents of the sampling circuit. This buffering makes it easy to drive the buffered inputs compared to an ADC without the buffer. The input common-mode is set internally using a 5kΩ resistor from each input pin to 1.7V, so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.375V) and (VCM – 0.375V), resulting in a 1.5VPP differential input swing. The input sampling circuit has a high 3dB bandwidth that extends up to 800MHz (measured from the input pins to the sampled voltage). Figure 41 shows an equivalent circuit for the analog input. LPKG 1nH INP RROUTING 23W CPAD 2.5pF CPIN 0.5pF Buffer RBIAS 5kW RPAD 200W VCM = 1.7V LPKG 1nH INM RROUTING 23W Sampling Circuit REQ RBIAS 5kW CPAD 2.5pF CPIN 0.5pF CEQ CEQ RPAD 200W Buffer REQ (1) CEQ refers to the equivalent input capacitance of the buffer = 4pF. (2) REQ refers to the REQ buffer = 10Ω. (3) This equivalent circuit is an approximation and valid for frequencies less than 700MHz. Figure 41. Analog Input Equivalent Circuit(3) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 37 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This technique improves the common-mode noise immunity and even-order harmonic rejection. A small resistor (5Ω to 10Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics. Figure 42 and Figure 43 show the differential impedance (ZIN = RIN || CIN) seen by looking into the ADC input pins. The presence of the analog input buffer produces an almost constant input capacitance, as shown in Figure 42. 10 RIN (kW) 1 0.1 RIN Simulation RIN Measurement 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Frequency (GHz) Figure 42. ADC Analog Input Resistance (RIN) Across Frequency 5 CIN (pF) 4 3 2 1 CIN Simulation CIN Measurement 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Frequency (GHz) Figure 43. ADC Analog Input Capacitance (CIN) Across Frequency 38 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Driving Circuit Two example driving circuit configurations are shown in Figure 44 and Figure 45—one optimized for low input frequencies and the other optimized for high input frequencies. In Figure 44, a single transformer is used and is suited for low input frequencies. To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended (see Figure 45). Note that both drive circuits have been terminated by 50Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. 5W T1 INP 0.1mF 25W 0.1mF 25W INM 1:1 5W Figure 44. Drive Circuit for Low Input Frequencies 5W T2 T1 INP 0.1mF 50W 0.1mF 50W 50W 50W INM 1:1 1:1 5W Figure 45. Drive Circuit for High Input Frequencies The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 44 and Figure 45. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω (for a 50Ω source impedance). Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 39 ADS41B25 SBAS548 – JUNE 2011 www.ti.com CLOCK INPUT The ADS41B25 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources. Figure 46 shows an equivalent circuit for the input clock. Clock Buffer LPKG 1nH 20W CLKP CBOND 1pF RESR 100W 5kW 2pF LPKG 1nH 20W CEQ CEQ 0.95V 5kW CLKM CBOND 1pF RESR 100W NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer. Figure 46. Input Clock Equivalent Circuit A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1μF capacitor, as shown in Figure 47. For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 48 shows a differential circuit. CMOS Clock Input 0.1mF 0.1mF CLKP CLKP Differential Sine-Wave, PECL, or LVDS Clock Input VCM 0.1mF 0.1mF CLKM CLKM Figure 47. Single-Ended Clock Driving Circuit 40 Figure 48. Differential Clock Driving Circuit Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com GAIN FOR SFDR/SNR TRADE-OFF The ADS41B25 includes gain settings that can be used to get improved SFDR performance. The gain is programmable from 0dB to 3.5dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 7. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR. After a reset, the gain is enabled with 0dB gain setting. For other gain settings, program the GAIN register bits. Table 7. Full-Scale Range Across Gains GAIN (dB) TYPE FULL-SCALE (VPP) 0 Default after reset 1.5 0.5 Programmable gain 1.41 1 Programmable gain 1.33 1.5 Programmable gain 1.26 2 Programmable gain 1.19 2.5 Programmable gain 1.12 3 Programmable gain 1.06 3.5 Programmable gain 1 OFFSET CORRECTION The ADS41B25 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 8. Table 8. Time Constant of Offset Correction Loop (1) OFFSET CORR TIME CONSTANT TIME CONSTANT, TCCLK (Number of Clock Cycles) TIME CONSTANT, TCCLK × 1/fS (sec) (1) 0000 1M 8ms 0001 2M 16ms 0010 4M 33.5ms 0011 8M 67ms 0100 16M 134ms 0101 32M 268ms 0110 64M 537ms 0111 128M 1.1s 1000 256M 2.2s 1001 512M 4.3s 1010 1G 8.6s 1011 2G 17s 1100 Reserved — 1101 Reserved — 1110 Reserved — 1111 Reserved — Sampling frequency, fS = 125MSPS. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 41 ADS41B25 SBAS548 – JUNE 2011 www.ti.com After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by a default after reset. After a reset, the offset correction is disabled. To use offset correction set EN OFFSET CORR to '1' and program the required time constant. Figure 49 shows the time response of the offset correction algorithm after it is enabled. Output Code (LSB) OFFSET CORRECTION Time Response 2050 2047 2044 2041 2038 2035 2032 2029 2026 2023 2020 2017 2014 2011 2008 2005 2002 1999 Offset Correction Converges to Output Code of 2048 2045 Offset of 3 LSBs 2048 Final Converged Value Offset Correction Begins -5 5 15 25 35 45 55 65 75 85 95 105 Time (ms) Figure 49. Time Response of Offset Correction POWER DOWN The ADS41B25 has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) is powered down, resulting in reduced total power dissipation of about 7mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To enter the global power-down mode, set the PDN GLOBAL register bit. Standby In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5µs. The total power dissipation in standby mode is approximately 145mW. To enter the standby mode, set the STBY register bit. Output Buffer Disable The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast, approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin. Input Clock Stop In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The power dissipation is approximately 92mW. POWER-SUPPLY SEQUENCE During power-up, the AVDD, AVDD_BUF, and DRVDD supplies can come up in any sequence. These supplies are separated in the device. Externally, they can be driven from separate supplies or from a single supply. 42 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com DIGITAL OUTPUT INFORMATION The ADS41B25 provides 12-bit data and an output clock synchronized with the data. Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the LVDS CMOS serial interface register bit or using the DFS pin. DDR LVDS Outputs In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 50. Pins CLKOUTP Output Clock CLKOUTM D0_D1_P Data Bits D0, D1 LVDS Buffers D0_D1_M D2_D3_P Data Bits D2, D3 D2_D3_M D4_D5_P 12-Bit ADC Data Data Bits D4, D5 D4_D5_M D6_D7_P Data Bits D6, D7 D6_D7_M D8_D9_P Data Bits D8, D9 D8_D9_M D10_D11_P Data Bits D10, D11 D10_D11_M ADS41B25 Figure 50. ADS41B25 LVDS Data Outputs Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 43 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 12 data bits, as shown in Figure 51. CLKOUTP CLKOUTM D0_D1_P, D0_D1_M D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 Sample N Sample N + 1 Figure 51. DDR LVDS Interface 44 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 52. After reset, the buffer presents an output impedance of 100Ω to match with the external 100Ω termination. The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV. Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively. The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. VDIFF High Low OUTP External 100W Load OUTM 1.1V ROUT VDIFF Low High NOTE: Use the default buffer strength to match 100Ω external termination (ROUT = 100Ω). To match with a 50Ω external termination, set the LVDS STRENGTH bit (ROUT = 50Ω). Figure 52. LVDS Buffer Equivalent Circuit Parallel CMOS Interface In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 53 depicts the CMOS output interface. Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window (even at 125MSPS) is provided so the data outputs have minimal load capacitance. It is recommended to use short traces (one to two inches or 2,54cm to 5,08cm) terminated with less than 5pF load capacitance, as shown in Figure 54. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 45 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Pins OVR CLKOUT CMOS Output Buffers D0 D1 D2 D3 ¼ ¼ 12-Bit ADC Data D9 D10 D11 ADS41B25 Figure 53. CMOS Output Interface 46 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CMOS Output Buffers D0 D1 D2 CLKIN D0_In D1_In D2_In 12-Bit ADC Data D10 D11 D10_In D11_In ADS41B25 Use short traces between ADC output and receiver pins (1 to 2 inches). Figure 54. Using the CMOS Data Outputs CMOS Interface Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG) where: CL = load capacitance, N × FAVG = average number of output bits switching. (1) Figure 36 illustrates the current across sampling frequencies at 2MHz analog input frequency. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 47 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Input Over-Voltage Indication (OVR Pin) The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS). For a positive overload, the D[11:0] output data bits are FFFh in offset binary output format and 7FFh in twos complement output format. For a negative input overload, the output code is 000h in offset binary output format and 800h in twos complement output format. Output Data Format Two output data formats are supported: twos complement and offset binary. They can be selected using the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout and grounding. Supply Decoupling Because the ADS41B25 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. Exposed Pad In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com). 48 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate – The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and EGCHAN. To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal. Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN. Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. SNR = 10Log10 PS PN (2) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. SINAD = 10Log10 PS PN + PD (3) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 49 ADS41B25 SBAS548 – JUNE 2011 www.ti.com Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (4) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (5) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V. AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (6) Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted. Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is the resulting change of the ADC output code (referred to the input), then: DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (7) Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. 50 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS41B25 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS41B25IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 AZ41B25 ADS41B25IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 AZ41B25 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of