ADS4242EVM

User's Guide SLAU333A – March 2011 – Revised June 2013 ADS42xx EVM This is the user’s guide for the ADS42xx EVM Rev B (EVM). The ADS42xx (dual channel, 12-bit and 14bit, up to 250 MSPS) is a dual analog-to-digital converter family. This EVM is specifically suited for interfacing with TI’s TSW1400 EVM to capture and display waveforms from the ADC. The EVM schematic, BOM, and layout files can be found in the design package in the ADS42xx EVM product folder on www.ti.com. 1 2 3 Contents Software Control ............................................................................................................ 2 1.1 Installation Instructions ............................................................................................ 2 1.2 Software Operation ................................................................................................ 2 Basic Test Procedure ....................................................................................................... 5 2.1 Test Block Diagram ................................................................................................ 5 2.2 Verify Board Set-up ................................................................................................ 5 2.3 Test Set-up Connections .......................................................................................... 6 2.4 TSW1400 Quick start Operation ................................................................................. 6 2.5 ADS42xx Test Procedure ......................................................................................... 8 Optional Configurations .................................................................................................... 9 3.1 THS4509 Input Op-Amp Configuration .......................................................................... 9 3.2 On-Board CDCE72010 Clock .................................................................................... 9 3.3 Parallel CMOS Output ........................................................................................... 10 List of Figures 1 ADS42xx/58C28 GUI Front Panel ........................................................................................ 3 2 ADS58C28-Only GUI Panel ............................................................................................... 4 3 Test Set-Up Block Diagram ................................................................................................ 5 4 FFT Plot: 160-MHz Clock, 15.5-MHz Input .............................................................................. 8 List of Tables 1 Default ADS42xx/58C28 EVM Rev B Jumper Setting for Serial Interface .......................................... 5 2 Parallel Interface with Pin Control of the ADS42xx/58C28 EVM Rev B Jumper Setting .......................... 6 3 Jumper Setting for Transformer-Coupled or OPA-Driven Input 4 Jumper Setting for Transformer-Coupled or CDCE72010 Input 5 ...................................................... ..................................................... Jumper and Component Setting for DDR LVDS Output and Parallel CMOS Output ............................ 9 9 10 Windows is a registered trademark of Microsoft Corporation. SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated ADS42xx EVM 1 Software Control 1 Software Control 1.1 Installation Instructions • • • • • • 1.2 www.ti.com Open the folder named: ADS58C28_ADS42xx_Installer_vxpx (where xpx represents the latest version). Double-click: setup.exe Follow on-screen instructions to complete GUI installation – Wait for ADS42xx_58C28 GUI vxpx Installer initializing screen to complete – Click Next to install files in the default destination directory – Select I accept the License Agreement and click Next – Select Next on the summary page – Wait for files to load and then click Next – Once all files are installed click Next If Windows® Logo Message window appears, click Continue Anyway. Once installed, launch by clicking on the ADS58C28_ADS42xx_GUI_vxpx program in Start→Texas Instruments ADCs When plugging in the USB cable for the first time, you are prompted to install the USB drivers – On the Welcome to the Found New Hardware Wizard window select No, not at this time – Select Install the software automatically button on the next window – Select Continue Anyway on the Windows Logo Message window – If computer cannot find the drivers automatically, then you can access them directly in the install directory: C:\Program Files\Texas Instruments\ADS58C28_ADS42xx\data\ – Click Finish once completed Software Operation The software allows full programming control of the ADC device. Figure 1 shows the GUI front panel that has two register tabs: Top Level and Advanced. The Top Level tab provides an interface to the most used registers. The Advanced tab includes less used registers and provides an option to manually input address and data values. 1.2.1 Top Level Figure 1 shows the Top Level tab of the register user interface. Below is a brief explanation of the controls. Refer to the ADS42xx (SBAS533) and ADS58C28(SBAS509) datasheet for more detailed explanations of the register functions, as needed. ● Device selection: ● Reset: ● PND Global: ● Data format: Device selection of ADS58C28 or ADS42xx for proper device. Device reset, click this switch to reset the registers in the device. Device power down, click this switch on to power down the device. Device output data format, click it to set 2’s complement or offset binary format. ● LVDS_CMOS Ctrl: Select this box for LVDS or CMOS output format. ● Digital Funct Ctrl: Enable or disable three digital functions: SNRboost/Gain Disable – Gain, test patterns, and offset correction are disabled. SNRboost Enable Only – Gain, test patterns and offset correction are disabled, SNRBoost enable. SNRboost/Gain Enable – Gain, test patterns, offset correction are enabled, SNRBoost enable. ● Gain_chA: Set this box for gain of channel A. ● Gain_chB: Set this box for gain of channel B. ● Test Pattern: Select device test pattern. ● High Perf Mode: High performance mode enable or disable. 2 ADS42xx EVM SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Software Control www.ti.com ● High Freq Mode ChA: ● High Freq Mode ChB: ● Low Speed Mode En: ● Low Speed Mode ChA: ● Low Speed Mode ChB: ● LVDS Data Strength: ● LVDS Clkout Strength: ● CMOS Clk Strength: ● Offset Correction: ● Freeze Offset Correction: ● Offset Corr Time Constant ● ChA Offset Pedestal: ● ChB Offset Pedestal: High frequency Mode enable for channel A. High frequency Mode enable for channel B. Low speed mode enable or disable. Low speed mode for channel A. Low speed mode for channel B. Set the data strength from this switch. Set the output clock strength from this switch. Set CMOS output clock strength from this switch. Enable or disable the offset correction. Set the freeze offset correction setting The offset correction loop time constant in number of clock cycles. Channel A offset pedestal selection Channel B offset pedestal selection Figure 1. ADS42xx/58C28 GUI Front Panel 1.2.2 ADS58C28-Only Controls Set the registers for the SNRBoost option on this panel, shown in Figure 2. By enabling SNRBoost Enable (DIGITAL MODE 2), select the SNRBoost mode from the SNRBoost Filter Number. For more detailed information, refer to Table 14 in the ADS58C28 datasheet (SBAS509B). SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated ADS42xx EVM 3 Software Control www.ti.com Figure 2. ADS58C28-Only GUI Panel 1.2.3 Register Control ● ● ● ● 1.2.4 Send All: Read All: Save: Load: Sends all the register configurations on the panel to the device. Not active. Saves the register configuration to text file. Loads a register file from a text file. After load register, the relative switches and selecting boxes are automatically updated. o Select the Load button. o Double click on the desired register file. o Clicking Send All ensures all of the values are loaded properly. Miscellaneous Settings ● Device Selection: ● Reset USB: ● Show USB Port: ● Exit: 4 ADS42xx EVM Select ADS58C28 or ADS42xx for proper operation. Toggle this button if the USB port is not responding. This generates a new USB handle address. Allows user to change USB port configuration. Default setting is appropriate for the EVM RevB. Stops the program SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Basic Test Procedure www.ti.com 2 Basic Test Procedure This section outlines the basic test procedure for testing the EVM. 2.1 Test Block Diagram The test set-up for general testing of the EVM with the TSW1400 capture card is shown in Figure 3. PC (HSDC Pro) Mini-USB Mini-USB J17 J5 J13 J4 LVDS TSW1400 CLK IN Signal Generator AIN_A/B Signal Generator J19 ADS42xx/ 58C28EVM J6/J3 J12 J23 +5V +5V Figure 3. Test Set-Up Block Diagram 2.2 Verify Board Set-up Verify jumper settings are in the correct position as outlined in Table 1. Table 1. Default ADS42xx/58C28 EVM Rev B Jumper Setting for Serial Interface (1) Jumper Default position Function JP15 Short 1 - 2 DC supply JP16 Short 1 - 2 DC supply JP17 Short 2 - 3 DC supply, LDO JP19 Short 3 - 2 DC supply, LDO JP28 Short 3 - 2 DC supply, LDO JP29 Short 3 - 2 DC supply, LDO JP26 Open DC supply for external buffer JP27 Open DC supply for external buffer JP3 Short 2 - 3 OPA power down JP4 Short 2 - 3 OPA power down JP22 Open SDOUT to FPGA JP20 Short 1 - 2 CDC JP21 Short 1 - 2 CDC J14 Short 1 - 2 CDC power down J18 Open CDC, VCXO JP8 Short 3 - 2 ADC SCLK for SPI JP9 Short 3 - 2 ADC SDATA for SPI JP10 Short 3 - 2 ADC SEN for SPI JP11 Short 3 - 2 ADC for SPI, also reset JP 12 Short 1 - 2 ADC low -speed mode disable (1) The EVM schematic shows the default setting of JP8 to JP11 as parallel interface (Table 2), which is for EVM installation. After EVM tested and released, these jumpers are set as serial interface (Table 1). SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated ADS42xx EVM 5 Basic Test Procedure www.ti.com Table 1. Default ADS42xx/58C28 EVM Rev B Jumper Setting for Serial Interface (1) (continued) Jumper Default position JP 13 Open Function JP14 Short 7 - 8 ADC 2’s complement, DDR LVDS JP5 Short 1 - 2 ADC CTRL3, normal operation JP6 Short 1 - 2 ADC CTRL2, normal operation JP7 Short 1 - 2 ADC CTRL1, normal operation JP 18 Short 1 - 2 Ext Buffer JP 23 Short 1 - 2 Ext Buffer JP 24 Short 1 - 2 Ext Buffer JP 25 Short 1 - 2 Ext Buffer Table 2. Parallel Interface with Pin Control of the ADS42xx/58C28 EVM Rev B Jumper Setting 2.3 Position Function JP8 Short 1 - 2 ADC SCLK for parallel control JP9 Short 1 - 2 ADC SDATA for parallel control JP10 Short 1 - 2 ADC SEN for parallel control JP11 Short 1 - 2 ADC parallel control Test Set-up Connections • • • • • • 2.4 Jumper Connect Connect Connect Connect Connect Connect the ADS42xx/ADS58C28 EVM to the TSW1400 EVM 5-V power to the banana jack at J10; connect ground to J12 the USB cable to the programming computer at J17 the USB and power supply jack to TSW1400 clock signal through appropriate BPF to J19 input signal through appropriate BPF to J6, J3 TSW1400 Quick start Operation See the TSW1400 user’s guide (SLWU079B) for a more detailed explanation of the TSW1400 set-up and operation. This document assumes the TSW1400 software is installed and functioning properly. The front panel of the TSW1400 is shown in Figure 4. • Download and install TSW1400 GUI (High Speed Data Converter Pro GUI Installer, vx.x (Rev.E)) and TSW140xEVM .ini File Update List from www.ti.com/tool/tsw1400evm • Open High Speed Data Converter Pro 6 ADS42xx EVM SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Basic Test Procedure www.ti.com • • Select OK Select ADS422x or ADS424x from Select ADC of GUI • • Select Yes to update the firmware from ADC selection Select the ADS422x or the ADS424x device name from the TI ADC Selection pull-down menu – If this option is not available, download the latest ADS422x.ini or ADS424x.ini file from the product folder of the TSW1400 at www.ti.com/tool/tsw1400evm – Place updated *.ini files in the TSW1400 product directory located at C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\1400 Details\ADC files Select Single Tone FFT from the Test Selection pull-down menu • SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated ADS42xx EVM 7 Basic Test Procedure www.ti.com Figure 4. FFT Plot: 160-MHz Clock, 15.5-MHz Input • • • • • • 2.5 ADS42xx Test Procedure • • • • 8 Select the desired channel (that is, Channel A or B) from the Channel Display pull-down menu Change the ADC sampling rate to the desired value (that is, 250 M) Change the input frequency to the desired value (that is, 15.5M) Select Rectangular of windowing option after checking Auto Calculation of Coherent Frequencies Set the same frequency of signal generator as ADC Input Target Frequency Press the Capture button to initiate a data capture Switch on the 5-V power supply on the ADC EVM. Verify source current is about 330 mA ±30 mA, with the clock and TSW1400 connected at EVM default (that is, connected at 250 MHz). Connect clock signal at J19 through an appropriate BPF – Adjust the signal generator amplitude output to 0.6 Vrms to provide approximately 0.8 Vpp at J19 through a BPF with about 5 dB attenuation, plus cable losses. – Use a high quality, low-phase noise generator for this input to ensure proper device evaluation Connect the input signal through an appropriate BPF at either J6 or J3 (Channel A or B, that is, 170 MHz) – Adjust the frequency of the generator to match the coherent frequency displayed in the TSW1400 GUI – Select the proper Display Channel on the TSW1400 GUI software that corresponds to the input connection – Adjust the signal generator amplitude output to achieve –1 dBFS on FFT plot. – Use a high quality, low-phase noise generator for this input to ensure proper device evaluation. Initiate a capture by pressing the Capture button on the TSW1400 GUI. ADS42xx EVM SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Optional Configurations www.ti.com 3 Optional Configurations 3.1 THS4509 Input Op-Amp Configuration The default analog input configuration is a transformer coupling through T1 and T2 for channel A, and T3 and T4 for channel B. The optional configuration for analog input is through an Operational-Amplifier (OPA), THS4509. The changes required to modify the transformer coupled input to the OPA-driven input are shown in Table 3. Table 3. Jumper Setting for Transformer-Coupled or OPA-Driven Input Jumpers or 0 Ω Transformer-Coupled Input (default) OPA-Driven Input R119 Install Do not install R123 Install Do not install R120 Do not install install R129 Do not install install R143 Install Do not install R141 Install Do not install R131 Do not install Install R132 Do not install Install R93 Install Do not install R94 Install Do not install R95 Do not install Install R96 Do not install Install R97 Install Do not install R98 Install Do not install R99 Do not install Install R114 Do not install Install SJP3 Shunt 2 - 3, default Shunt 1 - 2 SJP4 Shunt 2 - 3, default Shunt 1 - 2 J11 and J13 are the power supply for THS4509. An on-board layout option for an LPF or BPF is available between the amplifier and the ADC. By default, the filter is bypassed allowing the flexibility of designing according to the desired specifications. 3.2 On-Board CDCE72010 Clock The default clock input configuration is 1:4 transformer coupling through T6. The optional configuration is through clock driver CDCE72010. The changes required to modify the transformer coupled clock input to clock driver input are shown in Table 4. Table 4. Jumper Setting for Transformer-Coupled or CDCE72010 Input Jumper Transformer-Coupled (Default) CDCE72010 J14 shunt open JP20 Shunt 1 - 2 Shunt 1 - 2 JP21 Shunt 1 - 2 Shunt 1 - 2 J18 open open R121 0Ω DNI R122 DNI 0Ω SJP7 Short 1 - 2 Short 3 - 4 SJP6 Short 3 - 4 Short 5 - 6 SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated ADS42xx EVM 9 Optional Configurations www.ti.com The on-board layout is available for the option of VCXO and crystal BPF. The CDCE72010 comes with a default configuration See the CDCE72010 data sheet (SCAS858) for details about device default configuration. With a 10-MHz primary reference at J19 and a 983.04-MHz VCXO on-board, the CDC outputs a LVCMOS clock at U0P (pin 7) at 245.76 MHz. With a 491.52-MHz VCXO, the CDC outputs a LVCMOS clock at U0P at 122.88 MHz. The clock goes through an on-board crystal BPF (Y0) and is used as the input clock to the ADC through SJP6. 3.3 Parallel CMOS Output The default ADC output is configured as DDR LVDS output on the EVM. The layout provides an option of 1.8-V parallel CMOS output from the ADC. The changes required to modify from DDR LVDS output to parallel CMOS output are shown in Table 5. Table 5. Jumper and Component Setting for DDR LVDS Output and Parallel CMOS Output Jumper or Component DDR LVDS Output Parallel CMOS U12 (SN74AVC16T245) DNI Installed U13 (SN74AVC16T245) DNI Installed RN5 to RN8 Installed DNI RN9 to RN12 Installed DNI JP26 Open Shunt JP27 Open Shunt The CMOS output data is output from the EVM board at 40-pin connectors J1 (ch A) and J2 (ch B). 10 ADS42xx EVM SLAU333A – March 2011 – Revised June 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. 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These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help. 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To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada. Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement. 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Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER 【Important Notice for Users of EVMs for RF Products in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product, or Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. 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It is intended solely for use for preliminary feasibility evaluation in laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end product. Your Sole Responsibility and Risk. You acknowledge, represent and agree that: 1. 2. 3. 4. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees, affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes. 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