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ADS4249
SBAS534E – JULY 2011 – REVISED JANUARY 2016
ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
Maximum Sample Rate: 250 MSPS
Ultra-Low Power with Single 1.8-V Supply:
– 560-mW Total Power at 250 MSPS
High Dynamic Performance:
– 80-dBc SFDR at 170 MHz
– 71.7-dBFS SNR at 170 MHz
Crosstalk: > 90 dB at 185 MHz
Programmable Gain up to 6 dB for
SNR/SFDR Trade-off
DC Offset Correction
Output Interface Options:
– 1.8-V Parallel CMOS Interface
– Double Data Rate (DDR) LVDS with
Programmable Swing:
– Standard Swing: 350 mV
– Low Swing: 200 mV
Supports Low Input Clock Amplitude
Down to 200 mVPP
Package: 9-mm × 9-mm, 64-Pin VQFN Package
Wireless Communications Infrastructure
Software Defined Radios
Power Amplifier Linearization
3 Description
The ADS4249 is a member of the ADS42xx ultralowpower family of dual-channel, 12-bit and 14-bit
analog-to-digital converters (ADCs). Innovative
design techniques are used to achieve high dynamic
performance and consume extremely low power with
a 1.8-V supply. This topology makes the ADS4249
well-suited
for
multi-carrier,
wide-bandwidth
communications applications.
The ADS4249 has gain options that can be used to
improve SFDR performance at lower full-scale input
ranges. This device also includes a dc offset
correction loop that can be used to cancel the ADC
offset. Both DDR LVDS and parallel CMOS digital
output interfaces are available in a compact VQFN-64
PowerPAD™ package.
The device includes internal references and the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS4249 is
specified over the industrial temperature range
(–40°C to 85°C).
Device Information(1)
PART NUMBER
ADS4249
PACKAGE
VQFN (64)
BODY SIZE (NOM)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ADS4249 Block Diagram
ADS4249
INP_A
INM_A
LVDS
DA0P
DA0M
Sampling
Circuit
DA12P
DA12M
CLKP
CLK
Gen
CLKM
INP_B
INM_B
VCM
14-bit ADC
CLKOUTP
CLKOUTM
DB0P
DB0M
Sampling
Circuit
14-bit ADC
DB12P
DB12M
Reference
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS4249
SBAS534E – JULY 2011 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
ADS424x, ADS422x Family Comparison ............. 4
Pin Configuration and Functions ......................... 5
Specifications....................................................... 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
Absolute Maximum Ratings .................................... 10
ESD Ratings............................................................ 10
Recommended Operating Conditions..................... 11
Thermal Information ................................................ 11
Electrical Characteristics: ADS4249 (250 MSPS)... 12
Electrical Characteristics: General .......................... 13
Digital Characteristics ............................................. 14
LVDS and CMOS Modes Timing Requirements..... 15
LVDS Timings at Lower Sampling Frequencies ..... 16
CMOS Timings at Lower Sampling Frequencies .. 16
Serial Interface Timing Characteristics ................. 16
Reset Timing (Only when Serial Interface is
Used)........................................................................ 17
7.13 Typical Characteristics .......................................... 21
8
Detailed Description ............................................ 28
8.1 Overview ................................................................. 28
8.2
8.3
8.4
8.5
8.6
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
28
29
31
37
41
Application and Implementation ........................ 54
9.1 Application Information............................................ 54
9.2 Typical Application ................................................. 60
10 Power Supply Recommendations ..................... 62
10.1 Sharing DRVDD and AVDD Supplies ................... 62
10.2 Using DC-DC Power Supplies .............................. 62
10.3 Power Supply Bypassing ...................................... 62
11 Layout................................................................... 62
11.1 Layout Guidelines ................................................. 62
11.2 Layout Example .................................................... 63
12 Device and Documentation Support ................. 64
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
64
65
66
66
66
66
13 Mechanical, Packaging, and Orderable
Information ........................................................... 66
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2015) to Revision E
Page
•
Changed Pin Functions (LVDS Mode) table to comply with RGC Package (LVDS Mode) pin out diagram ......................... 5
•
Changed Pin Functions (CMOS Mode) table to comply with RGC Package (CMOS Mode) pin out diagram ..................... 8
•
Changed unit in last row of Clock Input, Input clock amplitude differential parameter to VPP in Recommended
Operating Conditions table ................................................................................................................................................... 11
•
Added text reference for Table 5 ......................................................................................................................................... 37
Changes from Revision C (July 2012) to Revision D
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (September 2011) to Revision C
Page
•
Changed footnote 1 in CMOS Timings at Lower Sampling Frequencies............................................................................. 16
•
Changed conditions for ADS4249 Typical Characteristics section ...................................................................................... 21
•
Changed register D5h bit names of bits D7, D4, D3, and D0 in Table 10 ........................................................................... 41
•
Changed register address D8 to DB in Table 10 ................................................................................................................. 41
•
Changed register address D5h to match change in Table 10.............................................................................................. 53
•
Changed register address DB to match change in Table 10 ............................................................................................... 53
2
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Changes from Revision A (September 2011) to Revision B
Page
•
Changed document status to Production Data....................................................................................................................... 1
•
Changed AC power-supply rejection ratio parameter test condition in ADS4249 Electrical Characteristics table .............. 12
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ADS4249
SBAS534E – JULY 2011 – REVISED JANUARY 2016
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5 ADS424x, ADS422x Family Comparison (1)
(1)
65 MSPS
125 MSPS
160 MSPS
250 MSPS
ADS422x
12-bit family
ADS4222
ADS4225
ADS4226
ADS4229
ADS424x
14-bit family
ADS4242
ADS4245
ADS4246
ADS4249
See Table 1 for details on migrating from the ADS62P49 family.
The ADS4249 is pin-compatible with the previous generation ADS62P49 data converter; this similar architecture
enables easy migration. However, there are some important differences between the two device generations,
summarized in Table 1.
Table 1. Migrating from the ADS62P49
ADS62P49
ADS4249
PINS
Pin 22 is NC (not connected)
Pin 22 is AVDD
Pins 38 and 58 are DRVDD
Pins 38 and 58 are NC (do not connect, must be floated)
Pins 39 and 59 are DRGND
Pins 39 and 59 are NC (do not connect, must be floated)
SUPPLY
AVDD is 3.3 V
AVDD is 1.8 V
DRVDD is 1.8 V
No change
INPUT COMMON-MODE VOLTAGE
VCM is 1.5 V
VCM is 0.95 V
SERIAL INTERFACE
Protocol: 8-bit register address and 8-bit register data
No change in protocol
New serial register map
EXTERNAL REFERENCE
Supported
4
Not supported
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6 Pin Configuration and Functions
49 DRGND
50 DA8M
51 DA8P
52 DA10M
53 DA10P
54 DA12M
55 DA12P
56 CLKOUTM
57 CLKOUTP
58 NC
59 NC
60 DB0M
61 DB0P
62 DB2M
63 DB2P
64 SDOUT
RGC Package (LVDS Mode)
64-Pin VQFN
Top View
DRVDD
1
48
DRVDD
DB4M
2
47
DA6P
DB4P
3
46
DA6M
DB6M
4
45
DA4P
DB6P
5
44
DA4M
DB8M
6
43
DA2P
DB8P
7
42
DA2M
DB10M
8
41
DA0P
DB10P
9
40
DA0M
DB12M 10
39
NC
DB12P 11
38
NC
RESET 12
37
CTRL3
SCLK 13
36
CTRL2
SDATA 14
35
CTRL1
SEN 15
34
AVDD
AVDD 16
33
AVDD
AGND 32
AGND 31
INM_A 30
INP_A 29
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
VCM 23
AVDD 22
AGND 21
INM_B 20
INP_B 19
AGND 18
AGND 17
Thermal Pad
(Connected to DRGND)
NOTE: The PowerPAD is connected to DRGND.
NC = do not connect; must float.
Pin Functions (LVDS Mode)
PIN
NAME
NO.
I/O
DESCRIPTION
17
18
21
AGND
24
27
I
Analog ground
I
Analog power supply
28
31
32
16
AVDD
22
33
34
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Pin Functions (LVDS Mode) (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
CLKM
26
I
Differential clock negative input
CLKP
25
I
Differential clock positive input
CLKOUTP
57
O
Differential output clock, true
CLKOUTM
56
O
Differential output clock, complement
CTRL1
35
CTRL2
36
I
Digital control input pins. Together, these pins control the various power-down
modes.
CTRL3
37
DA0M
40
DA0P
41
O
Channel A differential output data pair, D0 and D1 multiplexed
DA2M
42
DA2P
43
O
Channel A differential output data D2 and D3 multiplexed
DA4M
44
DA4P
45
O
Channel A differential output data D4 and D5 multiplexed
DA6M
46
DA6P
47
O
Channel A differential output data D6 and D7 multiplexed
DA8M
50
DA8P
51
O
Channel A differential output data D8 and D9 multiplexed
DA10M
52
DA10P
53
O
Channel A differential output data D10 and D11 multiplexed
DA12M
54
DA12P
55
O
Channel A differential output data D12 and D13 multiplexed
DB0M
60
DB0P
61
O
Channel B differential output data pair, D0 and D1 multiplexed
DB2M
62
DB2P
63
O
Channel B differential output data D2 and D3 multiplexed
DB4M
2
DB4P
3
O
Channel B differential output data D4 and D5 multiplexed
DB6M
4
DB6P
5
O
Channel B differential output data D6 and D7 multiplexed
DB8M
6
DB8P
7
O
Channel B differential output data D8 and D9 multiplexed
DB10M
8
DB10P
9
O
Channel B differential output data D10 and D11 multiplexed
DB12M
10
DB12P
11
O
Channel B differential output data D12 and D13 multiplexed
I
Output buffer ground
I
Output buffer supply
DRGND
DRVDD
49
PAD
1
48
INM_A
30
I
Differential analog negative input, channel A
INP_A
29
I
Differential analog positive input, channel A
INM_B
20
I
Differential analog negative input, channel B
INP_B
19
I
Differential analog positive input, channel B
6
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Pin Functions (LVDS Mode) (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
38
NC
39
58
—
Do not connect, must be floated
59
RESET
12
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this pin or by using the
software reset option; see the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high.
SCLK and SEN are used as parallel control pins in this mode. This pin has an
internal 150-kΩ pull-down resistor.
SCLK
13
I
This pin functions as a serial interface clock input when RESET is low. SCLK
controls the low-speed mode selection when RESET is tied high; see Table 7
for detailed information. This pin has an internal 150-kΩ pull-down resistor.
SDATA
14
I
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT
64
O
This pin functions as a serial interface register readout when the READOUT bit
is enabled. When READOUT = 0, this pin is put into a high-impedance state.
SEN
15
I
This pin functions as a serial interface enable input when RESET is low. SEN
controls the output interface and data format selection when RESET is tied
high; see Table 8 for detailed information. This pin has an internal 150-kΩ pullup resistor to AVDD.
VCM
23
O
This pin outputs the common-mode voltage (0.95 V) that can be used
externally to bias the analog input pins
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49 DRGND
50 DA8
51 DA9
52 DA10
53 DA11
54 DA12
55 DA13
56 UNUSED
57 CLKOUT
58 NC
59 NC
60 DB0
61 DB1
62 DB2
63 DB3
64 SDOUT
RGC Package (CMOS Mode)
64-Pin VQFN
Top View
DRVDD
1
48
DRVDD
DB4
2
47
DA7
DB5
3
46
DA6
DB6
4
45
DA5
DB7
5
44
DA4
DB8
6
43
DA3
DB9
7
42
DA2
DB10
8
41
DA1
DB11
9
40
DA0
DB12 10
39
NC
DB13 11
38
NC
RESET 12
37
CTRL3
SCLK 13
36
CTRL2
SDATA 14
35
CTRL1
SEN 15
34
AVDD
AVDD 16
33
AVDD
AGND 32
AGND 31
INM_A 30
INP_A 29
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
VCM 23
AVDD 22
AGND 21
INM_B 20
INP_B 19
AGND 18
AGND 17
Thermal Pad
(Connected to DRGND)
NOTE: The PowerPAD is connected to DRGND.
NC = do not connect; must float.
Pin Functions (CMOS Mode)
PIN
NAME
NO.
I/O
DESCRIPTION
17
18
21
AGND
24
27
I
Analog ground
I
Analog power supply
28
31
32
16
AVDD
22
33
34
CLKM
26
I
Differential clock negative input
CLKP
25
I
Differential clock positive input
8
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Pin Functions (CMOS Mode) (continued)
PIN
NAME
NO.
CLKOUT
57
CTRL1
35
CTRL2
36
CTRL3
37
DA0
40
DA1
41
DA2
42
DA3
43
DA4
44
DA5
45
DA6
46
DA7
47
DA8
50
DA9
51
DA10
52
DA11
53
DA12
54
DA13
55
DB0
60
DB1
61
DB2
62
DB3
63
DB4
2
DB5
3
DB6
4
DB7
5
DB8
6
DB9
7
DB10
8
DB11
9
DB12
10
DB13
11
DRGND
DRVDD
49
PAD
1
48
I/O
DESCRIPTION
O
CMOS output clock
I
Digital control input pins. Together, these pins control various power-down modes.
O
Channel A ADC output data bits, CMOS levels
O
Channel B ADC output data bits, CMOS levels
I
Output buffer ground
I
Output buffer supply
INM_A
30
I
Differential analog negative input, channel A
INP_A
29
I
Differential analog positive input, channel A
INM_B
20
I
Differential analog negative input, channel B
INP_B
19
I
Differential analog positive input, channel B
38
NC
39
58
—
Do not connect, must be floated
59
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Pin Functions (CMOS Mode) (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
RESET
12
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this pin or by using the
software reset option; see the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SDATA
and SEN are used as parallel control pins in this mode. This pin has an internal
150-kΩ pull-down resistor.
SCLK
13
I
This pin functions as a serial interface clock input when RESET is low. SCLK
controls the low-speed mode when RESET is tied high; see Table 7 for detailed
information. This pin has an internal 150-kΩ pull-down resistor.
SDATA
14
I
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT
64
O
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin is put into a high-impedance state.
This pin functions as a serial interface enable input when RESET is low. SEN
controls the output interface and data format selection when RESET is tied high;
see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up
resistor to AVDD.
SEN
15
I
UNUSED
56
—
This pin is not used in the CMOS interface
VCM
23
O
This pin outputs the common-mode voltage (0.95 V) that can be used externally to
bias the analog input pins
7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
Supply voltage, AVDD
–0.3
2.1
V
Supply voltage, DRVDD
–0.3
2.1
V
Voltage between AGND and DRGND
–0.3
0.3
V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
–2.4
2.4
V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
–2.4
2.4
V
INP_A, INM_A, INP_B, INM_B
–0.3
Minimum
(1.9, AVDD + 0.3)
CLKP, CLKM (2)
–0.3
AVDD + 0.3
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3
–0.3
3.9
Voltage applied to input pins
Operating free-air temperature, TA
–40
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
V
85
°C
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
When AVDD is turned off, switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|) is recommended.
This configuration prevents the ESD protection diodes at the clock input pins from turning on.
7.2 ESD Ratings
V(ESD)
(1)
10
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
MIN
NOM
MAX
UNIT
Analog supply voltage, AVDD
1.7
1.8
1.9
V
Digital supply voltage, DRVDD
1.7
1.8
1.9
V
SUPPLIES
ANALOG INPUTS
Differential input voltage
2
Input common-mode
VPP
VCM ± 0.05
V
Maximum analog input frequency with 2-VPP input amplitude (1)
400
MHz
Maximum analog input frequency with 1-VPP input amplitude (1)
600
MHz
CLOCK INPUT
Input clock sample rate
Low-speed mode enabled (2)
Low-speed mode disabled
(2)
(by default after reset)
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
1
80
80
250
0.2
1.5
LVPECL, ac-coupled
1.6
LVDS, ac-coupled
0.7
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
MSPS
VPP
1.5
Low-speed mode disabled
35%
50%
65%
Low-speed mode enabled
40%
50%
60%
DIGITAL OUTPUTS
Maximum external load capacitance from each output pin to DRGND, CLOAD
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD
Operating free-air temperature, TA
(1)
(2)
5
pF
100
Ω
–40
+85
°C
See the Theory of Operation section.
See the Serial Interface Configuration section for details on programming the low-speed mode.
7.4 Thermal Information
ADS4249
THERMAL METRIC (1)
RGC (VQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
23.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.9
°C/W
RθJB
Junction-to-board thermal resistance
4.3
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
4.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics: ADS4249 (250 MSPS)
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, LVDS
interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
SNR
Signal-to-noise ratio
14
fIN = 20 MHz
72.8
fIN = 70 MHz
72.5
fIN = 100 MHz
72.2
fIN = 170 MHz
67.5
fIN = 300 MHz
SINAD
Signal-to-noise and
distortion ratio
72
fIN = 70 MHz
71.6
fIN = 100 MHz
Total harmonic distortion
Second-order harmonic
distortion
68.7
80
fIN = 70 MHz
79
fIN = 100 MHz
82
71
76
fIN = 20 MHz
78
fIN = 70 MHz
77
fIN = 100 MHz
Third-order harmonic
distortion
79
69
75
fIN = 20 MHz
80
fIN = 70 MHz
79
fIN = 100 MHz
dBc
76
fIN = 300 MHz
81
71
76
fIN = 20 MHz
85
fIN = 70 MHz
87
fIN = 100 MHz
dBc
80
fIN = 300 MHz
96
fIN = 170 MHz
Worst spur
(other than second and
third harmonics)
dBc
80
fIN = 300 MHz
fIN = 170 MHz
HD3
dBFS
70.7
fIN = 20 MHz
fIN = 170 MHz
HD2
dBFS
71.6
66.5
fIN = 170 MHz
THD
Bits
69.4
fIN = 300 MHz
Spurious-free dynamic
range
UNIT
71.7
fIN = 20 MHz
fIN = 170 MHz
SFDR
MAX
71
fIN = 300 MHz
84
fIN = 20 MHz
92
fIN = 70 MHz
95
fIN = 100 MHz
dBc
80
94
fIN = 170 MHz
77
dBc
88
fIN = 300 MHz
85
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
95
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
82
Crosstalk
20-MHz full-scale signal on channel under observation;
170-MHz full-scale signal on other channel
95
dB
Input overload recovery
Recovery to within 1%
(of full-scale) for 6 dB overload with sine-wave input
1
Clock cycle
PSRR
AC power-supply rejection
ratio
For 50-mVPP signal on AVDD supply, up to 10 MHz
30
dB
ENOB
Effective number of bits
fIN = 170 MHz
DNL
Differential nonlinearity
fIN = 170 MHz
INL
Integrated nonlinearity
fIN = 170 MHz
IMD
12
Two-tone intermodulation
distortion
dBFS
11.45
–0.95
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LSBs
±0.5
1.7
LSBs
±2
±4.5
LSBs
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7.6 Electrical Characteristics: General
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1 dBFS differential analog input,
unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8 V, and DRVDD = 1.8 V.
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range
Differential input resistance (at 200 MHz)
VCM
2
VPP
0.75
kΩ
Differential input capacitance (at 200 MHz)
3.7
pF
Analog input bandwidth
(with 50-Ω source impedance, and 50-Ω termination)
550
MHz
Analog input common-mode current
(per input pin of each channel)
1.5
µA/MSPS
0.95 (1)
Common-mode output voltage
VCM output current capability
V
4
mA
DC ACCURACY
Offset error
–15
Temperature coefficient of offset error
2.5
15
0.003
EGREF
Gain error as a result of internal reference inaccuracy alone
EGCHAN
Gain error of channel alone
–2
Temperature coefficient of EGCHAN
mV/°C
2
±0.1
mV
1
%FS
%FS
Δ%/°C
0.002
POWER SUPPLY
IAVDD
Analog supply current
167
190
mA
IDRVDD
Output buffer supply current, LVDS interface, 350-mV swing with
100-Ω external termination, fIN = 2.5 MHz
144
160
mA
IDRVDD
Output buffer supply current, CMOS interface, no load capacitance,
fIN = 2.5 MHz (2)
Analog power
Digital power, LVDS interface, 350-mV swing with 100-Ω external
termination, fIN = 2.5 MHz
Digital power, CMOS interface, 8-pF external load capacitance
fIN = 2.5 MHz
mA
301
342
mW
259
288
mW
(2)
,
Global power-down
(1)
(2)
94
169
mW
25
mW
VCM changes to 0.87 V when serial register bits HIGH PERF MODE[7:2] are set.
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section).
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7.7 Digital Characteristics
At AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition where the digital
outputs do not switch, but are permanently at a valid logic level 0 or 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3) (1)
High-level input voltage
High-level input current
Low-level input current
1.3
All digital inputs support 1.8-V
and 3.3-V CMOS logic levels
Low-level input voltage
V
0.4
SDATA, SCLK (2)
VHIGH = 1.8 V
10
SEN (3)
VHIGH = 1.8 V
0
SDATA, SCLK
VLOW = 0 V
0
SEN
VLOW = 0 V
10
V
µA
µA
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage
DRVDD – 0.1
Low-level output voltage
DRVDD
V
0
0.1
V
DIGITAL OUTPUTS, LVDS INTERFACE
High-level output
differential voltage
VODH
With an external
100-Ω termination
270
350
430
mV
Low-level output
differential voltage
VODL
With an external
100-Ω termination
–430
–350
–270
mV
0.9
1.05
1.25
V
Output common-mode voltage VOCM
(1)
(2)
(3)
14
SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
SDATA, SCLK have internal 150-kΩ pull-down resistor.
SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8 V or 3.3 V CMOS
buffers.
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7.8 LVDS and CMOS Modes Timing Requirements
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD
= 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V. (1)
MIN
TYP
MAX
0.5
0.8
1.1
UNIT
GENERAL
tA
Aperture delay
Aperture delay matching between the two channels of the same device
Variation of aperture delay between two devices at the same temperature and
DRVDD supply
tJ
Aperture jitter
Wakeup time
ADC latency (2)
Time to valid data after coming out of STANDBY
mode
ns
±70
ps
±150
ps
140
fS rms
50
100
100
500
µs
Time to valid data after coming out of GLOBAL
power-down mode
Default latency after reset
16
Digital functions enabled (EN DIGITAL = 1)
24
Clock
cycles
DDR LVDS MODE (3)
tSU
Data setup time: data valid (4) to zero-crossing of CLKOUTP
tH
Data hold time: zero-crossing of CLKOUTP to data becoming invalid (4)
tPDI
Clock propagation delay: input clock rising edge cross-over to output clock rising
edge cross-over
0.6
0.88
ns
0.33
0.55
ns
5
6
7.5
ns
LVDS bit clock duty cycle of differential clock, (CLKOUTP-CLKOUTM)
48%
tRISE,
tFALL
Data rise time, data fall time: rise time measured from –100 mV to +100 mV,
fall time measured from +100 mV to –100 mV,
1 MSPS ≤ sampling frequency ≤ 250 MSPS
0.13
ns
tCLKRISE,
tCLKFALL
Output clock rise time, output clock fall time: rise time measured from –100 mV to
+100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling
frequency ≤ 250 MSPS
0.13
ns
PARALLEL CMOS MODE
Clock propagation delay: input clock rising edge cross-over to output clock rising
edge cross-over
tPDI
Output clock duty cycle of output clock (CLKOUT),
1 MSPS ≤ sampling frequency ≤ 200 MSPS
4.5
6.2
8.5
ns
50%
tRISE,
tFALL
Data rise time, data fall time: rise time measured from 20% to 80% of DRVDD,
fall time measured from 80% to 20% of DRVDD,
1 MSPS ≤ sampling frequency ≤ 200 MSPS
0.7
ns
tCLKRISE,
tCLKFALL
Output clock rise time output clock fall time: rise time measured from 20% to 80% of
DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling
frequency ≤ 200 MSPS
0.7
ns
(1)
(2)
(3)
(4)
Timing parameters are ensured by design and characterization and not tested in production.
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
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7.9 LVDS Timings at Lower Sampling Frequencies
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD
= 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
65
5.9
80
4.5
125
SETUP TIME (ns)
tPDI, CLOCK PROPAGATION
DELAY (ns)
HOLD TIME (ns)
MAX
MIN
TYP
6.6
0.35
5.2
0.35
2.3
2.9
160
1.5
185
200
230
MAX
MIN
TYP
MAX
0.6
5
6
7.5
0.6
5
6
7.5
0.35
0.6
5
6
7.5
2
0.33
0.55
5
6
7.5
1.3
1.6
0.33
0.55
5
6
7.5
1.1
1.4
0.33
0.55
5
6
7.5
0.76
1.06
0.33
0.55
5
6
7.5
7.10 CMOS Timings at Lower Sampling Frequencies
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD
= 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.
TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SAMPLING
FREQUENCY
(MSPS)
(1)
SETUP TIME (1) (ns)
MIN
TYP
65
6.1
80
4.7
125
tPDI, CLOCK PROPAGATION
DELAY (ns)
HOLD TIME (1) (ns)
MAX
MIN
TYP
6.7
6.7
5.2
5.3
2.7
3.1
160
1.6
185
200
MAX
MIN
TYP
MAX
7.5
4.5
6.2
8.5
6
4.5
6.2
8.5
3.1
3.6
4.5
6.2
8.5
2.1
2.3
2.8
4.5
6.2
8.5
1.1
1.6
1.9
2.4
4.5
6.2
8.5
1
1.4
1.7
2.2
4.5
6.2
8.5
In CMOS mode, setup time is measured from the beginning of data valid to 50% of the CLKOUT rising edge, whereas hold time is
measured from 50% of the CLKOUT rising edge to data becoming invalid. Data valid refers to a logic high of 1.26 V and a logic low of
0.54 V.
7.11 Serial Interface Timing Characteristics
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8 V, and DRVDD = 1.8 V, unless otherwise noted.
MIN
MAX
UNIT
20
MHz
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
16
> dc
TYP
fSCLK
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7.12 Reset Timing (Only when Serial Interface is Used)
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
unless otherwise noted.
MIN
t1
Power-on delay from AVDD and DRVDD power-up to active RESET pulse
t2
Reset pulse duration; active RESET signal pulse duration
t3
Register write delay from RESET disable to SEN active
TYP
MAX
1
UNIT
ms
10
ns
1
100
µs
ns
DAn_P
DBn_P
Logic 0
VODL = -350 mV
Logic 1
(1)
VODH = +350 mV
(1)
DAn_M
DBn_M
VOCM
GND
(1)
With external 100-Ω termination.
Figure 1. LVDS Output Voltage Levels
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
Output
Data
(1)
DAn,
DBn
tH
Dn
(1)
Dn = bits D0, D1, D2, and so forth, of channels A and B.
Figure 2. CMOS Interface Timing Diagram
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N+4
N+3
N+2
N + 18
N + 17
N + 16
N+1
Sample
N
Input
Signal
tA
Input
Clock
CLKP
CLKM
CLKOUTM
CLKOUTP
tPDI
tH
DDR
LVDS
16 Clock Cycles
tSU
(1)
(2)
Output Data
DAnP/M, DBnP/M
E
O
E
O
N - 16
E
O
N - 15
E
O
N - 14
E
O
O
E
N - 13
E
N - 12
O
N-1
O
E
N
O
E
O
E
E
N+1
tPDI
CLKOUT
tSU
Parallel
CMOS
16 Clock Cycles
Output Data
DAn, DBn
N - 16
N - 15
N - 14
tH
(1)
N - 13
N-1
N
N+1
(1)
ADC latency after reset. At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the
overall latency = ADC latency + 1.
(2)
E = even bits (D0, D2, D4, and so forth); O = odd bits (D1, D3, D5, and so forth).
Figure 3. Latency Timing Diagram
18
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CLKOUTM
CLKOUTP
DA0, DB0
D0
D1
D0
D1
DA2, DB2
D2
D3
D2
D3
DA4, DB4
D4
D5
D4
D5
DA6, DB6
D6
D7
D6
D7
DA8, DB8
D8
D9
D8
D9
DA10, DB10
D10
D11
D10
D11
DA12, DB12
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 4. LVDS Interface Timing Diagram
Register Address
SDATA
A7
A6
A5
A4
A3
Register Data
A2
A1
A0
D7
D6
D5
tSCLK
D4
tDSU
D3
D2
D1
D0
tDH
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 5. Serial Interface Timing
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Power Supply
AVDD, DRVDD
t1
RESET
t3
t2
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For
parallel interface operation, RESET must be permanently tied high.
Figure 6. Reset Timing Diagram
20
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7.13 Typical Characteristics
7.13.1 Typical Characteristics: ADS4249
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
0
0
SFDR = 85.3 dBc
SNR = 73 dBFS
SINAD = 72.6 dBFS
THD = 81.9 dBc
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
SFDR = 80.2 dBc
SNR = 71.7 dBFS
SINAD = 71 dBFS
THD = 78.8 dBc
0
25
50
75
Frequency (MHz)
100
−120
125
0
Figure 7. Input Signal (10 MHz)
100
125
0
SFDR = 77.9 dBc
SNR = 69.5 dBFS
SINAD = 69 dBFS
THD = 77.2 dBc
−20
Each Tone at
−7 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
Two−Tone IMD = 81 dBFS
SFDR = 93.8 dBFS
−20
−40
Amplitude (dB)
−40
Amplitude (dB)
50
75
Frequency (MHz)
Figure 8. Input Signal (150 MHz)
0
−60
−60
−80
−80
−100
−100
−120
25
0
25
50
75
Frequency (MHz)
100
−120
125
0
Figure 9. Input Signal (300 MHz)
0
50
75
Frequency (MHz)
100
125
Figure 10. Two-Tone Input Signal
86
Each Tone at
−36 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
Two−Tone IMD = 105 dBFS
SFDR = 104.2 dBFS
−20
25
84
82
80
SFDR (dBc)
Amplitude (dB)
−40
−60
78
76
−80
74
−100
72
−120
0
25
50
75
Frequency (MHz)
100
125
70
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
Figure 11. Two-Tone Input Signal
Figure 12. SFDR vs Input Frequency
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Typical Characteristics: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
74
88
73
86
72
84
71
82
SFDR (dBc)
SNR (dBFS)
70
69
68
80
78
76
67
74
66
65
72
64
70
0
50
100
150
200
250
300
350
400
70 MHz
150 MHz
0
0.5
1
Input Frequency (MHz)
Figure 13. SNR vs Input Frequency
1.5
2
2.5 3 3.5 4
Digital Gain (dB)
220 MHz
400 MHz
4.5
5
5.5
6
Figure 14. SFDR vs Gain and Input Frequency
73
75.5
110
Input Frequency = 40 MHz
72
75
100
71
90
74.5
80
74
70
73.5
60
73
50
72.5
69
68
67
SNR (dBFS)
SFDR (dBc,dBFS)
SINAD (dBFS)
70
66
65
70 MHz
150 MHz
0
0.5
1
1.5
220 MHz
400 MHz
2
2.5 3 3.5 4
Digital Gain (dB)
4.5
5
5.5
30
−50
6
Figure 15. SINAD vs Gain and Input Frequency
71.5
73.5
73.5
80
73
70
72.5
60
72
50
71.5
SFDR (dBc)
74
90
SNR (dBFS)
SFDR (dBc,dBFS)
0
Input Frequency = 40 MHz
100
82
73
81
72.5
80
72
79
71.5
71
40
−40
−30
−20
Amplitude (dBFS)
−10
71
78
SFDR (dBc)
SFDR (dBFS)
SNR
30
70.5
0
70
Figure 17. Performance vs Input Amplitude
22
−10
83
Input Frequency = 150 MHz
20
−50
−30
−20
Amplitude (dBFS)
Figure 16. Performance vs Input Amplitude
74.5
110
−40
72
SNR (dBFS)
63
SFDR (dBc)
SFDR (dBFS)
SNR
40
64
SFDR
SNR
77
0.8
0.85
0.9
0.95
Input CommonMode Voltage (V)
1
70.5
Figure 18. Performance vs Input Common-Mode Voltage
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Typical Characteristics: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
73
89
83
72.5
87
82
72
81
71.5
80
71
79
70.5
78
70
77
69.5
73
69
71
−40
84
Input Frequency = 150 MHz
Input Frequency = 40 MHz
85
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
83
81
79
77
75
SFDR
SNR
1
Figure 19. Performance vs Input Common-Mode Voltage
−15
10
35
Temperature (°C)
72.5
82
Input Frequency = 40 MHz
Input Frequency = 150 MHz
73.5
81
72
73
80
71.5
79
71
78
70.5
SFDR (dBc)
SNR (dBFS)
85
Figure 20. SFDR vs Temperature and AVDD Supply
74
72.5
72
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
71.5
71
−40
−15
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
10
35
Temperature (°C)
70
77
SFDR
SNR
60
76
1.7
85
Figure 21. SNR vs Temperature and AVDD Supply
1.75
1.8
1.85
1.9
DRVDD Supply (V)
1.95
2
69.5
Figure 22. Performance vs DRVDD Supply Voltage
74
90
72
83
Input Frequency = 40 MHz
Input Frequency = 150 MHz
73.5
82
71.5
86
73
81
71
84
72.5
80
70.5
82
72
79
70
80
71.5
78
69.5
78
71
77
69
70.5
76
76
SFDR (dBc)
88
SNR (dBFS)
SFDR (dBc)
60
68.5
SFDR
SNR
74
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
SNR (dBFS)
0.85
0.9
0.95
Input CommonMode Voltage (V)
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
1.8
2
SNR (dBFS)
76
0.8
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
SFDR
SNR
70
2.2
75
0.2
Differential Clock Amplitude (VPP)
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
68
2.2
Differential Clock Amplitudes (VPP)
Figure 23. Performance vs Input Clock Amplitude
Figure 24. Performance vs Input Clock Amplitude
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Typical Characteristics: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
0
76
82
Input Frequency = 40 MHz
50 mVPP Signal Superimposed on VCM
Input Frequency = 10 MHz
80
75.5
78
75
76
74.5
74
74
72
73.5
70
73
68
72.5
66
72
−5
−10
−20
−25
CMRR (dB)
SNR (dBFS)
THD (dBc)
−15
−30
−35
−40
−45
64
62
SNR
THD
25
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
70
75
−50
71.5
−55
71
−60
Figure 25. Performance vs Input Clock Duty Cycle
−10
−15
-60
fIN - fCM = 30 MHz
fCM = 10 MHz
Input Frequency = 10 MHz
50 mVPP Signal Superimposed on AVDD Supply
−5
−20
PSRR (dB)
Amplitude (dB)
-40
300
0
fIN = 40 MHz
fCM = 10 MHz, 50 mVPP
SFDR = 81.7 dBc
Amplitude (fIN) = -1 dBFS
Amplitude (fCM) = -108.2 dBFS
Amplitude (fIN + fCM) = -93.5 dBFS
Amplitude (fIN - fCM) = 93.9 dBFS
-20
50
100
150
200
250
Frequency of Input Common−Mode Signal (MHz)
Figure 26. CMRR vs Test Signal Frequency
0
fIN = 40 MHz
0
−25
−30
fIN + fCM = 50 MHz
-80
−35
−40
-100
−45
−50
-120
0
25
75
50
125
100
0
50
Frequency (MHz)
Figure 27. CMRR Spectrum
350
fIN = 10 MHz
fPSRR = 2 MHz, 50 mVPP
Amplitude (fIN) = -1 dBFS
Amplitude (fPSRR) = -95.1 dBFS
Amplitude (fIN + fPSRR) = -96.4 dBFS
Amplitude (fIN - fPSRR) = -96.8 dBFS
-20
AVDD = 1.8 V
Input Frequency = 2.5 MHz
310
270
Analog Power (mW)
Amplitude (dB)
-40
-60
fPSRR
fIN - fPSRR
300
Figure 28. PSRR vs Test Signal Frequency
0
fIN
100
150
200
250
Frequency of Signal on Supply (MHz)
fIN + fPSRR
230
190
-80
150
-100
110
70
-120
0
5
10
15
20
25
30
35
40
45
50
Frequency (MHz)
Figure 29. Zoomed View of PSRR Spectrum
24
0
25
50
75 100 125 150 175
Sampling Speed (MSPS)
200
225
250
Figure 30. Analog Power vs Sampling Frequency
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Typical Characteristics: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
260
320
Fin = 2.5 MHz
240
280
260
180
DRVDD Power (mW)
DRVDD Power (mW)
200
160
140
120
100
80
240
220
200
180
160
140
60
40
120
LVDS, 350mV Swing
LVDS, 200mV Swing
CMOS
20
0
Default
EN Digital = 1
EN Digital = 1, Offset Correction Enabled
300
220
0
25
50
75 100 125 150 175
Sampling Speed (MSPS)
200
225
100
250
G001
Figure 31. Digital Power LVDS CMOS
80
0
25
50
75 100 125 150 175
Sampling Speed (MSPS)
200
225
250
G001
Figure 32. Digital Power in Various Modes
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7.13.2 Typical Characteristics: Contour
All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode disabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
250
240
82
Sampling Frequency (MSPS)
220
82
82
82
79
200
75
82
79
180
82
160
140
75
82
85
79
85
88
120
88
100
71
82
82
85
79
88
80
91
60
0
75
85
50
100
150
200
250
300
350
400
Input Frequency (MHz)
76
74
72
70
78
80
82
84
86
88
90
SFDR (dBc)
Figure 33. Spurious-Free Dynamic Range (0-dB Gain)
250
240
82
85
79
76
76
85
220
Sampling Frequency (MSPS)
79
82
200
82
85
180
79
82
160
85
85
85
140
82
79
87
120
87
89
100
80
91
87
89
85
79
82
60
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
74
76
78
80
82
84
86
88
90
SFDR (dBc)
Figure 34. Spurious-Free Dynamic Range (6-dB Gain)
26
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Typical Characteristics: Contour (continued)
All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode disabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
250
240
71
71.5
Sampling Frequency (MSPS)
220
72
72.5
69
70
71.5
200
71
180
68
160
72
72.5
73
69
70
71.5
140
71
120
100
80
73.5
72.5
72
73
70
71
60
0
71.5
50
100
150
200
69
250
300
68
350
400
Input Frequency (MHz)
69
68
70
71
72
73
SNR (dBFS)
Figure 35. Signal-to-Noise Ratio (0-dB Gain)
250
240
66.5
66.8
Sampling Frequency (MSPS)
220
65.2
66.5
65.7
67.1
66.2
200
65.2
66.5
64.7
66.8
180
64.2
64.7
160
66.2
66.5
66.8
140
65.2
65.7
67.1
120
100
67.4
80
67.1
66.8
65.7
66.2
66.5
65.2
60
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
64
64.5
65
65.5
66
66.5
67
SNR (dBFS)
Figure 36. Signal-to-Noise Ratio (6-dB Gain)
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8 Detailed Description
8.1 Overview
The ADS4249 belongs to TI's ultralow power family of dual-channel, 14-bit analog-to-digital converters (ADCs).
High performance is maintained when reducing power for power sensitive applications. In addition to its low
power and high performance, the ADS4249 has a number of digital features and operating modes to enable
design flexibility.
8.2 Functional Block Diagram
AVDD
AGND
DRVDD
DRGND
LVDS Interface
DA0P
DA0M
DA2P
DA2M
DA4P
INP_A
Sampling
Circuit
INM_A
Digital and
DDR
Serializer
14-Bit
ADC
DA4M
DA6P
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKP
Output
Clock Buffer
CLOCKGEN
CLKM
CLKOUTP
CLKOUTM
DB0P
DB0M
DB2P
DB2M
DB4P
INP_B
Sampling
Circuit
INM_B
Digital and
DDR
Serializer
14-Bit
ADC
DB4M
DB6P
DB6M
DB8P
DB8M
DB10P
DB10M
DB12P
DB12M
28
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CTRL3
CTRL1
SDOUT
CTRL2
SEN
SCLK
RESET
Device
SDATA
Control
Interface
Reference
VCM
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8.3 Feature Description
8.3.1 Digital Functions
The device has several useful digital functions (such as test patterns, gain, and offset correction). These
functions require extra clock cycles for operation and increase the overall latency and power of the device. These
digital functions are disabled by default after reset and the raw ADC output is routed to the output data pins with
a latency of 16 clock cycles. Figure 37 shows more details of the processing after the ADC. In order to use any
of the digital functions, the EN DIGITAL bit must be set to '1'. After this, the respective register bits must be
programmed as described in the following sections and in the Serial Register Map section.
Output
Interface
14-Bit
ADC
14-Bit
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
EN DIGITAL Bit
Figure 37. Digital Processing Block
8.3.2 Gain for SFDR, SNR Trade-Off
The ADS4249 includes gain settings that can be used to get improved SFDR performance (compared to no
gain). The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally, as shown in Table 2.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the
default gain after reset is 0 dB.
Table 2. Full-Scale Range Across Gains
GAIN (dB)
TYPE
0
Default after reset
FULL-SCALE (VPP)
2
1
Fine, programmable
1.78
2
Fine, programmable
1.59
3
Fine, programmable
1.42
4
Fine, programmable
1.26
5
Fine, programmable
1.12
6
Fine, programmable
1
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8.3.3 Offset Correction
The ADS4249 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The
correction can be enabled using the ENABLE OFFSET CORR serial register bit. When enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 3.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. When frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
Table 3. Time Constant of Offset Correction Algorithm
(1)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
TIME CONSTANT, TCCLK × 1/fS (ms) (1)
0000
1M
4
0001
2M
8
0010
4M
16
0011
8M
32
0100
16 M
64
0101
32 M
128
0110
64 M
256
0111
128 M
512
1000
256 M
1024
1001
512 M
2048
1010
1G
4096
1011
2G
8192
1100
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
Sampling frequency, fS = 250 MSPS.
8.3.4 Power-Down
The ADS4249 has two power-down modes: global power-down and channel standby. These modes can be set
using either the serial register bits or using the control pins CTRL1 to CTRL3 (as shown in Table 4).
Table 4. Power-Down Settings
30
CTRL1
CTRL2
CTRL3
DESCRIPTION
Low
Low
Low
Default
Low
Low
High
Not available
Low
High
Low
Not available
Low
High
High
Not available
High
Low
Low
Global power-down
High
Low
High
Channel A powered down, channel B is active
High
High
Low
Not available
High
High
High
MUX mode of operation, channel A and B data is
multiplexed and output on DB[13:0] pins
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8.3.4.1 Global Power-Down
In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting
in reduced total power dissipation of approximately 20 mW when the CTRL pins are used and 3mW when the
PDN GLOBAL serial register bit is used. The output buffers are in high-impedance state. The wake-up time from
global power-down to data becoming valid in normal mode is typically 100 µs.
8.3.4.2 Channel Standby
In this mode, each ADC channel can be powered down. The internal references are active, resulting in a quick
wake-up time of 50 µs. The total power dissipation in standby is approximately 240 mW at 250 MSPS.
8.3.4.3 Input Clock Stop
In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls
below 1 MSPS. The power dissipation is approximately 160 mW.
8.3.5 Output Data Format
Two output data formats are supported: twos complement and offset binary. The format can be selected using
the DATA FORMAT serial interface register bit or by controlling the DFS pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 3FFFh for the ADS4249 in offset binary output format; the output code is 1FFFh for
the ADS4249 in twos complement output format. For a negative input overdrive, the output code is 0000h in
offset binary output format and 2000h for the ADS4249 in twos complement output format.
8.4 Device Functional Modes
8.4.1 Output Interface Modes
The ADS4249 provides 14-bit digital data for each channel and an output clock synchronized with the data.
8.4.1.1 Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit or by setting the proper voltage on the SEN pin in parallel
configuration mode.
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Device Functional Modes (continued)
8.4.1.2 DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 38.
Pins
CLKOUTP
CLKOUTM
DB0_P
LVDS Buffers
DB0_M
DB2_P
DB2_M
DB4_P
14-Bit ADC Data,
Channel B
DB4_M
DB6_P
DB6_M
DB8_P
DB8_M
DB10_P
DB10_M
DB12_P
DB12_M
Output
Clock
Data Bits
D0, D1
Data Bits
D2, D3
Data Bits
D4, D5
Data Bits
D6, D7
Data Bits
D8, D9
Data Bits
D10, D11
Data Bits
D12, D13
Figure 38. LVDS Interface
32
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Device Functional Modes (continued)
Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3,
D5, and so forth) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be
used to capture all the data bits, as shown in Figure 39.
CLKOUTM
CLKOUTP
DA0, DB0
D0
D1
D0
D1
DA2, DB2
D2
D3
D2
D3
DA4, DB4
D4
D5
D4
D5
DA6, DB6
D6
D7
D6
D7
DA8, DB8
D8
D9
D8
D9
DA10, DB10
D10
D11
D10
D11
DA12, DB12
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 39. DDR LVDS Interface Timing
8.4.1.3 LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 40. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100-Ω termination.
VDIFF
High
Low
OUTP
External
100-W Load
OUTM
VOCM
ROUT
VDIFF
Low
High
NOTE: Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing.
Figure 40. LVDS Buffer Equivalent Circuit
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Device Functional Modes (continued)
The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as
shown in Figure 41. This mode can be used when the output LVDS signal is routed to two separate receiver
chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS
CLKOUT STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. Absorbing reflections
from the receiver end helps improve signal integrity.
Receiver Chip # 1
(for example, GC5330)
DAnP/M
CLKIN1
100 W
CLKIN2
100 W
CLKOUTP
CLKOUTM
DBnP/M
Receiver Chip # 2
Device
Make LVDS CLKOUT STRENGTH = 1
Figure 41. LVDS Buffer Differential Termination
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Device Functional Modes (continued)
8.4.1.4 Parallel CMOS Interface
In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as
Figure 42 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver.
Minimizing the load capacitance of the data and clock output pins is recommended by using short traces to the
receiver. Furthermore, match the output data and clock traces to minimize the skew between them.
DB0
¼
¼
DB1
14-Bit ADC Data,
Channel B
DB12
DB13
SDOUT
CLKOUT
DA0
¼
¼
DA1
14-Bit ADC Data,
Channel A
DA12
DA13
Figure 42. CMOS Outputs
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Device Functional Modes (continued)
8.4.1.5 CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal. This relationship is shown by Equation 1:
Digital current as a result of CMOS output switching = CL × DRVDD × (N × FAVG)
where
•
•
CL = load capacitance,
N × FAVG = average number of output bits switching.
(1)
8.4.1.6 Multiplexed Mode of Operation
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[11:0] pins), as
shown in Figure 43. The channel A output pins (DA[11:0]) are in 3-state. Because the output data rate on the DB
bus is effectively doubled, this mode is recommended only for low sampling frequencies (less than 80 MSPS).
This mode can be enabled using the POWER-DOWN MODE register bits or using the CTRL[3:1] parallel pins.
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
Output
Data
DBn
(1)
Channel A
DAn
(2)
tH
Channel B
DBn
(2)
(1)
In multiplexed mode, both channels outputs come on the channel B output pins.
(2)
Dn = bits D0, D1, D2, and so forth.
Channel A
DAn
(2)
Figure 43. Multiplexed Mode Timing Diagram
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8.5 Programming
The ADS4249 can be configured independently using either parallel interface control or serial interface
programming. Table 5 lists the device high-performance modes.
Table 5. High-Performance Modes (1) (2)
PARAMETER
DESCRIPTION
High-performance mode
Set the HIGH PERF MODE[2:1] register bit to obtain best performance across sample clock and input signal
frequencies.
Register address = 03h, data = 03h
High-frequency mode
Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input signal frequencies
greater than 200 MHz.
Register address = 4Ah, data = 01h
Register address = 58h, data = 01h
High-speed mode
Set the HIGH PERF MODE[8:3] bits to obtain best performance across input signal frequencies for sampling
rates greater than 160 MSPS.
Note that this mode changes VCM to 0.87 V from its default value of 0.95 V.
Register address = 2h, data = 40h
Register address = D5h, data = 18h
Register address = D7h, data = 0Ch
Register address = DBh, data = 20h
(1)
(2)
Using these modes to obtain best performance is recommended.
See the Serial Interface Configuration section for details on register programming.
8.5.1 Parallel Configuration Only
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK,
CTRL1, CTRL2, and CTRL3 pins to directly control certain modes of the ADC. The device can be easily
configured by connecting the parallel pins to the correct voltage levels (as described in Table 6 to Table 9).
There is no need to apply a reset and SDATA can be connected to ground.
In this mode, SEN and SCLK function as parallel interface control pins. Some frequently-used functions can be
controlled using these pins. Table 6 describes the modes controlled by the parallel pins.
Table 6. Parallel Pin Definition
PIN
CONTROL MODE
SCLK
Low-speed mode selection
SEN
Output data format and output interface selection
CTRL1
CTRL2
Together, these pins control the power-down modes
CTRL3
8.5.2 Serial Interface Configuration Only
To enable this mode, the serial registers must first be reset to the default values and the RESET pin must be
kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the
internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by
setting the RESET bit high. The Serial Register Map section describes the register programming and the register
reset process in more detail.
8.5.3 Using Both Serial Interface and Parallel Controls
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To enable this option, keep RESET low. The parallel interface control
pins CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to the
voltage settings on these pins (see Table 9). SEN, SDATA, and SCLK function as serial interface digital pins and
are used to access the internal registers of the ADC. The registers must first be reset to the default values either
by applying a pulse on the RESET pin or by setting the RESET bit to '1'. After reset, the RESET pin must be kept
low. The Serial Register Map section describes register programming and the register reset process in more
detail.
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8.5.4 Parallel Configuration Details
The functions controlled by each parallel pin are described in Table 7, Table 8, and Table 9. A simple way of
configuring the parallel pins is shown in Figure 44.
Table 7. SCLK Control Pin
VOLTAGE APPLIED ON SCLK
DESCRIPTION
Low
Low-speed mode is disabled
High
Low-speed mode is enabled
Table 8. SEN Control Pin
VOLTAGE APPLIED ON SEN
0
(50 mV / 0 mV)
DESCRIPTION
Twos complement and parallel CMOS output
(3/8) AVDD
(±50 mV)
Offset binary and parallel CMOS output
(5/8) 2AVDD
(±5 0mV)
Offset binary and DDR LVDS output
AVDD
(0 mV / –50 mV)
Twos complement and DDR LVDS output
Table 9. CTRL1, CTRL2, and CTRL3 Pins
CTRL1
CTRL2
CTRL3
Low
Low
Low
Normal operation
DESCRIPTION
Low
Low
High
Not available
Low
High
Low
Not available
Low
High
High
Not available
High
Low
Low
Global power-down
High
Low
High
Channel A standby, channel B is active
High
High
Low
Not available
High
High
High
MUX mode of operation, channel A and B data are
multiplexed and output on the DB[13:0] pins. See the
Multiplexed Mode of Operation section for further
details.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
(3/8) AVDD
3R
(3/8) AVDD
To Parallel Pin
Figure 44. Simple Scheme to Configure the Parallel Pins
38
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8.5.5 Serial Interface Details
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight
bits are the register data. The interface can work with SCLK frequencies from 20 MHz down to very low speeds
(of a few hertz) and also with non-50% SCLK duty cycle.
8.5.5.1 Register Initialization
After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished
in one of two ways:
1. Through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), see
Figure 5 and the Serial Interface Timing Characteristics table; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes
the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET
pin is kept low. See the Reset Timing (Only when Serial Interface is Used) section and Figure 6 for reset
timing.
8.5.5.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC. To use readback mode, follow this procedure:
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
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The serial register readout works with both CMOS and LVDS interfaces on pin 64. Figure 45 shows the serial
readout timing diagram.
When READOUT is disabled, the SDOUT pin is in high-impedance state.
Register Address A[7:0] = 00h
SDATA
0
0
0
0
0
0
Register Data D[7:0] = 01h
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
The SDOUT pin is in high-impedance state.
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
SCLK
SEN
SDOUT
The SDOUT pin functions as serial readout (READOUT = 1).
b) Read contents of Register 45h. This register has been initialized with 04h (device is put into global power-down mode.)
Figure 45. Serial Readout Timing Diagram
40
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8.6 Register Maps
8.6.1 Serial Register Map
Table 10 summarizes the functions supported by the serial interface.
Table 10. Serial Interface Register Map (1)
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00
0
0
0
0
0
0
RESET
READOUT
0
0
0
HIGH PERF
MODE 2
HIGH PERF
MODE 1
01
03
LVDS SWING
0
0
0
0
25
29
0
0
CH A GAIN
2B
0
0
DATA FORMAT
CH B GAIN
3D
0
0
3F
0
0
CH A TEST PATTERNS
0
0
ENABLE
OFFSET
CORR
0
0
0
0
CH B TEST PATTERNS
0
0
0
CUSTOM PATTERN D[13:8]
40
(1)
0
CUSTOM PATTERN D[7:0]
41
LVDS CMOS
CMOS CLKOUT STRENGTH
0
0
42
CLKOUT FALL POSN
CLKOUT RISE POSN
EN DIGITAL
0
0
DIS OBUF
0
45
STBY
LVDS
CLKOUT
STRENGTH
4A
0
0
0
0
0
0
0
HIGH FREQ
MODE CH B
58
0
0
0
0
0
0
0
HIGH FREQ
MODE CH A
LVDS DATA
STRENGTH
0
0
PDN GLOBAL
0
0
BF
CH A OFFSET PEDESTAL
0
0
C1
CH B OFFSET PEDESTAL
0
0
0
0
0
CF
FREEZE
OFFSET
CORR
0
EF
0
0
0
EN LOW
SPEED MODE
F1
0
0
0
OFFSET CORR TIME CONSTANT
0
0
0
0
0
0
EN LVDS SWING
0
0
0
F2
0
0
0
0
LOW SPEED
MODE CH A
2
0
HIGH PERF
MODE3
0
0
0
0
0
0
D5
0
0
0
HIGH PERF
MODE4
HIGH PERF
MODE5
0
0
0
D7
0
0
0
0
HIGH PERF
MODE6
HIGH PERF
MODE7
0
0
DB
0
0
HIGH PERF
MODE8
0
0
0
0
LOW SPEED
MODE CH B
Multiple functions in a register can be programmed in a single write operation. All registers default to '0' after reset.
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8.6.2 Description of Serial Registers
8.6.2.1 Register Address 00h (Default = 00h)
Figure 46. Register Address 00h (Default = 00h)
7
0
6
0
5
0
4
0
Bits[7:2]
Always write '0'
Bit 1
RESET: Software reset applied
3
0
2
0
1
RESET
0
READOUT
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit 0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS logic
levels running from the DRVDD supply. See the Serial Register Readout section.
8.6.2.2 Register Address 01h (Default = 00h)
Figure 47. Register Address 01h (Default = 00h)
7
6
5
4
3
2
LVDS SWING
Bits[7:2]
1
0
0
0
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming
swing.
000000 = Default LVDS swing; ±350 mV with external 100-Ω termination
011011 = LVDS swing ±410 mV
110010 = LVDS swing ±465 mV
010100 = LVDS swing ±570 mV
111110 = LVDS swing ±200 mV
001111 = LVDS swing ±125 mV
Bits[1:0]
Always write '0'
8.6.2.3 Register Address 01h (Default = 00h)
Figure 48. Register Address 03h (Default = 00h)
7
6
5
4
3
2
0
0
0
0
0
0
Bits[7:2]
Always write '0'
Bits[1:0]
HIGH PERF MODE[2:1]: High-performance mode
00
01
10
11
42
=
=
=
=
1
HIGH PERF
MODE 2
0
HIGH PERF
MODE 1
Default performance
Do not use
Do not use
Obtain best performance across sample clock and input signal frequencies
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8.6.2.4 Register Address 25h (Default = 00h)
Figure 49. Register Address 25h (Default = 00h)
7
6
5
4
3
0
CH A GAIN
Bits[7:4]
2
1
CH A TEST PATTERNS
0
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5-dB steps for channel A.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default after reset)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
Bit 3
Always write '0'
Bits[2:0]
CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
8.6.2.5 Register Address 29h (Default = 00h)
Figure 50. Register Address 29h (Default = 00h)
7
0
6
0
5
0
4
3
DATA FORMAT
Bits[7:5]
Always write '0'
Bits[4:3]
DATA FORMAT: Data format selection
00
01
10
11
Bits[2:0]
=
=
=
=
2
0
1
0
0
0
Twos complement
Twos complement
Twos complement
Offset binary
Always write '0'
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8.6.2.6 Register Address 2Bh (Default = 00h)
Figure 51. Register Address 2Bh (Default = 00h)
7
6
5
4
CH B GAIN
Bits[7:4]
3
0
2
1
CH B TEST PATTERNS
0
CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5-dB steps for channel B.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default after reset)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
Bit 3
Always write '0'
Bits[2:0]
CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
44
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8.6.2.7 Register Address 3Dh (Default = 00h)
Figure 52. Register Address 3Dh (Default = 00h)
7
0
6
0
5
ENABLE OFFSET CORR
4
0
3
0
Bits[7:6]
Always write '0'
Bit 5
ENABLE OFFSET CORR: Offset correction setting
2
0
1
0
0
0
This bit enables the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
8.6.2.8 Register Address 3Fh (Default = 00h)
Figure 53. Register Address 3Fh (Default = 00h)
7
6
0
0
5
CUSTOM
PATTERN D13
4
CUSTOM
PATTERN D12
Bits[7:6]
Always write '0'
Bits[5:0]
CUSTOM PATTERN D[13:8]
3
CUSTOM
PATTERN D11
2
CUSTOM
PATTERN D10
1
CUSTOM
PATTERN D9
0
CUSTOM
PATTERN D8
These are the six upper bits of the custom pattern available at the output instead of ADC data.
The ADS4249 custom pattern is 14-bit.
8.6.2.9 Register Address 40h (Default = 00h)
Figure 54. Register Address 40h (Default = 00h)
7
CUSTOM
PATTERN D7
Bits[7:0]
6
CUSTOM
PATTERN D6
5
CUSTOM
PATTERN D5
4
CUSTOM
PATTERN D4
3
CUSTOM
PATTERN D3
2
CUSTOM
PATTERN D2
1
CUSTOM
PATTERN D1
0
CUSTOM
PATTERN D0
CUSTOM PATTERN D[7:0]
These are the eight lower bits of the custom pattern available at the output instead of ADC data.
The ADS4249 custom pattern is 14-bit; use the CUSTOM PATTERN D[13:0] register bits.
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8.6.2.10 Register Address 41h (Default = 00h)
Figure 55. Register Address 41h (Default = 00h)
7
6
LVDS CMOS
Bits[7:6]
5
4
CMOS CLKOUT STRENGTH
3
0
2
0
1
0
DIS OBUF
LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = DDR LVDS interface
10 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits[3:2]
Always write '0'
Bits[1:0]
DIS OBUF
These bits power down data and clock output buffers for both the CMOS and LVDS output
interface. When powered down, the output buffers are in 3-state.
00 = Default
01 = Power-down data output buffers for channel B
10 = Power-down data output buffers for channel A
11 = Power-down data output buffers for both channels as well as the clock output buffer
46
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8.6.2.11 Register Address 42h (Default = 00h)
Figure 56. Register Address 42h (Default = 00h)
7
6
CLKOUT FALL POSN
Bits[7:6]
2
0
1
0
0
0
of the output clock advances by 450 ps
of the output clock advances by 150 ps
of the output clock is delayed by 550 ps
of the output clock is delayed by 150 ps
of the output clock advances by 100 ps
CLKOUT RISE POSN
In LVDS mode:
00 = Default
01 = The rising edge
10 = The rising edge
11 = The rising edge
In CMOS mode:
00 = Default
01 = The rising edge
10 = Do not use
11 = The rising edge
Bit 3
3
EN DIGITAL
CLKOUT FALL POSN
In LVDS mode:
00 = Default
01 = The falling edge
10 = The falling edge
11 = The falling edge
In CMOS mode:
00 = Default
01 = The falling edge
10 = Do not use
11 = The falling edge
Bits[5:6]
5
4
CLKOUT RISE POSN
of the output clock advances by 450 ps
of the output clock advances by 150 ps
of the output clock is delayed by 250 ps
of the output clock is delayed by 150 ps
of the output clock advances by 100 ps
EN DIGITAL: Digital function enable
0 = All digital functions disabled
1 = All digital functions (such as test patterns, gain, and offset correction) enabled
Bits[2:0]
Always write '0'
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8.6.2.12 Register Address 45h (Default = 00h)
Figure 57. Register Address 45h (Default = 00h)
7
6
LVDS CLKOUT
STRENGTH
STBY
Bit 7
5
LVDS DATA
STRENGTH
4
3
2
1
0
0
0
PDN GLOBAL
0
0
STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50 µs).
Bit 6
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100-Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50-Ω external termination
Bit 5
LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100-Ω external termination
1 = All LVDS data buffers have double strength to be used with 50-Ω external termination
Bits[4:3]
Always write '0'
Bit 2
PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered
down. Wakeup time from this mode is slow (typically 100 µs).
Bits[1:0]
Always write '0'
8.6.2.13 Register Address 4Ah (Default = 00h)
Figure 58. Register Address 4Ah (Default = 00h)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bits[7:1]
Always write '0'
Bit 0
HIGH FREQ MODE CH B: High-frequency mode for channel B
0
HIGH FREQ MODE CH B
0 = Default
1 = Use this mode for high input frequencies greater than 200 MHz
8.6.2.14 Register Address 58h (Default = 00h)
Figure 59. Register Address 58h (Default = 00h)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bits[7:1]
Always write '0'
Bit 0
HIGH FREQ MODE CH A: High-frequency mode for channel A
0
HIGH FREQ MODE CH A
0 = Default
1 = Use this mode for high input frequencies greater than 200 MHz
48
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8.6.2.15 Register Address BFh (Default = 00h)
Figure 60. Register Address BFh (Default = 00h)
7
Bits[7:4]
6
5
4
CH A OFFSET PEDESTAL
3
2
1
0
0
0
CH A OFFSET PEDESTAL: Channel A offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC midcode value. A pedestal can be added to the final converged value by programming these
bits. See the Offset Correction section. Channels can be independently programmed for different
offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D7-D2.
Program bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits[3:0]
Always write '0'
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8.6.2.16 Register Address C1h (Default = 00h)
Figure 61. Register Address C1h (Default = 00h)
7
Bits[7:4]
6
5
4
CH B OFFSET PEDESTAL
3
2
1
0
0
0
CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When offset correction is enabled, the final converged value after the offset is corrected is the ADC
midcode value. A pedestal can be added to the final converged value by programming these bits;
see the Offset Correction section. Channels can be independently programmed for different offset
pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D7-D2.
Program Bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits[3:0]
50
Always write '0'
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8.6.2.17 Register Address CFh (Default = 00h)
Figure 62. Register Address CFh (Default = 00h)
7
FREEZE OFFSET CORR
Bit 7
6
0
5
4
3
OFFSET CORR TIME CONSTANT
2
1
0
0
0
FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen,
the last estimated value is used for offset correction of every clock cycle. See the Offset Correction
section.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. See the Offset Correction
section.
Bits[1:0]
Always write '0'
8.6.2.18 Register Address EFh (Default = 00h)
Figure 63. Register Address EFh (Default = 00h)
7
0
6
0
5
0
4
EN LOW SPEED MODE
3
0
2
0
1
0
Bits[7:5]
Always write '0'
Bit 4
EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits
0
0
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW
SPEED MODE CH A register bits.
0 = Low-speed mode is disabled
1 = Low-speed mode is controlled by serial register bits
Bits[3:0]
Always write '0'
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8.6.2.19 Register Address F1h (Default = 00h)
Figure 64. Register Address F1h (Default = 00h)
7
0
6
0
5
0
4
0
3
0
Bits[7:2]
Always write '0'
Bits[1:0]
EN LVDS SWING: LVDS swing enable
2
0
1
0
EN LVDS SWING
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
8.6.2.20 Register Address F2h (Default = 00h)
Figure 65. Register Address F2h (Default = 00h)
7
0
6
0
5
0
4
0
3
LOW SPEED MODE CH A
2
0
Bits[7:4]
Always write '0'
Bit 3
LOW SPEED MODE CH A: Channel A low-speed mode enable
1
0
0
0
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits[2:0]
Always write '0'
8.6.2.21 Register Address 2h (Default = 00h)
Figure 66. Register Address 2h (Default = 00h)
7
0
6
HIGH PERF
MODE3
Bit 7
Always write '0'
Bit 6
HIGH PERF MODE3
5
4
3
2
1
0
0
0
0
0
0
0
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bits[5:0]
52
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8.6.2.22 Register Address D5h (Default = 00h)
Figure 67. Register Address D5h (Default = 00h)
7
6
5
0
0
0
Bits[7:5]
Always write '0'
Bit 4
HIGH PERF MODE4
4
HIGH PERF
MODE4
3
HIGH PERF
MODE5
2
1
0
0
0
0
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bit 3
HIGH PERF MODE5
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bits[2:0]
Always write '0'
8.6.2.23 Register Address D7h (Default = 00h)
Figure 68. Register Address D7h (Default = 00h)
7
6
5
4
0
0
0
0
Bits[7:4]
Always write '0'
Bit 3
HIGH PERF MODE6
3
HIGH PERF
MODE6
2
HIGH PERF
MODE7
1
0
0
0
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bit 2
HIGH PERF MODE7
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bits[1:0]
Always write '0'
8.6.2.24 Register Address DBh (Default = 00h)
Figure 69. Register Address DBh (Default = 00h)
7
6
0
0
5
HIGH PERF
MODE8
Bits[7:6]
Always write '0'
Bit 5
HIGH PERF MODE8
4
3
2
1
0
0
0
0
0
LOW SPEED MODE CH B
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS).
Bits[4:1]
Always write '0'
Bit 0
LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS4249 dual channel 14-bit ADC is designed for use in communications receivers designed to receive
modern communication signals such as LTE, WIMAX, W-CDMA, and high-order QAM signals. A typical diversity
receiver example is shown in Figure 70, where the antennas are placed at some distance to optimize
performance in the presence of multipath fading. The path includes a low noise amplifier (LNA), RF mixer, and a
digital variable gain amplifier (DVGA). Filtering is used throughout the path to remove blocking signals and
mixing products and to prevent aliasing during sampling.
LNA
RF Mixer
DVGA
ADS4249
Ch A
LO Source
Clock
ADS4249
Ch B
Figure 70. Diversity Communications Receiver
9.1.1 Theory of Operation
At every rising edge of the input clock, the analog input signal of each channel is simultaneously sampled. The
sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage, the
sampled/held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference between the
stage input and the quantized equivalent is gained and propagates to the next stage. At every clock, each
succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are
combined in a digital correction logic block and digitally processed to create the final code after a data latency of
16 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight
offset binary or binary twos complement format. The dynamic offset of the first stage sub-ADC limits the
maximum analog input frequency to approximately 400 MHz (with 2-VPP amplitude) or approximately 600 MHz
(with 1-VPP amplitude).
54
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Application Information (continued)
9.1.2 Analog Input
The analog input consists of a switched-capacitor-based, differential sample-and-hold (S/H) architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 0.95 V, available on the
VCM pin. For a full-scale differential input, each input pin (INP and INM) must swing symmetrically between
VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The input sampling circuit has a high
3-dB bandwidth that extends up to 550 MHz (measured from the input pins to the sampled voltage). Figure 71
shows an equivalent circuit for the analog input.
Sampling
Switch
LPKG
2 nH
INP
10 W
CBOND
1 pF
100 W
RESR
200 W
INM
CPAR2 RON
1 pF 15 W
CSAMP
2 pF
3 pF
3 pF
LPKG
2 nH
Sampling
Capacitor
RCR Filter
10 W
CBOND
1 pF
CPAR1
0.5 pF
RON
10 W
100 W
RON
15 W
CPAR2
1 pF
RESR
200 W
CSAMP
2 pF
Sampling
Capacitor
Sampling
Switch
Figure 71. Analog Input Equivalent Circuit
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Application Information (continued)
9.1.2.1 Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This operation improves the commonmode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input pin is
recommended to damp out ringing caused by package parasitics.
SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches;
nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending
on the input frequency, sample rate, and input amplitude, one of these factors generally plays a dominant part in
limiting performance. At very high input frequencies (greater than approximately 300 MHz), SFDR is determined
largely by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually
limits performance.
Glitches are caused by the opening and closing of the sampling switches. The driving circuit must present a low
source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low input
frequencies (up to approximately 200 MHz). Low impedance (less than 50 Ω) must be presented for the
common-mode switching currents. This configuration can be achieved by using two resistors from each input
terminated to the common-mode voltage (VCM pin).
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff
frequency (larger C) absorbs glitches better but reduces the input bandwidth. On the other hand, with a higher
cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches must then be
supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package
bond-wire inductance.
In the ADS4249, the R-C component values have been optimized when supporting high input bandwidth (up to
550 MHz). However, in applications with input frequencies up to 200 MHz to 300 MHz, the filtering of the glitches
can be improved further using an external R-C-R filter; see Figure 74 and Figure 75.
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. Furthermore, the ADC input impedance must be considered.
Figure 72 and Figure 73 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.
5
Differential Input Capacitance (pF)
Differential Input Resistance (kW)
100
10
1
0.1
0.01
4.5
4
3.5
3
2.5
2
1.5
1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
Figure 72. ADC Analog Input Resistance (RIN) Across
Frequency
56
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Input Frequency (GHz)
Input Frequency (GHz)
Figure 73. ADC Analog Input Capacitance (CIN) Across
Frequency
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Application Information (continued)
9.1.2.2 Driving Circuit
Three example driving circuit configurations are shown in Figure 74, Figure 75, and Figure 76. They are
optimized for low bandwidth (low input frequencies), high bandwidth (higher input frequencies), and very high
bandwidth (very high input frequencies), respectively. Note that three of the drive circuits have been terminated
by 50 Ω near the ADC side. The termination is accomplished by a 25-Ω resistor from each input to the 0.95-V
common-mode (VCM) from the device. This architecture allows the analog inputs to be biased around the
required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch;
good performance is obtained for high-frequency input signals. For example, ADT1-1WT transformers can be
used for the first two configurations (Figure 74 and Figure 75) ADTL2-18 transformers can be used for the third
configuration (Figure 76). An optional termination resistor pair may be required between the two transformers, as
shown in Figure 74, Figure 75, and Figure 76. The center point of this termination is connected to ground to
improve the balance between the P and M sides. The values of the terminations between the transformers and
on the secondary side must be chosen to obtain an effective 50 Ω (in the case of 50-Ω source impedance).
0.1 mF
T1
5W
INx_P
T2
0.1 mF
0.1 mF
25 W
25 W
3.3 pF
25 W
RIN
CIN
25 W
INx_M
1:1
1:1
5W
0.1 mF
VCM
Device
Figure 74. Drive Circuit with Low Bandwidth (for Low Input Frequencies Less Than 150 MHz)
0.1 mF
T1
5W
INx_P
T2
0.1 mF
0.1 mF
25 W
50 W
3.3 pF
25 W
RIN
CIN
50 W
INx_M
1:1
1:1
5W
0.1 mF
VCM
Device
Figure 75. Drive Circuit with High Bandwidth
(for High Input Frequencies Greater Than 150 MHz and Less Than 270 MHz)
0.1 mF
T1
5W
T2
INx_P
0.1 mF
0.1 mF
25 W
RIN
CIN
25 W
INx_M
1:1
1:1
0.1 mF
5W
VCM
Device
Figure 76. Drive Circuit with Very High Bandwidth (Greater than 270 MHz)
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Application Information (continued)
All of these examples show 1:1 transformers being used with a 50-Ω source. As explained in the Drive Circuit
Requirements section, this configuration helps to present a low source impedance to absorb the sampling
glitches. With a 1:4 transformer, the source impedance is 200 Ω. The higher source impedance is unable to
absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1
transformers).
In almost all cases, either a band-pass or low-pass filter is required to obtain the desired dynamic performance,
as shown in Figure 77. Such filters present low source impedance at the high frequencies corresponding to the
sampling glitch and help avoid performance losses associated with the high source impedance.
5W
INx_P
T1
0.1 mF
Differential
Input Signal
Band-Pass
or
Low-Pass
Filter
0.1 mF
100 W
RIN
CIN
100 W
INx_M
1:4
5W
VCM
Device
Figure 77. Drive Circuit with a 1:4 Transformer
9.1.3 Clock Input
The ADS4249 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM
using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock
or ac-coupling for LVPECL and LVDS clock sources are illustrated in Figure 78, Figure 79, and Figure 80. The
internal clock buffer is illustrated in Figure 81.
0.1 mF
CLKP
Differential
Sine-Wave
Clock Input
RT
0.1 mF
CLKM
Device
(1)
RT = termination resister, if necessary.
Figure 78. Differential Sine-Wave Clock Driving Circuit
Zo
0.1 mF
CLKP
Typical LVDS
Clock Input
100 W
Zo
0.1 mF
CLKM
Device
Figure 79. LVDS Clock Driving Circuit
58
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Application Information (continued)
Zo
0.1 mF
CLKP
150 W
Typical LVPECL
Clock Input
100 W
Zo
0.1 mF
CLKM
Device
150 W
Figure 80. LVPECL Clock Driving Circuit
Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
RESR
100 W
LPKG
2 nH
5 kW
CEQ
2 pF
20 W
CEQ
VCM
5 kW
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 81. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 82. For best performance, the clock inputs must be driven differentially, thereby
reducing susceptibility to common-mode noise. For high input frequency sampling, using a clock source with very
low jitter is recommended. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no
change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
VCM
0.1 mF
CLKM
Device
Figure 82. Single-Ended Clock Driving Circuit
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9.2 Typical Application
An example schematic for a typical application of the ADS4249 is shown in Figure 83.
22 O
22 O
22 O
AVDD
SPI Controller
22 O
0.1 …F
0.1 …F
22 O
DRVDD
To FPGA
ADC
Driver
50 O
5O
0.1 …F
0.1 …F
50 O
5O
50 O
50 O
0.1 …F
AVDD
0.1 …F
LVPECL Clock
Driver
FPGA
0.1 …F
240 O
240 O
100 O
0.1 …F
50 O
50 O
5O
50 O
0.1 …F
ADC
Driver
50 O
0.1 …F
5O
To FPGA
0.1 …F
0.1 …F
AVDD
DRVDD
Figure 83. Example Schematic for ADS4249
9.2.1 Design Requirements
Example design requirements are listed in Table 11 for the ADC portion of the signal chain. These do not
necessary reflect the requirements of an actual system, but rather demonstrate why the ADS4249 may be
chosen for a system based on a set of requirements.
Table 11. Example Design Requirements for ADS4249
DESIGN PARAMETER
Sampling rate
Input frequency
SNR
SFDR
Input full scale voltage
Channel-to-channel isolation
Overload recovery time
Digital interface
Power consumption
60
EXAMPLE DESIGN REQUIREMENT
ADS4249 CAPABILITY
≥ 245.76 Msps to allow 80 MHz of unaliased bandwidth
Max sampling rate: 250 Msps
> 250 MHz to accommodate full 2nd nyquist zone
operation
Large signal –3 dB bandwidth: 400 MHz
> 69 dBFS at –1 dFBS, 170 MHz
71.7 dBFS at –1 dBFS, 170 MHz
> 75 dBc at –1 dFBS, 170 MHz
80 dBc at –1 dBFS, 170 MHz
2 Vpp
2 Vpp
< 80 dB
95 dB
< 3 clock cycles
1 clock cycle
Parallel LVDS
Parallel LVDS
< 300 mW per channel
273 mW per channel
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9.2.2 Detailed Design Procedure
9.2.2.1 Analog Input
The analog inputs of the ADS4249 are typically driven by a fully differential amplifier. The amplifier must have
sufficient bandwidth for the frequencies of interest. The noise and distortion performance of the amplifier affect
the combined performance of the ADC and amplifier. The amplifier is often ac coupled to the ADC to allow both
the amplifier and ADC to operate at the optimal common mode voltages. The amplifier can be dc-coupled to the
ADC if required. An alternate approach is to drive the ADC using transformers. DC coupling cannot be used with
the transformer approach.
9.2.2.2 Common Mode Voltage Output (VCM)
The common mode voltage output is shared between both ADC channels. To maintain optimal isolation, an LC
filter may need to be placed on the VCM node between the channels (not shown in schematic). At a minimum,
place a bypass capacitor on the node that has sufficiently low impedance at the desired operating frequencies.
Note the VCM pin maximum output current in the electrical tables when using VCM in alternate ways.
9.2.2.3 Clock Driver
The ADS4249 supports both LVDS and CMOS interfaces. The LVDS interface must be used for best
performance when operating at maximum sampling rate. The LVDS outputs can be connected directly to the
FPGA without any additional components. When using CMOS outputs, place resistors in series with the outputs
to reduce the output current spikes to limit the performance degradation. The resistors must be large enough to
limit current spikes but not so large as to significantly distort the digital output waveform. Use an external CMOS
buffer when driving distances greater than a few inches to reduce ground bounce within the ADC.
9.2.2.4 Digital Interface
The ADS4249 supports both LVDS and CMOS interfaces. Use the LVDS interface for best performance when
operating at maximum sampling rate. The LVDS outputs can be connected directly to the FPGA without any
additional components. When using CMOS outputs, place resistors in series with the outputs to reduce the
output current spikes to limit the performance degradation. The resistors must be large enough to limit current
spikes but not so large as to significantly distort the digital output waveform. Use an external CMOS buffer when
driving distances greater than a few inches to reduce ground bounce within the ADC.
9.2.3 Application Curve
Power (dBFS)
Figure 84 shows the results of a 10-MHz LTE signal centered at 184.32 MHz captured by the ADS4249.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
Ref. Power = –12.12 dFBS
24.576
49.152
73.728
Frequency (MHz)
98.304
122.88
D001
Lower Adj. = 72.26 dBc
Lower Alt. = 72.85 dBc
Upper Adj. = 72.17 dBc
Upper Alt. = 72.56 dBc
Figure 84. 10-MHz LTE Signal Captured by ADS4249
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10 Power Supply Recommendations
The ADS4249 has two power supplies, one analog (AVDD) and one digital (DRVDD) supply. Both supplies have
a nominal voltage of 1.8 V. The AVDD supply is noise sensitive and the digital supply is not.
10.1 Sharing DRVDD and AVDD Supplies
For best performance the AVDD supply must be driven by a low-noise linear regulator (LDO) and separated from
the DRVDD supply. AVDD and DRVDD can share a single supply but they must be isolated by a ferrite bead and
bypass capacitors, in a PI-filter configuration, at a minimum. The digital noise is concentrated at the sampling
frequency and harmonics of the sampling frequency and can contain noise related to the sampled signal. When
developing schematics, leave extra placeholders for additional supply filtering.
10.2 Using DC-DC Power Supplies
DC-DC switching power supplies can be used to power DRVDD without issue. AVDD can also be powered from
a switching regulator. Noise and spurs on the AVDD power supply affect the SNR and SFDR of the ADC and
show up near dc and as a modulated component around the input frequency. If a switching regulator is used,
then design it to have minimal voltage ripple. Use supply filtering to limit the amount of spurious noise at the
AVDD supply pins. Allow for extra placeholders on the schematic for additional filtering. Optimization of filtering in
the final system is likely required to achieve the desired performance. The choice of power supply ultimately
depends on the system requirements. For instance, if very low phase noise is required, then using a switching
regulator is not recommended.
10.3 Power Supply Bypassing
Because the ADS4249 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise; thus, the
optimum number of capacitors depends on the actual application. A 0.1-uF capacitor is recommended near each
supply pin. The decoupling capacitors must be placed very close to the converter supply pins.
11 Layout
11.1 Layout Guidelines
11.1.1 Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS4226 Evaluation Module (SLAU333) for details on layout and
grounding.
11.1.2 Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the
digital ground. Therefore, the exposed pad must be soldered to the ground plane for best thermal and electrical
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
11.1.3 Routing Analog Inputs
Routing differential analog input pairs (INP_x and INM_x) close to each other is advisable. To minimize the
possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels
must be routed perpendicular to the sampling clock; see the ADS4226 Evaluation Module (SLAU333) for
reference routing. Figure 85 illustrates a snapshot of the PCB layout from the ADS42xxEVM.
11.1.4 Routing Digital Inputs
The digital outputs must be routed away from the analog inputs and any noise sensitive circuits. Avoid routing
the digital outputs in parallel to any analog trace. The digital outputs must be routed over a solid ground plane all
the way to the FPGA. Keep the digital traces as short as possible to reduce EMI emissions. The traces must be
matched length to maintain timing, however mismatches in the trace lengths can be taken into account by
including the delay differences in the FPGA timing constraints.
62
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11.2 Layout Example
INP_A
INM_A
CLKP
CLKM
INP_B
INM_B
ADS42xx
Channel B
Channel A
Clock
Figure 85. ADS42xxEVM PCB Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Definition of Specifications
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified
independently as EGREF and EGCHAN.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(2)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
SINAD = 10Log10
64
PS
PN + PD
(3)
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Product Folder Links: ADS4249
ADS4249
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SBAS534E – JULY 2011 – REVISED JANUARY 2016
Device Support (continued)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
ENOB =
SINAD - 1.76
6.02
(4)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
THD = 10Log10
PS
PN
(5)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(6)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(7)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• ADS4226 Evaluation Module (SLAU333)
• QFN/SON PCB Attachment (SLUA271)
• QFN Layout Guidelines (SLOA122)
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: ADS4249
65
ADS4249
SBAS534E – JULY 2011 – REVISED JANUARY 2016
www.ti.com
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
66
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Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: ADS4249
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
TBD
Call TI
Call TI
-40 to 85
AZ4249
(4/5)
ADS4249IRGC25
ACTIVE
VQFN
RGC
64
ADS4249IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4249
ADS4249IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ4249
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS4249IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS4249IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS4249IRGCR
VQFN
RGC
64
2000
336.6
336.6
28.6
ADS4249IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
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