ADS42LB69IRGCT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 ADS42LBx9 14- and 16-Bit, 250-MSPS, Analog-to-Digital Converters 1 Features 2 Applications • • • • • • • • • • • • • • 1 • • • • • • • • • Dual Channel 14- and 16-Bit Resolution Maximum Clock Rate: 250 MSPS Analog Input Buffer with High Impedance Input Flexible Input Clock Buffer with Divide-by-1, -2, and -4 2-VPP and 2.5-VPP Differential Full-Scale Input (SPI-Programmable) DDR or QDR LVDS Interface 64-Pin VQFN Package (9-mm × 9-mm) Power Dissipation: 820 mW/ch Aperture Jitter: 85 fS Internal Dither Channel Isolation: 100 dB Performance at fIN = 170 MHz at 2 VPP, –1 dBFS – SNR: 73.2 dBFS – SFDR: – 87 dBc (HD2 and HD3) – 100 dBc (Non HD2 and HD3) Performance at fIN = 170 MHz: 2.5 VPP, –1 dBFS – SNR: 74.9 dBFS – SFDR: – 85 dBc (HD2 and HD3) – 97 dBc (Non HD2 and HD3) Communication and Cable Infrastructure Multi-Carrier, Multimode Cellular Receivers Radar and Smart Antenna Arrays Broadband Wireless Test and Measurement Systems Software-Defined and Diversity Radios Microwave and Dual-Channel I/Q Receivers Repeaters Power Amplifier Linearization 3 Description The ADS42LB49 and ADS42LB69 are a family of high-linearity, dual-channel, 14and 16-bit, 250-MSPS, analog-to-digital converters (ADCs) supporting DDR and QDR LVDS output interfaces. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS42LBx9 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with lowpower consumption. Device Information(1) PART NUMBER PACKAGE ADS42LB49 VQFN (64) ADS42LB69 VQFN (64) INTERFACE OPTION 14-bit DDR or QDR LVDS 14-bit JESD204B 16-bit DDR or QDR LVDS 16-bit JESD204B (1) For all available packages, see the orderable addendum at the end of the datasheet. space space Simplified Schematic ADS42LB49, ADS42LB69 14-, 16-Bit ADC CLKINP, CLKINM Output Formatter Digital Gain and Test Patterns QDR LVDS Divide by 1,2,4 SYNCINP, SYNCINM DACLKP, DACLKM Fs = 250Msps Fin = 170MHz Ain = -1dBFS HD2 = 90dBc HD3 = 89dBc Non HD2,3 = 100dBc -20 DA[3:0]P, DA[3:0]M -40 Delay DB[3:0]P, B[3:0]MM Digital Block 14-, 16-Bit ADC INBP, INBM 0 DAFRAMEP, AFRAMEM Output Formatter Digital Gain and Test Patterns QDR LVDS DBCLKP, BCLKM DBFRAMEP, BFRAMEM Amplitude (dB) INAP, INAM FFT for 170MHz Input Signal OVRA Digital Block -60 -80 OVRB VCM Common Mode Configuration Registers CTRL1 CTRL2 SDOUT SEN SCLK SDATA RESET -100 Copyright © 2016, Texas Instruments Incorporated -120 0 25 50 75 Frequency (MHz) 100 125 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 7 1 1 1 2 4 9 Absolute Maximum Ratings ...................................... 9 ESD Ratings.............................................................. 9 Recommended Operating Conditions..................... 10 Thermal Information ................................................ 10 Electrical Characteristics: ADS42LB69 (16-Bit) ...... 11 Electrical Characteristics: ADS42LB49 (14-Bit) ...... 12 Electrical Characteristics: General .......................... 13 Digital Characteristics ............................................. 14 Timing Requirements: General ............................... 15 Timing Requirements: DDR LVDS Mode.............. 15 Timing Requirements: QDR LVDS Mode ............ 16 Typical Characteristics: ADS42LB69 .................... 17 Typical Characteristics: ADS42LB49 .................... 22 Typical Characteristics: Common ......................... 27 Typical Characteristics: Contour ........................... 28 Parameter Measurement Information ................ 31 8 Detailed Description ............................................ 34 8.1 8.2 8.3 8.4 8.5 8.6 9 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 34 34 35 40 43 47 Application and Implementation ........................ 60 9.1 Application Information............................................ 60 9.2 Typical Application .................................................. 60 10 Power Supply Recommendations ..................... 67 11 Layout................................................................... 67 11.1 Layout Guidelines ................................................. 67 11.2 Layout Example .................................................... 68 12 Device and Documentation Support ................. 70 12.1 12.2 12.3 12.4 12.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 70 70 70 70 70 13 Mechanical, Packaging, and Orderable Information ........................................................... 70 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (December 2014) to Revision F Page • Added Using the ADS42LBx9 In Time-Domain, Low-Frequency Pulse Applications section.............................................. 63 • Added Community Resources section ................................................................................................................................ 70 Changes from Revision D (September 2013) to Revision E Page • Added ESD Ratings table and Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections..................................................................................................................... 1 • Deleted Ordering Information section..................................................................................................................................... 4 • Merged all Pin Functions tables into one table ...................................................................................................................... 7 • Changed INAP, INAM pin numbers for ADS42LB69 and ADS42LB49 DDR LVDS in pin assignments table ...................... 7 • Added footnote to Table 1 ................................................................................................................................................... 15 • Added footnote to Table 2 ................................................................................................................................................... 16 • Changed pin 34 to pin 37 in Figure 79 ................................................................................................................................ 36 Changes from Revision C (September 2013) to Revision D Page • Changed device status to Production Data ............................................................................................................................ 1 • Added pre-RTM changes throughout document .................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Changes from Revision B (March 2013) to Revision C • Page Added pre-RTM changes throughout document .................................................................................................................... 1 Changes from Revision A (November 2012) to Revision B • Page Added pre-RTM changes throughout document .................................................................................................................... 1 Changes from Original (October 2012) to Revision A • Page Added pre-RTM changes throughout document .................................................................................................................... 1 Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 3 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 5 Pin Configuration and Functions 49 DRVDD 50 DA10M 51 DA10P 52 DA12M 53 DA12P 54 DA14M 55 DA14P 56 CLKOUTM 57 CLKOUTP 58 DB14M 59 DB14P 60 DB12M 61 DB12P 62 DB10P DB8M 1 48 DB8P 2 47 DA8M DB6M 3 46 DA6P DB6P 4 45 DA6M DB4M 5 44 DA4P DB4P 6 43 DA4M DB2M 7 42 DA2P DB2P 8 41 DA2M DB0M 9 40 DA0P DA8P DB0P 10 39 DA0M DRVDD 11 38 AVDD CTRL2 12 37 CTRL1 AVDD 13 36 AVDD Submit Documentation Feedback 32 AVDD3V AVDD 31 SYNCINM 30 SYNCINP 29 RESERVED 28 VCM 27 AVDD 26 CLKINP 25 AVDD 23 33 AVDD CLKINM 24 16 RESET 22 AVDD SDOUT 21 34 INAM SEN 20 35 INAP SDATA 19 14 15 SCLK 18 INBP INBM AVDD3V 17 4 63 DB10P 64 DRVDD ADS42LB69 DDR LVDS: RGC Package 64-Pin VQFN Top View Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 49 DRVDD 50 DA8M 51 DA8P 52 DA10M 53 DA10P 54 DA12M 55 DA12P 56 CLKOUTM 57 CLKOUTP 58 DB12M 59 DB12P 60 DB10M 61 DB10P 62 DB8P 63 DB8P 64 DRVDD ADS42LB49 DDR LVDS: RGC Package 64-Pin VQFN Top View DB6M 1 48 DB6P 2 47 DA6M DB4M 3 46 DA4P DB4P 4 45 DA4M DB2M 5 44 DA2P DB2P 6 43 DA2M DB0M 7 DA6P 42 DA0P GND Pad (Backside) DB0P 8 NC/OVR 9 40 NC/OVR NC/OVR 10 39 NC/OVR DRVDD 11 38 AVDD CTRL2 12 37 CTRL1 AVDD 13 36 AVDD 41 DA0M Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 32 AVDD 31 AVDD3V SYNCINP 29 SYNCINM 30 RESERVED 28 VCM 27 AVDD 26 CLKINP 25 CLKINM 24 AVDD 23 33 AVDD RESET 22 16 SEN 20 AVDD SDOUT 21 34 INAM SDATA 19 35 INAP SCLK 18 14 15 AVDD3V 17 INBP INBM Submit Documentation Feedback 5 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 49 DRVDD 50 DA3M 51 DA3P 52 DAFRAMEM 53 DAFRAMEM 54 OVRA 55 NC 56 NC 57 NC 58 NC 59 OVRB 60 NC 61 NC 62 DB0M DB1M 1 48 DA2P DB1P 2 47 DA2M DBCLKM 3 46 DACLKP DBCLKP 4 45 DACLKM DB2M 5 44 DA1P DB2P 6 43 DA1M DB3M 7 42 DA0P DB3P 8 GND Pad (Backside) 41 DA0M AVDD 16 33 AVDD Submit Documentation Feedback AVDD3V 32 34 INAM AVDD 31 15 SYNCINM 30 INBM SYNCINP 29 35 INAP VCM 27 36 AVDD 14 RESERVED 28 13 INBP AVDD 26 AVDD CLKINP 25 37 CTRL1 AVDD 23 38 AVDD 12 CLKINM 24 11 CTRL2 RESET 22 DRVDD SDOUT 21 39 NC SEN 20 40 NC 10 SDATA 19 9 DBFRAMEP SCLK 18 DBFRAMEM AVDD3V 17 6 63 DB0P 64 DRVDD ADS42LB69, ADS42LB49 QDR LVDS: RGC Package 64-Pin VQFN Top View Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Pin Functions PIN I/O DESCRIPTION ADS42LB69 DDR LVDS ADS42LB49 DDR LVDS QDR LVDS INAP, INAM 35, 34 35, 34 34, 35 I Differential analog input for channel A INBP, INBM 14, 15 14, 15 14, 15 I Differential analog input for channel B 27 27 27 O Common-mode voltage for analog inputs, 1.9 V CLKINP, CLKINM 25, 24 25, 24 24, 25 I Differential clock input for ADC SYNCINP, SYNCINM 29, 30 29, 30 29, 30 I External sync input. If not used, connect SYNCINP to GND and SYNCINM to AVDD. CTRL1 37 37 37 I/O Can be configured as power-down input pin or as OVR output pin for channel A, depending on the register bit PDN/OVR FOR CTRL PINS. CTRL2 12 12 12 I/O Can be configured as power-down input pin or as OVR output pin for channel B, depending on the register bit PDN/OVR FOR CTRL PINS NC — — 39, 40, 55-58, 60, 61 — Do not connect NC/OVR — 9, 10, 39, 40 — — If the OVR ON LSB bit is set, these pins can be used because they carry overrange information. Otherwise, do not connect these pins. Reserved 28 28 28 — Do not connect RESET 22 22 22 I Hardware reset. Active high. SCLK 18 18 18 I Serial interface clock input SDATA 19 19 19 I Serial interface data input SDOUT 21 21 21 O Serial interface data output SEN 20 20 20 I Serial interface enable 57, 56 57, 56 — O Differential LVDS output clock — — 41-44, 47, 48, 50, 51 O 4-bit QDR LVDS output interface for channel A 39-48, 50-55 41-48, 50-55 — O DDR LVDS output interface for channel A DACLKP, DACLKM — — 45, 46 O Differential output clock for channel A DAFRAMEP, DAFRAMEM — — 52, 53 — Differential frame clock output for channel A DB[3:0]P, DB[3:0]M — — 1, 2, 5-8, 62, 63 — 4-bit QDR LVDS output interface for channel B 1-10, 58-63 1-8, 58-63 — O DDR LVDS output interface for channel B DBCLKP, DBCLKM — — 3, 4 — Differential output clock for channel A DBFRAMEP, DBFRAMEM — — 9, 10 — Differential frame clock output for channel A NAME INPUT AND REFERENCE VCM CLOCK AND SYNC CONTROL AND SERIAL DATA INTERFACE CLKOUTP, CLKOUTM DA[3:0]P, DA[3:0]M DA[14:0]P, DA[14:0]M DB[14:0]P, DB[14:0]M Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 7 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION ADS42LB69 DDR LVDS ADS42LB49 DDR LVDS QDR LVDS OVRA — — 54 O Overrange indication channel A OVRB — — 59 O Overrange indication channel A 13, 16, 23, 26, 31, 33, 36, 38 13, 16, 23, 26, 31, 33, 36, 38 13, 16, 23, 26, 31, 33, 36, 38 I Analog 1.8-V power supply NAME POWER SUPPLY AVDD AVDD3V 17, 32 17, 32 17, 32 I Analog 3.3 V power supply for analog buffer DRVDD 11, 49, 64 11, 49, 64 11, 49, 64 I Digital 1.8-V power supply Ground pad Ground pad Ground pad I Ground GND 8 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage MIN MAX AVDD3V –0.3 3.6 AVDD –0.3 2.1 DRVDD –0.3 2.1 –0.3 0.3 Voltage between AGND and DGND Voltage applied to input pins Temperature INA, INBP, INA, INBM –0.3 3 CLKINP, CLKINM –0.3 AVDD + 0.3 SYNCINP, SYNCINM –0.3 AVDD + 0.3 SCLK, SEN, SDATA, RESET, CTRL1, CTRL2 –0.3 3.9 Operating free-air, TA –40 +85 Operating junction, TJ Storage, Tstg (1) UNIT V V V +125 –65 °C +150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 9 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage AVDD3V Analog buffer supply voltage DRVDD Digital supply voltage 1.7 1.8 1.9 V 3.15 3.3 3.45 V 1.7 1.8 1.9 V ANALOG INPUTS VID Differential input voltage range VICR Input common-mode voltage Default after reset 2 Register programmable (2) VPP 2.5 VCM ± 0.025 V Maximum analog input frequency with 2.5-VPP input amplitude 250 MHz Maximum analog input frequency with 2-VPP input amplitude 400 MHz CLOCK INPUT Input clock sample rate QDR interface 30 250 DDR interface 10 250 0.3 (3) Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) 1.5 LVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 LVCMOS, single-ended, ac-coupled 1.5 Input clock duty cycle 35% MSPS 50% VPP V 65% DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND RLOAD Single-ended load resistance TA Operating free-air temperature (1) (2) (3) 3.3 pF Ω +50 –40 +85 °C After power-up, to reset the device for the first time, only use the RESET pin. Refer to the Register Initialization section. For details, refer to the Digital Gain section. Refer to the Performance vs Clock Amplitude curves, Figure 27 and Figure 28. 6.4 Thermal Information ADS42LBx9 THERMAL METRIC (1) RGC (VQFN) UNIT 64 PINS RθJA Junction-to-ambient thermal resistance 22.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 7.1 °C/W RθJB Junction-to-board thermal resistance 2.5 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 2.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W (1) 10 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 6.5 Electrical Characteristics: ADS42LB69 (16-Bit) Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V. PARAMETER SNR SINAD Signal-to-noise ratio Signal-to-noise and distortion ratio TEST CONDITIONS 2-VPP FULL-SCALE MIN SFDR THD HD2 HD3 Total harmonic distortion 2nd-order harmonic distortion 3rd-order harmonic distortion Worst spur (other than second and third harmonics) Two-tone intermodulation distortion MIN TYP 73.9 75.8 fIN = 70 MHz 73.7 75.5 73.2 74.7 fIN = 230 MHz 72.8 74.1 fIN = 10 MHz 73.7 75.1 fIN = 70 MHz 73.6 75.3 73.1 74.2 fIN = 170 MHz fIN = 170 MHz 70.8 69.6 72.5 73.4 fIN = 10 MHz 87 83 fIN = 70 MHz 90 88 87 85 fIN = 230 MHz 86 83 fIN = 10 MHz 86 82 fIN = 70 MHz 89 87 85 82 fIN = 230 MHz 83 81 fIN = 10 MHz 97 95 fIN = 70 MHz 90 88 87 85 fIN = 230 MHz 86 84 fIN = 10 MHz 87 83 fIN = 70 MHz 96 94 91 85 fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz 81 78 81 81 fIN = 230 MHz 87 83 fIN = 10 MHz 102 103 101 103 101 101 fIN = 70 MHz fIN = 170 MHz fIN = 230 MHz IMD MAX fIN = 10 MHz fIN = 230 MHz Spurious-free dynamic range (including second and third harmonic distortion) TYP 2.5-VPP FULL-SCALE 87 MAX UNIT dBFS dBFS dBc dBc dBc dBc dBc 100 100 f1 = 46 MHz, f2 = 50 MHz, each tone at –7 dBFS 97 94 f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS 94 90 100 100 1 1 > 40 > 40 dB dBFS Crosstalk 20-MHz, full-scale signal on channel under observation; 170-MHz, full-scale signal on other channel Input overload recovery Recovery to within 1% (of full-scale) for 6-dB overload with sine-wave input PSRR AC power-supply rejection ratio For 50-mVPP signal on AVDD supply, up to 10 MHz ENOB Effective number of bits fIN = 170 MHz 11.85 12.03 LSBs DNL Differential nonlinearity fIN = 170 MHz ±0.6 ±0.6 LSBs INL Integrated nonlinearity fIN = 170 MHz ±3 ±3.5 LSBs Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ±8 Submit Documentation Feedback dB Clock cycle 11 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 6.6 Electrical Characteristics: ADS42LB49 (14-Bit) Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V. PARAMETER SNR SINAD SFDR THD HD2 HD3 Signal-to-noise ratio Signal-to-noise and distortion ratio Spurious-free dynamic range (including second and third harmonic distortion) Total harmonic distortion 2nd-order harmonic distortion 3rd-order harmonic distortion Worst spur (other than second and third harmonics) IMD Two-tone intermodulation distortion TEST CONDITIONS 2-VPP FULL-SCALE MIN TYP 2.5-VPP FULL-SCALE MAX MIN TYP fIN = 10 MHz 73.3 74.9 fIN = 70 MHz 73.1 74.7 72.7 74.1 fIN = 230 MHz 72.3 73.5 fIN = 10 MHz 73.1 74.1 fIN = 70 MHz 73.1 74.4 72.6 73.6 fIN = 230 MHz 72 72.9 fIN = 10 MHz 87 82 fIN = 70 MHz 90 88 87 85 fIN = 230 MHz 86 83 fIN = 10 MHz 86 81 fIN = 70 MHz 89 87 85 82 fIN = 230 MHz 83 81 fIN = 10 MHz 97 95 fIN = 70 MHz 90 88 87 85 fIN = 230 MHz 86 84 fIN = 10 MHz 87 82 fIN = 70 MHz 96 94 91 85 fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz 69.5 68.5 79 76 79 79 MAX UNIT dBFS dBFS dBc dBc dBc dBc fIN = 230 MHz 87 83 fIN = 10 MHz 104 103 101 103 100 101 fIN = 230 MHz 99 100 f1 = 46 MHz, f2 = 50 MHz, each tone at –7 dBFS 99 95 f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS 93 93 100 90 dB Clock cycle fIN = 70 MHz fIN = 170 MHz 87 dBc dBFS Crosstalk 20-MHz, full-scale signal on channel under observation; 170-MHz, full-scale signal on other channel Input overload recovery Recovery to within 1% (of full-scale) for 6-dB overload with sine-wave input 1 1 PSRR AC power-supply rejection ratio For a 50-mVPP signal on AVDD supply, up to 10 MHz > 40 > 40 dB ENOB Effective number of bits fIN = 170 MHz 11.76 11.93 LSBs DNL Differential nonlinearity fIN = 170 MHz ±0.15 ±0.15 LSBs INL Integrated nonlinearity fIN = 170 MHz ±0.75 ±0.9 LSBs 12 Submit Documentation Feedback ±3 Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 6.7 Electrical Characteristics: General Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS VID Default (after reset) Differential input voltage range 2 2.5 Differential input resistance (at 170 MHz) 1.2 kΩ 4 pF Differential input capacitance (at 170 MHz) With 50-Ω source impedance, and 50-Ω termination Analog input bandwidth VCM VPP Register programmed (1) 900 MHz Common-mode output voltage 1.9 V VCM output current capability 10 mA DC ACCURACY Offset error –20 EGREF Gain error as a result of internal reference inaccuracy alone EGCHAN Gain error of channel alone 20 mV ±2 %FS –5 Temperature coefficient of EGCHAN %FS Δ%/°C 0.01 POWER SUPPLY IAVDD Analog supply current 141 182 mA IAVDD3V Analog buffer supply current 302 340 mA 219 245 mA IDRVDD Digital and output buffer supply current External 100-Ω differential termination on LVDS outputs Analog power 253 mW Analog buffer power 996 mW 393 mW Power consumption (includes digital blocks and output buffers) External 100-Ω differential termination on LVDS outputs Total power 1.64 Global power-down (both channels) (1) 1.85 W 160 mW Refer to the Serial Interface section. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 13 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 6.8 Digital Characteristics The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2) (1) VIH High-level input voltage VIL Low-level input voltage IIH High-level input current All digital inputs support 1.8-V and 3.3-V CMOS logic levels RESET, SDATA, SCLK, CTRL1, CTRL2 (2) Low-level input current V 0.4 VHIGH = 1.8 V 10 VHIGH = 1.8 V 0 RESET, SDATA, SCLK, CTRL1, CTRL2 VLOW = 0 V 0 SEN VLOW = 0 V 10 SEN IIL 1.3 (3) V µA µA DIGITAL OUTPUTS, CMOS INTERFACE (OVRA, OVRB, SDOUT) VOH High-level output voltage VOL Low-level output voltage DRVDD – 0.1 DRVDD V 0 0.1 V DIGITAL OUTPUTS, LVDS INTERFACE VODH High-level output differential voltage With an external 100-Ω termination 250 350 500 mV VODL Low-level output differential voltage With an external 100-Ω termination –500 –350 –250 mV VOCM Output common-mode voltage (1) (2) (3) 14 1.05 V SCLK, SDATA, and SEN function as digital input pins in serial configuration mode. SDATA and SCLK have an internal 150-kΩ pull-down resistor. SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V CMOS buffers. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 6.9 Timing Requirements: General Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.7 V to 1.9 V. MIN tA Aperture delay MAX 0.7 1.1 0.5 Aperture delay matching between two channels of the same device ps ps 85 Time to valid data after coming out of STANDBY mode Time to valid data after coming out of GLOBAL power-down mode (in this mode, both channels power-down) ADC latency (1) ns ±150 Aperture jitter Wakeup time UNIT ±70 Variation of aperture delay between two devices at the same temperature and supply voltage tJ TYP fS rms 50 100 µs 250 1000 µs Default latency after reset 14 Clock cycles Normal OVR latency 14 Clock cycles 9 Clock cycles Fast OVR latency tSU_SYNCIN Setup time for SYNCIN, referenced to input clock rising edge 400 ps tH_SYNCIN Hold time for SYNCIN, referenced to input clock rising edge 100 ps (1) Overall latency = ADC latency + tPDI. 6.10 Timing Requirements: DDR LVDS Mode (1) Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, and DRVDD = 1.7 V to 1.9 V. MIN TYP MAX UNIT tSU Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM) (2) 0.62 0.82 ns tHO Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid (2) 0.54 0.64 ns tPDI Clock propagation delay: input clock rising edge cross-over to output clock (CLKOUTP – CLKOUTM) rising edge cross-over 8 10.5 13 ns LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) 52% tFALL, tRISE Data fall time, data rise time: rise time measured from –100 mV to +100 mV, 10 MSPS ≤ sampling frequency ≤ 250 MSPS 0.14 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time: Rise time measured from –100 mV to +100 mV, 10 MSPS ≤ sampling frequency ≤ 250 MSPS 0.18 ns (1) (2) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to a logic high of +100 mV and a logic low of –100 mV. Table 1. DDR LVDS Timings at Lower Sampling Frequencies (1) SETUP TIME (1) SAMPLING FREQUENCY (MSPS) MIN TYP CLOCK PROPAGATION DELAY HOLD TIME tSU tHO MAX MIN TYP tPDI MAX MIN TYP MAX 80 2.40 2.96 2.16 2.82 9 11.9 15 120 1.57 1.92 1.40 1.84 8 11.1 14 160 1.17 1.40 1.02 1.36 8 10.6 13 200 0.82 1.07 0.72 1.02 8 10.5 13 230 0.69 0.91 0.61 0.84 8 10.5 13 UNIT ns See Figure 73 for a timing diagram in DDR LVDS mode. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 15 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 6.11 Timing Requirements: QDR LVDS Mode (1) (2) Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave input clock, CLOAD = 3.3 pF (3), and RLOAD = 100 Ω (4), unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, and DRVDD = 1.7 V to 1.9 V. (5) (6) tSU Data setup time tH Data hold time (5) (6): DxCLKP, DxCLKM zero-crossing to data becoming invalid : data valid to DxCLKP, DxCLKM zero-crossing MIN TYP 0.23 0.31 ns 0.16 0.29 ns LVDS bit clock duty cycle: differential bit clock duty cycle (DxCLKP, DxCLKM) tPDI Clock propagation delay: input clock rising edge cross-over to output frame clock (DxFRAMEP-DxFRAMEM) rising edge cross-over tRISE, tFALL Data rise and fall time: rise time measured from –100 mV to +100 mV tCLKRISE, tCLKFALL Output clock rise and fall time: rise time measured from –100 mV to +100 mV (1) (2) (3) (4) (5) (6) MAX UNIT 50% 7 10.1 13 ns 0.18 ns 0.2 ns Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Timing parameters are ensured by design and characterization and are not tested in production. CLOAD is the effective external single-ended load capacitance between each output pin and ground. RLOAD is the differential load resistance between the LVDS output pair. Data valid refers to a logic high of +100 mV and a logic low of –100 mV. The setup and hold times of a channel are measured with respect to the same channel output clock. Table 2. QDR LVDS Timings at Lower Sampling Frequencies (1) (1) 16 SETUP TIME HOLD TIME CLOCK PROPAGATION DELAY tSU tHO tPDI SAMPLING FREQUENCY (MSPS) MIN TYP MIN TYP MIN TYP MAX 80 1.06 1.21 0.84 1.29 6 9.3 12 120 0.63 0.77 0.66 0.88 7 9.5 13 160 0.43 0.55 0.39 0.61 7 9.7 13 200 0.31 0.42 0.28 0.47 7 9.8 13 230 0.24 0.34 0.17 0.36 7 9.9 13 MAX MAX UNIT ns See Figure 74 for a timing diagram in QDR LVDS mode. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 6.12 Typical Characteristics: ADS42LB69 Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 0 0 fIN = 10 MHz SFDR = 88 dBc SNR = 74 dBFS SINAD = 73.9 dBFS THD = 87 dBc SFDR Non HD2, HD3 = 102 dBc −40 −60 −20 Amplitude (dBFS) Amplitude (dBFS) −20 −80 −100 −120 fIN = 170 MHz SFDR = 90 dBc SNR = 73.1 dBFS SINAD = 73 dBFS THD = 87 dBc SFDR Non HD2, HD3 = 100 dBc −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 Figure 1. FFT for 10-MHz Input Signal fIN = 300 MHz SFDR = 76 dBc SNR = 72.2 dBFS SINAD = 70.5 dBFS THD = 74 dBc SFDR Non HD2,HD3 = 97 −40 −60 Amplitude (dBFS) Amplitude (dBFS) 125 G002 fIN = 10 MHz SFDR = 84 dBc SNR = 75.7 dBFS SINAD = 75.2 dBFS THD = 83 dBc SFDR Non HD2, HD3 = 104 dBc −20 −80 −100 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 25 G003 Figure 3. FFT for 300-MHz Input Signal 50 75 Frequency (MHz) 100 125 G004 Figure 4. FFT for 10-MHz Input Signal (2.5-VPP Full-Scale) 0 0 fIN = 170 MHz SFDR = 87 dBc SNR = 74.7 dBFS SINAD = 74.3 dBFS THD = 84 dBc SFDR Non HD2, HD3 = 93 dBc −40 −60 fIN = 300 MHz SFDR = 72 dBc SNR = 73.3 dBFS SINAD = 70 dBFS THD = 72 dBc SFDR Non HD2, HD3 = 93 dBc −20 Amplitude (dBFS) −20 Amplitude (dBFS) 100 0 −20 −80 −100 −120 50 75 Frequency (MHz) Figure 2. FFT for 170-MHz Input Signal 0 −120 25 G001 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 Figure 5. FFT for 170-MHz Input Signal (2.5-VPP Full-Scale) 125 −120 0 25 G005 50 75 Frequency (MHz) 100 125 G006 Figure 6. FFT for 300-MHz Input Signal (2.5-VPP Full-Scale) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 17 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Typical Characteristics: ADS42LB69 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 0 0 Each Tone at −7 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 97 dBFS SFDR = 101 dBFS −40 −60 −80 −100 −120 Each Tone at −36 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 101 dBFS SFDR = 103 dBFS −20 Amplitude (dBFS) Amplitude (dBFS) −20 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 Figure 7. FFT for Two-Tone Input Signal (At –7 dBFS, 46 MHz and 50 MHz) −40 Amplitude (dBFS) Amplitude (dBFS) 125 G008 Each Tone at −36 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 107 dBFS SFDR = 108 dBFS −20 −60 −80 −100 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 100 125 G010 −92 fIN1 = 46 MHz fIN2 = 50 MHz Two − Tone IMD (dBFS) −94 −98 −100 −102 −104 −106 −108 −36 50 75 Frequency (MHz) Figure 10. FFT for Two-Tone Input Signal (At –36 dBFS, 185 MHz and 190 MHz) −94 −96 25 G009 Figure 9. FFT for Two-Tone Input Signal (At –7 dBFS, 185 MHz and 190 MHz) Two − Tone IMD (dBFS) 100 0 Each Tone at −7 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 94 dBFS SFDR = 96 dBFS −20 fIN1 = 185 MHz fIN2 = 190 MHz −96 −98 −100 −102 −104 −106 −33 −30 −27 −24 −21 −18 −15 Each Tone Amplitude (dBFS) −12 Figure 11. IMD3 vs Input Amplitude (46 MHz and 50 MHz) 18 50 75 Frequency (MHz) Figure 8. FFT for Two-Tone Input Signal (At –36 dBFS, 46 MHz and 50 MHz) 0 −120 25 G007 Submit Documentation Feedback −9 −7 −108 −36 −33 −30 G011 −27 −24 −21 −18 −15 Each Tone Amplitude (dBFS) −12 −9 −7 G012 Figure 12. IMD3 vs Input Amplitude (185 MHz and 190 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Typical Characteristics: ADS42LB69 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 100 77 2−VPP Full−Scale 2.5−VPP Full−Scale 95 2−VPP Full−Scale 2.5−VPP Full−Scale 76 75 85 SNR (dBFS) SFDR (dBc) 90 80 75 70 74 73 72 65 71 60 0 50 100 150 200 250 300 Input Frequency (MHz) 350 70 400 0 50 70 65 60 10 MHz 70 MHz 100 MHz 130 MHz 170 MHz 230 MHz 270 MHz 350 MHz 400 MHz 491 MHz 10 MHz 70 MHz 100 MHz 130 MHz 78 76 G014 170 MHz 230 MHz 270 MHz 350 MHz 400 MHz 491 Mhz 72 70 68 66 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB) G015 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Gain (dB) G016 Figure 16. SNR vs Digital Gain 75.5 77.5 120 77 110 76.5 100 76 75 90 74.5 80 74 70 73.5 60 73 50 72.5 72 −60 −50 −40 −30 −20 Amplitude (dBFS) −10 0 130 Input Frequency = 170 MHz SNR(dBFS) SFDR(dBc) SFDR(dBFS) 120 110 100 75.5 90 75 80 74.5 70 74 60 73.5 50 40 73 40 30 72.5 30 20 Figure 17. Performance Across Input Amplitude (70 MHz) SNR (dBFS) SNR(dBFS) SFDR(dBc) SFDR(dBFS) 130 SFDR (dBc,dBFS) Input Frequency = 70 MHz 76 SNR (dBFS) 400 74 Figure 15. SFDR vs Digital Gain 71.5 −70 350 Figure 14. SNR vs Input Frequency 77 76.5 150 200 250 300 Input Frequency (MHz) 80 SNR (dB) SFDR (dBc) Figure 13. SFDR vs Input Frequency 120 115 110 105 100 95 90 85 80 75 100 G013 72 −70 −60 −50 G017 −40 −30 −20 Amplitude (dBFS) −10 0 SFDR (dBc,dBFS) 55 20 G018 Figure 18. Performance Across Input Amplitude (170 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 19 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Typical Characteristics: ADS42LB69 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. SFDR (dBc) 94 Input Frequency = 170 MHz 75.5 92 75 90 74.5 88 74 86 73.5 84 73 82 1.85 75 92 74.5 89 74 86 73.5 83 73 80 1.85 G019 Figure 19. Performance vs Input Common-Mode Voltage (70 MHz) 72.5 1.95 1.87 1.9 1.93 Input Common−Mode Voltage (V) G020 Figure 20. Performance vs Input Common-Mode Voltage (170 MHz) 93 75 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 92 91 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75V AVDD = 1.8 V 74.5 90 SNR (dBFS) SFDR (dBc) SFDR SNR 95 72.5 1.95 1.87 1.9 1.93 Input Common−Mode Voltage (V) 75.5 98 SFDR (dBc) SFDR SNR SNR (dBFS) Input Frequency = 70 MHz SNR (dBFS) 76 96 89 88 87 AVDD = 1.85 V AVDD = 1.9 V 74 73.5 73 86 72.5 85 84 −40 Input Frequency = 170 MHz −15 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 72 −40 85 Figure 21. SFDR vs AVDD Supply and Temperature (170 MHz) 10 35 Temperature (°C) 60 85 G022 Figure 22. SNR vs AVDD Supply and Temperature (170 MHz) 94 75 AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 93 92 91 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 74.5 90 SNR (dBFS) SNR (dBFS) −15 G021 89 88 87 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V 74 73.5 73 86 85 84 83 −40 72.5 Input Frequency = 170 MHz −15 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 85 Submit Documentation Feedback −15 G023 Figure 23. SFDR vs AVDD_BUF Supply and Temperature (170 MHz) 20 72 −40 10 35 Temperature (°C) 60 85 G024 Figure 24. SNR vs AVDD_BUF Supply and Temperature (170 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Typical Characteristics: ADS42LB69 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 92 76 DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 91 DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 75 SNR (dBFS) SFDR (dBc) 90 DRVDD = 1.85 V DRVDD = 1.9 V 89 88 87 86 DRVDD = 1.85 V DRVDD = 1.9 V 74 73 72 85 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 85 Figure 25. SFDR vs DRVDD Supply and Temperature (170 MHz) 76 92 75 90 74 88 73 86 72 84 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Differential Clock Amplitudes (Vpp) 1.9 71 2.1 90 74 88 72 86 70 84 0.1 77 76 90 75 88 74 86 73 84 30 40 50 60 Input Clock Duty Cycle (%) 70 1.9 68 2.1 G028 77 Input Frequency = 170 MHz 92 82 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Differential Clock Amplitudes (Vpp) 94 92 SNR SFDR 76 90 75 88 74 86 73 72 84 72 71 82 Figure 29. Performance vs Clock Duty Cycle (70 MHz) SFDR (dBc) SNR (dBFS) SFDR (dBc) 94 0.3 Figure 28. Performance vs Clock Amplitude (170 MHz) 78 SNR SFDR SFDR SNR 76 Figure 27. Performance vs Clock Amplitude (70 MHz) Input Frequency = 70 MHz G026 92 G027 96 85 78 Input Frequency =170 MHz SFDR (dBc) SFDR (dBc) 94 60 94 SNR (dBFS) SFDR SNR 10 35 Temperature (°C) Figure 26. SNR vs DRVDD Supply and Temperature (170 MHz) 77 96 Input Frequency = 70 MHz −15 G025 SNR (dBFS) −15 Input Frequency = 170 MHz 71 −40 G029 30 40 50 60 Input Clock Duty Cycle (%) 70 SNR (dBFS) 84 −40 71 G030 Figure 30. Performance vs Clock Duty Cycle (170 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 21 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 6.13 Typical Characteristics: ADS42LB49 Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 0 0 fIN = 10 MHz SFDR = 88 dBc SNR = 73.3 dBFS SINAD = 73.2 dBFS THD = 87 dBc SFDR Non HD2, HD3 = 102 dBc −40 −60 −20 Amplitude (dBFS) Amplitude (dBFS) −20 −80 −100 −120 fIN = 170 MHz SFDR = 89 dBc SNR = 72.75 dBFS SINAD = 72.6 dBFS THD = 87 dBc SFDR Non HD2, HD3 = 101 dBc −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 Figure 31. FFT for 10-MHz Input Signal fIN = 300 MHz SFDR = 76 dBc SNR = 71.75 dBFS SINAD = 70.3 dBFS THD = 74 dBc SFDR Non HD2, HD3 = 96 dBc −60 Amplitude (dBFS) Amplitude (dBFS) −40 −80 −40 −60 G032 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 25 G033 Figure 33. FFT for 300-MHz Input Signal 50 75 Frequency (MHz) 100 125 G034 Figure 34. FFT for 10-MHz Input Signal (2.5-VPP Full-Scale) 0 0 fIN = 170 MHz SFDR = 87 dBc SNR = 74 dBFS SINAD = 73.6 dBFS THD = 83 dBc SFDR Non HD2, HD3 = 92 dBc −40 −60 fIN = 300 MHz SFDR = 72 dBc SNR = 72.8 dBFS SINAD = 69.5 dBFS THD = 71 dBc SFDR Non HD2, HD3 = 95 dBc −20 Amplitude (dBFS) −20 Amplitude (dBFS) 125 fIN = 10 MHz SFDR = 85 dBc SNR = 74.8 dBFS SINAD = 74.4 dBFS THD = 84 dBc SFDR Non HD2, HD3 = 103 dBc −20 −100 −80 −100 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 Figure 35. FFT for 170-MHz Input Signal (2.5-VPP Full-Scale) 22 100 0 −20 −120 50 75 Frequency (MHz) Figure 32. FFT for 170-MHz Input Signal 0 −120 25 G031 Submit Documentation Feedback 125 −120 0 25 G035 50 75 Frequency (MHz) 100 125 G036 Figure 36. FFT for 300-MHz Input Signal (2.5-VPP Full-Scale) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Typical Characteristics: ADS42LB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 0 0 Each Tone at −7 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 99 dBFS SFDR = 103 dBFS −40 −60 −80 −100 −120 Each Tone at −36 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 100 dBFS SFDR = 103 dBFS −20 Amplitude (dBFS) Amplitude (dBFS) −20 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 Figure 37. FFT for Two-Tone Input Signal (At –7 dBFS, 46 MHz and 50 MHz) 125 G038 −40 Each Tone at −36 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 106dBFS SFDR = 108 dBFS −20 Amplitude (dBFS) Amplitude (dBFS) 100 0 Each Tone at −7 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 93 dBFS SFDR = 97 dBFS −20 −60 −80 −100 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 −120 125 0 100 125 G040 −92 fIN1 = 46 MHz fIN2 = 50 MHz Two − Tone IMD (dBFS) −94 −98 −100 −102 −104 −106 −108 −36 50 75 Frequency (MHz) Figure 40. FFT for Two-Tone Input Signal (At –36 dBFS, 185 MHz and 190 MHz) −94 −96 25 G039 Figure 39. FFT for Two-Tone Input Signal (At –7 dBFS, 185 MHz and 190 MHz) Two − Tone IMD (dBFS) 50 75 Frequency (MHz) Figure 38. FFT for Two-Tone Input Signal (At –36 dBFS, 46 MHz and 50 MHz) 0 −120 25 G037 fIN1 = 185 MHz fIN2 = 190 MHz −96 −98 −100 −102 −104 −106 −33 −30 −27 −24 −21 −18 −15 Each Tone Amplitude (dBFS) −12 Figure 41. IMD3 vs Input Amplitude (46 MHz and 50 MHz) −9 −7 −108 −36 −33 −30 G041 −27 −24 −21 −18 −15 Each Tone Amplitude (dBFS) −12 −9 −7 G042 Figure 42. IMD3 vs Input Amplitude (185 MHz and 190 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 23 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Typical Characteristics: ADS42LB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 100 77 2−VPP Full−Scale 2.5−VPP Full−Scale 95 2−VPP Full−Scale 2.5−VPP Full−Scale 76 90 75 SNR (dBFS) SFDR (dBc) 85 80 75 70 74 73 72 65 71 60 0 50 100 150 200 250 300 Input Frequency (MHz) 350 70 400 0 50 Figure 43. SFDR vs Input Frequency 10 MHz 70 MHz 130 MHz 350 MHz 400 MHz 491 MHz 10 MHz 70 MHz 100 MHz 130 MHz 76 SNR (dBFS) SFDR (dBc) 170 MHz 230 MHz 270 MHz 90 80 70 170 MHz 230 MHz 270 MHz 350 MHz 400 MHz 491 MHz 72 70 66 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Gain (dB) G045 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB) G046 Figure 46. SNR vs Digital Gain 75.5 77 120 76.5 110 76 100 75.5 75 90 74.5 80 74 70 73.5 60 73 50 72.5 72 −60 −50 −40 −30 −20 Amplitude (dBFS) −10 0 SNR(dBFS) SFDR(dBc) SFDR(dBFS) 120 110 100 90 74.5 80 74 70 73.5 60 73 50 40 72.5 40 30 72 30 20 Figure 47. Performance Across Input Amplitude (70 MHz) Submit Documentation Feedback 130 Input Frequency = 170 MHz 75 SNR (dBFS) SNR(dBFS) SFDR(dBc) SFDR(dBFS) 130 SFDR (dBc,dBFS) Input Frequency = 70 MHz 76 SNR (dBFS) G044 74 Figure 45. SFDR vs Digital Gain 24 400 68 77 71.5 −70 350 78 100 76.5 150 200 250 300 Input Frequency (MHz) Figure 44. SNR vs Input Frequency 110 60 100 G043 71.5 −70 −60 −50 G047 −40 −30 −20 Amplitude (dBFS) −10 0 SFDR (dBc,dBFS) 55 20 G048 Figure 48. Performance Across Input Amplitude (170 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Typical Characteristics: ADS42LB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. SFDR (dBc) 96 Input Frequency = 170 MHz 75.5 94 75 92 74.5 89 74 86 73.5 84 73 82 1.85 74.5 92 74 89 73.5 86 73 83 72.5 80 1.85 G049 Figure 49. Performance vs Input Common-Mode Voltage (70 MHz) 72 1.95 1.875 1.9 1.925 Input Common−Mode Voltage (V) G050 Figure 50. Performance vs Input Common-Mode Voltage (170 MHz) 93 75 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 92 91 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75V AVDD = 1.8 V 74.5 AVDD = 1.85 V AVDD = 1.9 V 74 90 SNR (dBFS) SFDR (dBc) SFDR SNR 95 72.5 1.95 1.875 1.9 1.925 Input Common−Mode Voltage (V) 75 98 SFDR (dBc) SFDR SNR SNR (dBFS) Input Frequency = 70 MHz SNR (dBFS) 76 99 89 88 87 73.5 73 72.5 86 85 84 −40 72 Input Frequency = 170 MHz −15 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 71.5 −40 85 Figure 51. SFDR vs AVDD Supply and Temperature (170 MHz) 10 35 Temperature (°C) 60 85 G052 Figure 52. SNR vs AVDD Supply and Temperature (170 MHz) 94 74.5 AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 93 92 91 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 74 90 SNR (dBFS) SFDR (dBc) −15 G051 89 88 87 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V 73.5 73 72.5 86 85 84 83 −40 72 Input Frequency = 170 MHz −15 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 85 71.5 −40 −15 G053 Figure 53. SFDR vs AVDD_BUF Supply and Temperature (170 MHz) 10 35 Temperature (°C) 60 85 G054 Figure 54. SNR vs AVDD_BUF Supply and Temperature (170 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 25 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Typical Characteristics: ADS42LB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 92 75 DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 91 DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 74.5 89 88 87 73.5 73 72.5 86 72 85 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 85 Figure 55. SFDR vs DRVDD Supply and Temperature (170 MHz) 76 92 75 90 74 88 73 86 72 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Differential Clock Amplitudes (Vpp) 1.9 71 2.1 90 74 88 72 86 70 84 0.1 1.9 68 2.1 G058 77 96 Input Frequency = 170 MHz SNR SFDR 94 92 76 92 75 90 75 90 74 88 74 88 73 86 73 86 72 84 72 84 71 71 82 82 30 40 50 60 Input Clock Duty Cycle (%) 70 Figure 59. Performance vs Clock Duty Cycle (70 MHz) Submit Documentation Feedback SFDR (dBc) SNR (dBFS) SFDR (dBc) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Differential Clock Amplitudes (Vpp) 77 94 26 0.3 Figure 58. Performance vs Clock Amplitude (170 MHz) 78 SNR SFDR SFDR SNR 76 Figure 57. Performance vs Clock Amplitude (70 MHz) Input Frequency = 70 MHz G056 92 G057 96 85 78 Input Frequency = 170 MHz SFDR (dBc) SFDR (dBc) 94 60 94 SNR (dBFS) SFDR SNR 10 35 Temperature (°C) Figure 56. SNR vs DRVDD Supply and Temperature (170 MHz) 77 96 Input Frequency = 70 MHz −15 G055 SNR (dBFS) −15 Input Frequency = 170 MHz 71.5 −40 G059 30 40 50 60 Input Clock Duty Cycle (%) 70 76 SNR (dBFS) 84 −40 84 0.1 DRVDD = 1.85 V DRVDD = 1.9 V 74 SNR (dBFS) SFDR (dBc) 90 DRVDD = 1.85 V DRVDD = 1.9 V 70 G060 Figure 60. Performance vs Clock Duty Cycle (170 MHz) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 6.14 Typical Characteristics: Common Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted. 0 Amplitude (dBFS) −20 −40 −60 CMRR (dB) fIN = 100 MHz SFDR = 82 dBc fCM = 5 MHz 50 − mVPP Amplitude(fIN) = −1 dBFS Amplitude(fCM) = −105 dBFS Amplitude(fIN + fCM) = −90 dBFS Amplitude(fIN − fCM) = −86 dBFS −80 −100 −120 0 25 50 75 Frequency (MHz) 100 125 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 −55 −60 −65 Input Frequency = 10MHz 50−mVPP Signal Superimposed on VCM 0 G061 Figure 61. CMRR FFT 300 G062 Figure 62. CMRR vs Test Signal Frequency 0 −20 fIN = 20 MHz SFDR = 89 dBc fPSRR = 4 MHz 50 − mVPP Amplitude(fIN) = −1 dBFS Amplitude(fPSRR) = −104.5 dBFS Amplitude(fIN + fPSRR) = −92.8 dBFS Amplitude(fIN − fPSRR) = −94.5 dBFS −40 −60 50−mVPP Signal Superimposed on AVDD 100−mVPP Signal Superimposed on AVDD3V −30 −40 PSRR (dB) −20 Amplitude (dBFS) 50 100 150 200 250 Common−Mode Test Signal Frequency (MHz) −80 −50 −60 −70 −100 −80 −120 −90 Input Frequency = 20MHz 0 25 50 75 Frequency (MHz) 100 125 0 50 100 150 200 250 Test Signal Frequency on Supply (MHz) G063 Figure 63. PSRR FFT for AVDD Supply 300 G064 Figure 64. PSRR vs Test Signal Frequency 2 AVDD Power DVDD Power AVDD3V Power Total Power 1.8 Total Power (W) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 Sampling Speed (MSPS) 200 250 G065 Figure 65. Total Power vs Sampling Frequency Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 27 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 6.15 Typical Characteristics: Contour Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 65k-point FFT, unless otherwise noted. 6.15.1 Spurious-Free Dynamic Range (SFDR): General Sampling Frequency, MSPS 240 91 91 220 75 79 87 83 71 67 91 200 180 91 91 160 83 87 75 79 71 67 140 120 87 87 100 91 83 87 80 50 100 65 150 200 250 Input Frequency, MHz 70 75 79 71 75 300 80 67 350 85 400 90 Figure 66. SFDR (0-dB Gain) 240 Sampling Frequency, MSPS 85 220 80 75 70 90 200 180 160 90 95 85 80 75 70 140 120 95 95 100 90 80 100 70 200 75 85 80 75 300 400 Input Frequency, MHz 80 85 70 500 600 90 95 Figure 67. SFDR (6-dB Gain) 28 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 6.15.2 Signal-to-Noise Ratio (SNR): ADS42LB69 240 Sampling Frequency, MSPS 73.5 72.5 73 220 72 71.5 71 200 180 73.5 160 72.5 73 72 71.5 71 140 120 100 73.5 74 80 69.5 50 100 70 70.5 72.5 72 71.5 73 150 200 250 Input Frequency, MHz 71 71.5 72 70.5 71 70 300 72.5 350 73 400 73.5 74 Figure 68. SNR (0-dB Gain, 16 Bits) Sampling Frequency, MSPS 240 220 67.75 68 67.5 67 66.5 200 180 160 67.75 68 67.5 67 66.5 140 120 100 68 80 65 100 65.5 67.75 67.5 200 66 67 66.5 66 300 400 Input Frequency, MHz 66.5 67 65.5 500 600 67.5 68 Figure 69. SNR (6-dB Gain, 16 Bits) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 29 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 6.15.3 Signal-to-Noise Ratio (SNR): ADS42LB49 Sampling Frequency, MSPS 240 73 220 71.5 72 72.5 71 200 180 160 72.5 73 72 71.5 71 70.5 140 120 100 73.5 80 50 69.5 72.5 73 100 70 72 71.5 71 150 200 250 Input Frequency, MHz 70.5 71 71.5 72 70.5 70 300 350 400 73 73.5 72.5 Figure 70. SNR (0-dB Gain, 14 Bits) 240 67.75 67.25 67.5 67 Sampling Frequency, MSPS 220 66.5 66 200 180 160 67.75 67.5 67.25 67 66.5 140 66 120 100 67.5 67.25 67.75 80 50 65 100 65.5 150 200 66.5 67 250 300 350 Input Frequency, MHz 66 66.5 400 66 450 67 65.5 500 550 600 67.5 Figure 71. SNR (6-dB Gain, 14 Bits) 30 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 7 Parameter Measurement Information Sample N tSU_SYNCIN tH_SYNCIN CLKIN SYNCIN Figure 72. Timing Diagram for SYNCINP and SYNCINM Inputs Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 31 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com tA INxP Sample N tPD Data Latency: 14 Clock Cycles CLKINP CLKINM CLKOUTP CLKOUT edges are centered within the data valid window CLKOUTM Dx[15:0] E O E E O E O E tSU O E O E N-1 tH O N CLKOUTM CLKOUTP Dx0P, Dx0M D0 D1 D0 D1 Dx2P, Dx2M D2 D3 D2 D3 Dx4P, Dx4M D4 D5 D4 D5 Dx6P, Dx6M D6 D7 D6 D7 Dx8P, Dx8M D8 D9 D8 D9 Dx10P, Dx10M D10 D11 D10 D11 Dx12P, Dx12M D12 D13 D12 D13 Dx14P, Dx14M (16-Bit Version Only) D14 D15 D14 D15 Sample N Sample N+1 Figure 73. DDR LVDS Output Timing Diagram 32 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 tA INxP Sample N TPD Data Latency: 14 Clock Cycles CLKINP CLKINM DxCLKP DxCLK edges are centered in the data valid window. DxCLKM DxFRAMEM DxFRAMEP N-1 CLKIN, DxCLK, DxFRAMEP (x = A or B) are differential: KvoÇ šZ ZW[ ‰}•]š]À •]Pv o •Z}Áv (}Œ o Œ]šÇ. N N+1 DA0M, DB0M 12 8 4 0 12 8 4 0 12 13 9 5 1 13 9 5 1 13 14 10 6 2 14 10 6 2 14 15 11 7 3 15 11 7 3 15 DA0P, DB0P DA1M, DB1M DA1P, DB1P DA2M, DB2M DA2P, DB2P DA3M, DB3M DA3P, DB3P tsu th Figure 74. QDR LVDS Output Timing Diagram DAn_P DBn_P Logic 0 VODL = -350 mV Logic 1 (1) VODH = +350 mV (1) DAn_M DBn_M VOCM GND (1) With an external 100-Ω termination. Figure 75. DDR LVDS Output Voltage Levels Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 33 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8 Detailed Description 8.1 Overview The ADS42LB69 and ADS42LB49 is a family of high linearity, buffered analog input, dual-channel ADCs with maximum sampling rates up to 250 MSPS employing either a quadruple data rate (QDR) or double data rate (DDR) LVDS interface. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 14 clock cycles. The output is available in LVDS logic levels in SPI-programmable QDR or DDR options. 8.2 Functional Block Diagrams ADS42LB69 16-Bit ADC INAP, INAM Digital Gain and Test Patterns CLKOUTP, CLKOUTM DDR LVDS Delay Digital Block 16-Bit ADC INBP, INBM Common Mode Output Formatter Digital Gain and Test Patterns DB[15:0]P, DB[15:0]M DDR LVDS CTRL2 CTRL1 SDOUT SEN SCLK SDATA Configuration Registers RESET VCM DA[15:0]P, DA[15:0]M Output Formatter Divide by 1,2,4 CLKINP, CLKINM SYNCINP, SYNCINM Digital Block Copyright © 2016, Texas Instruments Incorporated Figure 76. ADS42LB69 DDR LVDS ADS42LB49 14-Bit ADC INAP, INAM Digital Gain and Test Patterns CLKOUTP, CLKOUTM DDR LVDS Delay Digital Block 14-Bit ADC DB[13:0]P, DB[13:0]M DDR LVDS CTRL2 CTRL1 Configuration Registers RESET SEN SCLK Common Mode Output Formatter Digital Gain and Test Patterns SDATA SDOUT INBP, INBM VCM DA[13:0]P, DA[13:0]M Output Formatter Divide by 1,2,4 CLKINP, CLKINM SYNCINP, SYNCINM Digital Block Copyright © 2016, Texas Instruments Incorporated Figure 77. ADS42LB49 DDR LVDS 34 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Functional Block Diagrams (continued) ADS42LB49, ADS42LB69 OVRA Digital Block 14-, 16-Bit ADC INAP, INAM CLKINP, CLKINM Output Formatter Digital Gain and Test Patterns DAFRAMEP, AFRAMEM DACLKP, DACLKM QDR LVDS DA[3:0]P, DA[3:0]M Divide by 1,2,4 SYNCINP, SYNCINM Delay 14-, 16-Bit ADC INBP, INBM DB[3:0]P, B[3:0]MM Digital Block Output Formatter Digital Gain and Test Patterns DBCLKP, BCLKM DBFRAMEP, BFRAMEM QDR LVDS OVRB Common Mode CTRL1 CTRL2 SDATA SDOUT SEN SCLK Configuration Registers RESET VCM Copyright © 2016, Texas Instruments Incorporated Figure 78. ADS42LB69, ADS42LB49 QDR LVDS 8.3 Feature Description 8.3.1 Digital Gain The device includes gain settings that can be used to obtain improved SFDR performance (compared to no gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally. Table 3 shows how full-scale input voltage changes when digital gain are programmed in 1-dB steps. Refer to Table 16 to set digital gain using a serial interface register. SFDR improvement is achieved at the expense of SNR; for a 1-dB increase in digital gain, SNR degrades approximately between 0.5 dB and 1 dB (refer to Figure 15 and Figure 16). Therefore, gain can be used as a trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage. Table 3. Full-Scale Range Across Gains (1) DIGITAL GAIN FULL-SCALE INPUT VOLTAGE –2 dB 2.5 VPP (1) –1 dB 2.2 VPP 0 dB (default) 2.0 VPP 1 dB 1.8 VPP 2 dB 1.6 VPP 3 dB 1.4 VPP 4 dB 1.25 VPP 5 dB 1.1 VPP 6 dB 1.0 VPP Shaded cells indicate performance settings used in the Electrical Characteristics and Typical Characteristics. 8.3.2 Input Clock Divider The device is equipped with an internal divider on the clock input. This divider allows operation with a faster input clock, simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for operation with a 250-MHz clock. The divide-by-2 option supports a maximum 500-MHz input clock and the divide-by-4 option supports a maximum 1-GHz input clock frequency. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 35 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.3.3 Overrange Indication The device provides two different overrange indications: normal OVR and fast OVR. Normal OVR (default) is triggered if the final 16-bit data output exceeds the maximum code value. Normal OVR latency is the same as the output data (that is, 14 clock cycles). Fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after a latency of only nine clock cycles, thus enabling a quicker reaction to an overrange event. 8.3.3.1 OVR in a QDR Pinout In a QDR interface, the overrange indication is output on the OVRA and OVRB pins (pin 54 and 59) in 1.8-V CMOS logic levels. The same overrange indication can also be made available on the bidirectional CTRL1, CTRL2 pins by using the PDN/OVR FOR CTRL PINS register bit, as described in Figure 79. Using the FAST OVR EN register bit, the fast OVR indication can be presented on these pins instead of normal OVR. Pin 59 (OVRB) Pin 54 (OVRA) QDR Pinout (Default) Pin 12 (CTRL2) Pin 37 (CTRL1) NOTE: By default, normal OVR is output on the OVRA and OVRB pins. Using the FAST OVR EN register bit, fast OVR can be presented on these pins instead. NOTE: When the PDN/OVR FOR CTRL PINS register bit is set, the CTRL1 and CTRL2 pins function as output pins and carry the same information as the OVRA and OVRB pins (respectively) in 1.8-V CMOS logic levels. Figure 79. OVR in a QDR Pinout 36 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.3.3.2 OVR in a DDR Pinout In the DDR interface, there are no dedicated pins to provide overrange indication. However, by choosing the appropriate register bits, OVR can be transferred on the LSB of 16-bit output data as well as on the bidirectional CTRL1 and CTRL2 pins, as shown in Figure 80. Use the OVR ON LSB register bits to transfer channel A and channel B OVR information. Channel A OVR information is transferred on pins 39 and 40 in LVDS logic levels. Channel B OVR information is transferred on pins 9 and 10. Note that these pins are Dx0P, Dx0M in the ADS42LB69 and are NC in the ADS42LB49. Pin 9 (DB0M) Pin 40 (DA0P) Pin 10 (DB0P) Pin 39 (DA0M) DDR Pinout (Set the DDR-QDR register bit.) Pin 12 (CTRL2) Pin 37 (CTRL1) By default, the DDR pinout does not provide OVR information. Use the PDN/OVR FOR CTRL PINS register bit to transfer OVR information. Channel A OVR information is transferred on the CTRL1 pin and channel B OVR information is transferred on the CTRL2 pin in 1.8-V CMOS logic levels. Figure 80. OVR in a DDR Pinout The FAST OVR EN register bit can be used to transfer fast OVR indication on the CTRL1 and CTRL2 pins instead of normal OVR. The OVR ON LSB register bits can be used to transfer fast OVR indication on the LSB bits (Dx0P, Dx0M), as described in Table 4. Table 4. Fast OVR Transfer OVR ON LSB BIT SETTINGS PIN STATE FOR PINS 9, 10 AND 39, 40 00 D0 and D1 are output in the ADS42LB69, NC for the ADS42LB49 01 Fast OVR in LVDS logic level 10 Normal OVR in LVDS logic level 11 D0 and D1 are output in the ADS42LB69, NC for the ADS42LB49 Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 37 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Table 5 summarizes the availability of OVR information on different pins in the QDR and DDR interfaces and the required register settings. Table 5. OVR Information Availability OVR INFORMATION AVAILABILITY INTERFACE QDR DDR 8.3.3.3 SETTINGS PINS 9, 10 AND 39, 40 (LVDS Logic Levels) PINS 12 AND 37 (CMOS Logic Levels) PINS 54 AND 59 (CMOS Logic Levels) Default Not applicable No Yes Use the PDN/OVR FOR CTRL PINS register bits Not applicable Yes Yes Default No No Not applicable Use the OVR ON LSB register bits Yes No Not applicable Use the PDN/OVR FOR CTRL PINS register bits No Yes Not applicable Use the OVR ON LSB and PDN/OVR FOR CTRL PINS register bits Yes Yes Not applicable Programming Threshold for Fast OVR The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. Fast OVR is triggered nine output clock cycles after the overload condition occurs. The threshold voltage amplitude at which fast OVR is triggered is Equation 1: 1 × [the decimal value of the FAST OVR THRESH bits] / 127 (1) When digital gain is programmed (for gain values > 0 dB ), the threshold voltage amplitude is Equation 2: 10–Gain / 20 x [the decimal value of the FAST OVR THRESH bits] / 127 38 Submit Documentation Feedback (2) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.3.4 LVDS Buffer The equivalent circuit of each LVDS output buffer is shown in Figure 81. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination. VDIFF High Low OUTP External 100-W Load OUTM VOCM ROUT VDIFF Low High NOTE: Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing. Figure 81. LVDS Buffer Equivalent Circuit The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV. Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as shown in Figure 82. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100-Ω termination. The mode can be enabled for LVDS output data (and for the frame clock in the QDR interface) buffers by setting the LVDS DATA STRENGTH register bit. For LVDS output clock buffers (applicable for both DDR and QDR interfaces), set both the LVDS CLKOUT STRENGTH EN and LVDS CLKOUT STRENGTH register bits to '1'. The buffer output impedance behaves in the same way as a source-side series termination. Absorbing reflections from the receiver end helps improve signal integrity. Receiver Chip 1 (for example, GC5330) DAnP, DAnM CLKIN1 100 W CLKIN2 100 W CLKOUTP CLKOUTM DBnP, DBnM Receiver Chip 2 Device LVDS CLKOUT STRENGTH EN and LVDS CLKOUT STRENGTH = 1 Figure 82. LVDS Buffer Differential Termination Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 39 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.3.5 Output Data Format Two output data formats are supported: twos complement and offset binary. The format can be selected using the DATA FORMAT serial interface register bit. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 3FFFh for the ADS42LB49 and ADS42LB69 in offset binary output format; the output code is 1FFFh for the ADS42LB49 and ADS42LB69 in twos complement output format. For a negative input overdrive, the output code is 0000h in offset binary output format and 2000h for the ADS42LB49 and ADS42LB69 in twos complement output format. 8.4 Device Functional Modes 8.4.1 Digital Output Information The ADS42LB49 and ADS42LB69 provides 14- and 16-bit digital data for each channel and output clock synchronized with the data. 8.4.1.1 Output Interface Digital outputs are available in quadruple data rate (QDR) LVDS, and double data rate (DDR) LVDS formats, selectable by the DDR – QDR serial register bit. 8.4.1.2 DDR LVDS Outputs In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 83. Pins CLKOUTP CLKOUTM LVDS Output Buffers Dx0P 16-Bit ADC Data, (1) Channel X Dx0M Dx2P Dx2M Dx4P Dx4M Dx6P Dx6M Dx8P Dx8M Dx10P Dx10M Dx12P Dx12M Dx14P Dx14M Output Clock Data Bits D0, D1 Data Bits D2, D3 Data Bits D4, D5 Data Bits D6, D7 Data Bits D8, D9 Data Bits D10, D11 Data Bits D12, D13 Data Bits D14, D15 (1) X = A or B (for channel A or channel B). Figure 83. DDR LVDS Interface 40 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Device Functional Modes (continued) Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3, D5, and so forth) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be used to capture all the data bits, as shown in Figure 84. CLKOUTM CLKOUTP DA0, DB0 D0 D1 D0 D1 DA2, DB2 D2 D3 D2 D3 DA4, DB4 D4 D5 D4 D5 DA6, DB6 D6 D7 D6 D7 DA8, DB8 D8 D9 D8 D9 DA10, DB10 D10 D11 D10 D11 DA12, DB12 D12 D13 D12 D13 DA14, DB15 (ADS42LB69 Only) D14 D15 D14 D15 Sample N Sample N + 1 Figure 84. DDR LVDS Interface Timing Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 41 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com Device Functional Modes (continued) 8.4.1.3 QDR LVDS Outputs The data bits and output clocks are output using low-voltage differential signal (LVDS) levels. Four data bits are multiplexed and output on each LVDS differential data pair and are accompanied by a bit clock and a frame clock for each channel, as shown in Figure 85. QDR LVDS Data Buffers Dx0P(1), Dx0M Dx1P, Dx1M Serializer Dx2P, Dx2M 16-Bit Data Dx3P, Dx3M DxFRAMEP, DxFRAMEM Device (1) X = channels A and B. Figure 85. QDR LVDS Interface 42 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Device Functional Modes (continued) Figure 86 shows the QDR interface bit order for the ADS42LB69 and Figure 87 shows the QDR interface bit order for the ADS42LB49. DACLKM, DBCLKM DACLKM, DBCLKM DACLKP, DBCLKP DACLKP, DBCLKP DAFRAMEM, DBFRAMEM DAFRAMEM, DBFRAMEM DAFRAMEP, DBFRAMEP DAFRAMEP, DBFRAMEP DA0, DB0 12 8 4 0 12 8 4 0 12 DA1, DB1 13 9 5 1 13 9 5 1 13 DA2, DB2 14 10 6 2 14 10 6 2 14 DA3, DB3 15 11 7 3 15 11 7 3 15 Sample N DA0, DB0 10 6 2 Static 10 6 2 Static 10 DA1, DB1 11 7 3 Static 11 7 3 Static 11 DA2, DB2 12 8 4 0 12 8 4 0 12 DA3, DB3 13 9 5 1 13 9 5 1 13 Sample N Sample N+1 Figure 86. QDR LVDS Interface Timing: ADS42LB69 Sample N+1 Figure 87. QDR LVDS Interface Timing: ADS42LB49 8.5 Programming 8.5.1 Device Configuration The ADS42LB49 and ADS42LB69 can be configured using a serial programming interface, as described in this section. In addition, the device has two bidirectional parallel pins (CTRL1 and CTRL2). By default, these pins act as input pins and control the power-down modes, as described in Table 6 and Table 7. These pins can be programmed as output pins that deliver overrange information by setting the PDN/OVR_FOR_CTRL_PINS register bit. Table 6. PDN/OVR_FOR_CTRL_PINS Bit (Set to '0') CTRL2 CTRL1 PIN DIRECTION FUNCTION Low Low Input Default operation Low High Input Channel A power-down High Low Input Channel B powers down in QDR mode. Do not use in DDR mode. High High Input Channels A and B power-down Table 7. PDN/OVR_FOR_CTRL_PINS Bit (Set to '1') CTRL2 CTRL1 PIN DIRECTION Carries OVR for channel B Carries OVR for channel A Output Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 43 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.5.2 Details of Serial Interface The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and SDOUT (serial interface data output) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 16th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface can work with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty cycle. 8.5.2.1 Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns); see Figure 88 and Table 8. If required, serial interface registers can later be cleared during operation by: 1. Either through a hardware reset or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 08h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. Power Supply AVDD, AVDD3V, DRVDD t1 RESET t2 t3 SEN NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin. Figure 88. Reset Timing Diagram Table 8. Reset Timing (1) TEST CONDITIONS t1 Power-on delay Delay from AVDD and DRVDD power-up to active RESET pulse t2 Reset pulse width Active RESET signal pulse width t3 Register write delay Delay from RESET disable to SEN active (1) 44 MIN TYP MAX UNIT 1 ms 10 ns 1 100 µs ns Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless otherwise noted. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.5.2.2 Serial Register Write The internal register of the ADS42LB49 and ADS42LB69 can be programmed following these steps: 1. Drive SEN pin low 2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address) 3. Set bit A6 in the address field to ‘0’ 4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content must be written 5. Write 8 bit data which is latched in on the rising edge of SCLK. Figure 89 and Table 9 illustrate these steps. Register Address SDATA R/W 0 A5 A4 A3 A2 A1 Register Data A0 D7 D6 D5 D4 D3 =0 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 89. Serial Register Write Timing Diagram Table 9. Serial Interface Timing (Only when Serial Interface is Used) (1) MIN MAX UNIT 20 MHz fSCLK SCLK frequency (equal to 1 / tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDIO setup time 25 ns tDH SDIO hold time 25 ns (1) > dc TYP Typical values are at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD3V = 3.3 V, and AVDD = DRVDD = 1.8 V, unless otherwise noted. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 45 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.5.2.3 Serial Register Readout The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This read-back mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. 1. Drive SEN pin low 2. Set the R/W bit (A7) to '1'. This setting disables any further writes to the registers 3. Set bit A6 in the address field to 0. 4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content has to be read. 5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin. 6. The external controller can latch the contents at the SCLK falling edge. 7. To enable register writes, reset the R/W register bit to '0'. Figure 90 illustrates these steps. When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Register Address SDATA R/W 0 A5 A4 A3 A2 A1 Register Data: don’t care A0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 =1 Register Read Data SDOUT D7 D6 D5 D4 D3 D2 SCLK SEN Figure 90. Serial Register Readout Timing Diagram 46 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.6 Register Maps The serial interface registers are summarized in Table 10. Table 10. Summary of Serial Interface Registers REGISTER ADDRESS REGISTER DATA A[7:0] (Hex) D7 D6 D5 D4 D3 D2 06 1 0 0 0 0 0 07 0 0 0 0 0 STDBY DATA FORMAT DIS CTRL PINS 08 PDN CHA PDN CHB SYNCIN DELAY 0 0 0B CHA GAIN CHA GAIN EN CHBGAIN CHB GAIN EN 0 1 0F 1 0 1 RESET FLIP DATA OVR ON LSB 1 CHA TEST PATTERNS 10 D0 CLK DIV TEST PAT ALIGN 0C 0D D1 0 FAST OVR ON PIN CHB TEST PATTERNS CUSTOM PATTERN 1 (15:8) 11 CUSTOM PATTERN 1 (7:0) 12 CUSTOM PATTERN 2 (15:8) 13 CUSTOM PATTERN 2 (7:0) 14 0 0 0 0 15 0 0 0 0 16 0 0 17 LVDS CLK STRENGTH EN 18 0 1F Always write '0' 20 0 LVDS CLK STRENGTH LVDS DATA STRENGTH DISABLE OUTPUT CHA DISABLE OUTPUT CHB 0 0 0 DDR – QDR DDR OUTPUT TIMING 0 0 QDR TIMING CHA INV CLK OUT CHA 0 QDR TIMING CHB INV CLK OUT CHB FAST OVR THRESHOLD 0 0 0 0 0 0 PDN/OVR FOR CTRL PINS Table 11. High-Frequency Modes Summary REGISTER ADDRESS VALUE 0Dh 90h Enable high-frequency modes for input frequencies greater than 250 MHz. 0Eh 90h Enable high-frequency modes for input frequencies greater than 250 MHz. DESCRIPTION Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 47 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.6.1 Description of Serial Interface Registers 8.6.1.1 Register 6 (offset = 06h) [reset = 80h] Figure 91. Register 6 D7 1 W-1h D6 0 W-0h D5 0 W-0h D4 0 W-0h D3 0 W-0h D2 0 W-0h D1 D0 CLK DIV R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 12. (For example, CONTROL_REVISION Register) Field Descriptions Bit Field Type Reset Description D7 1 W 1h Always write '1' D[6:2] 0 W 0h Always write '0' 0h Internal clock divider for input sample clock 00 : Divide-by-1 (clock divider bypassed) 01 : Divide-by-2 10 : Divide-by-1 11 : Divide-by-4 D[1:0] CLK DIV R/W 8.6.1.2 Register 7 (offset = 07h) [reset = 00h] Figure 92. Register 7 D7 0 W-0h D6 0 W-0h D5 0 W-0h D4 0 W-0h D3 0 W-0h D2 D1 SYNCIN DELAY R/W-0h D0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 13. Register 7 Field Descriptions Bit D[7:3] D[2:0] 48 Field Type Reset Description 0 W 0h Always write '0' 0h Controls the delay of the SYNCIN input with respect to the input clock. Typical values for the expected delay of different settings are: 000 : 0-ps delay 001 : 60-ps delay 010 : 120-ps delay 011 : 180-ps delay 100 : 240-ps delay 101 : 300-ps delay 110 : 360-ps delay 111 : 420-ps delay SYNCIN DELAY Submit Documentation Feedback R/W Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.6.1.3 Register 8 (offset = 08h) [reset = 00h] Figure 93. Register 8 D7 D6 D5 PDN CHA PDN CHB STDBY R/W-0h R/W-0h R/W-0h D4 DATA FORMAT R/W-0h D3 DIS CTRL PINS R/W-0h D2 TEST PAT ALIGN R/W-0h D1 D0 0 RESET W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 14. Register 8 Field Descriptions Bit Field Type Reset Description PDN CHA, PDN CHB R/W 0h Power-down channels A and B. Effective only when bit DIS CTRL PINS is set to '1'. 00 : Normal operation 01 : Channel B powers down. Use only if the QDR interface is selected. Do not use in the DDR interface. 10 : Channel A powers down. Functions in both QDR and DDR interfaces. 11 : Both channels power down. Functions in both QDR and DDR interfaces. D5 STDBY R/W 0h Dual ADC is placed into standby mode 0 : Normal operation 1 : Power down D4 DATA FORMAT R/W 0h Digital output data format 0 : Twos complement 1 : Offset binary D[7:6] D3 DIS CTRL PINS R/W 0h Disables power-down control from the CTRL1, CTRL2 pins. This bit also functions as an enable bit for the INV CLK OUT CHA, INV CLK OUT CHB, and DDR OUTPUT TIMING bits. 0 : CTRL1 and CTRL2 pins control power-down options for channels A and B 1 : The PDN CHA and PDN CHB register bits determine power-down options for channels A and B. The INV CLK OUT CHA, INV CLK OUT CHB, and DDR OUTPUT TIMING register bits become effective. D2 TEST PAT ALIGN R/W 0h Aligns test patterns of two channels 0 : Test patterns for channel A and channel B are free running 1 : Test patterns for both channels are synchronized D1 0 W 0h Always write '0' D0 RESET R/W 0h Software reset applied This bit resets all internal registers to the default values and selfclears to ‘0’ Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 49 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.6.1.4 Register B (offset = 0Bh) [reset = 00h] Figure 94. Register B D7 D6 D5 CHA GAIN R/W-0h D4 D3 D2 CHA GAIN EN R/W-0h D1 0 W-0h D0 FLIP DATA R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 15. Register B Field Descriptions Bit Field Type Reset Description CHA GAIN R/W 0h Digital gain for channel A. Effective when the CHA GAIN EN register bit is set to '1'. Bit descriptions are listed in Table 16. D2 CHA GAIN EN R/W 0h Digital gain enable bit for channel A 0 : Digital gain disabled 1 : Digital gain enabled D1 0 W 0h Always write '0' 0h Flips bit order on the LVDS output bus (LSB versus MSB) 0 : Normal operation 1 : Output bus flipped. In the ADS42LB69, output data bit D0 becomes D15, D1 becomes D14, and so forth. In the ADS42LB49, output data bit D0 becomes D13, D1 becomes D12, and so forth. D[7:3] D0 FLIP DATA R/W Table 16. Digital Gain for Channel A DIGITAL GAIN FOR DIGITAL GAIN (dB) CHANNEL A 50 MAX INPUT VOLTAGE (VPP) DIGITAL GAIN FOR DIGITAL GAIN (dB) CHANNEL A MAX INPUT VOLTAGE (VPP) 00000 0 2.0 01010 1.5 1.7 00001 Do not use — 01011 2 1.6 00010 Do not use — 01100 2.5 1.5 00011 –2.0 2.5 01101 3 1.4 00100 –1.5 2.4 01110 3.5 1.3 00101 –1.0 2.2 01111 4 1.25 00110 –0.5 2.1 10000 4.5 1.2 00111 0 2.0 10001 5 1.1 01000 0.5 1.9 10010 5.5 1.05 01001 1 1.8 10011 6 1.0 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.6.1.5 Register C (offset = 0Ch) [reset = 00h] Figure 95. Register C D7 D6 D5 CHB GAIN R/W-0h D4 D3 D2 CHB GAIN EN R/W-0h D1 D0 OVR ON LSB R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 17. Register C Field Descriptions Bit D[7:3] D2 D[1:0] Field Type Reset Description CHB GAIN R/W 0h Digital gain for channel B. Effective when the CHB GAIN EN register bit is set to '1'. Bit descriptions are listed in Table 18. CHB GAIN EN R/W 0h Digital gain enable bit for channel B 0 : Digital gain disabled 1 : Digital gain disabled 0h Functions only with the DDR interface option. Replaces the LSB pair of 16-bit data (D1, D0) with OVR information. See the Overrange Indication section. 00 : D1 and D0 are output in the ADS42LB69, NC for the ADS42LB49 01 : Fast OVR in LVDS logic level 10 : Normal OVR in LVDS logic level 11 : D1 and D0 are output in the ADS42LB69, NC for the ADS42LB49 OVR ON LSB R/W Table 18. Digital Gain for Channel B DIGITAL GAIN FOR DIGITAL GAIN (dB) CHANNEL B MAX INPUT VOLTAGE (VPP) DIGITAL GAIN FOR DIGITAL GAIN (dB) CHANNEL B MAX INPUT VOLTAGE (VPP) 00000 0 2.0 01010 1.5 1.7 00001 Do not use — 01011 2 1.6 00010 Do not use — 01100 2.5 1.5 00011 –2.0 2.5 01101 3 1.4 00100 –1.5 2.4 01110 3.5 1.3 00101 –1.0 2.2 01111 4 1.25 00110 –0.5 2.1 10000 4.5 1.2 00111 0 2.0 10001 5 1.1 01000 0.5 1.9 10010 5.5 1.05 01001 1 1.8 10011 6 1.0 Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 51 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.6.1.6 Register D (offset = 0Dh) [reset = 6Ch] Figure 96. Register D D7 0 W-0h D6 1 W-1h D5 1 W-1h D4 0 W-0h D3 1 W-1h D2 1 W-1h D1 0 W-0h D0 FAST OVR ON PIN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 19. Register D Field Descriptions Bit Field Type Reset Description D7 0 W 0h Always write '0' D[6:5] 1 W 1h Always write '1' D4 0 W 0h Always write '0' D[3:2] 1 W 1h Always write '1' D1 0 W 0h Always write '0' D0 FAST OVR ON PIN R/W 0h Determines whether normal OVR or fast OVR information is brought on the OVRx, CTRL1, and CTRL2 pins. See the Overrange Indication section. 0 : Normal OVR available on the OVRx, CTRL1, and CTRL2 pins 1 : Fast OVR available on the OVRx, CTRL1, and CTRL2 pins 8.6.1.7 Register F (offset = 0Fh) [reset = 00h] Figure 97. Register F D7 D6 D5 CHA TEST PATTERNS R/W-0h D4 D3 D2 D1 CHB TEST PATTERNS R/W-0h D0 LEGEND: R/W = Read/Write; -n = value after reset 52 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Table 20. Register F Field Descriptions Bit D[7:4] D[3:0] Field CHA TEST PATTERNS CHB TEST PATTERNS Type R/W R/W Reset Description 0h Channel A test pattern programmability 0000 : Normal operation 0001 : Outputs all 0s 0010 : Outputs all 1s 0011 : Outputs toggle pattern: In the ADS42LB69, data are an alternating sequence of 1010101010101010 and 0101010101010101. In the ADS42LB49, data alternate between 10101010101010 and 01010101010101. 0100 : Output digital ramp: In the ADS42LB69, data increment by 1 LSB every clock cycle from code 0 to 65535. In the ADS42LB49 data increment by 1 LSB every fourth clock cycle from code 0 to 16383. 0101 : Increment pattern: Do not use 0110 : Single pattern: In the ADS42LB69, data are the same as programmed by the CUSTOM PATTERN 1[15:0] registers bits. In the ADS42LB49, data are the same as programmed by the CUSTOM PATTERN 1[15:2] register bits. 0111 : Double pattern: In the ADS42LB69, data alternate between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN 2[15:0]. In the ADS42LB49 data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2]. 1000 : Deskew pattern: In the ADS42LB69, data are AAAAh. In the ADS42LB49, data are 3AAAh. 1001 : Do not use 1010 : PRBS pattern: Data are a sequence of pseudo-random numbers 1011 : 8-point sine wave: In the ADS42LB69, data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos complement format: 1, 9598, 32768, 55938, 65535, 55938, 32768, and 9598. In the ADS42LB49, data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos complement format: 0, 2399, 8192, 13984, 16383, 13984, 8192, and 2399. 0h Channel B test pattern programmability 0000 : Normal operation 0001 : Outputs all 0s 0010 : Outputs all 1s 0011 : Outputs toggle pattern: In the ADS42LB69, data are an alternating sequence of 1010101010101010 and 0101010101010101. In the ADS42LB49, data alternate between 10101010101010 and 01010101010101. 0100 : Output digital ramp: In the ADS42LB69, data increment by 1 LSB every clock cycle from code 0 to 65535. In the ADS42LB49 data increment by 1 LSB every fourth clock cycle from code 0 to 16383. 0101 : Increment pattern: Do not use 0110 : Single pattern: In the ADS42LB69, data are the same as programmed by the CUSTOM PATTERN 1[15:0] registers bits. In the ADS42LB49, data are the same as programmed by the CUSTOM PATTERN 1[15:2] register bits. 0111 : Double pattern: In the ADS42LB69, data alternate between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN 2[15:0]. In the ADS42LB49 data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2]. 1000 : Deskew pattern: In the ADS42LB69, data are AAAAh. In the ADS42LB49, data are 3AAAh. 1001 : Do not use 1010 : PRBS pattern: Data are a sequence of pseudo-random numbers 1011 : 8-point sine wave: In the ADS42LB69, data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos complement format: 1, 9598, 32768, 55938, 65535, 55938, 32768, and 9598. In the ADS42LB49, data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos complement format: 0, 2399, 8192, 13984, 16383, 13984, 8192, and 2399. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 53 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.6.1.8 Register 10 (offset = 10h) [reset = 00h] Figure 98. Register 10 D7 D6 D5 D4 D3 CUSTOM PATTERN 1[15:8] R/W-0h D2 D1 D0 LEGEND: R/W = Read/Write; -n = value after reset Table 21. Register 10 Field Descriptions Bit D[7:0] Field Type Reset Description CUSTOM PATTERN 1[15:8] R/W 0h Sets the CUSTOM PATTERN 1[15:8] with these bits for both channels 8.6.1.9 Register 11 (offset = 11h) [reset = 00h] Figure 99. Register 11 D7 D6 D5 D4 D3 CUSTOM PATTERN 1[7:0] R/W-0h D2 D1 D0 LEGEND: R/W = Read/Write; -n = value after reset Table 22. Register 11 Field Descriptions Bit D[7:0] Field Type Reset Description CUSTOM PATTERN 1[7:0] R/W 0h Sets the CUSTOM PATTERN 1[7:0] with these bits for both channels 8.6.1.10 Register 12 (offset = 12h) [reset = 00h] Figure 100. Register 12 D7 D6 D5 D4 D3 CUSTOM PATTERN 2[15:8] R/W-0h D2 D1 D0 LEGEND: R/W = Read/Write; -n = value after reset Table 23. Register 12 Field Descriptions Bit D[7:0] Field Type Reset Description CUSTOM PATTERN 2[15:8] R/W 0h Sets the CUSTOM PATTERN 2[15:8] with these bits for both channels 8.6.1.11 Register 13 (offset = 13h) [reset = 00h] Figure 101. Register 13 D7 D6 D5 D4 D3 CUSTOM PATTERN 2[7:0] R/W-0h D2 D1 D0 LEGEND: R/W = Read/Write; -n = value after reset Table 24. Register 13 Field Descriptions Bit D[7:0] 54 Field Type Reset Description CUSTOM PATTERN 2[7:0] R/W 0h Sets the CUSTOM PATTERN 2[7:0] with these bits for both channels Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.6.1.12 Register 14 (offset = 14h) [reset = 00h] Figure 102. Register 14 D7 D6 D5 D4 0 0 0 0 W-0h W-0h W-0h W-0h D3 LVDS CLK STRENGTH R/W-0h D2 LVDS DATA STRENGTH R/W-0h D1 DISABLE OUTPUT CHA R/W-0h D0 DISABLE OUTPUT CHB R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 25. Register 14 Field Descriptions Bit D[7:4] D3 Field Type Reset Description 0 W 0h Always write '0' 0h Increases the LVDS drive strength of the CLKOUTP, CLKOUTM buffers in the DDR pinout and the DxCLKP, DxCLKM buffers in the QDR pinout 0 : LVDS output clock buffer at default strength used with 100-Ω external termination 1 : LVDS output clock buffer has double strength used with 50-Ω external termination. Effective only when the LVDS CLK STRENGTH EN bit is set to '1'. LVDS CLK STRENGTH R/W D2 LVDS DATA STRENGTH R/W 0h Increases the LVDS drive strength 0 : LVDS output data buffers (including frame clock buffers in the QDR interface) at default strength used with a 100-Ω external termination 1 : LVDS output data buffers (including frame clock buffers in the QDR interface) at double strength used with a 50-Ω external termination D1 DISABLE OUTPUT CHA R/W 0h Disables LVDS output buffers of channel A 0 : Normal operation 1 : Channel A output buffers are in 3-state D0 DISABLE OUTPUT CHB R/W 0h Disables LVDS output buffers of channel B 0 : Normal operation 1 : Channel B output buffers are in 3-state 8.6.1.13 Register 15 (offset = 15h) [reset = 00h] Figure 103. Register 15 D7 0 W-0h D6 0 W-0h D5 0 W-0h D4 0 W-0h D3 0 W-0h D2 0 W-0h D1 0 W-0h D0 DDR – QDR R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 26. Register 15 Field Descriptions Bit D[7:1] D0 Field Type Reset Description 0 W 0h Always write '0' DDR – QDR R/W 0h Selects output interface between DDR and QDR LVDS mode 0 : QDR LVDS mode 1 : DDR LVDS mode Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 55 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.6.1.14 Register 16 (offset = 16h) [reset = 00h] Figure 104. Register 16 D7 0 W-0h D6 0 W-0h D5 D4 D3 DDR OUTPUT TIMING R/W-0h D2 D1 D0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 27. Register 16 Field Descriptions Field Type Reset Description D[7:6] Bit 0 W 0h Always write '0' D[5:1] DDR OUTPUT TIMING R/W 0h Effective only when the DIS CTRL PINS bit is set to '1'. Bit descriptions are listed in Table 28. 0 W 0h Always write '0' D0 Table 28. DDR Output Timing (After Setting Bits DIS CTRL PINS To '1') DELAY (ps) IN OUTPUT CLOCK WITH RESPECT TO DEFAULT POSITION 56 BIT SETTING fS = 250 MSPS fS = 200 MSPS fS = 150 MSPS fS = 100 MSPS 00101 –180 –220 –310 –440 00111 –100 –130 –190 –260 00000 0 0 0 0 01101 120 130 170 260 01110 230 240 330 520 01011 320 360 480 740 10100 400 460 620 940 10000 500 600 790 1220 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.6.1.15 Register 17 (offset = 17h) [reset = 00h] Figure 105. Register 17 D7 LVDS CLK STRENGTH EN R/W-0h D6 D5 D4 D3 D2 D1 D0 0 QDR OUTPUT TIMING CHA INVCLK OUT CHA W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 29. Register 17 Field Descriptions Bit Field Type Reset Description D7 LVDS CLK STRENGTH EN R/W 0h 0 : Default 1 : Enables clock strength programmability with the LVDS CLK STRENGTH bit D6 0 W 0h Always write '0' QDR OUTPUT TIMING CHA R/W 0h Adjusts position of output data clock on channel A with respect to output data. Bit settings are listed in Table 30. 0h Inverts polarity of the output clock for channel A (QDR mode only) 0 : Normal operation 1 : Polarity of channel A output clock DACLKP, DACLKM is inverted. Effective only when the DIS CTRL PINS bit is set to '1'. D[5:1] D0 INV CLK OUT CHA R/W Table 30. QDR Timing Channel A Timing DELAY (ps) IN OUTPUT CLOCK WITH RESPECT TO DEFAULT POSITION BIT SETTING fS = 250 MSPS fS = 200 MSPS fS = 150 MSPS fS = 100 MSPS 00101 –80 –120 –150 –225 00111 –55 –75 –90 –130 00000 0 0 0 0 01101 55 65 90 130 01110 95 115 165 235 01011 140 165 230 350 10100 180 220 290 450 10000 230 290 370 565 Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 57 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 8.6.1.16 Register 18 (offset = 18h) [reset = 00h] Figure 106. Register 18 D7 0 W-0h D6 0 W-0h D5 D4 D3 D2 QDR OUTPUT TIMING CHB R/W-0h D1 D0 INVCLK OUT CHB R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 31. Register 18 Field Descriptions Field Type Reset Description D[7:6] Bit 0 W 0h Always write '0' D[5:1] QDR OUTPUT TIMING CHB R/W 0h Adjusts position of output data clock on channel B with respect to output data. Bit settings are listed in Table 32. 0h Inverts output clock polarity for channel B in QDR mode, or output clock CLKOUTP, CLKOUTM in DDR mode. 0 : Normal operation 1 : In QDR mode, the polarity of the channel B output clock DBCLKP, DBCLKM is inverted. Effective only when the DIS CTRL PINS bit is set to '1'. In DDR mode, the output clock polarity of CLKOUTP, CLKOUTM is inverted. D0 INV CLK OUT CHB R/W Table 32. QDR Timing Channel B Timing DELAY (ps) IN OUTPUT CLOCK WITH RESPECT TO DEFAULT POSITION 58 BIT SETTING fS = 250 MSPS fS = 200 MSPS fS = 150 MSPS fS = 100 MSPS 00101 –80 –120 –150 –225 00111 –55 –75 –90 –130 00000 0 0 0 0 01101 55 65 90 130 01110 95 115 165 235 01011 140 165 230 350 10100 180 220 290 450 10000 230 290 370 565 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 8.6.1.17 Register 1F (offset = 1Fh) [reset = 7Fh] Figure 107. Register 1F D7 0 W-0h D6 D5 D4 D3 FAST OVR THRESHOLD R/W-0h D2 D1 D0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 33. Register 1F Field Descriptions Bit Field Type Reset Description D7 0 W 1h Always write '0' Default value of this bit is '1'. Always write this bit to '0' when fast OVR thresholds are programmed. 0h The device has a fast OVR mode that indicates an overload condition at the ADC input. The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload condition occurs. The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESHOLD bits] / 127). See the Overrange Indication section for details. D[6:0] FAST OVR THRESHOLD R/W 8.6.1.18 Register 20 (offset = 20h) [reset = 00h] Figure 108. Register 20 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 W-0h W-0h W-0h W-0h W-0h W-0h W-0h D0 PDN/OVR FOR CTRL PINS R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 34. Register 20 Field Descriptions Bit D[7:1] D0 Field Type Reset Description 0 W 0h Always write '0' 0h Determines if the CTRL1, CTRL2 pins are power-down control or OVR outputs 0 : CTRL1 and CTRL2 pins function as input pins to control power-down operation. 1 : CTRL1 and CTRL2 pins function as output pins for overrange indications of channels A and B, respectively. The PDN CH A, PDN CH B register bits along with DIS CTRL PINS can be used for power-down operation. PDN/OVR FOR CTRL PINS R/W Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 59 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information To obtain the best performance in an application, careful consideration must be given to the design of the input analog circuit and common-mode, clock circuit, and power-supply rails. The Typical Application section discusses these critical design considerations in detail. 9.2 Typical Application Because the ADS42LBx9 is a dual-channel device, it can be used in a dual-channel superheterodyne receiver, as shown in Figure 109. In a superheterodyne receiver, the high-frequency RF signal is first mixed down to a lower Intermediate frequency (IF). The ADS42LBxx can be used in the IF stage to sample and digitize the IF signal. The digital data can be encoded either in offset binary or twos complement format and transmitted to a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). Inside the FPGA or ASIC, the digital data are down-converted to the baseband frequency with a digital mixer and numerically controlled oscillator (NCO). Mixer RF1 Ch A Baseband Processor (FPGA, ASIC) Ch B RF2 IF Amplifier IF Filter ADS42LBxx Copyright © 2016, Texas Instruments Incorporated LO Figure 109. The ADS42LBx9 in a Dual-Channel Superheterodyne Receiver 9.2.1 Design Requirements Specific design requirements are provided in Table 35. Table 35. ADS42LBx9 Design Requirements DESIGN PARAMETER VALUE fSAMPLING 250 MSPS IF 10 MHz (Figure 123), 170 MHz (Figure 124) SNR > 72 dBc SFDR > 80 dBc HDn > 90 dBc 9.2.2 Detailed Design Procedure The choice of drive circuit at the analog and clock inputs can degrade the performance of the ADC. In order to obtain the design specifications given in Table 35, the following design guidelines discussed in this section must be followed. 60 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 9.2.2.1 Analog Input The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (at dc, a 10-kΩ differential input resistance is provided in shunt with a 4-pF differential input capacitance). The buffer helps isolate the external driving source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier than when compared to an ADC without the buffer. The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. When programmed for 2.5-VPP full-scale, each input pin must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V. The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to approximately 400 MHz (with a 2-VPP full-scale amplitude). This maximum analog input frequency is different than the analog bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency. 9.2.2.1.1 Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics. Figure 110, Figure 111, and Figure 112 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz. INxP(1) ZIN(2) RIN CIN INxM (1) X = A or B. (2) ZIN = RIN || (1 / jωCIN). Figure 110. ADC Equivalent Input Impedance 5 Differential Capacitance, Cin (pF) Differential Resistance, Rin (kΩ) 10 1 0.1 0.05 0 200 400 600 Frequency (MHz) 800 1000 4 3 2 1 0 0 200 G073 Figure 111. ADC Analog Input Resistance (RIN) Across Frequency 400 600 Frequency (MHz) 800 1000 G074 Figure 112. ADC Analog Input Capacitance (CIN) Across Frequency Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 61 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 9.2.2.1.2 Driving Circuit An example driving circuit configuration is shown in Figure 113. To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as shown in Figure 113. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. If HD2 optimization is a concern, using a 10-Ω series resistor on the INP side and a 9.5-Ω series resistor on the INM side may help improve HD2 by 2 dB to 3 dB at a 85-dBFS level on a 170-MHz IF. An additional R-C-R (39 Ω - 6.8 pF - 39 Ω) circuit placed near device pins helps further improve HD3. 0.1 PF 0.1 PF 10 : INP RINT 39 : 25 : 0.1 PF 6.8 pF 25 : RINT 39 : INM 1:1 10 : (or 9.5 :) 0.1 PF 1:1 Device Figure 113. Drive Circuit for Input Frequencies up to 250 MHz The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 113. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω source impedance). For high input frequencies (>250MHz), the R-C-R circuit can be removed as indicated in Figure 114. 0.1 PF 0.1 PF 10 : INP RINT 0.1 PF 25 : 25 : RINT INM 1:1 1:1 0.1 PF 10 : (or 9.5 :) Device Figure 114. Drive Circuit for Input Frequencies > 250 MHz 62 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 9.2.2.1.3 Using the ADS42LBx9 In Time-Domain, Low-Frequency Pulse Applications The analog buffers inside the device are implemented to provide excellent linearity over a wide range of frequencies. However, at very low frequencies (< 100 kHz) the buffer presents a high-pass response, as shown in Figure 115 and Figure 116. This response does not affect most frequency-domain applications, but can require compensation techniques for time-domain, dc-coupled applications. Application report SBAA220 discusses simple techniques to compensate for the analog buffer response. Device Analog Input (INxP-INxM) Buffer Output Sampling Switch Sampling Cap Analog Buffer Figure 115. Analog Buffer in the ADS42LBx9 0.1 Buffer Response (dB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 Frequency (KHz) G075 Figure 116. Buffer Response at Very Low Input Frequencies Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 63 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 9.2.2.2 Clock Input The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADS42LB69 and ADS42LB49 can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 117, Figure 118, and Figure 119. Figure 119 details the internal clock buffer. Note: RT = termination resistor, if necessary. 0.1 mF 0.1 mF Zo CLKP Differential Sine-Wave Clock Input CLKP RT Typical LVDS Clock Input 0.1 mF 100 W CLKM Device 0.1 mF Zo CLKM Figure 117. Differential Sine-Wave Clock Driving Circuit Zo Device Figure 118. LVDS Clock Driving Circuit 0.1 mF CLKP 150 W Typical LVPECL Clock Input 100 W Zo 0.1 mF CLKM Device 150 W Figure 119. LVPECL Clock Driving Circuit Clock Buffer LPKG 2 nH 20 W CLKP CBOND 1 pF 5 kW RESR 100 W LPKG 2 nH CEQ CEQ 1.4 V 20 W 5 kW CLKM CBOND 1 pF RESR 100 W NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 120. Internal Clock Buffer 64 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 121. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM Device Figure 121. Single-Ended Clock Driving Circuit 9.2.2.3 SNR and Clock Jitter The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 3. Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies. SNRQuantization _ Noise æ SNR ADC [dBc] = -20 ´ log çç 10 20 è 2 2 2 ö æ SNRThermalNoise ö æ SNRJitter ö ÷÷ + ç 10 ÷ + ç 10 ÷ 20 20 ø è ø ø è SNR limitation is a result of sample clock jitter and can be calculated by Equation 4: SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter) (3) (4) The total clock jitter (TJitter) has three components: the internal aperture jitter (85 fS for the device) is set by the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. TJitter can be calculated by Equation 5: TJitter = (TJitter,Ext.Clock_Input)2 + (TAperture_ADC)2 (5) External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS thermal noise and an 85-fS internal aperture jitter. The SNR value depends on the amount of external jitter for different input frequencies, as shown in Figure 122. 76 SNR (dBFS) 74 72 35 fs 70 50 fs 68 100 fs 150 fs 66 200 fs 64 10 100 1000 Fin (MHz) Figure 122. SNR versus Input Frequency and External Clock Jitter Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 65 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 9.2.3 Application Curves 0 0 fIN = 10 MHz SFDR = 88 dBc SNR = 74 dBFS SINAD = 73.9 dBFS THD = 87 dBc SFDR Non HD2, HD3 = 102 dBc −40 −60 −80 −100 −120 −40 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 Figure 123. FFT for 10-MHz Input Signal 66 fIN = 170 MHz SFDR = 90 dBc SNR = 73.1 dBFS SINAD = 73 dBFS THD = 87 dBc SFDR Non HD2, HD3 = 100 dBc −20 Amplitude (dBFS) Amplitude (dBFS) −20 Submit Documentation Feedback 125 −120 0 25 G001 50 75 Frequency (MHz) 100 125 G002 Figure 124. FFT for 170-MHz Input Signal Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 10 Power Supply Recommendations Three different power-supply rails are required for the ADS42LBx9: • A 3.3-V AVDD is used to power the analog buffers. • A 1.8-V AVDD is used to power the analog core of the ADC. • A 1.8-V DRVDD is used to power the digital core of the ADC. TI recommends providing the 1.8-V digital and analog supplies from separate sources because of the switching activities on the digital rail. An example power-supply scheme suitable for the ADS42LBx9 device family is shown in Figure 125. In this example supply scheme, AVDD is provided from a dc-dc converter and an low-dropout (LDO) regulator to increase the efficiency of the implementation. Where cost and area rather than power-supply efficiency are the main design goals, AVDD can be provided using only the LDO. 3.3 V (340 mA) AVDD3V 3.3 V DC-DC Converter 2V 1.8 V (182 mA) AVDD LDO 1.8 V (245 mA) DC-DC Converter DRVDD Figure 125. Example Power-Supply Scheme 11 Layout 11.1 Layout Guidelines • • • • • The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each other. Each differential pair length must be matched within 10 mils of each other. When the ADC is used on the same printed circuit board (PCB) with a digital intensive component [such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)], use separate digital and analog ground planes to minimize undesired coupling. Note that these ground planes must not overlap. Connect decoupling capacitors directly to ground and place these capacitors close to the ADC power pins and the power-supply pins to filter high-frequency current transients directly to the ground plane, as illustrated in Figure 126. Ground and power planes must be wide enough to keep the impedance very low. In a multilayer PCB, dedicate one layer to ground and another to power planes. AVDD DRVDD 10 F 10 F Place the decoupling capacitor close to the power-supply pin. 10 F 10 F Place the decoupling capacitor close to the ADC power-supply pin. Device Figure 126. Recommended Placement of Power-Supply Decoupling Capacitors Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 67 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 11.2 Layout Example Figure 127. Example Layout 68 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 ADS42LB49, ADS42LB69 www.ti.com SLAS904F – OCTOBER 2012 – REVISED MAY 2016 Layout Example (continued) Copper Layer 1 Signal Dielectric GND Dielectric PWR Dielectric PWR Dielectric GND Dielectric Layer 6 Signal Dielectric = 0.011 inches Copper = 0.25 oz Figure 128. Example PCB Layer Stack Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 Submit Documentation Feedback 69 ADS42LB49, ADS42LB69 SLAS904F – OCTOBER 2012 – REVISED MAY 2016 www.ti.com 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 36. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS42LB49 Click here Click here Click here Click here Click here ADS42LB69 Click here Click here Click here Click here Click here 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 70 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: ADS42LB49 ADS42LB69 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS42LB49IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 AZ42LB49 ADS42LB49IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 AZ42LB49 ADS42LB69IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 AZ42LB69 ADS42LB69IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 AZ42LB69 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of