ADS4449EVM

ADS4449 ADS4449 SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 www.ti.com ADS4449 Quad-Channel, 14-Bit, 250-MSPS, Low-Power ADC 1 Features 3 Description • • • • The ADS4449 is a high-linearity, quad-channel, 14-bit, 250-MSPS, analog-to-digital converter (ADC). Designed for low power consumption and high spurious-free dynamic range (SFDR), the device has low-noise performance and outstanding SFDR over a large input frequency range. • • • • Quad Channel 14-Bit Resolution Maximum Sampling Data Rate: 250 MSPS Power Dissipation: – 365 mW per Channel Spectral Performance at 170-MHz IF (typ): – SNR: 69 dBFS – SFDR: 86 dBc DDR LVDS Digital Output Interface Internal Dither Package: 144-Terminal NFBGA (10.00 mm × 10.00 mm) Device Information PACKAGE(1) PART NUMBER ADS4449 (1) NFBGA (144) BODY SIZE (NOM) 10.00 mm × 10.00 mm For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • Multi-Carrier GSM Cellular Infrastructure Base Stations • RADAR and Smart Antenna Arrays • Multi-Carrier Multi-Mode Cellular Infrastructure Base Stations • Active Antenna Arrays for Wireless Infrastructures • Communications Test Equipment spacer spacer 0 fIN = 170 MHz SFDR = 89 dBc SINAD = 68.9 dBFS SNR = 69 dBFS THD = 85 dBc Amplitude (dB) −20 −40 −60 −80 −100 −120 0 25 50 75 Frequency (MHz) 100 125 G005 Spectrum for 170-MHz Input Frequency An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: ADS4449 1 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................7 6.6 Digital Characteristics................................................. 9 6.7 Timing Requirements................................................ 10 6.8 Timing Characteristics, Serial interface.....................10 6.9 Typical Characteristics.............................................. 12 6.10 Typical Characteristics: Contour............................. 18 7 Parameter Measurement Information.......................... 19 7.1 LVDS Output Timing................................................. 19 8 Detailed Description......................................................21 8.1 Overview................................................................... 21 8.2 Functional Block Diagram......................................... 21 8.3 Feature Description...................................................22 8.4 Device Functional Modes..........................................24 8.5 Programming............................................................ 27 8.6 Register Maps...........................................................29 9 Application and Implementation.................................. 43 9.1 Application Information............................................. 43 9.2 Typical Application.................................................... 43 10 Power Supply Recommendations..............................48 11 Layout........................................................................... 49 11.1 Layout Guidelines................................................... 49 11.2 Layout Example...................................................... 49 12 Device and Documentation Support..........................50 12.1 Device Nomenclature..............................................50 12.2 Documentation Support.......................................... 51 12.3 Receiving Notification of Documentation Updates..51 12.4 Support Resources................................................. 51 12.5 Trademarks............................................................. 51 12.6 Electrostatic Discharge Caution..............................51 12.7 Glossary..................................................................51 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (April 2013) to Revision B (November 2020) Page • Added Low Sampling Rate mode to Table 8-2 ................................................................................................ 24 Changes from Revision * (April 2013) to Revision A (January 2016) Page • Added Internal Dither Features bullet ................................................................................................................ 1 • Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 • Deleted Package and Ordering Information because the data is repeated in the Package Option Addendum 1 • Deleted SNRB from the configuration registers block in the functional block diagram ......................................1 • Changed Clock Inputs, Input clock sample rate parameter minimum specification in Recommended Operating Conditions table.................................................................................................................................................. 5 • Changed Table 8-1 .......................................................................................................................................... 23 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 5 Pin Configuration and Functions 1 2 3 4 5 6 7 8 9 10 11 12 A AVDD AVDD CINM CINP AVDD VCM VCM AVDD BINM BINP AVDD AVDD B DINP AVSS AVDD AVDD AVSS AVDD33 AVDD33 AVSS AVDD AVDD AVSS AINM C DINM AVSS AVSS AVSS AVSS CLKINM CLKINP AVSS AVSS AVSS AVSS AINP D AVDD AVDD VCM AVSS AVSS AVSS AVSS AVSS AVSS VCM AVDD AVDD E AVDD33 AVDD33 NC DRVSS DRVSS DRVSS DRVSS DRVSS DRVSS PDN AVDD33 AVDD33 F DCD13M DCD13P DRVDD DRVSS DRVSS DRVSS DRVSS DRVSS DRVSS DRVDD DAB13P DAB13M G DCD12M DCD12P NC NC NC RESET SCLK SDATA SEN SDOUT DAB12P DAB12M H DCD11M DCD11P DCD6P DCD6M DRVDD DRVDD DRVDD DRVDD DAB6M DAB6P DAB11P DAB11M J DCD10M DCD10P DCD5P DCD5M DCD2P DRVDD DRVDD DAB2M DAB5M DAB5P DAB10P DAB10M K DCD9M DCD9P DCD4P DCD4M DCD2M DRVDD DRVDD DAB2P DAB4M DAB4P DAB9P DAB9M L DCD8M DCD8P DCD3P DCD3M DCD1P DCD1M DAB1M DAB1P DAB3M DAB3P DAB8P DAB8M M DCD7M DCD7P CLKOUT CDP CLKOUT CDM DCD0P/ OVRCDP DCD0M/ OVRCDM DAB0M/ OVRABM DAB0P/ OVRABP CLKOUT ABM CLKOUT ABP DAB7P DAB7M Figure 5-1. ZCR Package, 144-Pin NFBGA, Top View Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 3 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 Table 5-1. Pin Functions PIN NAME I/O DESCRIPTION AINM B12 I Negative differential analog input for channel A AINP C12 I Positive differential analog input for channel A AVDD33 B6, B7, E1, E2, E11, E12 I Analog 3.3-V power supply AVDD A1, A2, A5, A8, A11, A12, B3, B4, B9, B10, D1, D2, D11, D12 I Analog 1.9-V power supply AVSS B2, B5, B8, B11, C2-C5, C8-C11, D4-D9 I Analog ground BINM A9 I Negative differential analog input for channel B BINP A10 I Positive differential analog input for channel B CINM A3 I Negative differential analog input for channel C CINP A4 I Positive differential analog input for channel C CLKINM C6 I Negative differential clock input CLKINP C7 I Positive differential clock input CLKOUTABM M9 O Negative differential LVDS clock output for channel A and B CLKOUTABP M10 O Positive differential LVDS clock output for channel A and B CLKOUTCDM M4 O Negative differential LVDS clock output for channels C and D CLKOUTCDP M3 O Positive differential LVDS clock output for channels C and D DAB[13:1]P, DAB0P/ OVRABP, DAB[13:1]M, DAB0M/ OVRABM F11, F12, G11, G12, H9-H12, J8-J12, K8-K12, L7-L12, M7, M8, M11, M12 O DDR LVDS outputs for channels A and B. DCD[13:1]P, DCD0P/ OVRCDP, DCD[13:1]M, DCD0M/ OVRCDM F1, F2, G1, G2, H1-H4, J1-J5, K1-K5, L1-L6, M1, M2, M5, M6 O DDR LVDS outputs for channels C and D. DINM C1 I Negative differential analog input for channel D DINP B1 I Positive differential analog input for channel D F3, F10, H5-H8, J6, J7, K6, K7 I Digital 1.8-V power supply DRVDD DRVSS E4-E9, F4-F9 I Digital ground E3, G3, G4, G5 - Do not connect PDN E10 I Power-down control; active high. Logic high is power down. RESET G6 I Hardware reset; active high SCLK G7 I Serial interface clock input SDATA G8 I Serial interface data input SDOUT G10 O Serial interface data output SEN G9 I Serial interface enable VCM A6, A7, D3, D10 O Common-mode voltage for analog inputs. All VCM terminals are internally connected together. NC 4 NO. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Supply voltage Voltage between Voltage applied to input terminals Temperature MIN MAX AVDD33 –0.3 3.6 AVDD –0.3 2.1 DRVDD –0.3 2.1 AVSS and DRVSS –0.3 0.3 AVDD and DRVDD –2.4 2.4 AVDD33 and DRVDD –2.4 3.9 AVDD33 and AVDD –2.4 3.9 XINP, XINM –0.3 minimum (1.9, AVDD + 0.3) CLKP, CLKM(2) –0.3 minimum (1.9, AVDD + 0.3) RESET, SCLK, SDATA, SEN, PDN –0.3 3.9 Operating free-air, TA –40 (2) V V V 85 Operating junction, TJ °C 150 Storage, Tstg (1) UNIT –65 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKM is less than | 0.3 V |). This recommendation prevents the ESD protection diodes at the clock input terminals from turning on. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101(2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 3.15 3.3 3.45 V 1.8 1.9 2 V 1.7 1.8 2 V SUPPLIES AVDD33 AVDD Supply voltage DRVDD ANALOG INPUTS Differential input voltage range VIC 2 Input common-mode voltage VPP VCM ± 0.025 Analog input common-mode current (per input terminal of each channel) V 1.5 VCM current capability µA/MSPS 5 Maximum analog input frequency amplitude(2) 400 1.4-VPP input amplitude 500 2-VPP input mA MHz CLOCK INPUTS Input clock sample rate (1) 10 250 MSPS Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 5 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6.3 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM 0.2 1.5 Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) LVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 LVCMOS, single-ended, ac-coupled Input clock duty cycle MAX UNIT VPP 1.8 40% 50% 60% DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output terminal to DRVSS (default strength) 3.3 pF RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω TEMPERATURE RANGE TA Operating free-air temperature TJ Operating junction temperature (1) (2) –40 85 Recommended Maximum rated 105 (2) 125 °C °C When input clock sample rate is below 200 MSPS Low Sample Rate Mode is required. Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate. 6.4 Thermal Information ADS4449 THERMAL METRIC(1) ZCR (NFBGA) UNIT 144 PINS RθJA Junction-to-ambient thermal resistance 35.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.1 °C/W RθJB Junction-to-board thermal resistance 12.6 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 12.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6.5 Electrical Characteristics Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC clock frequency = 250 MHz, 50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RESOLUTION Default resolution 14 Bits 2 VPP ANALOG INPUTS Differential input full-scale VCM Common mode input voltage 1.15 RIN Input resistance, differential V At 170-MHz input frequency 700 Ω CIN Input capacitance, differential At 170-MHz input frequency 3.3 pF Analog input bandwidth, 3 dB with a 50-Ω source driving the ADC analog inputs 500 MHz DYNAMIC ACCURACY EO EG Offset error Gain error(2) Specified across devices and channels –15 15 As a result of internal reference inaccuracy alone Specified across devices and channels –5 5 Of channel alone Specified across channels within a device mV %FS ±0.2 Channel gain error temperature coefficient(2) 0.001 Δ%/°C POWER SUPPLY(1) IAVDD33 IAVDD 3.3-V analog supply Supply current 51 mA 1.9-V analog supply 350 mA IDRVDD 1.8-V digital supply 355 mA PTOTAL Total 1.47 PDISS(standby) Power dissipation Standby 400 PDISS(global) Global power-down 6 1.6 W mW 52 mW DYNAMIC AC CHARACTERISTICS fIN = 40 MHz 71.1 fIN = 70 MHz 71 fIN = 140 MHz SNR Signal-to-noise ratio fIN = 170 MHz 69.5 67.5 68.5 fIN = 307 MHz 67.5 fIN = 350 MHz SINAD Signal-to-noise and distortion ratio 70.9 fIN = 70 MHz 70.8 fIN = 140 MHz 69.3 fIN = 170 MHz Spurious-free dynamic range 66.9 68.8 fIN = 220 MHz 68.3 fIN = 307 MHz 66.8 fIN = 350 MHz 66.3 fIN = 40 MHz 84 fIN = 70 MHz 87 fIN = 170 MHz dBFS 67 fIN = 40 MHz fIN = 140 MHz SFDR 69 fIN = 220 MHz dBFS 85 78.5 86 fIN = 220 MHz 84 fIN = 307 MHz 78 fIN = 350 MHz 77 dBc Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 7 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6.5 Electrical Characteristics (continued) Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC clock frequency = 250 MHz, 50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN 83 fIN = 70 MHz 84 fIN = 140 MHz THD Total harmonic distortion Second-order harmonic distortion(3) (4) 75 Third-order harmonic distortion Worst spur (non HD2, HD3) 82 fIN = 307 MHz 76 fIN = 350 MHz 75 fIN = 40 MHz 96 fIN = 70 MHz 87 Differential nonlinearity INL Integral nonlinearity PSRR (1) (2) (3) (4) 8 UNITS dBc 86 fIN = 170 MHz 78.5 dBc 86 fIN = 220 MHz 84 fIN = 307 MHz 78 fIN = 350 MHz 77 fIN = 40 MHz 83 fIN = 70 MHz 89 85 fIN = 170 MHz 79.5 86 fIN = 220 MHz 85 fIN = 307 MHz 80 fIN = 350 MHz 78 fIN = 40 MHz 100 fIN = 70 MHz 100 fIN = 140 MHz dBc 95 fIN = 170 MHz 87 95 fIN = 220 MHz, 95 fIN = 307 MHz 85 fIN = 350 MHz DNL 83 fIN = 220 MHz fIN = 140 MHz HD3 MAX 82 fIN = 170 MHz fIN = 140 MHz HD2 TYP fIN = 40 MHz dBc 85 –0.95 ±0.5 ±1.5 LSBs ±5.25 LSBs Input overload recovery Recovery to within 1% (of final value) for 6dB output overload with sine-wave input 1 Clock cycle Crosstalk with a full-scale, 220-MHz signal on aggressor channel and no signal on victim channel 90 dB AC power-supply rejection ratio For 50-mVPP signal on AVDD supply < 30 dB A 185-MHz, full-scale, sine-wave input signal is applied to all four channels. There are two sources of gain error: internal reference inaccuracy and channel gain error. Phase and amplitude imbalances onboard must be minimized to obtain good performance. The minimum value across temperature is ensured by bench characterization. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6.6 Digital Characteristics The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD33 = 3.3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS(1) (RESET, SCLK, SDATA, SEN, PDN) VIH High-level input voltage All digital inputs support 1.8-V logic levels. SPI supports 3.3-V logic levels. VIL Low-level input voltage All digital inputs support 1.8-V logic levels. SPI supports 3.3-V logic levels. IIH High-level input current IIL Low-level input current 1.25 V 0.45 RESET, SCLK, PDN terminals VHIGH = 1.8 V 10 SEN(2) VHIGH = 1.8 V 0 RESET, SCLK, PDN terminals VLOW = 0 V 0 SEN terminal VLOW = 0 V 10 terminal V µA µA DIGITAL OUTPUTS (SDOUT) VOH High-level output voltage VOL Low-level output voltage DRVDD – 0.1 DRVDD V 0 0.1 V DIGITAL OUTPUTS, LVDS INTERFACE (DAB[13:0]P, DAB[13:0]M, DCD[13:0]P, DCD[13:0]M, CLKOUTABP, CLKOUTABM, CLKOUTCDP, CLKOUTCDM) High-level output differential voltage(3) Standard-swing LVDS 270 350 465 mV VODL Low-level output differential Standard-swing LVDS –465 –350 –270 mV VOCM Output common-mode voltage VODH (1) (2) (3) 1.05 V RESET, SDATA, and SCLK have an internal 150-kΩ pull-down resistor. SEN has an internal 150-kΩ pull-up resistor to DRVDD. with an external 100-Ω termination. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 9 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6.7 Timing Requirements Typical values are at 25°C, AVDD33 = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, sine-wave input clock, CLOAD = 3.3 pF(2), and R (3) LOAD = 100 Ω , unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C. See Note (1) tA Aperture delay tJ Aperture delay matching Between any two channels of the same device Variation of aperture delay Between two devices at the same temperature and DRVDD supply MIN NOM MAX 0.7 1.2 1.6 ps ±150 ps 140 fs rms Time to valid data after coming out of global power down ADC latency(4) (5) ns ±70 Aperture jitter Wake up time UNIT 100 µs Time to valid data after coming out of channel power down 10 Default latency in 14-bit mode 10 Digital gain enabled 13 Digital gain and offset correction enabled 14 Output clock cycles OUTPUT TIMING(6) tSU Data setup time(7) (8) (9) Data valid to CLKOUTxxP zero-crossing 0.6 0.85 ns tH Data hold time(7) (8) (9) CLKOUTxxP zero-crossing to data becoming invalid 0.6 0.84 ns LVDS bit clock duty cycle Differential clock duty cycle (CLKOUTxxP – CLKOUTxxM) tPDI Clock propagation delay(5) Input clock falling edge cross-over to output clock falling edge cross-over, 184 MSPS ≤ sampling frequency ≤ 250 MSPS tdelay Delay time Input clock falling edge cross-over to output clock falling edge cross-over, 184 MSPS ≤ sampling frequency ≤ 250 MSPS tRISE, t Data rise and fall time Rise time measured from –100 mV to 100 mV 0.1 ns Rise time measured from –100 mV to 100 mV 0.1 ns FALL tCLKRISE, Output clock rise and fall tCLKFALL time (1) (2) (3) (4) (5) (6) (7) (8) (9) 50% 0.25 × tS + tdelay 6.9 8.65 ns 10.5 ns Timing parameters are ensured by design and characterization and are not tested in production. CLOAD is the effective external single-ended load capacitance between each output terminal and ground. RLOAD is the differential load resistance between the LVDS output pair. ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles. Overall latency = ADC latency + tPDI. Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to a logic high of 100 mV and a logic low of –100 mV. Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address ACh, value 60h. Refer to the section. By default after reset, minimum setup time and minimum hold times are 520 ps each. The setup and hold times of a channel are measured with respect to the same channel output clock. 6.8 Timing Characteristics, Serial interface see Figure 6-1 fSCLK SCLK frequency (equal to 1 / tSCLK) MIN > dc NOM MAX UNIT 20 MHz tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDI setup time 25 ns tDH SDI hold time 25 ns 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 Table 6-1. LVDS Timings Across Lower Sampling Frequencies SETUP TIME (ns) SAMPLING FREQUENCY (MSPS) MIN TYP 210 0.89 185 1.06 HOLD TIME (ns) MAX MIN TYP 1.03 0.82 1.01 1.21 0.95 1.15 Register Address SDATA A7 A6 A5 A4 A3 MAX Register Data A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 6-1. Serial Interface Timing Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 11 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6.9 Typical Characteristics 0 0 −20 −20 Amplitude (dBFS) Amplitude (dBFS) At 25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock, 1.5-V PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. −40 −60 −80 −100 −120 0 25 50 75 Frequency (MHz) 100 −80 −120 125 SFDR = 84 dBc SNR = 71.1 dBFS SINAD = 70.9 dBFS THD = 84 dBc 25 fIN = 70 MHz 50 75 Frequency (MHz) 100 125 G002 SFDR = 87 dBc SNR = 70.9 dBFS SINAD = 70.8 dBFS THD = 84 dBc Figure 6-3. FFT for 70-MHz Input Signal 0 −20 −20 −40 −40 Amplitude (dB) 0 −60 −80 −100 −120 0 G001 Figure 6-2. FFT for 40-MHz Input Signal Amplitude (dBFS) −60 −100 fIN = 40 MHz −60 −80 −100 0 fIN = 100 MHz 25 50 75 Frequency (MHz) 100 125 −120 0 G003 SFDR = 85 dBc SNR = 70.2 dBFS SINAD = 70.1 dBFS THD = 84 dBc Figure 6-4. FFT for 100-MHz Input Signal 12 −40 fIN = 140 MHz 25 50 75 Frequency (MHz) 100 125 G004 SFDR = 87 dBc SNR = 69.7 dBFS SINAD = 69.6 dBFS THD = 84 dBc Figure 6-5. FFT for 140-MHz Input Signal Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) www.ti.com −60 −80 0 25 50 75 Frequency (MHz) fIN = 170 MHz 100 125 −120 0 25 SFDR = 89 dBc SNR = 69 dBFS SINAD = 68.9 dBFS THD = 85 dBc fIN = 230 MHz −20 −20 Amplitude (dBFS) 0 −40 −60 −80 0 25 50 75 Frequency (MHz) 100 G006 SFDR = 86 dBc SNR = 68.9 dBFS SINAD = 68.5 dBFS THD = 84 dBc −40 −60 −80 fIN2 = 50 MHz −120 125 0 25 G007 Each Tone at –7-dBFS Amplitude fIN1 = 45 MHz 50 75 Frequency (MHz) 100 125 G008 Each Tone at –36-dBFS Amplitude SFDR = 92 dBFS fIN1 = 45 MHz 2-Tone IMD = 87 dBFS fIN2 = 50 MHz SFDR = 99 dBFS 2-Tone IMD = 99 dBFS Figure 6-8. FFT for Two-Tone Input Signal Figure 6-9. FFT for Two-Tone Input Signal 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) 125 −100 −100 −60 −80 −100 −120 100 Figure 6-7. FFT for 230-MHz Input Signal 0 −120 50 75 Frequency (MHz) G005 Figure 6-6. FFT for 170-MHz Input Signal Amplitude (dBFS) −80 −100 −100 −120 −60 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 125 Each Tone at –7-dBFS Amplitude fIN1 = 185.1 MHz fIN2 = 190.1 MHz −120 0 25 G009 50 75 Frequency (MHz) 100 125 G010 Each Tone at –36-dBFS Amplitude SFDR = 102 dBFS fIN1 = 185.1 MHz 2-Tone IMD = 97 dBFS fIN2 = 190.1 MHz SFDR = 100 dBFS 2-Tone IMD = 101 dBFS Figure 6-10. FFT for Two-Tone Input Signal Figure 6-11. FFT for Two-Tone Input Signal Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 13 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 93 25 Temperature = −40°C Temperature = 25°C Temperature = 85°C 91 20 85 Count (%) SFDR (dBc) 88 82 79 15 10 76 5 73 40 80 120 160 200 240 280 Input Frequency (MHz) 320 360 −108 −105 −104 −103 −102 −101 −100 −99 −98 −97 −96 −95 −94 −93 −92 −91 −90 −89 −88 −87 −86 −85 −84 −83 −82 0 70 400 HD2 (dBc) G011 Figure 6-12. Spurious-Free Dynamic Range vs Input Frequency G039 Input Frequency = 170 MHz Figure 6-13. HD2 Distribution over Multiple Devices 72 104 40 MHz 100 MHz 130 MHz 100 71 96 350 MHz 400 MHz 450 MHz 92 SFDR (dBc) SNR (dBFS) 70 170 MHz 230 MHz 300 MHz 69 68 88 84 80 76 67 72 66 40 80 120 160 200 240 280 Input Frequency (MHz) 320 360 64 400 Figure 6-14. Signal-to-Noise Ratio vs Input Frequency 1 1.5 2 2.5 3 3.5 4 Digital Gain (dB) 4.5 5 5.5 6 G013 130 75.5 40 MHz 100 MHz 130 MHz 73 72 71 70 170 MHz 230 MHz 300 MHz 350 MHz 400 MHz 450 MHz SNR(dBFS) SFDR(dBc) SFDR(dBFS) 75 74.5 120 110 100 74 SNR (dBFS) SNR (dBFS) 0.5 Figure 6-15. Spurious-Free Dynamic Range vs Digital Gain 74 69 68 67 66 65 64 63 62 0 G012 0 0.5 1 1.5 2 2.5 3 3.5 4 Digital Gain (dB) 4.5 5 5.5 6 73.5 90 73 80 72.5 70 72 60 71.5 50 71 40 70.5 30 70 −70 −60 G014 Figure 6-16. Signal-to-Noise Ratio vs Digital Gain −50 −40 −30 −20 Amplitude (dBFS) −10 0 SFDR (dBc,dBFS) 65 68 20 Input Frequency = 70 MHz Figure 6-17. Performance vs Input Amplitude 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 G015 ADS4449 74 94 72 110 73.5 92 71.5 100 73 90 71 88 70.5 86 70 84 69.5 90 72.5 80 72 70 71.5 60 71 50 70.5 SFDR (dBc) SFDR (dBFS) SNR 40 30 20 −50 −40 SFDR (dBc) 120 −10 0 69 78 0.7 68.5 68 1.3 0.9 1 1.1 1.2 Input Common−Mode Voltage (V) G017 Input Frequency = 185 MHz Figure 6-18. Performance vs Input Amplitude Figure 6-19. Performance vs Input Common-Mode Voltage 90 71 DRVDD = 1.7 V DRVDD = 1.8 V DRVDD = 1.9 V DRVDD = 2 V 89 DRVDD = 1.7 V DRVDD = 1.8 V DRVDD = 1.9 V DRVDD = 2 V 70.5 SNR (dBFS) 88 SFDR (dBc) 0.8 G016 Input Frequency = 185 MHz 87 86 85 70 69.5 69 68.5 84 83 −40 −15 10 35 Temperature (°C) 60 68 −40 85 −15 G018 Input Frequency = 185 MHz 10 35 Temperature (°C) 60 85 G019 Input Frequency = 185 MHz Figure 6-20. Spurious-Free Dynamic Range vs DRVDD Supply and Temperature Figure 6-21. Signal-to-Noise Ratio vs DRVDD Supply and Temperature 90 71 AVDD = 1.8 V AVDD = 1.9 V AVDD = 2 V 89 AVDD = 1.8 V AVDD = 1.9 V AVDD = 2 V 70.5 SNR (dBFS) 88 SFDR (dBc) SFDR SNR 80 69.5 −30 −20 Amplitude (dBFS) 69 82 70 SNR (dBFS) SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 SNR (dBFS) SFDR (dBc,dBFS) www.ti.com 87 86 85 70 69.5 69 84 68.5 83 82 −40 −15 10 35 Temperature (°C) 60 85 68 −40 G020 Input Frequency = 185 MHz −15 10 35 Temperature (°C) 60 85 G021 Input Frequency = 185 MHz Figure 6-22. Spurious-Free Dynamic Range vs AVDD Supply and Temperature Figure 6-23. Signal-to-Noise Ratio vs AVDD Supply and Temperature Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 15 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 71 90 89 AVDD3V = 3.15 V AVDD3V = 3.3 V AVDD3V = 3.45 V 70.5 SNR (dBFS) 87 86 85 84 AVDD3V = 3.15 V AVDD3V = 3.3 V AVDD3V = 3.45 V 83 82 −40 −15 10 35 Temperature (°C) 60 70 69.5 69 68.5 68 −40 85 Input Frequency = 185 MHz 0.8 1.1 1.4 1.7 Differential Clock Amplitudes (Vpp) 2 92 72 SNR THD SNR (dBFS) 90 70.5 89 70 88 69.5 87 69 86 68.5 85 68 84 67.5 83 25 30 G024 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 70 75 82 G025 Input Frequency = 185 MHz Figure 6-27. Performance vs Clock Duty Cycle 0 −20 Amplitude (dB) CMRR (dB) 91 71 67 Figure 6-26. Performance vs Clock Amplitude −40 −60 −80 −100 −120 0 50 100 150 200 250 Frequency of Input Common-Mode Signal (MHz) G026 0 25 50 75 Frequency (MHz) fIN = 185 MHz 300 Input Frequency = 185 MHz 100 125 G027 Amplitude (fIN – fCM) = –80.9 dBFS Amplitude (fIN) = –1 dBFS Amplitude (fCM) = –95 dBFS fCM = 10 MHz, 50 mVPP Amplitude (fIN + fCM) = –77.2 dBFS SFDR = 76 dBc 50-mVPP Signal Superimposed on VCM Figure 6-28. Common-Mode Rejection Ratio Spectrum 16 85 G023 71.5 SNR (dBFS) SFDR (dBc) 71 70.5 70 69.5 69 68.5 68 67.5 67 66.5 66 65.5 65 2.3 Input Frequency = 185 MHz 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 −55 −60 60 Figure 6-25. Signal-to-Noise Ratio vs AVDD3V Supply and Temperature SFDR SNR 0.5 10 35 Temperature (°C) Input Frequency = 185 MHz Figure 6-24. Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature 100 98 96 94 92 90 88 86 84 82 80 78 76 0.2 −15 G022 THD (dBc) SFDR (dBc) 88 Figure 6-29. Common-Mode Rejection Ratio vs Test Signal Frequency Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 0 −20 PSRR on AVDD Supply PSRR on AVDD3V Supply −25 −20 −30 Amplitude (dB) PSRR (dB) −35 −40 −45 −50 −40 −60 −80 −55 −100 −60 −65 −70 −120 0 50 100 150 200 250 Frequency of Signal on Supply (MHz) 0 10 300 G028 20 30 Frequency (MHz) 40 50 G029 Amplitude (fIN) = –1 dBFS Amplitude (fPSRR) = –87 dBFS Input Frequency = 10 MHz fIN = 10 MHz Amplitude (fIN + fPSRR) = –60.6 dBFS 50-mVPP Signal Superimposed on Supply fPSRR = 2 MHz, 50 mVPP Amplitude (fIN – fPSRR) = –60 dBFS Figure 6-31. Power-Supply Rejection Ratio vs Test Signal Frequency 1.6 800 1.4 700 Analog Power (mW) Total Power (W) Figure 6-30. Power-Supply Rejection Ratio Spectrum for AVDD 1.2 1.0 0.8 0.6 0.4 0.2 AVDD Power AVDD3V Power DRVDD Power 600 500 400 300 200 100 1 26 51 76 101 126 151 176 201 226 250 Sampling Speed (MSPS) G030 Input Frequency = 185 MHz 0 1 26 51 76 101 126 151 176 201 226 250 Sampling Speed (MSPS) G031 Input Frequency = 185 MHz Figure 6-32. Total Power vs Sampling Frequency Figure 6-33. Power Breakup vs Sampling Frequency Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 17 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 6.10 Typical Characteristics: Contour At 25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock, 1.5-V PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 250 250 83 Sampling Frequency, MSPS 87 230 91 83 95 200 91 80 75 87 87 190 87 50 87 100 70 150 75 80 220 400 85 88 86 84 82 79 76 90 90 88 50 100 95 74 76 150 82 200 250 300 350 Input Frequency, MHz 78 80 82 84 79 76 400 86 450 88 90 Figure 6-35. Spurious-Free Dynamic Range (6-dB Gain) 250 69 68.5 68 67.5 66.5 67 64.5 66 240 Sampling Frequency, MSPS 70.2 69.8 69.4 240 Sampling Frequency, MSPS 84 200 Figure 6-34. Spurious-Free Dynamic Range (0-dB Gain) 70.6 230 220 70.2 69.8 69.4 69 68.5 68 67.5 67 66.5 200 190 50 69.4 6968.568 69.8 70.2 100 66 150 67.5 67 66.5 200 250 300 350 Input Frequency, MHz 400 67 68 69 66 450 70 Figure 6-36. Signal-to-Noise Ratio (0-dB Gain) 64.1 63.7 63.3 64.9 230 62.5 62.9 64.7 65.5 220 64.5 64.1 63.7 66 210 18 86 210 450 250 76 90 70 70 200 250 300 350 Input Frequency, MHz 79 82 230 190 75 80 83 91 88 86 84 90 240 87 87 87 210 70 75 87 91 220 80 Sampling Frequency, MSPS 87 240 210 64.9 63.3 64.7 62.9 64.7 200 190 64.5 63.3 63.7 64.1 64.5 50 100 62.5 150 62.9 62.5 200 250 300 350 Input Frequency, MHz 63 63.5 64 400 450 64.5 Figure 6-37. Signal-to-Noise Ratio (6-dB Gain) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 7 Parameter Measurement Information 7.1 LVDS Output Timing Figure 7-1 shows a timing diagram of the LVDS output voltage levels. Figure 7-2 shows the latency described in the Section 6.7 table. DxnP Logic 0 VODL Logic 1 VODH DxnM VOCM GND Figure 7-1. LVDS Output Voltage Levels Input Signal N+3 N+2 N+1 Sample N N+4 N+12 N+11 N+10 tA CLKINM Input Clock CLKINP CLKOUTABM (CLKOUTCDM) CLKOUTABP (CLKOUTCDP) 10 Clock Cycles DDR LVDS tPDI Output Data DABP, DABM (DCDP, DCDM) Ch B Ch A Ch B Ch A Ch B Ch A Ch B Ch A Ch B Ch A (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) N-10 N-9 N-8 N-7 Ch A Ch B Ch A Ch B Ch A Ch B Ch A Ch B Ch A (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) N-1 N N+1 Figure 7-2. Latency Timing All 14 data bits of one channel are included in the digital output interface at the same time, as shown in Figure 7-3. Channel A and C data are output on the rising edge of the output clock while channels B and D are output on the falling edge of the output clock. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 19 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 CLKOUTABM CLKOUTABP DAB[13:0]P, DAB[13:0]M DA[13:0]P, DA[13:0]M DB[13:0]P, DB[13:0]M Sample N DA[13:0]P, DA[13:0]M DB[13:0]P, DB[13:0]M DA[13:0]P, DA[13:0]M Sample N + 1 DB[13:0]P, DB[13:0]M Sample N + 2 CLKOUTCDM CLKOUTCDP DCD[13:0]P, DCD[13:0]M DC[13:0]P, DC[13:0]M DD[13:0]P, DD[13:0]M Sample N DC[13:0]P, DC[13:0]M DD[13:0]P, DD[13:0]M DC[13:0]P, DC[13:0]M Sample N + 1 DD[13:0]P, DD[13:0]M Sample N + 2 Figure 7-3. LVDS Output Interface Timing 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8 Detailed Description 8.1 Overview The ADS4449 belong to TI’s low-power family of quad-channel, 14-bit, analog-to-digital converters (ADCs). High performance is maintained while power is reduced for power-sensitive applications. In addition to its low power and high performance, the ADS4449 has a number of digital features and operating modes to enable design flexibility. At every falling edge of the input clock, the analog input signal for each channel is sampled simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage, the sampledand-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference (residue) between the stage input and quantized equivalent is gained and propagates to the next stage. At every clock, each subsequent stage resolves the sampled input with greater accuracy. The digital outputs from all stages are combined in a digital correction logic block and are digitally processed to create the final code, after a data latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential signaling (LVDS) interface and is coded in binary twos complement format. The ADS4449 can be configured with a serial programming interface (SPI), as described in the Section 8.5.1 section. In addition, the device has control terminals that control power-down. 8.2 Functional Block Diagram DAB0P, DAB0M or OVRABP, OVRABM 14-Bit ADC AINP, AINM 14 Digital Block CLKOUTABP, CLKOUTABM 14-Bit ADC BINP, BINM DAB[13:1]P, DAB[13:1]M Output Formatter CLKINP, CLKINM DDR LVDS 14-Bit ADC CINP, CINM DCD0P, DCD0M or OVRCDP, OVRCDM Digital Block 14-Bit ADC DINP, DINM VCM 14 DCD[13:1]P, DCD[13:1]M CLKOUTCDP, CLKOUTCDM Common Mode PDN SDATA SDOUT SEN SCLK RESET Configuration Registers Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 21 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.3 Feature Description 8.3.1 Overrange Indication (OVRxx) After reset, all serial interface register "ALWAYS WRITE 1". Bits must be set to 1. Afterwards, 13-bit data are output on the Dxx13P, Dxx13M to Dxx1P, Dxx1M terminals and overrange information is output on the Dxx0P and Dxx0M terminals (where xx = channels A and B or channels C and D). When the DIS OVR ON LSB bit is set to 1, 14-bit data are output on the Dxx13P, Dxx13M to Dxx0P, Dxx0M terminals without overrange information on the LSB bits. The OVR timing diagram (13-bit data with OVR) is shown in Figure 8-1. In 14-bit mode, OVR is disabled by setting the DIS OVR ON LSB bit to 1, as shown in Figure 8-2. CLKOUTM CLKOUTP DA[13:1]P, DA[13:1]M DB[13:1]P, DB[13:1]M DAB0P, DAB0M DA[13:1]P, DA[13:1]M DB[13:1]P, DB[13:1]M OVR A OVR B Sample N DA[13:1]P, DA[13:1]M DB[13:1]P, DB[13:1]M OVR A OVR B 13-Bit Output Overrange Indicator Sample N+1 Figure 8-1. 13-Bit Data with OVR (Register Bits ALWAYS WRITE 1 = 1 and DIS OVR ON LSB = 0) CLKOUTM CLKOUTP DA[13:0]P, DA[13:0]M DB[13:0]P, DB[13:0]M DA[13:0]P, DA[13:0]M Sample N DB[13:0]P, DB[13:0]M DA[13:0]P, DA[13:0]M DB[13:0]P, DB[13:0]M 14-Bit Output Sample N+1 Figure 8-2. 14-Bit Mode (Register Bits ALWAYS WRITE 1 = 1 and DIS OVR ON LSB = 1) Normal overrange indication (OVR) shows the event of the device digital output being saturated when the input signal exceeds the ADC full-scale range. Normal OVR has the same latency as digital output data. However, an overrange event can be indicated earlier (than normal latency) by using the fast OVR mode. The fast OVR mode (enabled by default) is triggered seven clock cycles after the overrange condition that occurred at the ADC input. The fast OVR thresholds are programmable with the FAST OVR THRESH PROG bits (refer to Table 8-3, register address C3h). At any time, either normal or fast OVR mode can be programmed on the Dxx0P and Dxx0M terminals. 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.3.2 Gain for SFDR and SNR Trade-Off The device includes gain settings that can be used to obtain improved SFDR performance. The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps) using the DIGITAL GAIN CH X register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 8-1. Table 8-1. Full-Scale Range Across Gains GAIN (dB) TYPE FULL-SCALE (VPP) 0 Default after reset 2 0.5 Fine, programmable 1.89 1 Fine, programmable 1.78 1.5 Fine, programmable 1.68 2 Fine, programmable 1.59 2.5 Fine, programmable 1.5 3 Fine, programmable 1.42 3.5 Fine, programmable 1.34 4 Fine, programmable 1.26 4.5 Fine, programmable 1.19 5 Fine, programmable 1.12 5.5 Fine, programmable 1.06 6 Fine, programmable 1 SFDR improvement is achieved at the expense of SNR; for each gain setting, SNR degrades by approximately 0.5 dB to 1 dB. SNR degradation is diminished at high input frequencies. As a result, fine gain is very useful at high input frequencies because SFDR improvement is significant with marginal degradation in SNR. Therefore, fine gain can be used to trade-off between SFDR and SNR. After a reset, the gain function is disabled. To use fine gain: • First, program the DIGITAL ENABLE bits to enable digital functions. • This setting enables the gain for all four channels and places the device in a 0-dB gain mode. • For other gain settings, program the DIGITAL GAIN CH X register bits. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 23 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.4 Device Functional Modes 8.4.1 Special Performance Modes Best performance can be achieved by writing certain modes depending upon source impedance, band of operation and sampling speed. Table 8-2 summarizes the different these modes. Table 8-2. High-Performance Modes Summary SPECIAL MODES SUMMARY(1) SPECIAL MODE NAME ADDRESS (Hex) DATA (Hex) INPUT FREQUENCIES (Up to 125 MHz) INPUT FREQUENCIES (> 125 MHz) High-frequency mode F1 20 Not required Must 58 20 Optional Optional 70 20 Optional Optional 88 20 Optional Optional A0 20 Optional Optional ADDRESS (Hex) DATA (Hex) SAMPLING RATE (Up to 200 MSPS) SAMPLING RATE (>200MHz) 4A 1 Must Not required High SNR mode(2) SPECIAL MODE NAME Low Sampling Rate mode (1) (2) 62 1 Must Not required 7A 1 Must Not required 92 1 Must Not required See the Section 8.5.1 section for details. High SNR mode improves SNR typically by 1 dB at 170 MHz input frequency. See the Section 8.4.3 section. 8.4.2 Digital Output Information The device provides 14-bit digital data for each channel and two output clocks in LVDS mode. Output terminals are shared by a pair of channels that are accompanied by one dedicated output clock. 8.4.2.1 DDR LVDS Outputs In the LVDS interface mode, the data bits and clock are output using LVDS levels. The data bits of two channels are multiplexed and output on each LVDS differential pair of terminals; see Figure 8-3 and Figure 8-4. 24 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 CLKOUTxxP, CLKOUTxxM Dxx0P, Dxx0M Dxx1P, Dxx1M Dxx2P, Dxx2M 14-Bit Output Dxx12P, Dxx12M Dxx13P, Dxx13M Device NOTE: xx = channels A and B or C and D. Figure 8-3. DDR LVDS Interface CLKOUTABM CLKOUTABP DAB[13:0]P, DAB[13:0]M DA[13:0]P, DA[13:0]M DB[13:0]P, DB[13:0]M Sample N DA[13:0]P, DA[13:0]M DB[13:0]P, DB[13:0]M DA[13:0]P, DA[13:0]M Sample N + 1 DB[13:0]P, DB[13:0]M Sample N + 2 CLKOUTCDM CLKOUTCDP DCD[13:0]P, DCD[13:0]M DC[13:0]P, DC[13:0]M DD[13:0]P, DD[13:0]M Sample N DC[13:0]P, DC[13:0]M DD[13:0]P, DD[13:0]M DC[13:0]P, DC[13:0]M Sample N + 1 DD[13:0]P, DD[13:0]M Sample N + 2 Figure 8-4. DDR LVDS Interface Timing Diagram Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 25 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.4.2.1.1 LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 8-5. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination. The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The V DIFF voltage is programmable using the LVDS SWING register bits (refer to Table 8-3, register address 01h). The buffer output impedance behaves similar to a source-side series termination. By absorbing reflections from the receiver end, the source-side termination helps improve signal integrity. VDIFF(high) High Low OUTP External 100-W Load OUTM 1.1 V ROUT VDIFF(low) High Low Figure 8-5. LVDS Buffer Equivalent Circuit 8.4.2.1.2 Output Data Format The device transmits data in binary twos complement format. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 3FFh. For a negative input overdrive, the output code is 400h. 8.4.3 Using High SNR Mode Register Settings 0 0 −20 −20 Amplitude (dBFS) Amplitude (dBFS) The HIGH SNR MODE register settings can be used to further improve the SNR. However, there is a trade off between improved SNR and degraded THD when these settings are used. These settings shut down the internal spectrum-cleaning algorithm, resulting in THD performance degradation. Figure 8-6 and Figure 8-7 show the effect of using HIGH SNR MODE. SNR improves by approximately 1 dB and THD degrades by 3 dB. −40 −60 −80 −100 −120 −60 −80 −100 0 25 50 75 Frequency (MHz) fIN = 170 MHz SFDR = 93 dBc SINAD = 69 dBFS THD = 89 dBc 100 125 −120 0 G036 SNR = 69.1 dBFS Figure 8-6. FFT (Default) at 170 MHz 26 −40 25 50 75 Frequency (MHz) fIN = 170 MHz SFDR = 89 dBc SINAD = 70 dBFS THD = 86 dBc 100 125 G037 SNR = 70.1 dBFS Figure 8-7. FFT with High SNR Mode at 170 MHz Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 Figure 8-8 shows SNR versus input frequency with and without these settings. 72 Default HIGH SNR MODE Enable 71 SNR (dBFS) 70 69 68 67 66 65 64 40 90 140 190 240 290 340 Input Frequency (MHz) 390 440 490 G038 Figure 8-8. SNR vs Input Frequency with High SNR Mode To obtain best performance, TI recommends keeping termination impedance between INP and INM low (for instance, at 50 Ω differential). This setting helps absorb the kickback noise component of the spectrum-cleaning algorithm. However, when higher termination impedances (such as 100 Ω) are required, shutting down the spectrum-cleaning algorithm by using the HIGH SNR MODE register settings can be helpful. 8.4.4 Input Common Mode To ensure a low-noise, common-mode reference, the VCM terminal should be filtered with a 0.1-µF, lowinductance capacitor connected to ground. The VCM terminal is designed to directly bias the ADC inputs (refer to Figure 9-4 to Figure 9-7). Each ADC input terminal sinks a common-mode current of approximately 1.5 µA per MSPS of clock frequency. When a differential amplifier is used to drive the ADC (with dc-coupling), ensure that the output common-mode of the amplifier is within the acceptable input common-mode range of the ADC inputs (VCM ± 25 mV). 8.5 Programming 8.5.1 Serial Interface The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface input data), and SDOUT (serial interface readback data) terminals. Serially shifting bits into the device is enabled when SEN is low. Serial data (SDATA) are latched at every SCLK falling edge when SEN is active (low). Serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. 8.5.1.1 Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways: 1. Either through a hardware reset by applying a high pulse on the RESET terminal (of widths greater than 10ns), as shown in Figure 6-1; or 2. By applying a software reset. When using the serial interface, set the RESET bit (D1 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET terminal is kept low. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 27 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.5.1.2 Serial Register Readout The device includes a mode where the contents of the internal registers can be read back, as shown in Figure 8-9. This readback mode can be useful as a diagnostic check to verify the serial interface communication between the external controller and ADC. 1. Set the READOUT register bit to 1. This setting disables any further writes to the registers except register address 00h. 2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read. 3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT terminal (terminal G10). 4. The external controller can latch the contents at the SCLK falling edge. 5. To enable register writes, reset the READOUT register bit to 0. Note that the contents of register 00h cannot be read back because the register contains RESET and READOUT bits. When the READOUT bit is disabled, the SDOUT terminal is in a high-impedance state. If serial readout is not used, the SDOUT terminal must not be connected (must float). Register Address A[7:0] = 00h SDATA A7 A6 A5 A4 A3 A2 Register Data D[7:0] = 01h A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN The SDOUT pin is in a high-impedance state (READOUT = 0). SDOUT a) Enable serial readout (READOUT = 1) Register Address A[7:0] = 45h SDATA A7 A6 A5 A4 A3 A2 Register Data D[7:0] = XX (don’t care) A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 SCLK SEN SDOUT The SDOUT pin functions as a serial readout (READOUT = 1). b) Read contents of Register 45h. This register is initialized with 04h. Figure 8-9. Serial Readout Timing Diagram SDOUT comes out at the SCLK rising edge with an approximate delay (t SD_DELAY) of 8 ns, as shown in Figure 8-10. SCLK tSD_DELAY SDOUT Figure 8-10. Sdout Delay Timing 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6 Register Maps Table 8-3 summarizes the device registers. Table 8-3. Register Map REGISTER DATA REGISTER ADDRESS A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 RESET READOUT 0 0 01 LVDS SWING 25 DIGITAL GAIN CH B DIGITAL GAIN BYPASS CH B 2B DIGITAL GAIN CH A DIGITAL GAIN BYPASS CH A TEST PATTERN CH A 31 DIGITAL GAIN CH D DIGITAL GAIN BYPASS CH D TEST PATTERN CH D 37 DIGITAL GAIN CH C DIGITAL GAIN BYPASS CH C TEST PATTERN CH C 3D 0 0 3F 0 0 OFFSET CORR EN1 0 0 42 0 0 0 0 45 0 0 0 DIS OVR ON LSB 4A 0 0 0 62 0 0 0 7A 0 0 TEST PATTERN CH B 0 0 0 DIGITAL ENABLE 0 0 0 SEL OVR GLOBAL POWER DOWN 0 CONFIG PDN PIN 0 0 0 0 LSR MODE CH A 0 0 0 0 LSR MODE CH B 0 0 0 0 0 LSR MODE CH D 0 0 0 LSR MODE CH C CUSTOM PATTERN[13:8] 40 CUSTOM PATTERN[7:0] 92 0 0 0 0 A9 0 0 0 0 AC 0 CLOCKOUT DELAY PROG CH AB CLOCKOUT DELAY PROG CH CD 0 0 ALWAYS WRITE 1 FAST OVR THRESH PROG C3 C4 EN FAST OVR THRESH 0 0 0 0 0 0 0 CF 0 0 0 0 OFFSET CORR EN2 0 0 0 D6 ALWAYS WRITE 1 0 0 0 0 0 0 0 D7 0 0 0 0 ALWAYS WRITE 1 ALWAYS WRITE 1 0 0 F1 0 0 HIGH FREQ MODE 0 0 58 0 0 HIGH SNR MODE CH A 0 0 0 0 0 59 ALWAYS WRITE 1 0 0 0 0 0 0 0 70 0 0 HIGH SNR MODE CH B 0 0 0 0 0 71 ALWAYS WRITE 1 0 0 0 0 0 0 0 88 0 0 HIGH SNR MODE CH D 0 0 0 0 0 89 ALWAYS WRITE 1 0 0 0 0 0 0 0 A0 0 0 HIGH SNR MODE CH C 0 0 0 0 0 A1 ALWAYS WRITE 1 0 0 0 0 0 0 0 FE 0 0 0 0 PDN CH D PDN CH C PDN CH A PDN CH B ENABLE LVDS SWING PROG Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 29 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1 Register Description 8.6.1.1 Register Address 00h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RESET READOUT Bits 7-2 Always write 0 Bit 1 RESET: Software reset applied This bit resets all internal registers to the default values and self-clears to 0. Bit 0 READOUT: Serial readout This bit sets the serial readout of the registers. 0 = Serial readout of registers disabled; the SDOUT terminal is placed in a high-impedance state. (default) 1 = Serial readout enabled; the SDOUT terminal functions as a serial data readout with CMOS logic levels running from the DRVDD supply. 8.6.1.2 Register Address 01h (Default = 00h) 7 6 5 4 3 LVDS SWING Bits 7-2 2 1 0 0 0 LVDS SWING: LVDS swing programmability These bits program the LVDS swing only after the ENABLE LVDS SWING PROG bits are set to 11. 000000 = Default LVDS swing; ±350 mV with an external 100-Ω termination (default) 011011 = ±420-mV LVDS swing with an external 100-Ω termination 110010 = ±470-mV LVDS swing with an external 100-Ω termination 010100 = ±560-mV LVDS swing with an external 100-Ω termination 001111 = ±160-mV LVDS swing with an external 100-Ω termination Bits 1-0 30 Always write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.3 Register Address 25h (Default = 00h) 7 6 5 4 DIGITAL GAIN BYPASS CH B DIGITAL GAIN CH B Bits 7-4 3 2 1 0 TEST PATTERN CH B DIGITAL GAIN CH B: Channel B digital gain programmability These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for channel B. Set the DIGITAL ENABLE bit to 1 beforehand to enable this feature. 0000 = 0-dB gain (default) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain Bit 3 DIGITAL GAIN BYPASS CH B: Channel B digital gain bypass 0 = Normal operation (default) 1 = Digital gain feature for channel B is bypassed Bits 2-0 TEST PATTERN CH B: Channel B test pattern programmability These bits program the test pattern for channel B. 000 = Normal operation (default) 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern Output data ([D:0]) are an alternating sequence of 01010101010101 and 10101010101010. 100 = Outputs digital ramp Output data increments by one 14-bit LSB every clock cycle from code 0 to code 16383 101 = Outputs custom pattern To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh and 40h. 110 = Unused 111 = Unused Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 31 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.4 Register Address 2bh (Default = 00h) 7 6 5 4 DIGITAL GAIN BYPASS CH A DIGITAL GAIN CH A Bits 7-4 3 2 1 0 TEST PATTERN CH A DIGITAL GAIN CH A: Channel A digital gain programmability These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for channel A. Set the DIGITAL ENABLE bit to 1 beforehand to enable this feature. 0000 = 0-dB gain (default) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain Bit 3 DIGITAL GAIN BYPASS CH A: Channel A digital gain bypass 0 = Normal operation (default) 1 = Digital gain feature for channel A is bypassed Bits 2-0 TEST PATTERN CH A: Channel A test pattern programmability These bits program the test pattern for channel A. 000 = Normal operation (default) 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern Output data ([D:0]) are an alternating sequence of 01010101010101 and 10101010101010. 100 = Outputs digital ramp Output data increments by one 14-bit LSB every clock cycle from code 0 to code 16383 101 = Outputs custom pattern To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh and 40h. 110 = Unused 111 = Unused 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.5 Register Address 31h (Default = 00h) 7 6 5 4 DIGITAL GAIN BYPASS CH D DIGITAL GAIN CH D Bits 7-4 3 2 1 0 TEST PATTERN CH D DIGITAL GAIN CH D: Channel D digital gain programmability These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for channel D. Set the DIGITAL ENABLE bit to 1 beforehand to enable this feature. 0000 = 0-dB gain (default) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain Bit 3 DIGITAL GAIN BYPASS CH D: Channel D digital gain bypass 0 = Normal operation (default) 1 = Digital gain feature for channel A is bypassed Bits 2-0 TEST PATTERN CH D: Channel D test pattern programmability These bits program the test pattern for channel D. 000 = Normal operation (default) 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern Output data ([D:0]) are an alternating sequence of 01010101010101 and 10101010101010. 100 = Outputs digital ramp Output data increments by one 14-bit LSB every clock cycle from code 0 to code 16383 101 = Outputs custom pattern To program test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh and 40h. 110 = Unused 111 = Unused Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 33 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.6 Register Address 37h (Default = 00h) 7 6 5 4 DIGITAL GAIN BYPASS CH C DIGITAL GAIN CH C Bits 7-4 3 2 1 0 TEST PATTERN CH C DIGITAL GAIN CH C: Channel C digital gain programmability These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for channel C. Set the DIGITAL ENABLE bit to 1 beforehand to enable this feature. 0000 = 0-dB gain (default) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain Bit 3 DIGITAL GAIN BYPASS CH C: Channel C digital gain bypass 0 = Normal operation (default) 1 = Digital gain feature for channel A is bypassed Bits 2-0 TEST PATTERN CH C: Channel C test pattern programmability These bits program the test pattern for channel C. 000 = Normal operation (default) 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern Output data ([D:0]) are an alternating sequence of 01010101010101 and 10101010101010. 100 = Outputs digital ramp Output data increments by one 14-bit LSB every clock cycle from code 0 to code 16383 101 = Outputs custom pattern To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh and 40h. 110 = Unused 111 = Unused 34 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.7 Register Address 3dh (Default = 00h) 7 6 5 4 3 2 1 0 0 0 OFFSET CORR EN1 0 0 0 0 0 Bits 7-6 Always write 0 Bit 5 OFFSET CORR EN1: Offset correction setting This bit enables the offset correction feature for all four channels after the DIGITAL ENABLE bit is set to ‘1,’ correcting mid-code to 8191. In addition, write the OFFSET CORR EN2 bit (register CFh, value 08h) for proper operation of the offset correction feature. 0 = Offset correction disabled (default) 1 = Offset correction enabled Bits 4-0 Always write 0 8.6.1.8 Register Address 3fh (Default = 00h) 7 6 5 4 3 2 1 0 0 0 CUSTOM PATTERN D13 CUSTOM PATTERN D12 CUSTOM PATTERN D11 CUSTOM PATTERN D10 CUSTOM PATTERN D9 CUSTOM PATTERN D8 Bits 7-6 Always write 0 Bits 5-0 CUSTOM PATTERN D[13:8] Set the custom pattern using these bits for all four channels. 8.6.1.9 Register Address 40h (Default = 00h) 7 6 5 4 3 2 1 0 CUSTOM PATTERN D7 CUSTOM PATTERN D6 CUSTOM PATTERN D5 CUSTOM PATTERN D4 CUSTOM PATTERN D3 CUSTOM PATTERN D2 CUSTOM PATTERN D1 CUSTOM PATTERN D0 Bits 7-0 CUSTOM PATTERN D[7:0] Set the custom pattern using these bits for all four channels. 8.6.1.10 Register Address 42h (Default = 00h) 7 0 6 5 0 0 Bits 7-4 Always write 0 Bit 3 DIGITAL ENABLE 4 3 2 1 0 0 DIGITAL ENABLE 0 0 0 1 = Digital gain and offset correction features disabled 1 = Digital gain and offset correction features enabled Bits 2-0 Always write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 35 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.11 Register Address 45h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 DIS OVR ON LSB SEL OVR GLOBAL POWER DOWN 0 CONFIG PDN PIN Bits 7-5 Always write 0 Bit 4 DIS OVR ON LSB 0 = Effective ADC resolution is 13 bits (the LSB of a 14-bit output is OVR) (default) 1 = ADC resolution is 14 bits Bit 3 SEL OVR: OVR selection 0 = Fast OVR selected (default) 1 = Normal OVR selected. See the Section 8.3.1 section for details. Bit 2 GLOBAL POWER DOWN 0 = Normal operation (default) 1 = Global power down. All ADC channels, internal references, and output buffers are powered down. Wakeup time from this mode is slow (100 µs). Bit 1 Always write 0 Bit 0 CONFIG PDN PIN Use this bit to configure PDN terminal. 0 = The PDN terminal functions as a standby terminal. All channels are put in standby. Wake-up time from standby mode is fast (10 µs). (default) 1 = The PDN terminal functions as a global power-down terminal. All ADC channels, internal references, and output buffers are powered down. Wake-up time from global power mode is slow (100 µs). 8.6.1.12 Register Address 4ah (Defalut = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LSR CH A Bits 7-1 Always write 0 Bit 0 LSR CH A Use this bit to put Channel A into Low Sampling Rate Mode when sampling at a rate below 200MSPS. 8.6.1.13 Register Address 62h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LSR CH B Bits 7-1 Always write 0 Bit 0 LSR CH B: Enables Low Sampling Rate Mode for channel B Use this bit to put Channel B into Low Sampling Rate Mode when sampling at a rate below 200MSPS. 8.6.1.14 Register Address 7ah (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LSR CH D Bits 7-1 Always write 0 Bit 0 LSR CH D: Enables Low Sampling Rate Mode for channel D Use this bit to put Channel D into Low Sampling Rate Mode when sampling at a rate below 200MSPS. 36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.15 Register Address 92h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LSR CH C Bits 7-1 Always write 0 Bit 0 LSR CH C: Enables Low Sampling Rate Mode for channel C Use this bit to put Channel C into Low Sampling Rate Mode when sampling at a rate below 200MSPS. 8.6.1.16 Register Address A9h (Default = 00h) 7 6 5 4 0 0 0 0 Bits 7-4 Always write 0 Bits 3-0 CLOCKOUT DELAY PROG CH AB 3 2 1 0 CLOCKOUT DELAY PROG CH AB These bits program the clock out delay for channels A and B, see Table 8-4. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 37 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.17 Register Address Ach (Default = 00h) 7 6 5 0 4 3 CLOCKOUT DELAY PROG CH CD Bit 7 Always write 0 Bits 6-4 CLOCKOUT DELAY PROG CH CD 2 1 0 0 0 ALWAYS WRITE 1 These bits program the clock out delay for channels C and D, as shown in Table 8-4 . Bits 2-1 Always write 0 Bit 0 Always write 1 This bit is set to 0 by default. User must set it to 1 after reset or power-up. Table 8-4. Clockout Delay Programmability For All Channels CLOCKOUT DELAY PROG CHxx DELAY (ps) 0000 (default) 0 (default) 0001 –30 0010 70 0011 30 0100 –150 0101 –180 0110 –70 0111 –110 1000 270 1001 230 1010 340 1011 300 1100 140 1101 110 1110 200 1111 170 8.6.1.18 Register Address C3h (Default = 00h) 7 6 5 4 3 2 1 0 FAST OVR THRESH PROG Bits 7-0 FAST OVR THRESH PROG The device has a fast OVR mode that indicates an overload condition at the ADC input. The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESH PROG bits. FAST OVR is triggered seven output clock cycles after the overload condition occurs. To enable the FAST OVR programmability, enable the EN FAST OVR THRESH register bit. The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESH PROG bits] / 255). After reset, when EN FAST OVR THRESH PROG is set, the default value of the FAST OVR THRESH PROG bits is 230 (decimal). 38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.19 Register Address C4h (Default = 00h) 7 6 5 4 3 2 1 0 EN FAST OVR THRESH 0 0 0 0 0 0 0 Bit 7 EN FAST OVR THRESH This bit enables the device to be programmed to select the fast OVR threshold. Bits 6-0 Always write 0 8.6.1.20 Register Address Cfh (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 OFFSET CORR EN2 0 0 0 Bits 7-4 Always write 0 Bit 3 OFFSET CORR EN2 This bit must be set to ‘1’ when the OFFSET CORR EN1 bit is selected. Bits 2-0 Always write 0 8.6.1.21 Register Address D6h (Default = 00h) 7 6 5 4 3 2 1 0 ALWAYS WRITE 1 0 0 0 0 0 0 0 Bits 7 Always write 1 This bit is set to 0 by default. User must set it to 1 after reset or power-up. Bits 6-0 Always write 0 8.6.1.22 Register Address D7h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 ALWAYS WRITE 1 ALWAYS WRITE 1 0 0 Bits 7-4 Always write 0 Bits 3-2 Always write 1 This bit is set to 0 by default. User must set it to 1 after reset or power-up. Bits 1-0 Always write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 39 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.23 Register Address F1h (Default = 00h) 7 6 5 4 3 0 0 HIGH FREQ MODE 0 0 Bits 7-6 Always write 0 Bit 5 HIGH FREQ MODE 2 1 0 ENABLE LVDS SWING PROG 0 = Default (default) 1 = Use for input frequencies > 125 MHz Bits 4-3 Always write 0 Bits 2-0 ENABLE LVDS SWING PROG This bit enables the LVDS swing control with the LVDS SWING bits. 00 = LVDS swing control disabled (default) 01 = Do not use 10 = Do not use 11 = LVDS swing control enabled 8.6.1.24 Register Address 58h (Default = 00h) 7 0 6 5 4 3 2 1 0 0 HIGH SNR MODE CH A 0 0 0 0 0 Bits 7-6 Always write 0 Bit 5 HIGH SNR MODE CH A See the Section 8.4.3 section. Bits 4-0 Always write 0 8.6.1.25 Register Address 59h (Default = 00h) 7 6 5 4 3 2 1 0 ALWAYS WRITE 1 0 0 0 0 0 0 0 Bits 7 Always write 1 This bit is set to 0 by default. User must set it to 1 after reset or power-up. Bits 6-0 40 Always write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.26 Register Address 70h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 HIGH SNR MODE CH B 0 0 0 0 0 Bits 7-6 Always write 0 Bit 5 HIGH SNR MODE CH B See the Section 8.4.3 section. Bits 4-0 Always write 0 8.6.1.27 Register Address 71h (Default = 00h) 7 6 5 4 3 2 1 0 ALWAYS WRITE 1 0 0 0 0 0 0 0 Bits 7 Always write 1 This bit is set to 0 by default. User must set it to 1 after reset or power-up. Bits 6-0 Always write 0 8.6.1.28 Register Address 88h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 HIGH SNR MODE CH D 0 0 0 0 0 Bits 7-6 Always write 0 Bit 5 HIGH SNR MODE CH D See the Section 8.4.3 section. Bits 4-0 Always write 0 8.6.1.29 Register Address 89h (Default = 00h) 7 6 5 4 3 2 1 0 ALWAYS WRITE 1 0 0 0 0 0 0 0 Bits 7 Always write 1 This bit is set to 0 by default. User must set it to 1 after reset or power-up. Bits 6-0 Always write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 41 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 8.6.1.30 Register Address A0h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 HIGH SNR MODE CH C 0 0 0 0 0 Bits 7-6 Always write 0 Bit 5 HIGH SNR MODE CH C See the Section 8.4.3 section. Bits 4-0 Always write 0 8.6.1.31 Register Address A1h (Default = 00h) 7 6 5 4 3 2 1 0 ALWAYS WRITE 1 0 0 0 0 0 0 0 Bits 7 Always write 1 This bit is set to 0 by default. User must set it to 1 after reset or power-up. Bits 6-0 Always write 0 8.6.1.32 Register Address Feh (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 PDN CH D PDN CH C PDN CH A PDN CH B Bits 7-4 Always write 0 Bit 3 PDN CH D: Power-down channel D Channel D is powered down. Bit 2 PDN CH C: Power-down channel C Channel C is powered down. Bit 1 PDN CH B: Power-down channel B Channel B is powered down. Bit 0 PDN CH A: Power-down channel A Channel A is powered down. 42 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 9-1 shows that ADC input impedance is represented by parallel combination of resistance and capacitance. XINP(1) RIN ZIN(2) CIN XINM(1) A. X = A, B, C, or D. B. ZIN = RIN || (1 / jωCIN). Figure 9-1. ADC Equivalent Input Impedance Figure 9-2 and Figure 9-3 show how input impedance (ZIN= RIN|| CIN) varies over input frequency. Differential Input Capacitance, Cin (pF) Differential Input Resistance, Rin (kΩ) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 100 200 300 Frequency (MHz) 400 500 6 5 4 3 2 1 0 100 G037 Figure 9-2. ADC Analog Input Resistance (RIN) vs Frequency 200 300 Frequency (MHz) 400 500 G038 Figure 9-3. ADC Analog Input Capacitance (CIN) vs Frequency 9.2 Typical Application Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance. Glitches are caused by opening and closing the sampling switches. The driving circuit should present a low source impedance to absorb these glitches, otherwise these glitches may limit performance. A low impedance path between the analog input terminals and VCM is required from the common-mode switching currents perspective as well. This impedance can be achieved by using two resistors from each input terminated to the commonSubmit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 43 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 mode voltage (VCM). The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the sampling glitches inside the device itself. The R-C component values are also optimized to support high input bandwidth (up to 500 MHz). However, using an external R-LC-R filter as a part of drive circuit can improve glitch filtering, thus further resulting in better performance. In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched source impedance. In doing so, the ADC input impedance (shown in Figure 9-2 and Figure 9-3) must be considered. 9.2.1 Design Requirements For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor inseries with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source. 9.2.2 Detailed Design Procedure Two example driving circuits with a 50-Ω source impedance are shown in Figure 9-4 and Figure 9-5. The driving circuit in Figure 9-4 is optimized for input frequencies in the second Nyquist zone (centered at 185 MHz), whereas the circuit in Figure 9-5 is optimized for input frequencies in third Nyquist zone (centered at 310 MHz). Note that both drive circuits are terminated by 50 Ω near the ADC side. This termination is accomplished with a 25-Ω resistor from each input to the 1.15-V common-mode (VCM) from the device. This architecture allows the analog inputs to be biased around the required common-mode voltage. The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. 50 : T1 T2 0.1 PF 10 : INP 25 : Band-Pass Filter Centered at f0 = 185 MHz BW = 125 MHz 25 : 82 nH RIN 10 pF CIN 0.1 PF 25 : 25 : INM 1:1 1:1 10 : 0.1 PF VCM Device Figure 9-4. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies in the Second Nyquist Zone 50 : T1 T2 0.1 PF 10 : INP 25 : Band-Pass Filter Centered at f0 = 310 MHz BW = 125 MHz 25 : 27 nH RIN 10 pF CIN 0.1 PF 25 : 25 : INM 1:1 1:1 0.1 PF 10 : VCM Device Figure 9-5. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies in the Third Nyquist Zone 44 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 TI recommends terminating the drive circuit by a 50-Ω (or lower) impedance near the ADC for best performance. However, in some applications higher impedances be required to terminate the drive circuit. Two example driving circuits with 100-Ω differential termination are shown in Figure 9-6 and Figure 9-7. In these example circuits, the 1:2 transformer (T1) is used to transform the 50-Ω source impedance into a differential 100 Ω at the input of the band-pass filter. In Figure 9-6, the parallel combination of two 68-Ω resistors and one 120-nH inductor and two 100-Ω resistors is used (100 Ω is the effective impedance in pass-band) for better performance. T1 50 : 0.1 PF T2 10 : INP 68 : Band-Pass Filter Centered at f0 = 185 MHz BW = 125 MHz 25 : 100 : 120 nH 82 nH RIN 10 pF CIN 0.1 PF 100 : 68 : 25 : 10 : 1:2 INM 0.1 PF 1:1 VCM Device Figure 9-6. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies in the Second Nyquist Zone 50 : T1 T2 0.1 PF 10 : INP 25 : 50 : Band-Pass Filter Centered at f0 = 310 MHz BW = 125 MHz 27 nH RIN 10 pF CIN 0.1 PF 50 : 25 : 10 : 1:2 1:1 INM 0.1 PF VCM Device Figure 9-7. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies in the Third Nyquist Zone 9.2.3 Application Curves 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) Figure 10 and Figure 11 below show performance obtained at 170-MHz and 230-MHz input frequencies respectively using appropriate driving circuit. −60 −80 −100 −120 −60 −80 −100 0 25 50 75 Frequency (MHz) 100 125 −120 0 G005 Figure 9-8. FFT For 170-MHz Input Signal 25 50 75 Frequency (MHz) 100 125 G006 Figure 9-9. FFT For 230MHz Input Signal Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 45 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 9.2.4 Enabling 14-Bit Resolution By default after reset, the device outputs 11-bit data on the Dxx13P, Dxx13M and Dxx3P, Dxx3M terminals and OVR information on the Dxx0P, Dxx0M terminals. When the ALWAYS WRITE 1 bits are set, the ADC outputs 13bit data on the Dxx13P, Dxx13M and Dxx1P, Dxx1M terminals and OVR information on the Dxx0P, Dxx0M terminals. To enable 14-bit resolution, the DIS OVR ON LSB register bit must be set to 1 as indicated in Table 9-1. Table 9-1. ADC Configuration DATA ON ADC TERMINALS ADC TERMINAL NAMES AFTER RESET ALWAYS WRITE 1 = 1 ALWAYS WRITE 1 = 1 DIS OVR ON LSB = 1 Dxx13 D13 D13 D13 — — — — Dxx3 D3 D3 D3 Dxx2 Logic 0 D2 D2 Dxx1 Logic 1 D1 D1 Dxx0 OVR OVR D0 Comments 11-bit data (D[13:3]) and OVR come on ADC output terminals 13-bit data (D[13:1]) and OVR come on ADC output terminals 14-bit data comes on ADC output terminals 9.2.5 Analog Input The analog input consists of a switched-capacitor-based differential sample-and-hold architecture. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM terminals must be externally biased around a common-mode voltage of 1.15 V, available on the VCM terminal. For a full-scale differential input, each input terminal (INP, INM) must swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The input sampling circuit has a high 3-dB bandwidth that extends up to 500 MHz when a 50-Ω source drives the ADC analog inputs. 9.2.6 Drive Circuit Requirements This configuration improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15Ω resistor in series with each input terminal is recommended to damp out ringing caused by package parasitics. Glitches are caused by opening and closing the sampling switches. The driving circuit should present a low source impedance to absorb these glitches, otherwise these glitches may limit performance. A low impedance path between the analog input terminals and VCM is required from the common-mode switching currents perspective as well. This impedance can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM). The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the sampling glitches inside the device itself. The R-C component values are also optimized to support high input bandwidth (up to 500 MHz). However, using an external R-LC-R filter (refer to Figure 9-4, Figure 9-5, Figure 9-6, Figure 9-7, and Figure 9-10) improves glitch filtering, thus further resulting in better performance. In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched source impedance. In doing so, the ADC input impedance must be considered. Figure 9-1, Figure 9-2, and Figure 9-3 show the impedance (ZIN = RIN || CIN) at the ADC input terminals. Spurious-free dynamic range (SFDR) performance can be limited because of several reasons (such as the effect of sampling glitches, sampling circuit nonlinearity, and quantizer nonlinearity that follows the sampling circuit). Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance. 46 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 9.2.7 Clock Input The device clock inputs can be driven differentially with a sine, LVPECL, or LVDS source with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors, as shown in Figure 9-10. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL, LVDS, and LVCMOS clock sources (see Figure 9-11, Figure 9-12, and Figure 9-13). For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to commonmode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 V PP to obtain best performance. A clock source with very low jitter is recommended for high input frequency sampling. Bandpass filtering of the clock source can help reduce the effects of jitter. With a non-50% duty cycle clock input, performance does not change. Clock Buffer LPKG ~ 2 nH 20 Ω CLKP CBOND ~ 1 pF CEQ RESR ~ 100 Ω CEQ 5 kΩ 0.95V LPKG ~ 2 nH 5 kΩ 20 Ω CLKM CBOND ~ 1 pF RESR ~ 100 Ω NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 9-10. Internal Clock Buffer 0.1 mF CLKP Differential Sine-Wave Clock Input RT 0.1 mF CLKM A. RT is the termination resistor (optional). Figure 9-11. Differential Sine-Wave Clock Driving Circuit Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 47 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 ZO 0.1 mF CLKP 150 W Typical LVPECL Clock Input 100 W ZO 0.1 mF CLKM 150 W Figure 9-12. LVPECL Clock Driving Circuit ZO 0.1 mF CLKP Typical LVDS Clock Input 100 W ZO 0.1 mF CLKM Figure 9-13. LVDS Clock Driving Circuit 0.1 mF CLKP CMOS Clock Input VCM 0.1 mF CLKM Figure 9-14. Typical LVCMOS Clock Driving Circuit 10 Power Supply Recommendations The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply requirements during device power-up. AVDD and DVDD can power up in any order. 48 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 11 Layout 11.1 Layout Guidelines The ADS4449 EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 11-1. Some important points to remember during laying out the board are: • Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs should exit the pin out in opposite directions, as shown in the reference layout of Figure 66 as much as possible. • In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 66 as much as possible. • Digital outputs should be kept away from the analog inputs. When these digital outputs exit the pin out, the digital output traces should not be kept parallel to the analog input traces because this configuration may result in coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] should be matched in length to avoid skew among outputs. • At each power-supply pin (AVDD and DVDD), a 0.1-µF decoupling capacitor should be kept close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source. 11.2 Layout Example Figure 11-1. ADS4449 Layout Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 49 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 12 Device and Documentation Support 12.1 Device Nomenclature Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as an aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate, unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral INL is the deviation of the ADC transfer function from a best-fit line determined by a leastNonlinearity (INL) squares curve fit of that transfer function, measured in units of LSBs. Gain Error Gain error is the deviation of the ADC actual input full-scale range from the ideal value. Gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and EGCHAN. To a first-order approximation, the total gain error of E TOTAL is approximately E GREF + E GCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) × fS ideal to (1 + 0.5 / 100) × fS ideal. Offset Error Offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. The coefficient is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference of TMAX – TMIN. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. SNR = 10Log10 PS PN (1) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. 50 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 ADS4449 www.ti.com SBAS603B – APRIL 2013 – REVISED NOVEMBER 2020 Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all other spectral components, including noise (PN) and distortion (PD) but excluding dc. SINAD = 10Log10 PS PN + PD (2) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: • • • ADS4449 User Guide, SLAU485 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Data Interface with FPGA, SLAA592 Why Oversample when Undersampling can do the Job?, SLAA594 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS4449 51 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS4449IZCR ACTIVE NFBGA ZCR 144 184 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS4449I ADS4449IZCRR ACTIVE NFBGA ZCR 144 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADS4449I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of