ADS5231
SBAS295A – JULY 2004 – REVISED JANUARY 2007
Dual, 12-Bit, 40MSPS, +3.3V
Analog-to-Digital Converter
FEATURES
•
•
•
•
•
•
•
DESCRIPTION
Single +3.3V Supply
High SNR: 70.7dBFS at fIN = 5MHz
Total Power Dissipation:
Internal Reference: 321mW
External Reference: 285mW
Internal or External Reference
Low DNL: ±0.3LSB
Flexible Input Range: 1.5VPP to 2VPP
TQFP-64 Package
The ADS5231 is a dual, high-speed, high dynamic
range, 12-bit pipelined analog-to-digital converter
(ADC). This converter includes a high-bandwidth
sample-and-hold amplifier that gives excellent
spurious performance up to and beyond the Nyquist
rate. The differential nature of the sample-and-hold
amplifier and ADC circuitry minimizes even-order
harmonics and gives excellent common-mode noise
immunity.
The ADS5231 provides for setting the full-scale
range of the converter without any external reference
circuitry. The internal reference can be disabled,
allowing low-drive, external references to be used for
improved tracking in multichannel systems.
APPLICATIONS
•
•
•
•
•
•
Communications IF Processing
Communications Base Stations
Test Equipment
Medical Imaging
Video Digitizing
CCD Digitizing
The ADS5231 provides an over-range indicator flag
to indicate an input signal that exceeds the full-scale
input range of the converter. This flag can be used to
reduce the gain of front-end gain control circuitry.
There is also an output enable pin to allow for
multiplexing and testing on a printed circuit board
(PCB).
The ADS5231 employs digital error correction
techniques to provide excellent differential linearity
for demanding imaging applications. The ADS5231 is
available in a TQFP-64 package.
AVDD
SDATA SEN SCLK SEL
VDRV
OEA
ADS5231
Serial
Interface
DISABLE_PLL
12-Bit
Pipelined
ADC
INA
VIN
S/H
INA
Error
Correction
Logic
3-State
Output
D11A
·
·
·
D0A
OVRA
DVA
Timing/Duty Cycle
Adjust (PLL)
Internal
Reference
INT/EXT
CLK
CM
REFT
REFB
DVB
12-Bit
Pipelined
ADC
INB
VIN
S/H
INB
Error
Correction
Logic
3-State
Output
D11B
·
·
·
D0B
OVRB
STPD
OEB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
ADS5231
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
ADS5231
TQFP-64
PAG
(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +85°C
ADS5231IPAG
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5231IPAG
Tray, 160
ADS5231IPAGT
Tape and Reel, 250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage Range, AVDD
–0.3V to +3.8V
Supply Voltage Range, VDRV
–0.3V to +3.8V
Voltage Between AVDD and VDRV
–0.3V to +0.3V
Voltage Applied to External REF Pins
–0.3V to +2.4V
Analog Input Pins (2)
–0.3V to min. [3.3V, (AVDD + 0.3V)]
Case Temperature
+100°C
Operating Free-Air Temperature Range, TA
–40°C to +85°C
Lead Temperature
Junction Temperature
+105°C
Storage Temperature
–65°C to +150°C
(1)
(2)
2
+260°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
The dc voltage applied on the input pins should not go below –0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or
(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25Ω should be added in series with each
of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either
as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and
+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed
1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
RECOMMENDED OPERATING CONDITIONS
ADS5231
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, VDRV
3.0
3.3
3.6
V
REFT — External Reference Mode
1.875
2.0
2.05
V
REFB — External Reference Mode
0.95
1.0
1.125
V
REFCM = (REFT + REFB)/2 – External Reference
VCM ± 50mV
Mode (1)
Reference = (REFT – REFB) – External Reference Mode
0.75
1.0
V
1.1
VCM ± 50mV
Analog Input Common-Mode Range (1)
V
V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate
PLL Enabled (default)
20
40
MSPS
PLL Disabled
2
30 (2)
MSPS
ADCLK Duty Cycle
PLL Enabled (default)
45
Low-Level Voltage Clock Input
High-Level Voltage Clock Input
2.2
Operating Free-Air Temperature, TA
–40
55
MSPS
0.6
V
+85
°C
V
Thermal Characteristics:
(1)
(2)
θJA
42.8
°C/W
θJC
18.7
°C/W
These voltages need to be set to 1.5V ± 50mV if they are derived independent of VCM.
When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45%–55% duty cycle variation
is acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then the
duty cycle needs to be maintained within 48%–52% duty cycle.
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
ELECTRICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
ADS5231
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LSB
DC ACCURACY
No Missing Codes
Tested
DNL Differential Nonlinearity
INL Integral Nonlinearity
fIN = 5MHz
–0.9
±0.3
+0.9
fIN = 5MHz
–2.5
±0.4
+2.5
LSB
–0.75
±0.2
+0.75
% FS
Offset Error (1)
±6
Offset Temperature Coefficient (2)
Fixed Attenuation in
Channel (3)
ppm/°C
1
Fixed Attenuation Matching Across Channels
Gain Error/Reference Error (4)
–3.5
%FS
0.01
0.2
dB
±1.0
+3.5
% FS
±40
Gain Error Temperature Coefficient
ppm/°C
POWER REQUIREMENTS (5)
Internal Reference
Power Dissipation (5)
Analog Only (AVDD)
235.5
271
mW
Output Driver (VDRV)
85.5
109
mW
321
380
mW
Total Power Dissipation
External Reference
Power Dissipation
Analog Only (AVDD)
200
mW
Output Driver (VDRV)
85.5
mW
285.5
mW
Total Power Dissipation
Total Power-Down
Clock Running
83
mW
REFERENCE VOLTAGES
VREFT Reference Top (internal)
1.9
2.0
2.1
V
VREFB Reference Bottom (internal)
0.9
1.0
1.1
V
VCM Common-Mode Voltage
1.4
1.5
1.6
VCM Output Current (6)
±50mV Change in Voltage
VREFT Reference Top (external)
±2
1.875
V
VREFB Reference Bottom (external)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
V
mA
1.125
V
External Reference Common-Mode
VCM ± 50mV
V
External Reference Input Current (7)
1.0
mA
Offset error is the deviation of the average code from mid-code with –1dBFS sinusoid from ideal mid-code (2048). Offset error is
expressed in terms of % of full-scale.
If the offset at temperatures T1 and T2 are O1 and O2, respectively (where O1 and O2 are measured in LSBs), the offset temperature
coefficient in ppm/°C is calculated as (O1 – O2)/(T1 – T2) × 1E6/4096.
Fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold amplifier. When the differential voltage at
the analog input pins is changed from –VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code
(4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT – REFB).
The reference voltages are trimmed at production so that (VREFT – VREFB) is within ± 35mV of the ideal value of 1V. This specification
does not include fixed attenuation.
Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.
The VCM output current specified is the drive of the VCM buffer if loaded externally.
Average current drawn from the reference pins in the external reference mode.
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
ADS5231
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Differential Input Capacitance
3
VCM ± 0.05
V
Internal Reference
2.02
VPP
External Reference
2.02 × (VREFT – VREFB)
VPP
3
CLK Cycles
300
MHz
Analog Input Common-Mode Range
Differential Input Voltage Range
Voltage Overload Recovery
Time (8)
Input Bandwidth
pF
–3dBFS Input, 25Ω Series
Resistance
DIGITAL DATA INPUTS
Logic Family
+3V CMOS Compatible
VIH High-Level Input Voltage
VIN = 3.3V
VIL Low-Level Input Voltage
VIN = 3.3V
2.2
V
0.6
CIN Input Capacitance
3
V
pF
DIGITAL OUTPUTS
Straight Offset Binary (9)
Data Format
Logic Family
CMOS
Logic Coding
Straight Offset Binary or BTC
Low Output Voltage (IOL = 50µA)
+0.4
High Output Voltage (IOH = 50µA)
+2.4
V
V
3-State Enable Time
2
Clocks
3-State Disable Time
2
Clocks
Output Capacitance
3
pF
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
20
MHz
CONVERSION CHARACTERISTICS
Sample Rate
20
Data Latency
(8)
(9)
40
6
MSPS
CLK Cycles
A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
Option for Binary Two’s Complement Output.
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
AC CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, VDRV = 3.3V, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless otherwise noted.
ADS5231
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fIN = 5MHz
75
86
dBc
fIN = 32.5MHz
85
dBc
fIN = 70MHz
83
dBc
92
dBc
fIN = 32.5MHz
87
dBc
fIN = 70MHz
85
dBc
86
dBc
fIN = 32.5MHz
85
dBc
fIN = 70MHz
83
dBc
70.7
dBFS
fIN = 32.5MHz
69.5
dBFS
fIN = 70MHz
67.5
dBFS
70.3
dBFS
fIN = 32.5MHz
69
dBFS
fIN = 70MHz
67
dBFS
5MHz Full-Scale Signal Applied to 1 Channel;
Measurement Taken on the Channel with No Input Signal
–85
dBc
90.9
dBFS
DYNAMIC CHARACTERISTICS
SFDR Spurious-Free Dynamic Range
fIN = 5MHz
HD2 2nd-Order Harmonic Distortion
82
fIN = 5MHz
HD3 3rd-Order Harmonic Distortion
75
fIN = 5MHz
SNR Signal-to-Noise Ratio
68
fIN = 5MHz
SINAD Signal-to-Noise and Distortion
Crosstalk
IMD3
67.5
f1 = 4MHz at –7dBFS
Two-Tone, Third-Order
Intermodulation Distortion
f2 = 5MHz at –7dBFS
TIMING DIAGRAM
tA
Analog
Input
N+2
N
N+4
N+3
N+1
tC
CLK
t1
t2
DATA[D11:D0]
tDV
DV
OE
t OE
tOE
DATA
6
D11:D0
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TIMING CHARACTERISTICS
(1)
Typical values at TA = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty
cycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
40MSPS With PLL ON
tA Aperture Delay
2.1
ns
1.0
ps
3.7
5.5
ns
11.5
13.5
ns
6
Clocks
Aperture Jitter
t1 Data Setup
Time (2)
t2 Data Hold Time (3)
tD Data Latency
tDR, tDF Data Rise/Fall Time (4)
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
2
3
30
40
55
ns
%
13.5
16
18.5
ns
30MSPS With PLL OFF
tA Aperture Delay
Aperture Jitter
2.1
ns
1.0
ps
ns
t1 Data Setup Time
8
10
t2 Data Hold Time
14
19
ns
6
Clocks
tD Data Latency
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
2
3.5
30
45
55
ns
%
16
19
21
ns
20MSPS With PLL ON
tA Aperture Delay
Aperture Jitter
2.1
ns
1.0
ps
t1 Data Setup Time
10
12
ns
t2 Data Hold Time
20
25
ns
tD Data Latency
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
6
Clocks
0.5
2
3.5
30
45
55
ns
%
20
25
30
ns
20MSPS With PLL OFF
tA Aperture Delay
Aperture Jitter
2.1
ns
1.0
ps
ns
t1 Data Setup Time
10
12
t2 Data Hold Time
20
25
ns
6
Clocks
tD Data Latency
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
2
3.5
30
45
55
ns
%
20
25
30
ns
2MSPS With PLL OFF
tA Aperture Delay
Aperture Jitter
ns
1.0
ps
ns
t1 Data Setup Time
150
200
t2 Data Hold Time
200
250
ns
6
Clocks
tD Data Latency
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
(1)
(2)
(3)
(4)
2.1
0.5
2
3.5
ns
30
45
55
%
200
225
250
ns
Specifications assured by design and characterization; not production tested.
Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.
Measured from the 50% point of the falling edge of DV to the data becoming invalid.
Measured between 20% to 80% of logic levels.
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SERIAL INTERFACE TIMING
Outputs change on
next rising clock edge
after SEN goes high.
CLK
SEN
Start Sequence
t1
t6
t7
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
D7
(MSB)
SDATA
D6
D5
D4
D3
D2
D1
D0
t4
t5
NOTE: Data is shifted in MSB first.
8
PARAMETER
DESCRIPTION
MIN
t1
Serial CLK Period
50
ns
t2
Serial CLK High Time
20
ns
t3
Serial CLK Low Time
20
ns
t4
Data Setup Time
5
ns
t5
Data Hold Time
5
ns
t6
SEN Fall to SCLK Rise
8
ns
t7
SCLK Rise to SEN Rise
8
ns
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TYP
MAX
UNIT
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
SERIAL REGISTER MAP: Shown for the Case Where Serial Interface is Used (1)
ADDRESS
(1)
DATA
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
X
X
X
0
Normal Mode
0
0
0
0
X
X
X
1
Power-Down Both Channels
0
0
0
0
X
X
0
X
Straight Offset Binary Output
0
0
0
0
X
X
1
X
Binary Two's Complement Output
0
0
0
0
X
0
X
X
Channel B Digital Outputs Enabled
0
0
0
0
X
1
X
X
Channel B Digital Outputs Tri-Stated
0
0
0
0
0
X
X
X
Channel A Digital Outputs Enabled
0
0
0
0
1
X
X
X
Channel A Digital Outputs Tri-Stated
0
0
1
0
0
0
0
0
Normal Mode
0
0
1
0
0
1
0
0
All Digital Outputs Set to '1'
0
0
1
0
1
0
0
0
All Digital Outputs Set to '0'
0
0
1
1
0
0
X
0
Normal Mode
0
0
1
1
1
X
X
0
Channel A Powered Down
0
0
1
1
X
1
X
0
Channel B Powered Down
0
0
1
1
X
X
0
0
PLL Enabled (default)
0
0
1
1
X
X
1
0
PLL Disabled
X = don't care.
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RECOMMENDED POWER-UP SEQUENCING
Shown for the case where the serial interface is used.
AVDD (3V to 3.6V)
t1
AVDD
VDRV (3V to 3.6V)
t2
VDRV
t3
t4
t7
t5
Device Ready
For ADC Operation
t6
SEL
Device Ready
For Serial Register Write
SEN
Device Ready
For ADC Operation
Start of Clock
CLK
t8
NOTE: 10ms < t1 < 50ms; 10ms < t2 < 50ms; -10ms < t3 < 10ms; t4 > 10ms; t5 > 100ns; t6 > 100ns; t7 > 10ms; and t8 > 100ms.
POWER-DOWN TIMING
1ms
500ms
STPD
Device Fully
Powers Down
Device Fully
Powers Up
NOTE: The shown power-up time is based on 1mF bypass capacitors on the reference pins.
See the Theory of Operation section for details.
10
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PIN CONFIGURATION
AGND
57
56
55
54
53
52
51
50
AGND
INT/EXT
58
INA+
AVDD
59
INA-
AGND
60
CM
AGND
61
REFT
ISET
62
REFB
AGND
63
TQFP
INB-
64
INB+
AGND
Top View
49
SEL
1
48 AGND
AGND
2
47 AGND
AVDD
3
46 AVDD
GND
4
45 STPD/SDATA
VDRV
5
44 GND
OEB
6
43 VDRV
GND
7
42 OEA/SCLK
VDRV
8
OVRB
9
40 VDRV
D0_B (LSB)
10
39 OVRA
D1_B
11
38 D11_A (MSB)
D2_B
12
37 D10_A
D3_B
13
36 D9_A
D4_B
14
35 D8_A
D5_B
15
34 D7_A
D6_B
16
33 D6_A
41 MSBI/SEN
26
27
28
29
30
31
32
D3_A
D4_A
D5_A
D11_B (MSB)
25
D2_A
D10_B
24
D1_A
D9_B
23
D0_A (LSB)
D7_B
22
DVA
21
GND
20
CLK
19
GND
18
DVB
17
D8_B
ADS5231
PIN DESCRIPTIONS
NAME
PIN #
AGND
2, 47–49, 55, 58, 59, 61, 64
I/O
DESCRIPTION
AVDD
3, 46, 57
CLK
24
CM
52
D0_A (LSB)
27
O
Data Bit 12 (D0), Channel A
D1_A
28
O
Data Bit 11 (D1), Channel A
D2_A
29
O
Data Bit 10 (D2), Channel A
D3_A
30
O
Data Bit 9 (D3), Channel A
D4_A
31
O
Data Bit 8 (D4), Channel A
D5_A
32
O
Data Bit 7 (D5), Channel A
D6_A
33
O
Data Bit 6 (D6), Channel A
D7_A
34
O
Data Bit 5 (D7), Channel A
D8_A
35
O
Data Bit 4 (D8), Channel A
D9_A
36
O
Data Bit 3 (D9), Channel A
D10_A
37
O
Data Bit 2 (D10), Channel A
D11_A (MSB)
38
O
Data Bit 1 (D11), Channel A
D0_B (LSB)
10
O
Data Bit 12 (D0), Channel B
Analog Ground
Analog Supply
I
Clock Input
Common-Mode Voltage Output
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PIN DESCRIPTIONS (continued)
NAME
PIN #
I/O
DESCRIPTION
D1_B
11
O
Data Bit 11 (D1), Channel B
D2_B
12
O
Data Bit 10 (D2), Channel B
D3_B
13
O
Data Bit 9 (D3), Channel B
D4_B
14
O
Data Bit 8 (D4), Channel B
D5_B
15
O
Data Bit 7 (D5), Channel B
D6_B
16
O
Data Bit 6 (D6), Channel B
D7_B
17
O
Data Bit 5 (D7), Channel B
D8_B
18
O
Data Bit 4 (D8), Channel B
D9_B
19
O
Data Bit 3 (D9), Channel B
D10_B
20
O
Data Bit 2 (D10), Channel B
D11_B (MSB)
21
O
Data Bit 1 (D11), Channel B
DVA
26
O
Data Valid, Channel A
DVB
22
O
Data Valid, Channel B
GND
4, 7, 23, 25, 44
INA
50
I
Analog Input, Channel A
IN
A
51
I
Complementary Analog Input, Channel A
INB
63
I
Analog Input, Channel B
IN
62
I
Complementary Analog Input, Channel B
INT/EXT
56
I
Reference Select; 0 = External (Default), 1 = Internal; Force high to set for internal reference
operation.
ISET
60
O
Bias Current Setting Resistor of 56.2kΩ to Ground
MSBI/SEN
41
I
When SEL = 0, MSBI (Most Significant Bit Invert)
1 = Binary Two's Complement, 0 = Straight Offset Binary (Default)
When SEL = 1, SEN (Serial Write Enable)
OEA/SCLK
42
I
When SEL = 0, OEA (Output Enable Channel A)
0 = Enabled (Default), 1 = Tri-State
When SEL = 1, SCLK (Serial Write Clock)
B
Output Buffer Ground
OE B
6
I
Output Enable, Channel B (0 = Enabled [Default], 1 = Tri-State)
OVRA
39
O
Over-Range Indicator, Channel A
OVRB
9
O
Over-Range Indicator, Channel B
REFB
54
I/O
Bottom Reference/Bypass (2Ω resistor in series with a 0.1µF capacitor to ground)
REFT
53
I/O
Top Reference/Bypass (2Ω resistor in series with a 0.1µF capacitor to ground)
SEL
1
I
Serial interface select signal. Setting SEL = 0 configures pins 41, 42, and 45 as MSBI, OEA, and
STPD, respectively. With SEL = 0, the serial interface is disabled. Setting SEL = 1 enables the serial
interface and configures pins 41, 42, and 45 as SEN, SCLK, and SDATA, respectively. Serial
registers can be programmed using these three signals. When used in this mode of operation, it is
essential to provide a low-going pulse on SEL in order to reset the serial interface registers as soon
as the device is powered up. SEL therefore also has the functionality of a RESET signal.
STPD/SDATA
45
I
When SEL = 0, STPD (Power-Down)
0 = Normal Operation (Default), 1 = Enabled
When SEL = 1, SDATA (Serial Write Data)
VDRV
5, 8, 40, 43
12
Output Buffer Supply
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DEFINITION OF SPECIFICATIONS
Minimum Conversion Rate
Analog Bandwidth
The analog input frequency at which the spectral
power of the fundamental frequency (as determined
by FFT analysis) is reduced by 3dB.
Aperture Delay
The delay in time between the rising edge of the
input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Duty Cycle
Pulse width high is the minimum amount of time that
the ADCLK pulse should be left in logic ‘1’ state to
achieve rated performance. Pulse width low is the
minimum time that the ADCLK pulse should be left in
a low state (logic ‘0’). At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are
exactly 1 LSB apart. DNL is the deviation of any
single LSB transition at the digital output from an
ideal 1 LSB step at the analog input. If a device
claims to have no missing codes, it means that all
possible codes (for a 12-bit converter, 4096 codes)
are present over the full operating range.
This is the minimum sampling rate where the ADC
still works.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but not including dc.
PS
SINAD + 10Log 10
PN ) PD
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first eight harmonics.
P
SNR + 10Log 10 S
PN
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Spurious-Free Dynamic Range
Effective Number of Bits (ENOB)
The ENOB is a measure of converter performance
as compared to the theoretical limit based on
quantization noise.
ENOB + SINAD * 1.76
6.02
Integral Nonlinearity (INL)
INL is the deviation of the transfer function from a
reference line measured in fractions of 1 LSB using a
best straight line or best fit determined by a least
square curve fit. INL is independent from effects of
offset, gain or quantization errors.
Maximum Conversion Rate
The encode rate at which parametric testing is
performed. This is the maximum sampling rate where
certified operation is given.
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
Two-Tone, Third-Order Intermodulation
Distortion
Two-tone IMD3 is the ratio of power of the
fundamental (at frequencies f1 and f2) to the power of
the worst spectral component of third-order
intermodulation distortion at either frequency 2f1 – f2
or 2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full-scale)
when the power of the fundamental is extrapolated to
the full-scale range of the converter.
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TYPICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
SPECTRAL PERFORMANCE
0
fIN = 1MHz
SNR = 71.4dBFS
SINAD = 71.3dBFS
SFDR = 88.8dBFS
-40
-60
-80
fIN = 5MHz
SNR = 71.3dBFS
SINAD = 71.1dBFS
SFDR = 87.8dBFS
-20
Amplitude (dB)
-20
Amplitude (dB)
SPECTRAL PERFORMANCE
0
-100
-40
-60
-80
-100
-120
-120
0
4
8
12
16
0
20
4
Input Frequency (MHz)
8
Figure 1.
Amplitude (dB)
Amplitude (dB)
16
20
fIN = 70MHz
SNR = 67.9dBFS
SINAD = 67.7dBFS
SFDR = 82.8dBFS
-20
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
4
8
12
16
0
20
4
Input Frequency (MHz)
12
Figure 4.
INTERMODULATION DISTORTION
DIFFERENTIAL NONLINEARITY
0.5
0
f1 = 4MHz (-7dBFS)
f2 = 5MHz (-7dBFS)
IMD = -89.6dBFS
-20
8
Input Frequency (MHz)
Figure 3.
fIN = 5MHz
0.4
0.3
0.2
-40
DNL (LSB)
Amplitude (dB)
20
SPECTRAL PERFORMANCE
0
fIN = 20MHz
SNR = 70.9dBFS
SINAD = 70.7dBFS
SFDR = 85.9dBFS
-20
16
Figure 2.
SPECTRAL PERFORMANCE
0
12
Input Frequency (MHz)
-60
-80
0.1
0
-0.1
-0.2
-0.3
-100
-0.4
-120
-0.5
0
4
8
12
16
20
0
Figure 5.
14
1024
2048
Code
Input Frequency (MHz)
Figure 6.
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4096
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
INTEGRAL NONLINEARITY
IAVDD, IVDRV vs CLOCK FREQUENCY
1.00
0.10
fIN = 5MHz
0.75
IAVDD, IDVDD (mA)
INL (LSB)
0.25
0
-0.25
-0.50
0.07
0.06
0.05
0.04
0.03
0.01
0
-1.00
0
1024
2048
3072
4096
20
25
30
35
40
Code
Sample Rate (MHz)
Figure 7.
Figure 8.
DYNAMIC PERFORMANCE vs CLOCK FREQUENCY
45
50
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
110
fIN = 5MHz
90
100
SNR (dBFS), SFDR (dBc)
SNR, SINAD (dBFS), SFDR (dBc)
IVDRV
0.02
-0.75
SFDR
85
80
SNR
75
70
SINAD
65
60
90
SFDR
80
70
SNR
60
50
40
55
30
20
25
30
35
40
45
50
55
60
65
0
70
20
40
60
80
100
Clock Frequency (MHz)
Input Frequency (MHz)
Figure 9.
Figure 10.
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE
WITH PLL ENABLED (default)
110
95
90
SFDR
80
70
SNR
60
50
fIN = 5MHz
90
SNR, SFDR (dBc, dBFS)
External Reference:
REFT = 2V
REFB = 1V
100
SNR (dBFS), SFDR (dBc)
IAVDD
0.08
0.50
95
fIN = 5MHz
0.09
SFDR
85
80
75
SNR
70
65
40
60
30
0
20
40
60
80
100
30
35
40
45
50
55
Input Frequency (MHz)
Duty Cycle (%)
Figure 11.
Figure 12.
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65
70
15
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
DYNAMIC PERFORMANCE vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
95
340
fIN = 5MHz
fIN = 5MHz
335
SFDR
Power Dissipation (mW)
SNR (dBFS), SFDR (dBc)
90
85
80
75
SNR
70
65
330
325
320
315
60
310
55
-40
+10
-15
+35
+60
+85
-40
Figure 13.
Figure 14.
3500
90
SNR, SFDR (dBc), SNR (dBFS)
100
3000
2500
2000
1500
1000
500
fIN = 5MHz
80
SNR (dBFS)
70
60
50
SFDR (dBc)
40
30
SNR (dBc)
20
10
-70
-60
-50
-40
-30
Figure 15.
Figure 16.
SWEPT INPUT POWER
SNR, SFDR (dBc), SNR (dBFS)
fIN = 20MHz
80
SNR (dBFS)
70
60
50
SFDR (dBc)
40
30
SNR (dBc)
20
10
0
-70
-60
-50
-40
-30
-20
Input Amplitude (dBFS)
Figure 17.
16
-20
Input Amplitude (dBFS)
Code
90
+85
0
N+5
N+4
N+3
N+2
N+1
N
N-1
N-2
N-3
N-4
0
100
+60
SWEPT INPUT POWER
4000
N-5
+35
Temperature (°C)
OUTPUT NOISE
Samples
+10
-15
Temperature (°C)
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0
-10
0
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SBAS295A – JULY 2004 – REVISED JANUARY 2007
APPLICATION INFORMATION
THEORY OF OPERATION
INPUT CONFIGURATION
The ADS5231 is a dual-channel, simultaneous
sampling analog-to-digital converter (ADC). Its low
power and high sampling rate of 40MSPS is
achieved using a state-of-the-art switched capacitor
pipeline architecture built on an advanced
low-voltage CMOS process. The ADS5231 operates
from a +3.3V supply voltage for both its analog and
digital supply connections. The ADC core of each
channel consists of a combination of multi-bit and
single-bit internal pipeline stages. Each stage feeds
its data into the digital error correction logic, ensuring
excellent differential linearity and no missing codes
at the 12-bit level. The conversion process is initiated
by the rising edge of the external clock. Once the
signal is captured by the input sample-and-hold
amplifier, the input sample is sequentially converted
within the pipeline stages. This process results in a
data latency of six clock cycles, after which the
output data is available as a 12-bit parallel word,
coded in either straight offset binary (SOB) or binary
two's complement (BTC) format. Since a common
clock controls the timing of both channels, the analog
signal is sampled simultaneously. The data on the
parallel ports is updated simultaneously as well.
Further processing can be timed using the individual
data valid output signal of each channel. The
ADS5231 features internal references that are
trimmed to ensure a high level of accuracy and
matching. The internal references can be disabled to
allow for external reference operation.
The analog input for the ADS5231 consists of a
differential
sample-and-hold
architecture
implemented using a switched capacitor technique;
see Figure 18. The sampling circuit consists of a
low-pass RC filter at the input to filter out noise
components that potentially could be differentially
coupled on the input pins. The inputs are sampled on
two 4pF capacitors. The RLC model is illustrated in
Figure 18.
INPUT DRIVER CONFIGURATIONS
Transformer-Coupled Interface
If the application requires a signal conversion from a
single-ended source to drive the ADS5231
differentially, an RF transformer could be a good
solution. The selected transformer must have a
center tap in order to apply the common-mode dc
voltage (VCMV) necessary to bias the converter
inputs. AC grounding the center tap will generate the
differential signal swing across the secondary
winding. Consider a step-up transformer to take
advantage of signal amplification without the
introduction of another noise source. Furthermore,
the reduced signal swing from the source may lead
to improved distortion performance. The differential
input configuration may provide a noticeable
advantage for achieving good SFDR performance
over a wide range of input frequencies. In this mode,
both inputs (IN and IN) of the ADS5231 see matched
impedances.
Figure 19 illustrates the schematic for the suggested
transformer-coupled interface circuit. The component
values of the RC low-pass filter may be optimized
depending on the desired roll-off frequency.
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IN
OUT
5nH
to 9nH
INP
1.5pF to
2.5pF
15W
to 25W
1W
3.2pF
to 4.8pF
15W
to 25W
IN
60W
to 120W
OUT
IN
OUT
OUT
OUTP
1.5pF
to 1.9pF
IN
OUTN
15W to 35W
15W
to 25W
3.2pF
to 4.8pF
15W
to 25W
IN
OUT
60W
to 120W
IN
OUT
5nH
to 9nH
INN
1.5pF to
2.5pF
Switches that are ON
in SAMPLE phase.
1W
Switches that are ON
in HOLD phase.
IN
OUT
Figure 18. Input Circuitry
RG
VIN
49.9Ω
0.1µF
1:n
24.9Ω
IN
OPA690
R1
RT
1/2
ADS5231
22pF
24.9Ω
IN
R2
CM
+1.5V
0.1µF
One Channel of Two
Figure 19. Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer
18
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DC-Coupled Input with Differential Amplifier
REFERENCE CIRCUIT
Applications that have a requirement for DC-coupling
a differential amplifier, such as the THS4503, can be
used to drive the ADS5231; this design is shown in
Figure 20. The THS4503 amplifier easily allows a
single-ended to differential conversion, which
reduces component cost.
CF
RS
RG
RF
+5V
VS
AVDD
RT
10µF
0.1µF
RISO
IN
VOCM
THS4503
1µF
RISO
1/2
ADS5231
IN
Internal Reference
All bias currents required for the proper operation of
the ADS5231 are set using an external resistor at
ISET (pin 60), as shown in Figure 21. Using a 56.2kΩ
resistor on ISET generates an internal reference
current of about 20µA. This current is mirrored
internally to generate the bias current for the internal
blocks. While a 5% resistor tolerance is adequate,
deviating from this resistor value alters and degrades
device performance. For example, using a larger
external resistor at ISET reduces the reference bias
current and thereby scales down the device
operating power.
CM
RG
RF
AVDD
CF
ADS5231
0.1µF
REFT
Figure 20. Using the THS4503 with the ADS5231
In addition, the VOCM pin on the THS4503 can be
directly tied to the common-mode pin (CM) of the
ADS5231 to set up the necessary bias voltage for
the converter inputs. In the circuit example shown in
Figure 20, the THS4503 is configured for unity gain.
If required, a higher gain can easily be achieved as
well by adding small capacitors (such as 10pF) in
parallel with the feedback resistors to create a
low-pass filter. Since the THS4503 is driving a
capacitive load, small series resistors in the output
ensure stable operation. Further details of this and
the overall operation of the THS4503 may be found
in its product data sheet (available for download at
www.ti.com). In general, differential amplifiers
provide a high-performance driver solution for
baseband applications, and other differential
amplifier models may be selected depending on the
system requirements.
Input Over-Voltage Recovery
The differential full-scale input range supported by
the ADS5231 is 2VPP. For a nominal value of VCM
(+1.5V), IN and IN can swing from 1V to 2V. The
ADS5231 is especially designed to handle an
over-voltage differential peak-to-peak voltage of 4V
(2.5V and 0.5V swings on IN and IN). If the input
common-mode voltage is not considerably different
from VCM during overload (less than 300mV),
recovery from an over-voltage input condition is
expected to be within three clock cycles. All of the
amplifiers in the sample-and-hold stage and the ADC
core are especially designed for excellent recovery
from an overload signal.
CM
INT/EXT
ISET
2W
0.1mF
+
2.2mF
56.2kW
REFB
2W
+
2.2mF
0.1mF
Figure 21. Internal Reference Circuit
As part of the internal reference circuit, the ADS5231
provides a common-mode voltage output at pin 52,
CM. This common-mode voltage is typically +1.5V.
While this is similar to the common-mode voltage
used internally within the ADC pipeline core, the
CM-pin has an independent buffer amplifier, which
can deliver up to ±2mA of current to an external
circuit for proper input signal level shifting and
biasing. In order to obtain optimum dynamic
performance, the analog inputs should be biased to
the recommended common-mode voltage (1.5V).
While good performance can be maintained over a
certain CM-range, larger deviations may compromise
device performance and could also negatively affect
the overload recovery behavior. Using the internal
reference mode requires the INT/EXT pin to be
forced high, as shown in Figure 21.
The ADS5231 requires solid high-frequency
bypassing on both reference pins, REFT and REFB;
see Figure 21. Use ceramic 0.1µF capacitors (size
0603, or smaller), located as close as possible to the
pins.
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External Reference
The ADS5231 also supports the use of external
reference voltages. External reference voltage mode
involves applying an external top reference at REFT
(pin 53) and a bottom reference at REFB (pin 54).
Setting the ADS5231 for external reference mode
also requires taking the INT/EXT pin low. In this
mode, the internal reference buffer is tri-stated. Since
the switching current for the two ADC channels
comes from the externally-forced references, it is
possible for the device performance to be slightly
lower than when the internal references are used. It
should be noted that in external reference mode, VCM
and ISET continue to be generated from the internal
bandgap voltage, as they are in the internal
reference mode. Therefore, it is important to ensure
that
the
common-mode
voltage
of
the
externally-forced reference voltages matches to
within 50mV of VCM (+1.5VDC).
The external reference circuit must be designed to
drive the internal reference impedance seen between
the REFT and REFB pins. To establish the drive
requirements, consider that the external reference
circuit needs to supply an average switching current
of at least 1mA. This dynamic switching current
depends on the actual device sampling rate and the
signal level. The external reference voltages can
vary as long as the value of the external top
reference stays within the range of +1.875V to
+2.0V, and the external bottom reference stays
within +1.0V to +1.125V. Consequently, the full-scale
input range can be set between 1.5VPP and 2VPP
(FSR = 2x [REFT – REFB] ).
CLOCK INPUT
The ADS5231 requires a single-ended clock source.
The
clock
input,
CLK,
represents
a
CMOS-compatible logic input with an input
impedance of about 5pF. For high input frequency
sampling, it is recommended to use a clock source
with very low jitter. A low-jitter clock is essential in
order to preserve the excellent ac performance of the
ADS5231. The converter itself is specified for a low
1.0ps (rms) jitter. Generally, as the input frequency
increases, clock jitter becomes more dominant in
20
maintaining a good signal-to-noise ratio (SNR). This
condition is particularly critical in IF-sampling
applications; for example, where the sampling
frequency is lower than the input frequency
(under-sampling). The following equation can be
used to calculate the achievable SNR for a given
input frequency and clock jitter (tJA in psRMS):
1
SNR + 20LOG 10
ǒ2p f IN t JAǓ
(1)
The ADS5231 will enter into a power-down mode if
the sampling clock rate drops below a limit of
approximately 2MSPS. If the sampling rate is
increased above this threshold, the ADS5231 will
automatically resume normal operation.
PLL CONTROL
The ADS5231 has an internal PLL that is enabled by
default. The PLL enables a wide range of clock duty
cycles. Good performance is obtained for duty cycles
up to 40%–60%, though the ensured electrical
specifications presume that the duty cycle is between
45%–55%. The PLL automatically limits the minimum
frequency of operation to 20MSPS. For operation
below 20MSPS, the PLL can be disabled by
programming the internal registers through the serial
interface. With the PLL disabled, the clock speed can
go down to 2MSPS. With the PLL disabled, the clock
duty cycle needs to be constrained closer to 50%.
OUTPUT INFORMATION
The ADS5231 provides two channels with 12 data
outputs (D11 to D0, with D11 being the MSB and D0
the LSB), data-valid outputs (DVA, DVB, pin 26 and
pin 22, respectively), and individual out-of-range
indicator output pins (OVRA/OVRB, pin 39 and pin 9,
respectively).
The output circuitry of the ADS5231 has been
designed to minimize the noise produced by
transients of the data switching, and in particular its
coupling to the ADC analog circuitry.
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DATA OUTPUT FORMAT (MSBI)
The ADS5231 makes two data output formats
available: the Straight Offset Binary code (SOB) or
the Binary Two's Complement code (BTC). The
selection of the output coding is controlled by the
MSBI (pin 41). Because the MSBI pin has an internal
pull-down, the ADS5231 will operate with the SOB
code as its default setting. Forcing the MSBI pin high
will enable BTC coding. The two code structures are
identical, with the exception that the MSB is inverted
for BTC format; as shown in Table 1.
OUTPUT ENABLE (OE)
Digital outputs of the ADS5231 can be set to
high-impedance (tri-state), exercising the output
enable pins, OEA (pin 42), and OEB (pin 6). Internal
pull-downs configure the output in enable mode for
normal operation. Applying a logic high voltage will
disable the outputs. Note that the OE-function is not
designed to be operated dynamically (that is, as a
fast multiplexer) because it may lead to corrupt
conversion results. Refer to the Electrical
Characteristics table to observe the specified tri-state
enable and disable times.
OVER-RANGE INDICATOR (OVR)
If the analog input voltage exceeds the full-scale
range set by the reference voltages, an over-range
condition exists. The ADS5231 incorporates a
function that monitors the input voltage and detects
any such out-of-range condition. This operation
functions for each of the two channels independently.
The current state can be read at the over-range
indicator pins (pins 9 and 39). This output is low
when the input voltage is within the defined input
range. It will change to high if the applied signal
exceeds the full-scale range. It should be noted that
each of the OVR outputs is updated along with the
data output corresponding to the particular sampled
analog input voltage. Therefore, the OVR state is
subject to the same pipeline delay as the digital data
(six clock cycles).
OUTPUT LOADING
It is recommended that the capacitive loading on the
data output lines be kept as low as possible,
preferably below 15pF. Higher capacitive loading will
cause larger dynamic currents as the digital outputs
are changing. Such high current surges can feed
back to the analog portion of the ADS5231 and
adversely affect device performance. If necessary,
external buffers or latches close to the converter
output pins may be used to minimize the capacitive
loading.
SERIAL INTERFACE
The ADS5231 has a serial interface that can be used
to program internal registers. The serial interface is
disabled if SEL is connected to 0.
When the serial interface is to be enabled, SEL
serves the function of a RESET signal. After the
supplies have stabilized, it is necessary to give the
device a low-going pulse on SEL. This results in all
internal registers resetting to their default value of 0
(inactive). Without a reset, it is possible that registers
may be in their non-default state on power-up. This
condition may cause the device to malfunction.
Table 1. Coding Table for Differential Input Configuration and 2VPP Full-Scale Input Range
STRAIGHT OFFSET BINARY (SOB; MSBI = 0)
BINARY TWO'S COMPLEMENT (BTC; MSBI = 1)
DIFFERENTIAL INPUT
D11............D0
D11............D0
+FS (IN = +2V, IN = +1V)
1111 1111 1111
0111 1111 1111
+1/2 FS
1100 0000 0000
0100 0000 0000
Bipolar Zero (IN = IN = CMV)
1000 0000 0000
0000 0000 0000
–1/2 FS
0100 0000 0000
1100 0000 0000
–FS (IN = +1V, IN = +2V)
0000 0000 0000
1000 0000 0000
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21
ADS5231
www.ti.com
SBAS295A – JULY 2004 – REVISED JANUARY 2007
POWER-DOWN MODE
The ADS5231 has a power-down pin, STPD (pin 45).
The internal pull-down is in default mode for the
device during normal operation. Forcing the STPD
pin high causes the device to enter into power-down
mode. In power-down mode, the reference and clock
circuitry as well as all the channels are powered
down. Device power consumption drops to less than
90mW. As previously mentioned, the ADS5231 also
enters into a power-down mode if the clock speed
drops below 2MSPS (see the Clock Input section).
When STPD is pulled high, the internal buffers
driving REFT and REFB are tri-stated and the outputs
are forced to a voltage roughly equal to half of the
voltage on AVDD. Speed of recovery from the
power-down mode depends on the value of the
external capacitance on the REFT and REFB pins.
For capacitances on REFT and REFB less than 1µF,
the reference voltages settle to within 1% of their
steady-state values in less than 500µs. Either of the
two channels can also be selectively powered-down
through the serial interface when it is enabled.
The ADS5231 also has an internal circuit that
monitors the state of stopped clocks. If ADCLK is
stopped for longer than 250ns, or if it runs at a speed
less than 2MHz, this monitoring circuit generates a
logic signal that puts the device in a partial
power-down state. As a result, the power
consumption of the device is reduced when CLK is
stopped. The recovery from such a partial
power-down takes approximately 100µs. This
constraint is described in Table 2.
Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION
TYP
Recovery from power-down mode (STPD = 1 to STPD = 0).
500µs
Recovery from momentary clock stoppage ( < 250ns).
10µs
Recovery from extended clock stoppage ( > 250ns).
100µs
22
Submit Documentation Feedback
REMARKS
Capacitors on REFT and REFB less than 1µF.
ADS5231
www.ti.com
SBAS295A – JULY 2004 – REVISED JANUARY 2007
LAYOUT AND DECOUPLING
CONSIDERATIONS
Proper grounding and bypassing, short lead length,
and the use of ground planes are particularly
important for high-frequency designs. Achieving
optimum performance with a fast sampling converter
such as the ADS5231 requires careful attention to
the printed circuit board (PCB) layout to minimize the
effects of board parasitics and to optimize
component placement. A multilayer board usually
ensures best results and allows convenient
component placement.
The ADS5231 should be treated as an analog
component and the supply pins connected to clean
analog supplies. This layout ensures the most
consistent performance results, since digital supplies
often carry a high level of switching noise, which
could couple into the converter and degrade device
performance. As mentioned previously, the output
buffer supply pins (VDRV) should also be connected
to a low-noise supply. Supplies of adjacent digital
circuits may carry substantial current transients. The
supply voltage should be filtered before connecting
to the VDRV pin of the converter. All ground pins
should directly connect to an analog ground.
Because of its high sampling frequency, the
ADS5231
generates
high-frequency
current
transients and noise (clock feed-through) that are fed
back into the supply and reference lines. If not
sufficiently bypassed, this feed-through adds noise to
the conversion process. All AVDD pins may be
bypassed with 0.1µF ceramic chip capacitors (size
0603, or smaller). A similar approach may be used
on the output buffer supply pins, VDRV. In order to
minimize the lead and trace inductance, the
capacitors should be located as close to the supply
pins as possible. Where double-sided component
mounting is allowed, they are best placed directly
under the package. In addition, larger bipolar
decoupling capacitors (2.2µF to 10µF), effective at
lower frequencies, may also be used on the main
supply pins. They can be placed on the PCB in
proximity (< 0.5") to the ADC.
If the analog inputs to the ADS5231 are driven
differentially, it is especially important to optimize
towards a highly symmetrical layout. Small trace
length differences may create phase shifts,
compromising a good distortion performance. For
this reason, the use of two single op amps rather
than one dual amplifier enables a more symmetrical
layout and a better match of parasitic capacitances.
The pin orientation of the ADS5231 quad-flat
package follows a flow-through design, with the
analog inputs located on one side of the package
while the digital outputs are located on the opposite
side. This design provides a good physical isolation
between the analog and digital connections. While
designing the layout, it is important to keep the
analog signal traces separated from any digital lines
to prevent noise coupling onto the analog portion.
Single-ended clock lines must be short and should
not cross any other signal traces.
Short circuit traces on the digital outputs will
minimize capacitive loading. Trace length should be
kept short to the receiving gate (< 2") with only one
CMOS gate connected to one digital output.
Submit Documentation Feedback
23
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS5231IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
ADS5231IPAG
ADS5231IPAGG4
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
ADS5231IPAG
ADS5231IPAGT
ACTIVE
TQFP
PAG
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
ADS5231IPAG
ADS5231IPAGTG4
ACTIVE
TQFP
PAG
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
ADS5231IPAG
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS5231IPAGT
Package Package Pins
Type Drawing
TQFP
PAG
64
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5231IPAGT
TQFP
PAG
64
250
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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