ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Dual, 10-Bit, 65MSPS, +3.3V
Analog-to-Digital Converter
FEATURES
1
DESCRIPTION
• Single +3.3V Supply
• High SNR: 61.7dBFS at fIN = 5MHz
• Total Power Dissipation:
Internal Reference: 366mW
External Reference: 330mW
• Internal or External Reference
• Low DNL: ±0.1LSB
• Flexible Input Range: 1.5VPP to 2VPP
• TQFP-64 Package
2
The ADS5237 is a dual, high-speed, high dynamic
range, 10-bit, pipelined analog-to-digital converter
(ADC). This device includes a high-bandwidth
sample-and-hold amplifier that gives excellent
spurious performance up to and beyond the Nyquist
rate. The differential nature of the sample-and-hold
amplifier and ADC circuitry minimizes even-order
harmonics and gives excellent common-mode noise
immunity.
The ADS5237 provides for setting the full-scale range
of the converter without any external reference
circuitry. The internal reference can be disabled,
allowing low-drive, external references to be used for
improved tracking in multichannel systems.
APPLICATIONS
•
•
•
•
•
•
Communications IF Processing
Communications Base Stations
Test Equipment
Medical Imaging
Video Digitizing
CCD Digitizing
The ADS5237 provides an over-range indicator flag
to indicate an input signal that exceeds the full-scale
input range of the converter. This flag can be used to
reduce the gain of front-end gain control circuitry.
There is also an output enable pin to allow for
multiplexing and testing on a printed circuit board
(PCB).
The ADS5237 employs digital error correction
techniques to provide excellent differential linearity for
demanding imaging applications. The ADS5237 is
available in a TQFP-64 package.
AVDD
SDATA SEN SCLK SEL
VDRV
OEA
ADS5237
Serial
Interface
DISABLE_PLL
10-Bit
Pipelined
ADC
INA
VIN
S/H
INA
Error
Correction
Logic
3-State
Output
D9A
·
·
·
D0A
OVRA
DVA
Internal
Reference
INT/EXT
Timing/Duty Cycle Adjust (PLL)
CLK
CM
REFT
REFB
DVB
INB
VIN
10-Bit
Pipelined
ADC
S/H
INB
Error
Correction
Logic
3-State
Output
D9B
·
·
·
D0B
OVRB
STPD
OEB
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
ADS5237
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SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
ADS5237
TQFP-64
PAG
(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +85°C
ADS5237IPAG
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5237IPAG
Tray, 160
ADS5237IPAGT
Tape and Reel, 250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
ADS5237
UNIT
Supply voltage range, AVDD
–0.3 to +3.8
V
Supply voltage range, VDRV
–0.3 to +3.8
V
Voltage between AVDD and VDRV
–0.3 to +0.3
V
Voltage applied to external REF pins
–0.3 to +2.4
V
(2)
–0.3 to min [3.3, (AVDD + 0.3)]
V
+100
°C
–40 to +85
°C
Lead temperature
+260
°C
Junction temperature
+105
°C
Storage temperature
–65 to +150
°C
Analog input pins
Case temperature
Operating free-air temperature range, TA
(1)
(2)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
The dc voltage applied on the input pins should not go below –0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or
(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25Ω should be added in series with each
of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either
as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and
+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed
1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
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RECOMMENDED OPERATING CONDITIONS
ADS5237
PARAMETER
MIN
TYP
MAX
UNIT
3.0
3.3
3.6
V
SUPPLIES AND REFERENCES
Analog supply voltage, AVDD
Output driver supply voltage, VDRV
3.0
3.3
3.6
V
REFT — External reference mode
1.875
2.0
2.05
V
REFB — External reference mode
0.95
1.0
1.125
V
REFCM = (REFT + REFB)/2 – External reference mode
(1)
Reference = (REFT – REFB) – External reference mode
VCM ±50mV
0.75
Analog input common-mode range (1)
1.0
V
1.1
V
VCM 50mV
V
CLOCK INPUT AND OUTPUTS
ADCLK Input sample rate
PLL enabled (default)
20
65
MSPS
PLL disabled
2
30 (2)
MSPS
ADCLK duty cycle
PLL enabled (default)
45
Low-level voltage clock input
High-level voltage clock input
2.2
Operating free-air temperature, TA
–40
55
MSPS
0.6
V
+85
°C
V
Thermal characteristics:
(1)
(2)
θJA
42.8
°C/W
θJC
18.7
°C/W
These voltages need to be set to 1.5V ±50mV if they are derived independent of VCM.
When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45%–55% duty cycle variation
is acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then the
duty cycle needs to be maintained within a 48%–52% duty cycle.
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ELECTRICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 65MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
ADS5237
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LSB
DC ACCURACY
No missing codes
Tested
DNL Differential nonlinearity
INL Integral nonlinearity
fIN = 5MHz
–0.5
±0.1
+0.5
fIN = 5MHz
–1
±0.1
+1
LSB
–0.75
0.2
+0.75
%FS
Offset error (1)
Offset temperature coefficient (2)
Fixed attenuation in channel
±6
(3)
ppm/°C
1
Fixed attenuation matching across channels
Gain error/reference error (4)
–3.5
Gain error temperature coefficient
%FS
0.01
0.2
dB
±1.0
+3.5
% FS
±40
ppm/°C
POWER REQUIREMENTS (5)
Internal Reference
Power dissipation (5)
Analog only (AVDD)
260
297
mW
Output driver (VDRV)
106
136
mW
366
433
mW
Total power dissipation
External Reference
Power dissipation
Analog only (AVDD)
224
mW
Output driver (VDRV)
106
mW
330
mW
Total power dissipation
VREFT
1.875
2
2.05
mW
VREFB
0.95
1
1.125
mW
Total Power-Down
88
mW
REFERENCE VOLTAGES
VREFT Reference top (internal)
1.9
2.0
2.1
V
VREFB Reference bottom (internal)
0.9
1.0
1.1
V
VCM Common-mode voltage
1.4
1.5
1.6
V
VCM output current
(6)
±50mV change in voltage
VREFT Reference top (external)
±2
V
VREFB Reference bottom (external)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
mA
1.875
1.125
V
External reference common-mode
VCM ±50mV
V
External reference input current (7)
1.0
mA
Offset error is the deviation of the average code from mid-code with –1dBFS sinusoid from ideal mid-code (512). Offset error is
expressed in terms of percent of full-scale.
If the offset at temperatures T1 and T2 is O1 and O2, respectively (where O1 and O2 are measured in LSBs), the offset temperature
coefficient in ppm/°C is calculated as (O1 – O2)/(T1 – T2) × 16/1024.
Fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold amplifier. When the differential voltage at
the analog input pins is changed from –VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code
(1024LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT – REFB).
The reference voltages are trimmed at production so that (VREFT – VREFB) is within ± 35mV of the ideal value of 1V. This specification
does not include fixed attenuation.
Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.
The VCM output current specified is the drive of the VCM buffer if loaded externally.
Average current drawn from the reference pins in the external reference mode.
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ELECTRICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 65MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
ADS5237
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Differential input capacitance
3
Analog input common-mode range
Differential input voltage range
Voltage overload recovery time
VCM ±0.05
V
Internal reference
2.02
VPP
External reference
2.02 × (VREFT – VREFB)
VPP
(8)
Input bandwidth
pF
–3dBFS input, 25Ω series
resistance
3
CLK
cycles
300
MHz
DIGITAL DATA INPUTS
Logic family
+3V CMOS Compatible
VIH High-level input voltage
VIN = 3.3V
VIL Low-level input voltage
VIN = 3.3V
2.2
V
0.6
CIN Input capacitance
3
V
pF
DIGITAL OUTPUTS
Straight offset binary (9)
Data format
Logic family
CMOS
Logic coding
Straight offset binary or BTC
Low output voltage (IOL = 50μA)
+0.4
High output voltage (IOH = 50μA)
+2.4
V
V
3-state enable time
2
Clocks
3-state disable time
2
Clocks
Output capacitance
3
pF
SERIAL INTERFACE
SCLK Serial clock input frequency
20
MHz
65
MSPS
CONVERSION CHARACTERISTICS
Sample rate
20
Data latency
(8)
(9)
6
CLK
cycles
A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
Option for binary two’s complement output.
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AC CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, VDRV = 3.3V, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless otherwise noted.
ADS5237
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 5MHz
75
86
dBc
fIN = 32.5MHz
85
dBc
fIN = 70MHz
83
dBc
92
dBc
fIN = 32.5MHz
87
dBc
fIN = 70MHz
85
dBc
86
dBc
fIN = 32.5MHz
85
dBc
fIN = 70MHz
83
dBc
61.7
dBFS
fIN = 32.5MHz
61.0
dBFS
fIN = 70MHz
60.7
dBFS
61.6
dBFS
fIN = 32.5MHz
60.9
dBFS
fIN = 70MHz
60.5
dBFS
5MHz full-scale signal applied to one channel;
measurement taken on the channel with no input signal
–85
dBc
90.9
dBFS
DYNAMIC CHARACTERISTICS
SFDR Spurious-free dynamic range
fIN = 5MHz
HD2 2nd-order harmonic distortion
82
fIN = 5MHz
HD3 3rd-order harmonic distortion
75
fIN = 5MHz
SNR Signal-to-noise ratio
60.5
fIN = 5MHz
SINAD Signal-to-noise and distortion
Crosstalk
IMD3
6
Two-tone, third-order
intermodulation distortion
f1 = 4MHz at –7dBFS
f2 = 5MHz at –7dBFS
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TIMING DIAGRAMS
tA
N+2
N
Analog
Input
N+4
N+3
N+1
tC
CLK
t1
t2
DATA[D9:D0]
tDV
DV
OE
tOE
tOE
D9:D0
DATA
TIMING CHARACTERISTICS (1)
Typical values at TA = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty
cycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
65MSPS With PLL ON
tA Aperture delay
Aperture jitter
ns
1.0
ps
ns
t1 Data setup time (2)
2
3.2
t2 Data hold time (3)
6.3
8.5
ns
6
Clocks
tD Data latency
tDR, tDF Data rise/fall time (4)
Data valid (DV) duty cycle
tDV Input clock rising to DV fall edge
(1)
(2)
(3)
(4)
2.1
0.5
2
3
30
40
55
ns
%
10
11.5
14
ns
Specifications assured by design and characterization; not production tested.
Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.
Measured from the 50% point of the falling edge of DV to the data becoming invalid.
Measured between 20% to 80% of logic levels.
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TIMING CHARACTERISTICS (continued)
Typical values at TA = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty
cycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
50MSPS With PLL ON
tA Aperture delay
Aperture jitter
2.1
ns
1.0
ps
ns
t1 Data setup time
3.2
4.5
t2 Data hold time
10
11
ns
6
Clocks
tD Data latency
tDR, tDF Data rise/fall time
Data valid (DV) duty cycle
tDV Input clock rising to DV fall edge
0.5
2
3
30
40
55
ns
%
11.5
13.5
15.5
ns
40MSPS With PLL ON
tA Aperture delay
Aperture jitter
2.1
ns
1.0
ps
ns
t1 Data setup time
3.7
5.5
t2 Data hold time
11.5
13.5
ns
6
Clocks
tD Data latency
tDR, tDF Data rise/fall time
Data valid (DV) duty cycle
tDV Input clock rising to DV fall edge
0.5
2
3
30
40
55
ns
%
13.5
16
18.5
ns
30MSPS With PLL OFF
tA Aperture delay
Aperture jitter
2.1
ns
1.0
ps
ns
t1 Data setup time
8
10
t2 Data hold time
14
19
ns
6
Clocks
tD Data latency
tDR, tDF Data rise/fall time
Data valid (DV) duty cycle
tDV Input clock rising to DV fall edge
0.5
2
3.5
30
45
55
ns
%
16
19
21
ns
20MSPS With PLL ON
tA Aperture delay
Aperture jitter
2.1
ns
1.0
ps
ns
t1 Data setup time
10
12
t2 Data hold time
20
25
ns
6
Clocks
tD Data latency
tDR, tDF Data rise/fall time
Data valid (DV) duty cycle
tDV Input clock rising to DV fall edge
0.5
2
3.5
30
45
55
ns
%
20
25
30
ns
20MSPS With PLL OFF
tA Aperture delay
Aperture jitter
ns
1.0
ps
ns
t1 Data setup time
10
12
t2 Data hold time
20
25
ns
6
Clocks
tD Data latency
tDR, tDF Data rise/fall time
Data valid (DV) duty cycle
tDV Input clock rising to DV fall edge
8
2.1
0.5
2
3.5
30
45
55
%
20
25
30
ns
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TIMING CHARACTERISTICS (continued)
Typical values at TA = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty
cycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
2MSPS With PLL OFF
tA Aperture delay
Aperture jitter
2.1
ns
1.0
ps
ns
t1 Data setup time
150
200
t2 Data hold time
200
250
ns
6
Clocks
tD Data latency
tDR, tDF Data rise/fall time
Data valid (DV) duty cycle
tDV Input clock rising to DV fall edge
0.5
2
3.5
30
45
55
ns
%
200
225
250
ns
SERIAL INTERFACE TIMING
Outputs change on
next rising clock edge
after SEN goes high.
CLK
SEN
Start Sequence
t1
t6
t7
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
D7
(MSB)
SDATA
D6
D5
D4
D3
D2
D0
D1
t4
t5
NOTE: Data are shifted in MSB first.
ADS5237
PARAMETER
DESCRIPTION
MIN
t1
Serial CLK period
50
TYP
MAX
UNIT
ns
t2
Serial CLK high time
20
ns
t3
Serial CLK low time
20
ns
t4
Data setup time
5
ns
t5
Data hold time
5
ns
t6
SEN fall to SCLK rise
8
ns
t7
SCLK rise to SEN rise
8
ns
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Table 1. SERIAL REGISTER MAP (1) (2)
ADDRESS
(1)
(2)
10
DATA
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
X
X
X
0
Normal mode
0
0
0
0
X
X
X
1
Power-down both channels
0
0
0
0
X
X
0
X
Straight offset binary output
0
0
0
0
X
X
1
X
Binary two's complement output
0
0
0
0
X
0
X
X
Channel B digital outputs enabled
0
0
0
0
X
1
X
X
Channel B digital outputs 3-stated
0
0
0
0
0
X
X
X
Channel A digital outputs enabled
0
0
0
0
1
X
X
X
Channel A digital outputs 3-stated
0
0
1
0
0
0
0
0
Normal mode
0
0
1
0
0
1
0
0
All digital outputs set to '1'
0
0
1
0
1
0
0
0
All digital outputs set to '0'
0
0
1
1
0
0
X
0
Normal mode
0
0
1
1
1
X
X
0
Channel A powered down
0
0
1
1
X
1
X
0
Channel B powered down
0
0
1
1
X
X
0
0
PLL enabled (default)
0
0
1
1
X
X
1
0
PLL disabled
X = do not care.
Shown for the case where serial interface is used.
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RECOMMENDED POWER-UP SEQUENCING
Shown for the case where the serial interface is used.
AVDD (3V to 3.6V)
t1
AVDD
VDRV (3V to 3.6V)
t2
VDRV
t3
t4
t7
t5
Device Ready
For ADC Operation
t6
SEL
Device Ready
For Serial Register Write
SEN
Device Ready
For ADC Operation
Start of Clock
CLK
t8
NOTE: 10μs < t1 < 50ms; 10μs < t2 < 50ms; –10ms < t3 < 10ms; t4 > 10ms; t5 > 100ns; t6 > 100ns; t7 > 10ms; and t8 > 100μs.
POWER-DOWN TIMING
1m s
500ms
STPD
Device Fully
Powers Down
Device Fully
Powers Up
NOTE: The shown power-up time is based on 1μF bypass capacitors on the reference pins. See the Theory of Operation section for details.
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PIN CONFIGURATION
55
54
53
AGND
56
INA+
REFT
57
CM
REFB
58
INA-
AGND
59
INT/EXT
60
AGND
61
AVDD
62
AGND
63
AGND
INB-
64
ISET
AGND
INB+
TQFP-64
(Top View)
52
51
50
49
SEL
1
48
AGND
AGND
2
47
AGND
AVDD
3
46
AVDD
GND
4
45
STPD/SDATA
VDRV
5
44
GND
OEB
6
43
VDRV
GND
7
42
OEA/SCLK
VDRV
8
41
MSBI/SEN
OVRB
9
40
VDRV
NC
10
39
OVRA
NC
11
38
D9_A (MSB)
D0_B (LSB)
12
37
D8_A
D1_B
13
36
D7_A
D2_B
14
35
D6_A
D3_B
15
34
D5_A
D4_B
16
33
D4_A
26
27
28
29
30
NC
D0_A (LSB)
D1_A
31
32
D3_A
25
D2_A
24
NC
D8_B
23
DVA
D7_B
22
GND
D6_B
21
CLK
20
GND
19
DVB
18
D9_B (MSB)
17
D5_B
ADS5237
Table 2. TERMINAL FUNCTIONS
NAME
PIN #
AGND
2, 47–49, 55, 58, 59, 61, 64
AVDD
3, 46, 57
CLK
24
I
Clock input
CM
52
O
Common-mode voltage output
D0_A (LSB)
29
O
Data bit 10 (D0), channel A
D1_A
30
O
Data bit 9 (D1), channel A
D2_A
31
O
Data bit 8 (D2), channel A
D3_A
32
O
Data bit 7 (D3), channel A
D4_A
33
O
Data bit 6 (D4), channel A
D5_A
34
O
Data bit 5 (D5), channel A
D6_A
35
O
Data bit 4 (D6), channel A
D7_A
36
O
Data bit 3 (D7), channel A
D8_A
37
O
Data bit 2 (D8), channel A
D9_A (MSB)
38
O
Data bit 1 (D9), channel A
D0_B (LSB)
12
O
Data bit 10 (D0), channel B
D1_B
13
O
Data bit 9 (D1), channel B
12
I/O
DESCRIPTION
Analog ground
Analog supply
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Table 2. TERMINAL FUNCTIONS (continued)
NAME
PIN #
I/O
DESCRIPTION
D2_B
14
O
Data bit 8 (D2), channel B
D3_B
15
O
Data bit 7 (D3), channel B
D4_B
16
O
Data bit 6 (D4), channel B
D5_B
17
O
Data bit 5 (D5), channel B
D6_B
18
O
Data bit 4 (D6), channel B
D7_B
19
O
Data bit 3 (D7), channel B
D8_B
20
O
Data bit 2 (D8), channel B
D9_B (MSB)
21
O
Data bit 1 (D9), channel B
DVA
26
O
Data valid, channel A
DVB
22
O
Data valid, channel B
GND
4, 7, 23, 25, 44
INA
50
I
Analog input, channel A
IN
A
51
I
Complementary analog input, channel A
INB
63
I
Analog input, channel B
IN
62
I
Complementary analog input, channel B
INT/EXT
56
I
Reference select; 0 = External (default), 1 = Internal; force high to set for internal reference operation.
ISET
60
O
Bias current setting resistor of 56.2kΩ to ground
MSBI/SEN
41
I
When SEL = 0, MSBI (most significant bit Invert)
1 = Binary two's complement, 0 = Straight offset binary (default)
When SEL = 1, SEN (serial write enable)
NC
10, 11, 27, 28
OEA/SCLK
42
I
When SEL = 0, OEA (output enable channel A)
0 = Enabled (default), 1 = 3-state
When SEL = 1, SCLK (serial write clock)
B
Output buffer ground
OE B
6
I
Output enable, channel B (0 = Enabled [default], 1 = 3-state)
OVRA
39
O
Over-range Indicator, channel A
OVRB
9
O
Over-range Indicator, channel B
REFB
54
I/O
Bottom reference/bypass (2Ω resistor in series with a 0.1μF capacitor to ground)
REFT
53
I/O
Top reference/bypass (2Ω resistor in series with a 0.1μF capacitor to ground)
SEL
1
I
Serial interface select signal. Setting SEL = 0 configures pins 41, 42, and 45 as MSBI, OEA, and
STPD, respectively. With SEL = 0, the serial interface is disabled. Setting SEL = 1 enables the serial
interface and configures pins 41, 42, and 45 as SEN, SCLK, and SDATA, respectively. Serial
registers can be programmed using these three signals. When used in this mode of operation, it is
essential to provide a low-going pulse on SEL in order to reset the serial interface registers as soon
as the device is powered up. SEL therefore also has the functionality of a RESET signal.
STPD/SDATA
45
I
When SEL = 0, STPD (power-down)
0 = Normal operation (default), 1 = Enabled
When SEL = 1, SDATA (serial write data)
VDRV
5, 8, 40, 43
Output buffer supply
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DEFINITION OF SPECIFICATIONS
Minimum Conversion Rate
Analog Bandwidth
The analog input frequency at which the spectral
power of the fundamental frequency (as determined
by FFT analysis) is reduced by 3dB.
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Duty Cycle
Pulse width high is the minimum amount of time that
the ADCLK pulse should be left in logic ‘1’ state to
achieve rated performance. Pulse width low is the
minimum time that the ADCLK pulse should be left in
a low state (logic ‘0’). At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are
exactly 1 LSB apart. DNL is the deviation of any
single LSB transition at the digital output from an
ideal 1 LSB step at the analog input. If a device
claims to have no missing codes, it means that all
possible codes (for a 10-bit converter, 1024 codes)
are present over the full operating range.
This is the minimum sampling rate where the ADC
still works.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but not
including dc.
PS
SINAD = 10Log10
PN + PD
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first eight harmonics.
PS
SNR = 10Log10
PN
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Effective Number of Bits (ENOB)
Spurious-Free Dynamic Range
The ENOB is a measure of converter performance as
compared to the theoretical limit based on
quantization noise.
SINAD - 1.76
ENOB =
6.02
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier).
Integral Nonlinearity (INL)
INL is the deviation of the transfer function from a
reference line measured in fractions of 1 LSB using a
best straight line or best fit determined by a least
square curve fit. INL is independent from effects of
offset, gain or quantization errors.
Maximum Conversion Rate
The encode rate at which parametric testing is
performed. This is the maximum sampling rate where
certified operation is given.
14
Two-Tone, Third-Order Intermodulation
Distortion
Two-tone IMD3 is the ratio of power of the
fundamental (at frequencies f1 and f2) to the power of
the worst spectral component of third-order
intermodulation distortion at either frequency 2f1 – f2
or 2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full-scale)
when the power of the fundamental is extrapolated to
the full-scale range of the converter.
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TYPICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 65MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
Amplitude (dBFS)
-20
-30
-40
-50
-60
-70
-80
fIN = 5MHz, -1dBFS
SNR = 61.7dBFS
SINAD = 61.7dBFS
SFDR = 85dBc
16k Point Data, 16 Averages
-10
-20
Amplitude (dBFS)
fIN = 1MHz, -1dBFS
SNR = 61.8dBFS
SINAD = 61.7dBFS
SFDR = 84dBc
16k Point Data, 16 Averages
-10
-30
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
5
10
15
20
25
0
30 32.5
10
15
Figure 1.
Figure 2.
SPECTRAL PERFORMANCE
fIN = 20MHz, -1dBFS
SNR = 61.6dBFS
SINAD = 61.6dBFS
SFDR = 81dBc
16k Point Data, 16 Averages
-30
-40
-20
-50
-60
-70
-80
-30
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
5
10
15
20
25
0
30 32.5
5
10
15
20
Input Frequency (MHz)
Input Frequency (MHz)
Figure 3.
Figure 4.
DIFFERENTIAL NONLINEARITY
25
30 32.5
INTEGRAL NONLINEARITY
0.15
0.15
fIN = 5MHz
fIN = 5MHz
0.10
0.10
0.05
0.05
INL (LSB)
DNL (LSB)
30 32.5
f1 = 9.5MHz
f2 = 10.2MHz
2-Tone IMD = 93dBFS
16 k-Point Data
16 Averages
-10
Amplitude (dBFS)
-20
25
INTERMODULATION DISTORTION
0
-10
20
Input Frequency (MHz)
0
Amplitude (dBFS)
5
Input Frequency (MHz)
0
0
-0.05
-0.05
-0.10
-0.10
-0.15
-0.15
0
256
512
768
1024
0
128
256
384
512
Code
Code
Figure 5.
Figure 6.
640
768
896
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 65MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
IAVDD, IVDRV vs CLOCK FREQUENCY
0.10
SNR vs INPUT FREQUENCY
64
0.09
Signal-to-Noise Ratio (dBFS)
fIN = 5MHz
IAVDD, IDVDD (mA)
0.08
IAVDD
0.07
0.06
0.05
0.04
0.03
IVDRV
0.02
0.01
External Reference
REFT = 1.95V
REFB = 0.95V
63
62
61
60
59
58
57
56
0
20
25
30
35
40
45
50
55
60
65
0
70
10
20
30
Figure 7.
Signal-to-Noise Ratio (dBFS)
Spurious-Free Dynamic Range (dBc)
Internal Reference
85
80
75
70
65
64
62
60
58
56
54
0
10
20
30
40
50
60
0
70
10
20
30
40
50
60
70
Input Frequency (MHz)
Input Frequency (MHz)
Figure 9.
Figure 10.
SFDR vs INPUT FREQUENCY
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE
WITH PLL ENABLED (default)
95
95
fIN = 5MHz
Internal Reference
90
90
SNR (dBFS), SFDR (dBc)
Spurious-Free Dynamic Range (dBc)
70
SNR vs INPUT FREQUENCY
60
85
80
75
70
80
75
70
65
60
60
10
20
30
40
50
60
70
SFDR
85
65
0
16
60
66
External Reference
REFT = 1.95V
REFB = 0.95V
90
50
Figure 8.
SFDR vs INPUT FREQUENCY
95
40
Input Frequency (MHz)
Sample Rate (MHz)
SNR
30
35
40
45
50
55
Input Frequency (MHz)
Duty Cycle (%)
Figure 11.
Figure 12.
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60
65
70
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 65MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
DYNAMIC PERFORMANCE vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
95
405
fIN = 5MHz
fIN = 5MHz
SFDR
Power Dissipation (mW)
SNR (dBFS), SFDR (dBc)
90
85
80
75
70
65
60
390
375
360
345
SNR
55
330
-40
-15
+10
+35
+60
+85
-40
+35
Temperature (°C)
Figure 13.
Figure 14.
SWEPT POWER — SNR
+60
+85
SWEPT POWER — SFDR
70
90
dBFS
80
60
dBFS
70
50
SFDR (dBc, dBFS)
SNR (dBFS, dBc)
+10
-15
Temperature (°C)
dBc
40
30
20
60
50
dBc
40
30
20
10
10
fIN = 10MHz
0
fIN = 10MHz
0
-50
-40
-30
-20
-10
0
-50
-40
-30
-20
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 15.
Figure 16.
-10
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APPLICATION INFORMATION
THEORY OF OPERATION
INPUT CONFIGURATION
The ADS5237 is a dual-channel, simultaneous
sampling analog-to-digital converter (ADC). Its low
power and high sampling rate of 65MSPS are
achieved using a state-of-the-art switched capacitor
pipeline architecture built on an advanced low-voltage
CMOS process. The ADS5237 operates from a +3.3V
supply voltage for both its analog and digital supply
connections. The ADC core of each channel consists
of a combination of multi-bit and single-bit internal
pipeline stages. Each stage feeds its data into the
digital error correction logic, ensuring excellent
differential linearity and no missing codes at the
10-bit level. The conversion process is initiated by the
rising edge of the external clock. Once the signal is
captured by the input sample-and-hold amplifier, the
input sample is sequentially converted within the
pipeline stages. This process results in a data latency
of six clock cycles, after which the output data is
available as a 10-bit parallel word, coded in either
straight offset binary (SOB) or binary two's
complement (BTC) format. Because a common clock
controls the timing of both channels, the analog
signal is sampled simultaneously. Data on the parallel
ports are updated simultaneously as well. Further
processing can be timed using the individual data
valid output signal of each channel. The ADS5237
features internal references that are trimmed to
ensure a high level of accuracy and matching. The
internal references can be disabled to allow for
external reference operation.
The analog input for the ADS5237 consists of a
differential sample-and-hold architecture implemented
using a switched capacitor technique; see Figure 17.
The sampling circuit consists of a low-pass RC filter
at the input to filter out noise components that
potentially could be differentially coupled on the input
pins. The inputs are sampled on two 4pF capacitors.
The RLC model is illustrated in Figure 17.
INPUT DRIVER CONFIGURATIONS
Transformer-Coupled Interface
If the application requires a signal conversion from a
single-ended source to drive the ADS5237
differentially, an RF transformer could be a good
solution. The selected transformer must have a
center tap in order to apply the common-mode dc
voltage (VCM) necessary to bias the converter inputs.
AC grounding the center tap generates the differential
signal swing across the secondary winding. Consider
a step-up transformer to take advantage of signal
amplification without the introduction of another noise
source. Furthermore, the reduced signal swing from
the source may lead to improved distortion
performance. The differential input configuration may
provide a noticeable advantage for achieving good
SFDR performance over a wide range of input
frequencies. In this mode, both inputs (IN and IN) of
the ADS5237 see matched impedances.
Figure 18 illustrates the schematic for the suggested
transformer-coupled interface circuit. The component
values of the RC low-pass filter may be optimized,
depending on the desired roll-off frequency.
18
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IN
OUT
5nH
to 9nH
INP
1.5pF to
2.5pF
15W
to 25W
1W
15W
to 25W
IN
3.2pF
to 4.8pF
60W
to 120W
OUT
IN
OUT
OUT
OUTP
1.5pF
to 1.9pF
IN
OUTN
15W to 35W
15W
to 25W
15W
to 25W
IN
3.2pF
to 4.8pF
OUT
60W
to 120W
IN
OUT
5nH
to 9nH
INN
1.5pF to
2.5pF
Switches that are ON
in SAMPLE phase.
1W
Switches that are ON
in HOLD phase.
IN
OUT
Figure 17. Input Circuitry
RG
VIN
49.9W
0.1mF
1:n
24.9W
IN
OPA690
R1
RT
1/2
ADS5237
22pF
24.9W
IN
R2
CM
+1.5V
0.1mF
One Channel of Two
Figure 18. Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer
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DC-Coupled Input with Differential Amplifier
REFERENCE CIRCUIT
Applications that have a requirement for DC-coupling
a differential amplifier, such as the THS4503, can be
used to drive the ADS5237; this design is shown in
Figure 19. The THS4503 amplifier easily allows a
single-ended to differential conversion, which reduces
component cost.
CF
RS
RG
RF
+5V
VS
AVDD
RT
10mF
0.1mF
RISO
IN
VOCM
THS4503
1m F
1/2
ADS5237
RISO
IN
Internal Reference
All bias currents required for the proper operation of
the ADS5237 are set using an external resistor at ISET
(pin 60), as shown in Figure 20. Using a 56.2kΩ
resistor on ISET generates an internal reference
current of about 20μA. This current is mirrored
internally to generate the bias current for the internal
blocks. While a 5% resistor tolerance is adequate,
deviating from this resistor value alters and degrades
device performance. For example, using a larger
external resistor at ISET reduces the reference bias
current and thereby scales down the device operating
power.
CM
RG
RF
AVDD
CF
ADS5237
INT/EXT
ISET
CM
REFB
0.1mF
REFT
Figure 19. Using the THS4503 with the ADS5237
In addition, the VOCM pin on the THS4503 can be
directly tied to the common-mode pin (CM) of the
ADS5237 to set up the necessary bias voltage for the
converter inputs. In the circuit example shown in
Figure 19, the THS4503 is configured for unity gain. If
required, a higher gain can easily be achieved as well
by adding small capacitors (such as 10pF) in parallel
with the feedback resistors to create a low-pass filter.
Because the THS4503 is driving a capacitive load,
small series resistors in the output ensure stable
operation. Further details of this design and the
overall operation of the THS4503 may be found in its
product data sheet (available for download at
www.ti.com). In general, differential amplifiers provide
a high-performance driver solution for baseband
applications, and other differential amplifier models
may be selected depending on the system
requirements.
Input Over-Voltage Recovery
The differential full-scale input range supported by the
ADS5237 is 2VPP. For a nominal value of VCM
(+1.5V), IN and IN can swing from 1V to 2V. The
ADS5237 is especially designed to handle an
over-voltage differential peak-to-peak voltage of 4V
(2.5V and 0.5V swings on IN and IN). If the input
common-mode voltage is not considerably different
from VCM during overload (less than 300mV),
recovery from an over-voltage input condition is
expected to be within three clock cycles. All of the
amplifiers in the sample-and-hold stage and the ADC
core are especially designed for excellent recovery
from an overload signal.
20
2W
0.1mF
+
2.2mF
56kW
2W
+
2.2mF
0.1mF
Figure 20. Internal Reference Circuit
As part of the internal reference circuit, the ADS5237
provides a common-mode voltage output at pin 52,
CM. This common-mode voltage is typically +1.5V.
While this voltage is similar to the common-mode
voltage used internally within the ADC pipeline core,
the CM pin has an independent buffer amplifier,
which can deliver up to ±2mA of current to an
external circuit for proper input signal level shifting
and biasing. In order to obtain optimum dynamic
performance, the analog inputs should be biased to
the recommended common-mode voltage (1.5V).
While good performance can be maintained over a
certain CM-range, larger deviations may compromise
device performance and could also negatively affect
the overload recovery behavior. Using the internal
reference mode requires the INT/EXT pin to be
forced high, as shown in Figure 20.
The ADS5237 requires solid high-frequency
bypassing on both reference pins, REFT and REFB;
see Figure 20. Use ceramic 0.1μF capacitors (size
0603, or smaller), located as close as possible to the
pins.
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External Reference
The ADS5237 also supports the use of external
reference voltages. External reference voltage mode
involves applying an external top reference at REFT
(pin 53) and a bottom reference at REFB (pin 54).
Setting the ADS5237 for external reference mode
also requires taking the INT/EXT pin low. In this
mode, the internal reference buffer is 3-stated.
Because the switching current for the two ADC
channels
comes
from
the
externally-forced
references, it is possible for the device performance
to be slightly lower than when the internal references
are used. It should be noted that in external reference
mode, VCM and ISET continue to be generated from
the internal bandgap voltage, as they are in the
internal reference mode. Therefore, it is important to
ensure that the common-mode voltage of the
externally-forced reference voltages matches to
within 50mV of VCM (+1.5VDC).
The external reference circuit must be designed to
drive the internal reference impedance seen between
the REFT and REFB pins. To establish the drive
requirements, consider that the external reference
circuit needs to supply an average switching current
of at least 1mA. This dynamic switching current
depends on the actual device sampling rate and the
signal level. The external reference voltages can vary
as long as the value of the external top reference
stays within the range of +1.875V to +2.0V, and the
external bottom reference stays within +1.0V to
+1.125V. Consequently, the full-scale input range can
be set between 1.5VPP and 2VPP (FSR = 2x [REFT –
REFB] ).
CLOCK INPUT
The ADS5237 requires a single-ended clock source.
The clock input, CLK, represents a CMOS-compatible
logic input with an input impedance of about 5pF. For
high input frequency sampling, it is recommended to
use a clock source with very low jitter. A low-jitter
clock is essential in order to preserve the excellent ac
performance of the ADS5237. The converter itself is
specified for a low 1.0ps (rms) jitter. Generally, as the
input frequency increases, clock jitter becomes more
dominant in maintaining a good signal-to-noise ratio
(SNR). This condition is particularly critical in
IF-sampling applications; for example, where the
sampling frequency is lower than the input frequency
(under-sampling). The following equation can be used
to calculate the achievable SNR for a given input
frequency and clock jitter (tJA in psRMS):
1
SNR = 20Log10
(2pfINtJA)
(1)
The ADS5237 enters into a power-down mode if the
sampling clock rate drops below a limit of
approximately 2MSPS. If the sampling rate is
increased above this threshold, the ADS5237
automatically resumes normal operation.
PLL CONTROL
The ADS5237 has an internal PLL that is enabled by
default. The PLL enables a wide range of clock duty
cycles. Good performance is obtained for duty cycles
up to 40%–60%, though the ensured electrical
specifications presume that the duty cycle is between
45%–55%. The PLL automatically limits the minimum
frequency of operation to 20MSPS. For operation
below 20MSPS, the PLL can be disabled by
programming the internal registers through the serial
interface. With the PLL disabled, the clock speed can
go down to 2MSPS. With the PLL disabled, the clock
duty cycle needs to be constrained closer to 50%.
OUTPUT INFORMATION
The ADS5237 provides two channels with 10 data
outputs (D9 to D0, with D9 being the MSB and D0 the
LSB), data-valid outputs (DVA, DVB, pin 26 and pin
22, respectively), and individual out-of-range indicator
output pins (OVRA/OVRB, pin 39 and pin 9,
respectively).
The output circuitry of the ADS5237 has been
designed to minimize the noise produced by
transients of the data switching, and in particular its
coupling to the ADC analog circuitry.
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DATA OUTPUT FORMAT (MSBI)
The ADS5237 makes two data output formats
available: the Straight Offset Binary code (SOB) or
the Binary Two's Complement code (BTC). The
selection of the output coding is controlled by the
MSBI (pin 41). Because the MSBI pin has an internal
pull-down, the ADS5237 operates with the SOB code
as its default setting. Forcing the MSBI pin high
enables BTC coding. The two code structures are
identical, with the exception that the MSB is inverted
for BTC format, as shown in Table 3.
OUTPUT ENABLE (OE)
Digital outputs of the ADS5237 can be set to
high-impedance (3-state), exercising the output
enable pins, OEA (pin 42), and OEB (pin 6). Internal
pull-downs configure the output in enable mode for
normal operation. Applying a logic high voltage
disables the outputs. Note that the OE-function is not
designed to be operated dynamically (that is, as a
fast multiplexer) because it may lead to corrupt
conversion results. Refer to the Electrical
Characteristics table to observe the specified 3-state
enable and disable times.
OVER-RANGE INDICATOR (OVR)
If the analog input voltage exceeds the full-scale
range set by the reference voltages, an over-range
condition exists. The ADS5237 incorporates a
function that monitors the input voltage and detects
any such out-of-range condition. This operation
functions for each of the two channels independently.
The current state can be read at the over-range
indicator pins (pins 9 and 39). This output is low
when the input voltage is within the defined input
range. It changes to high if the applied signal
exceeds the full-scale range. It should be noted that
each of the OVR outputs is updated along with the
data output corresponding to the particular sampled
analog input voltage. Therefore, the OVR state is
subject to the same pipeline delay as the digital data
(six clock cycles).
OUTPUT LOADING
It is recommended that the capacitive loading on the
data output lines be kept as low as possible,
preferably below 15pF. Higher capacitive loading
causes larger dynamic currents as the digital outputs
are changing. Such high current surges can feed
back to the analog portion of the ADS5237 and
adversely affect device performance. If necessary,
external buffers or latches close to the converter
output pins may be used to minimize the capacitive
loading.
SERIAL INTERFACE
The ADS5237 has a serial interface that can be used
to program internal registers. The serial interface is
disabled if SEL is connected to '0'.
When the serial interface is to be enabled, SEL
serves the function of a RESET signal. After the
supplies have stabilized, it is necessary to give the
device a low-going pulse on SEL. This pulse results
in all internal registers resetting to the default value of
'0' (inactive). Without a reset, it is possible that
registers may be in the non-default state on
power-up. This condition may cause the device to
malfunction.
Table 3. Coding Table for Differential Input Configuration and 2VPP Full-Scale Input Range
STRAIGHT OFFSET BINARY (SOB; MSBI = 0)
22
BINARY TWO'S COMPLEMENT (BTC; MSBI = 1)
DIFFERENTIAL INPUT
D9............D0
D9............D0
+FS (IN = +2V, IN = +1V)
1111 1111 11
0111 1111 11
+1/2 FS
1100 0000 00
0100 0000 00
Bipolar Zero (IN = IN = CMV)
1000 0000 00
0000 0000 00
–1/2 FS
0100 0000 00
1100 0000 00
–FS (IN = +1V, IN = +2V)
0000 0000 00
1000 0000 00
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POWER-DOWN MODE
The ADS5237 has a power-down pin, STPD (pin 45).
The internal pull-down is in default mode for the
device during normal operation. Forcing the STPD pin
high causes the device to enter into power-down
mode. In power-down mode, the reference and clock
circuitry as well as all the channels are powered
down. Device power consumption drops to less than
90mW. As previously mentioned, the ADS5237 also
enters into a power-down mode if the clock speed
drops below 2MSPS (see the Clock Input section).
When STPD is pulled high, the internal buffers driving
REFT and REFB are 3-stated and the outputs are
forced to a voltage roughly equal to half of the
voltage on AVDD. Speed of recovery from the
power-down mode depends on the value of the
external capacitance on the REFT and REFB pins. For
capacitances on REFT and REFB less than 1μF, the
reference voltages settle to within 1% of their
steady-state values in less than 500μs. Either of the
two channels can also be selectively powered-down
through the serial interface when it is enabled.
The ADS5237 also has an internal circuit that
monitors the state of stopped clocks. If ADCLK is
stopped for longer than 250ns, or if it runs at a speed
less than 2MHz, this monitoring circuit generates a
logic signal that puts the device in a partial
power-down state. As a result, the power
consumption of the device is reduced when CLK is
stopped. The recovery from such a partial
power-down takes approximately 100μs. This
constraint is described in Table 4.
Table 4. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION
TYP
Recovery from power-down mode (STPD = 1 to STPD = 0).
500μs
Recovery from momentary clock stoppage ( < 250ns).
10μs
Recovery from extended clock stoppage ( > 250ns).
100μs
REMARKS
Capacitors on REFT and REFB less than 1μF.
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LAYOUT AND DECOUPLING
CONSIDERATIONS
Proper grounding and bypassing, short lead length,
and the use of ground planes are particularly
important for high frequency designs. Achieving
optimum performance with a fast sampling converter
such as the ADS5237 requires careful attention to the
PCB layout to minimize the effects of board parasitics
and to optimize component placement. A multilayer
board usually ensures best results and allows
convenient component placement.
The ADS5237 should be treated as an analog
component and the supply pins connected to clean
analog supplies. This layout ensures the most
consistent performance results, because digital
supplies often carry a high level of switching noise
that could couple into the converter and degrade
device performance. As mentioned previously, the
output buffer supply pins (VDRV) should also be
connected to a low-noise supply. Supplies of adjacent
digital circuits may carry substantial current
transients. The supply voltage should be filtered
before connecting to the VDRV pin of the converter.
All ground pins should directly connect to an analog
ground.
Because of its high sampling frequency, the
ADS5237 generates high frequency current transients
and noise (clock feedthrough) that are fed back into
the supply and reference lines. If not sufficiently
bypassed, this feedthrough adds noise to the
conversion process. All AVDD pins may be bypassed
with 0.1μF ceramic chip capacitors (size 0603, or
smaller). A similar approach may be used on the
output buffer supply pins, VDRV. In order to minimize
24
the lead and trace inductance, the capacitors should
be located as close to the supply pins as possible.
Where double-sided component mounting is allowed,
they are best placed directly under the package. In
addition, larger bipolar decoupling capacitors (2.2μF
to 10μF), effective at lower frequencies, may also be
used on the main supply pins. They can be placed on
the PCB in proximity (< 0.5in) to the ADC.
If the analog inputs to the ADS5237 are driven
differentially, it is especially important to optimize
towards a highly symmetrical layout. Small trace
length differences may create phase shifts,
compromising a good distortion performance. For this
reason, the use of two single op amps rather than
one dual amplifier enables a more symmetrical layout
and a better match of parasitic capacitances. The pin
orientation of the ADS5237 quad-flat package follows
a flow-through design, with the analog inputs located
on one side of the package while the digital outputs
are located on the opposite side. This design
provides a good physical isolation between the
analog and digital connections. While designing the
layout, it is important to keep the analog signal traces
separated from any digital lines to prevent noise
coupling onto the analog portion.
Single-ended clock lines must be short and should
not cross any other signal traces.
Short circuit traces on the digital outputs will minimize
capacitive loading. Trace length should be kept short
to the receiving gate (< 2in) with only one CMOS gate
connected to one digital output.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
ADS5237IPAG
ACTIVE
TQFP
PAG
64
160
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS5237IPAG
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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