ADS5296
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SBAS606A – MAY 2013 – REVISED MAY 2013
10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel
Analog-to-Digital Converter
Check for Samples: ADS5296
FEATURES
DESCRIPTION
•
The ADS5296 is a low-power, 12-bit, 8-channel,
analog-to-digital converter (ADC) with sample rates
up to 80 MSPS. However, the device can also be
configured to operate as a 4-channel ADC running at
2x the sample rate by interleaving data from two ADC
channels. In interleaving mode, the device accepts a
double frequency input clock. Each ADC in a pair
converts a common analog input signal at alternate
rising edges of the 2x input clock. The device can
either be configured as a 10-bit, 4-channel ADC with
sample rates up to 200 MSPS or as a 12-bit, 4channel ADC with sample rates up to 160 MSPS.
1
2
•
•
•
•
•
•
•
•
•
•
Configurable Modes of Operation:
– 10-Bit, 200-MSPS, 4-Channel ADC
– 12-Bit, 160-MSPS, 4-Channel ADC
– 10-Bit, 100-MSPS, 8-Channel ADC
– 12-Bit, 80-MSPS, 8-Channel ADC
Designed for Low Power:
– 65 mW per Channel at 80 MSPS
(12-Bit, 8-Channel)
– 150 mW per Channel at 200 MSPS
(10-Bit, 4-Channel)
12-Bit, 80 MSPS:
– SNR: 70.3 dBFS
10-Bit, 200 MSPS:
– SNR: 61.3 dBFS
– Interleaving Spur: > 60 dBc at 90 MHz
Serial LVDS One-Wire Interface:
– 10x Serialization up to 1000 Mbps Data Rate
per Wire
– 12x Serialization up to 960 Mbps Data Rate
per Wire
Digital Processing Block:
– Programmable FIR Decimation Filter and
Oversampling to Minimize Harmonic
Interference
– Programmable IIR High-Pass Filter to
Minimize DC Offset
– Programmable Digital Gain: 0 dB to 12 dB
Low-Frequency Noise Suppression Mode
Programmable Mapping Between ADC Input
Channels and LVDS Output Pins
Channel Averaging Mode
Variety of LVDS Test Patterns to Verify
Data Capture by FPGA or Receiver
Package: 9-mm × 9-mm QFN-64
The data from each ADC within the interleaved pair is
output in serial format over one LVDS pair up to a
maximum data rate of 1 Gbps (10 bits at 100 MSPS).
With interleaving disabled, the ADS5296 can also be
operated as an 8-channel, 10-bit device with sample
rates up to 100 MSPS.
Several digital functions commonly used in systems
are included in the device. These functions include a
low-frequency noise suppression (LFNS) mode,
digital filtering options, and programmable mapping of
LVDS output pins and analog input channels.
For low input frequency applications, the LFNS mode
enables the suppression of noise at low frequencies
and improves SNR in the 1-MHz band near dc by
approximately 3 dB. Digital filtering options include
low-pass, high-pass, and band-pass digital filters as
well as dc offset removal filters.
Low power consumption and integration of multiple
channels in a small package makes the device
attractive for high channel count data acquisition
systems. The device is available in a compact 9-mm
× 9-mm QFN-64 package. The ADS5296 is specified
over the –40°C to +85°C operating temperature
range.
APPLICATIONS
•
•
•
Ultrasound Imaging
Communication Applications
Multichannel Data Acquisition
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ADS5296
SBAS606A – MAY 2013 – REVISED MAY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
SPECIFIED TEMPERATURE RANGE
ADS5296
QFN-64
RGC
–40°C to +85°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
Supply voltage range
Voltage between:
VALUE
UNIT
AVDD
–0.3 to 2.2
V
LVDD
–0.3 to 2.2
V
AGND and LGND
–0.3 to 0.3
V
0 to 2.2
V
AVDD to LVDD (when AVDD leads LVDD)
LVDD to AVDD (when LVDD leads AVDD)
IN_p, IN_n
RESET, SCLK, SDATA, CS, PD, SYNC
Voltage applied to:
CLKP, CLKN
(2)
Digital outputs
Operating free-air, TA
Temperature range
Operating junction, TJ
Storage, Tstg
Electrostatic discharge (ESD) rating
(1)
(2)
Human body model (HBM)
0 to 2.2
V
–0.3 to min (2.2, AVDD + 0.3)
V
–0.3 to 3.6
V
–0.3 to min (2.2, AVDD + 0.3)
V
–0.3 to min (2.2, LVDD + 0.3)
V
–40 to +85
°C
+105
°C
–55 to +150
°C
2000
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKN is less than |0.3 V|.
This setting prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS5296
THERMAL METRIC
(1)
QFN (RGC)
UNITS
64 PINS
θJA
Junction-to-ambient thermal resistance
22.8
θJCtop
Junction-to-case (top) thermal resistance
6.9
θJB
Junction-to-board thermal resistance
2.4
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
2.4
θJCbot
Junction-to-case (bottom) thermal resistance
0.2
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
1.7
1.8
1.9
V
LVDD
Digital supply voltage
1.7
1.8
1.9
V
ANALOG INPUTS
VID
Differential input voltage range
2
VPP
Input common-mode voltage
VCM ± 0.05
V
REFT
External reference mode, top
1.45
V
REFB
External reference mode, bottom
0.45
V
VCM
Common-mode voltage output
0.95
V
CLOCK INPUT
Input Clock Frequency (1 / tC)
Input clock amplitude differential
(VCLKP – VCLKN)
Input clock CMOS single-ended
(VCLKP)
4-channel, 10-bit ADC with interleaving
20
200
MSPS
4-channel, 12-bit ADC with interleaving
20
160
MSPS
8-channel, 10-bit ADC without interleaving
10
100
MSPS
8-channel,12-bit ADC without interleaving
10
80
MSPS
Sine-wave, ac-coupled
0.2
1.5
VPP
LVPECL, ac-coupled
0.2
1.6
VPP
LVDS, ac-coupled
0.2
0.7
VPP
VILwith < 0.1-mA current sink
< 0.3
VIH
> 1.5
Input clock duty cycle
35
50
V
V
65
%
DIGITAL OUTPUTS
ADCLKP and ADCLKN outputs (LVDS)
1x
(sample rate in MSPS)
MHz
LCLKP and LCLKN outputs (LVDS)
6x or 5x
(sample rate in MSPS)
MHz
Output data rate
12x serialization
960
Mbps
10x serialization
1000
Mbps
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ELECTRICAL CHARACTERISTICS: General
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and
LVDD = 1.8 V.
8-CHANNEL, 12-BIT
(Non-Interleaving)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4-CHANNEL, 10-BIT
(Interleaving)
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
12
10
Bits
ANALOG INPUTS
Differential input voltage range
(0-dB gain)
2.0
VPP
kΩ
Differential input resistance
At dc
>1
>1
Differential input capacitance
At dc
2.2
2.2
> 500
> 500
1
1
0.95
0.95
5
5
Analog input bandwidth
Analog input common-mode current
(per input pin)
VCM
2.0
Common-mode output voltage
VCM output current capability
pF
MHz
µA/MSPS
V
mA
DYNAMIC ACCURACY
EO
EGREF
Offset error
Gain error
EGCHAN
Resulting from internal
reference inaccuracy alone
Of channel itself
EGCHAN temperature coefficient
–20
20
–20
20
mV
–1.5
1.5
–1.5
1.5
%FS
0.5
0.5
< 0.01
< 0.01
%FS
Δ%FS/°C
POWER SUPPLY
IAVDD
ILVDD
AVDD
LVDD
Analog supply current
Output buffer supply current
Analog power
Digital power
Total power
80 MSPS, non-interleaving
176
80 MSPS with 100-Ω external
termination
207
148
372
408.6
199
225
mW
mW
597
40
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266.4
516
175
mW
mW
200 MSPS with 100-Ω external
termination
Standby power
mA
mW
200 MSPS with 100-Ω external
termination
80 MSPS with 100-Ω external
termination
125
317
200 MSPS, interleaving
80 MSPS with 100-Ω external
termination
mA
mA
200 MSPS with 100-Ω external
termination
80 MSPS, non-interleaving
227
111
Global power-down
4
mA
200 MSPS, interleaving
190
675
mW
40
mW
mW
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ELECTRICAL CHARACTERISTICS: Dynamic Performance
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, maximum rated input clock frequency, 50% clock duty cycle,
and –1-dBFS differential analog input, unless otherwise noted.
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and
LVDD = 1.8 V.
8-CHANNEL, 12-BIT
(Non-Interleaving)
PARAMETER
TEST CONDITIONS
fIN = 5 MHz
Signal-to-noise ratio (1)
SNR
SINAD
ENOB
Signal-to-noise and distortion
ratio
Effective number of bits
Spurious-free dynamic
range (1)
Total harmonic distortion
Second-harmonic distortion
Third-harmonic distortion
Worst spur
(other than second and third
harmonics) (2)
MIN
TYP
59.9
61.3
MAX
dBFS
UNIT
61
dBFS
68.7
60.3
dBFS
fIN = 5 MHz
70.1
61.3
dBFS
fIN = 30 MHz
69.7
60.8
dBFS
fIN = 90 MHz
67.9
59.8
dBFS
fIN = 5 MHz
11.3
9.8
LSBs
83
dBc
73
83
70.5
fIN = 30 MHz
80
79
dBc
fIN = 90 MHz
76
72.5
dBc
81
dBc
71
81
67.5
fIN = 30 MHz
78
77.5
dBc
fIN = 90 MHz
74
70
dBc
86
dBc
73
90
70.5
fIN = 30 MHz
88
84
dBc
fIN = 90 MHz
85
83
dBc
83
dBc
fIN = 5 MHz
HD3
MAX
70.1
fIN = 5 MHz
HD2
70.3
fIN = 90 MHz
fIN = 5 MHz
THD
TYP
66
fIN = 30 MHz
fIN = 5 MHz
SFDR
MIN
4-CHANNEL, 10-BIT
(Interleaving)
73
83
70.5
fIN = 30 MHz
80
79
dBc
fIN = 90 MHz
76
72.5
dBc
79
dBc
74
dBc
71
dBc
fIN = 5 MHz
75
93
65
fIN = 30 MHz
92
fIN = 90 MHz
90
Two-tone intermodulation
distortion
f1 = 8 MHz, f2 = 10 MHz, each tone at –7 dBFS
83
With a full-scale, 10-MHz
aggressor signal applied and
no input on victim channel
86
95
dBc
Crosstalk
110
110
dBc
Overload recovery
Recovery to < 1% of full-scale after a 6-dB input
overload
1
1
PSRR
AC power-supply rejection
ratio
For a 50-mVPP signal on AVDD supply, up to 10
MHz, no signal applied to analog inputs
> 50
> 50
DNL
Differential nonlinearity
fIN = 5 MHz
INL
Integrated nonlinearity
fIN = 5 MHz
IMD
(1)
(2)
Adjacent channel
Far channel
–0.8
60
dBc
Clock
cycle
dB
±0.3
+0.95
LSBs
±0.2
±1.1
LSBs
In the 4-channel interleaving mode, this parameter does not include interleaving spur. Spur is specified separately as part of the worst
spur parameter.
In the 4-channel interleaving mode, worst spur includes interleaving spur. Also see Figure 44, which shows interleaving spur across
input frequency.
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DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level '0' or '1'. AVDD = 1.8 V and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, CS, SYNC, PDN, INTERLEAVE_MUX)
VIH
High-level input voltage
All pins support 1.8-V and 3.3-V CMOS logic
levels
VIL
Low-level input voltage
All pins support 1.8-V and 3.3-V CMOS logic
levels
(1)
IIH
High-level input current
CS, SDATA, SCLK
IIL
Low-level input current
CS, SDATA, SCLK (1)
1.3
V
0.4
VHIGH = 1.8 V
VLOW = 0 V
V
6
µA
0.1
µA
DIGITAL OUTPUTS (CMOS INTERFACE: SDOUT)
VOH
High-level output voltage
VOL
Low-level output voltage
AVDD – 0.1
V
0.1
V
DIGITAL OUTPUTS (LVDS INTERFACE: OUT1_p, OUT1_n to OUT8_p, OUT8_n, ADCLKp, ADCLKn, LCLKp, LCLKn)
VODH
High-level output differential voltage (2)
340
560
mV
VODL
Low-level output differential voltage (2)
–560
–340
mV
VOCM
Output common-mode voltage
0.93
1.2
mV
(1)
(2)
6
CS, SDATA, and SCLK have an internal 220-kΩ pull-down resistor.
With an external 100-Ω termination.
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TIMING REQUIREMENTS (1)
Typical values are at +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, sine-wave input clock, CLOAD
= 5 pF, and RLOAD = 100 Ω, unless otherwise noted.
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and
LVDD = 1.7 V to 1.9 V, with decimation filters DISABLED.
PARAMETER
tA
TEST CONDITIONS
MIN
Aperture delay
tJ
Aperture delay matching
Between any two channels of the same device
Variation of aperture delay
Between two devices at the same temperature and
AVDD supply
Aperture jitter
Sample uncertainty
Time to valid data after coming out of standby
Wake-up time
TYP
MAX
UNIT
4
ns
±200
ps
±1
ns
300
fs rms
6
µs
100
µs
Interleaving disabled
12
Input clock
cycles
Interleaving enabled
24
Input clock
cycles
Time to valid data after coming out of global powerdown mode
ADC latency (2)
10x SERIALIZATION
tSU
Data setup time
Data valid to LCLKP zero-crossing
0.200
ns
tH
Data hold time
LCLKP zero-crossing to data becoming invalid
0.160
ns
tPDI
Clock propagation delay
Input clock rising edge crossover to output clock
rising edge crossover
tDELAY
Delay time
tPDI = (4 / 5)
× tS + tDELAY
7.8
Variation of tDELAY
Between two devices at the same temperature and
LVDD supply
LVDS bit clock duty cycle
Duty cycle of differential clock
(LCLKP – LCLKN)
ns
11.8
ns
±0.8
ns
50
%
ACROSS ALL SERIALIZATION MODES
tFALL
Data fall time
Rise time measured from –100 mV to +100 mV,
10 MSPS ≤ sampling frequency ≤ 100 MSPS
0.13
ns
tRISE
Data rise time
Rise time measured from –100 mV to +100 mV,
10 MSPS ≤ sampling frequency ≤ 100 MSPS
0.13
ns
tCLKRISE
Output clock rise time
Rise time measured from –100 mV to +100 mV,
10 MSPS ≤ sampling frequency ≤ 100 MSPS
0.13
ns
tCLKFALL
Output clock fall time
Rise time measured from –100 mV to +100 mV,
10 MSPS ≤ sampling frequency ≤ 100 MSPS
0.13
ns
(1)
(2)
Timing parameters are ensured by design and characterization, but are not tested in production.
At higher frequencies, tPDI is greater than one clock period. Overall latency = ADC latency + 1.
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Table 1. 12x Serialization with Decimation Filters Disabled (1) (2)
INPUT CLOCK FREQUENCY
(MHz)
(1)
(2)
(3)
(4)
SETUP TIME (ns) (3)
HOLD TIME (ns) (3)
MIN
tPDI = (9 / 12) × tS + tDELAY
(Where tDELAY is
specified as below, ns)
Noninterleaved
Mode
Interleaved
Mode (4)
OUTPUT DATA
RATE (Mbps)
MIN
10
20
120
3.80
3.80
8
13
20
40
240
1.60
1.80
8
13
40
80
480
0.80
0.69
8
13
65
130
780
0.38
0.19
8
13
80
160
960
0.22
0.14
8
13
TYP
MAX
TYP
MAX
MIN
TYP
MAX
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and LVDD = 1.7
V to 1.9 V.
All timing specifications are taken with default output clock and data delay settings (0 ps). Refer to the Programmable LVDS Output
Clock and Data Edges section in the Application Information for additional output clock and data delay options.
When decimation filters are ENABLED, the minimum setup and minimum hold time will further reduce by 100ps compared to their value
with the filters disabled (at the same output data rate).
Example: At 80 MHz input clock frequency, with decimation by 2 enabled, output data rate = 480 Mbps. At 480 Mbps, as per the above
table, the setup time with the decimation disabled is 0.80 ns. Hence, the set up time with filter enabled will be 100ps lower (0.8 -0.1 =
0.7). Similarly the hold time with filter enabled will be 0.59 ns.
Refer to the INTERLEAVING MODE section in the Application Information for details on Interleaving Mode.
Table 2. 10x Serialization with Decimation Filters Disabled (1) (2)
INPUT CLOCK FREQUENCY
(MHz)
(1)
(2)
(3)
(4)
8
SETUP TIME (ns)
(3)
HOLD TIME (ns)
(3)
tPDI = (8 / 10) × tS + tDELAY
(Where tDELAY is specified as
below, ns)
Noninterleaved
Mode
Interleaved
Mode (4)
OUTPUT DATA
RATE (Mbps)
MIN
40
80
400
0.85
1
7.8
11.8
65
130
650
0.52
0.35
7.8
11.8
80
160
800
0.33
0.19
7.8
11.8
100
200
1000
0.2
0.16
7.8
11.8
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and LVDD = 1.7
V to 1.9 V.
All timing specifications are taken with default output clock and data delay settings (0 ps). Refer to the Programmable LVDS Output
Clock and Data Edges section in the Application Information for additional output clock and data delay options.
When decimation filters are ENABLED, the minimum setup and minimum hold time will further reduce by 100ps compared to their value
with the filters disabled (at the same output data rate).
Example: At 80 MHz input clock frequency, with decimation by 2 enabled, output data rate = 400 Mbps. At 400 Mbps, as per the above
table, the setup time with the decimation disabled is 0.85 ns. Hence, the set up time with filter enabled will be 100ps lower (0.85 -0.10 =
0.75). Similarly the hold time with filter enabled will be 0.90 ns.
Refer to the INTERLEAVING MODE section in the Application Information for details on Interleaving Mode.
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Table 3. 14x Serialization with Decimation by two filter enabled (Data Rate = 0.5x) (1) (2) (3)
SAMPLING FREQUENCY
(MSPS)
OUTPUT
DATA
RATE
(Mbps)
MIN
65
455
0.73
0.75
80
560
0.54
0.50
100
700
0.32
0.25
(1)
(2)
(3)
SETUP TIME (ns)
TYP
HOLD TIME (ns)
MAX
MIN
TYP
MAX
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and LVDD = 1.7
V to 1.9 V.
All timing specifications are taken with default output clock and data delay settings (0 ps).
Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for additional output clock and
data delay options.
Table 4. 14x Serialization with Decimation by four filter enabled (Data Rate = 0.25x) (1) (2) (3)
SAMPLING FREQUENCY
(MSPS)
OUTPUT
DATA
RATE
(Mbps)
MIN
65
227.5
1.7
1.9
80
280
1.3
1.45
100
350
0.9
1.1
(1)
(2)
(3)
SETUP TIME (ns)
TYP
HOLD TIME (ns)
MAX
MIN
TYP
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and LVDD = 1.7
V to 1.9 V.
All timing specifications are taken with default output clock and data delay settings (0 ps).
Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for additional output clock and
data delay options.
Table 5. 14x Serialization with Decimation by eight filter enabled (Data Rate = 0.125x)
SAMPLING FREQUENCY
(MSPS)
OUTPUT
DATA
RATE
(Mbps)
MIN
65
113.75
3.8
80
140
3
3
100
175
2.2
2.2
(1)
(2)
(3)
MAX
SETUP TIME (ns)
TYP
(1) (2) (3)
HOLD TIME (ns)
MAX
MIN
TYP
MAX
3.8
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and LVDD = 1.7
V to 1.9 V.
All timing specifications are taken with default output clock and data delay settings (0 ps).
Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for additional output clock and
data delay options.
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PARAMETRIC MEASUREMENT INFORMATION
Figure 1 shows a timing diagram of the LVDS output voltage levels.
OUTP
Logic 0
(1)
VODL = -350 mV
Logic 1
VODH = +350 mV
(1)
OUTN
VOCM
GND
(1) With an external 100-Ω termination.
Figure 1. LVDS Output Voltage Levels
Figure 2 shows the latency timing diagram.
Sample
N + 11
Sample
N + 12
Sample
N + 13
Sample
N
Input Signal
tA
Input Clock
Frequency = fS
CLKN
CLKP
Latency = 12 Clocks
Bit Clock
Frequency = 6x fS
Output Data
Rate = 12x fS
tPDI
LCLKP
LCLKN
OUTP
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11
D10
D9
D8
Sample N-1
Frame Clock
Frequency = 1x fS
D7
D6
D5
D4
D3
D2
D1
D0
D11 D10
D9
D8
OUTN
Sample N
ADCLKN
ADCLKP
Figure 2. Latency Timing Diagram
10
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PARAMETRIC MEASUREMENT INFORMATION (continued)
LVDS OUTPUT TIMING
Figure 3 shows the output timing described in the Timing Requirements table.
CLKN
Input
Clock
CLKP
tPDI
ADCLKN
Frame
Clock
ADCLKP
tSU
tH
LCLKP
Bit
Clock
LCLKN
tSU
Output
Data
OUT1, OUT2,
OUT3, OUT4,
OUT5, OUT6,
OUT7, OUT8
tH
Dn
tSU
(1)
tH
Dn+1
(1)
(1) n = 0 to 11.
Figure 3. LVDS Output Timing
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PIN DESCRIPTION
RESET
SCLK
SDATA
CS
AVDD
CLKN
CLKP
AVDD
INTERLEAVE_MUX
REFT
REFB
VCM
SDOUT
NC
AVDD
SYNC
RGC PACKAGE
QFN-64
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
IN1_p
1
48
IN8_n
IN1_n
2
47
IN8_p
AGND
3
46
AGND
IN2_p
4
45
IN7_n
IN2_n
5
44
IN7_p
AGND
6
43
AGND
IN3_p
7
42
IN6_n
IN3_n
8
41 IN6_p
Thermal Pad
36
LGND
LGND
14
35
LVDD
OUT1_p 15
34
OUT8_n
16
33
OUT8_p
OUT1_n
12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
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31
32
OUT7_n
13
OUT7_p
PDN
OUT6_n
AGND
OUT6_p
37
OUT5_n
12
OUT5_p
LGND
LCLKN
IN5_p
LCLKP
38
ADCLKN
11
ADCLKP
IN4_n
OUT4_n
IN5_n
OUT4_p
39
OUT3_n
IN4_p 10
OUT3_p
AGND
OUT2_n
40
OUT2_p
9
AGND
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PIN DESCRIPTIONS
NAME
NO.
FUNCTION (1)
ADCLKN
24
DO
Differential LVDS frame clock, negative
ADCLKP
23
DO
Differential LVDS frame clock, positive
AGND
3, 6, 9, 37, 40, 43, 46
G
Analog ground pin
AVDD
50, 57, 60
S
Analog supply pin, 1.8 V
CLKN
59
AI
Differential clock input, negative
CLKP
58
AI
Differential clock input, positive
CS
61
DI
Serial enable chip select; active low digital input
INTERLEAVE_MUX
56
DI
Control input to select conversion of odd channels (1, 3, 5, and 7) or
even channels (2, 4, 6, and 8).
IN1_n
2
AI
Differential analog input for channel 1, negative
IN1_p
1
AI
Differential analog input for channel 1, positive
IN2_n
5
AI
Differential analog input for channel 2, negative
IN2_p
4
AI
Differential analog input for channel 2, positive
IN3_n
8
AI
Differential analog input for channel 3, negative
IN3_p
7
AI
Differential analog input for channel 3, positive
IN4_n
11
AI
Differential analog input for channel 4, negative
IN4_p
10
AI
Differential analog input for channel 4, positive
IN5_n
39
AI
Differential analog input for channel 5, negative
IN5_p
38
AI
Differential analog input for channel 5, positive
IN6_n
42
AI
Differential analog input for channel 6, negative
IN6_p
41
AI
Differential analog input for channel 6, positive
IN7_n
45
AI
Differential analog input for channel 7, negative
IN7_p
44
AI
Differential analog input for channel 7, positive
IN8_n
48
AI
Differential analog input for channel 8, negative
(1)
DESCRIPTION
IN8_p
47
AI
Differential analog input for channel 8, positive
LCLKN
26
DO
LVDS differential bit clock output pins (6x), negative
LCLKP
25
DO
LVDS differential bit clock output pins (6x), positive
LGND
12, 14, 36
G
Digital ground pin
LVDD
35
S
Digital and I/O power supply, 1.8 V
NC
51
—
Do not connect
OUT1_n
16
DO
Channel 1 differential LVDS negative data output
OUT1_p
15
DO
Channel 1 differential LVDS positive data output
OUT2_n
18
DO
Channel 2 differential LVDS negative data output
OUT2_p
17
DO
Channel 2 differential LVDS positive data output
OUT3_n
20
DO
Channel 3 differential LVDS negative data output
OUT3_p
19
DO
Channel 3 differential LVDS positive data output
OUT4_n
22
DO
Channel 4 differential LVDS negative data output
OUT4_p
21
DO
Channel 4 differential LVDS positive data output
OUT5_n
28
DO
Channel 5 differential LVDS negative data output
OUT5_p
27
DO
Channel 5 differential LVDS positive data output
OUT6_n
30
DO
Channel 6 differential LVDS negative data output
OUT6_p
29
DO
Channel 6 differential LVDS positive data output
OUT7_n
32
DO
Channel 7 differential LVDS negative data output
OUT7_p
31
DO
Channel 7 differential LVDS positive data output
OUT8_n
34
DO
Channel 8 differential LVDS negative data output
OUT8_p
33
DO
Channel 8 differential LVDS positive data output
PDN
13
DI
Power-down control input pin
Pin functionality: AI = analog input; DI = digital input; DO = digital output; G = ground; and S = supply.
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PIN DESCRIPTIONS (continued)
NAME
REFB
14
NO.
54
FUNCTION (1)
DESCRIPTION
AI
Negative reference input/output.
Internal reference mode: Reference bottom voltage (0.45 V) is
output on this pin. A decoupling capacitor is not required on this pin.
External reference mode: Reference bottom voltage (0.45 V) must
be externally applied to this pin.
REFT
55
AI
Positive reference input/output.
Internal reference mode: Reference top voltage (1.45 V) is output
on this pin. A decoupling capacitor is not required on this pin.
External reference mode: Reference top voltage (1.45 V) must be
externally applied to this pin.
RESET
64
DI
Active high RESET input
SCLK
63
DI
Serial clock input
SDATA
62
DI
Serial data input
SDOUT
52
DO
Serial data output
SYNC
49
DI
Control input pin to synchronize test patterns and decimation filters
across devices
VCM
53
AI
Common-mode voltage output pin, 0.95 V.
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SBAS606A – MAY 2013 – REVISED MAY 2013
LGND
LVDD
AGND
AVDD
FUNCTIONAL BLOCK DIAGRAMS
IN1_p
IN1_n
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
OUT1_p
OUT1_n
IN2_p
IN2_n
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
OUT2_p
OUT2_n
IN3_p
IN3_n
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
OUT3_p
OUT3_n
IN4_p
IN4_n
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
OUT4_p
OUT4_n
CLKP
CLKN
LCLKP
LCLKN
CLOCKGEN
PLL
ADCLKP
ADCLKN
SYNC
IN5_p
IN5_n
IN6_p
IN6_n
IN7_p
IN7_n
IN8_p
IN8_n
OUT5_p
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
Sampling
Circuit
12 BIT
12-Bit ADC
ADAC
Digital Processing
Block
Serializer
Reference
OUT5_n
OUT6_p
OUT6_n
OUT7_p
OUT7_n
OUT8_p
OUT8_n
Control Interface
CS
SDATA
SCLK
RESET
PDN
VCM
REFB
REFT
Device
Figure 4. 10- and 12-Bit, 8-Channel ADC, Non-Interleaving Mode
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Sampling
Circuit
IN1_p
IN1_n
LGND
LVDD
AGND
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AVDD
SBAS606A – MAY 2013 – REVISED MAY 2013
OUT1_p
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
Serializer
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
Serializer
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
Serializer
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
Serializer
OUT1_n
IN2_p
IN2_n
Sampling
Circuit
Sampling
Circuit
OUT2_p
OUT2_n
OUT3_p
OUT3_n
IN3_p
IN3_n
IN4_p
IN4_n
Sampling
Circuit
OUT4_p
OUT4_n
0
180
LCLKP
CLKP
Divideby-2
CLKN
LCLKN
CLOCKGEN
PLL
ADCLKP
180
0
ADCLKN
SYNC
Sampling
Circuit
IN5_p
IN5_n
OUT5_p
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
Serializer
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
Serializer
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
10 BIT
12-Bit ADC
ADAC
Digital Processing Block
OUT5_n
IN6_p
IN6_n
Sampling
Circuit
Sampling
Circuit
OUT6_p
OUT6_n
OUT7_p
Serializer
OUT7_n
IN7_p
IN7_n
IN8_p
IN8_n
Sampling
Circuit
OUT8_p
Serializer
OUT8_n
Reference
Control Interface
VCM
REFB
REFT
PDN
CS
SDATA
SCLK
RESET
INTERLEAVE_MUX
Device
Figure 5. 10- and 12-Bit, 4-Channel ADC, Interleaving Mode
16
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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and
–1-dBFS differential analog input, unless otherwise noted.
0
0
SNR = 70.4 dBFS
SINAD = 70.2 dBFS
SFDR = 82.8 dBc
THD = 82.5 dBc
−10
−20
−30
−30
−40
−40
−50
−50
Amplitude (dBFS)
Amplitude (dBFS)
−20
−60
−70
−80
−90
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
−130
−130
−140
0
10
20
Frequency (MHz)
30
SNR = 70.3 dBFS
SINAD = 70.1 dBFS
SFDR = 82.1 dBc
THD = 81.7 dBc
−10
−140
40
0
10
20
Frequency (MHz)
30
40
G001
G002
Figure 6. FFT FOR 5-MHz INPUT SIGNAL
(Sample Rate = 80 MSPS)
Figure 7. FFT FOR 15-MHz INPUT SIGNAL
(Sample Rate = 80 MSPS)
0
0
SNR = 69.4 dBFS
SINAD = 68.8 dBFS
SFDR = 77.1 dBc
THD = 76.3 dBc
−10
−20
−30
−30
−40
−40
−50
−50
Amplitude (dBFS)
Amplitude (dBFS)
−20
−60
−70
−80
−90
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
−130
−130
−140
0
10
20
Frequency (MHz)
30
SNR = 70.7 dBFS
SINAD = 70.4 dBFS
SFDR = 82.6 dBc
THD = 82.4 dBc
−10
40
−140
0
5
10
Frequency (MHz)
15
G003
Figure 8. FFT FOR 70-MHz INPUT SIGNAL
(Sample Rate = 80 MSPS)
G004
Figure 9. FFT FOR 5-MHz INPUT SIGNAL
(Sample Rate = 40 MSPS)
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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and
–1-dBFS differential analog input, unless otherwise noted.
0
0
SNR = 70.7 dBFS
SINAD = 70.5 dBFS
SFDR = 83.6 dBc
THD = 83.4 dBc
−10
−20
−30
−30
−40
−40
−50
−50
Amplitude (dBFS)
Amplitude (dBFS)
−20
−60
−70
−80
−90
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
−130
−130
−140
0
5
SNR = 69.7 dBFS
SINAD = 68.7 dBFS
SFDR = 75 dBc
THD = 74.5 dBc
−10
10
Frequency (MHz)
15
−140
20
0
5
10
Frequency (MHz)
15
20
G005
G006
Figure 10. FFT FOR 15-MHz INPUT SIGNAL
(Sample Rate = 40 MSPS)
Figure 11. FFT FOR 70-MHz INPUT SIGNAL
(Sample Rate = 40 MSPS)
71
0
fIN1 = 8 MHz
fIN2 = 10 MHz
Each Tone at −7−dBFS Amplitude
Two−Tone IMD = −90 dBFS
−10
−20
70.5
−30
70
−50
SNR (dBFS)
Amplitude (dBFS)
−40
−60
−70
−80
−90
69.5
69
−100
−110
68.5
−120
−130
−140
0
10
20
Frequency (MHz)
30
40
68
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
G007
Figure 12. FFT WITH TWO-TONE SIGNAL
18
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90
100
G008
Figure 13. SIGNAL-TO-NOISE RATIO vs
INPUT SIGNAL FREQUENCY
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SBAS606A – MAY 2013 – REVISED MAY 2013
TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and
–1-dBFS differential analog input, unless otherwise noted.
86
74
Input Frequency = 10 MHz
Input Frequency = 70 MHz
84
70
SNR (dBFS)
SFDR (dBc)
82
80
78
66
76
62
74
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
90
58
100
0
1
2
3
4
5
6
7
8
Digital Gain (dB)
9
10
11
G009
G010
Figure 14. SPURIOUS-FREE DYNAMIC RANGE vs
INPUT SIGNAL FREQUENCY
Figure 15. SIGNAL-TO-NOISE RATIO vs
DIGITAL GAIN
73
120
90
Input Frequency = 10 MHz
Input Frequency = 70 MHz
SNR
SFDR (dBc)
SFDR (dBFS)
110
Input Frequency = 5 MHz
72.5
72
100
SFDR (dBFS,dBc)
86
SFDR (dBc)
12
82
78
90
71.5
80
71
70
70.5
60
70
50
69.5
40
69
30
68.5
SNR (dBFS)
72
74
20
−50
70
0
1
2
3
4
5
6
7
8
Digital Gain (dB)
9
10
11
−45
12
−40
−35 −30 −25 −20 −15
Input amplitude (dBFS)
−10
−5
0
68
G012
G011
Figure 16. SPURIOUS-FREE DYNAMIC RANGE vs
DIGITAL GAIN
Figure 17. PERFORMANCE vs INPUT AMPLITUDE
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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and
–1-dBFS differential analog input, unless otherwise noted.
Input Frequency = 5 MHz
70.5
80.5
0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
Input Clock Amplitude, differential (VP−P)
2
THD (dBc)
71
70.5
80.5
70
80
69.5
79.5
71.5
81
70
80
72
81.5
SNR (dBFS)
71
81
72.5
82
71.5
81.5
THD
SNR
82.5
72
82
SFDR (dBc)
Input Frequency = 5 MHz
72.5
82.5
79
0.2
73
83
SFDR
SNR
69.5
79.5
69
2.2
79
SNR (dBFS)
73
83
35
40
45
50
55
Input Clock Duty Cycle (%)
60
65
69
G013
G014
Figure 18. PERFORMANCE vs INPUT CLOCK AMPLITUDE
Figure 19. PERFORMANCE vs INPUT CLOCK DUTY CYCLE
72
86
Input Frequency = 5 MHz
72
SFDR
SNR
Input Frequency = 5 MHz
84
71.5
82
71
71.5
AVDD = 1.7 V
AVDD = 1.8 V
AVDD = 1.9 V
78
70
76
69.5
70.5
SNR (dBFS)
70.5
80
SNR (dBFS)
SFDR (dBc)
71
70
69.5
69
68.5
74
0.8
69
1.1
0.85
0.9
0.95
1
1.05
Analog Input Common−Mode Voltage (V)
G015
68
−40 −27.5 −15 −2.5
10 22.5 35 47.5
Temperature (°C)
60
72.5
85
G016
Figure 20. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE
20
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Figure 21. SIGNAL-TO-NOISE RATIO vs
AVDD AND TEMPERATURE
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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and
–1-dBFS differential analog input, unless otherwise noted.
84
120
Input Frequency = 5 MHz
AVDD = 1.7 V
AVDD = 1.8 V
AVDD = 1.9 V
83.5
Adjacent Channel
Near Channel
Far Channel
115
110
105
Crosstalk (dB)
SFDR (dBc)
83
82.5
100
95
90
85
82
80
75
81.5
70
81
−40 −27.5 −15 −2.5
10 22.5 35 47.5
Temperature (°C)
60
72.5
65
85
10
20
30
40
50
60
Frequency of Aggressor Channel (MHz)
70
G017
G018
Figure 22. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD AND TEMPERATURE
Figure 23. CROSSTALK vs FREQUENCY
0.2
(1)
0.4
0.3
0.1
0.1
0
DNL (LSB)
INL (LSB)
0.2
−0.1
0
−0.1
−0.2
−0.2
−0.3
−0.3
0
500
1000
1500 2000 2500
Output Codes (LSB)
3000
3500
4000
−0.4
0
500
1000
1500 2000 2500
Output Codes (LSB)
3000
3500
G020
Figure 24. INTEGRAL NONLINEARITY
(1)
4000
G021
Figure 25. DIFFERENTIAL NONLINEARITY
Adjacent channel: Neighboring channels on the immediate left and right of the channel of interest.
Near channel: Channels on the same side of the package, except the immediate neighbors.
Far channel: Channels on the opposite side of the package.
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TYPICAL CHARACTERISTICS:
Digital Processing (8-Channel, 12-Bit, Non-Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and
–1-dBFS differential analog input, unless otherwise noted.
40
20
Low−Pass
High−Pass
10
Low−Pass
Band−Pass 1
Band−Pass 2
High−Pass
30
20
0
Normalized Amplitude (dB)
Normalized Amplitude (dB)
10
−10
−20
−30
−40
−50
0
−10
−20
−30
−40
−50
−60
−60
−70
−80
−70
0
0.1
0.2
0.3
0.4
Normalized Frequency (fIN fS)
−80
0.5
0
0.1
0.2
0.3
0.4
Normalized Frequency (fIN fS)
0.5
G021
G022
Figure 26. DIGITAL FILTER RESPONSE
(Decimate-by-2)
Figure 27. DIGITAL FILTER RESPONSE
(Decimate-by-4)
0
0
SNR = 75.4 dBFS
SINAD = 75 dBFS
SFDR = 85.7 dBc
THD = 85.5 dBc
Decimate−by−2 Filter Enabled
−10
−20
−20
−30
−40
−40
−50
−50
Amplitude (dBFS)
Amplitude (dBFS)
−30
−60
−70
−80
−90
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
−130
−130
−140
0
5
10
Frequency (MHz)
15
SNR = 74.9 dBFS
SINAD = 74.2 dBFS
SFDR = 84.3 dBc
THD = 81.5 dBc
2 Channels Averaged
−10
20
−140
0
G023
Figure 28. FFT FOR 5-MHz INPUT SIGNAL
(Sample Rate = 80 MSPS, Decimation Filter = 2)
(1)
14x serialization is used to capture data.
22
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(1)
10
20
Frequency (MHz)
30
40
G024
Figure 29. FFT FOR 5-MHz INPUT SIGNAL
(Sample Rate = 80 MSPS by Averaging Two Channels)(1)
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TYPICAL CHARACTERISTICS:
Digital Processing (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and
–1-dBFS differential analog input, unless otherwise noted.
0
0
SNR = 76.7 dBFS
SINAD = 76.6 dBFS
SFDR = 93.9 dBc
THD = 98.6 dBc
Decimate−by−4 Filter
Enabled
−10
−20
−30
−20
−30
−40
−50
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−70
−80
−90
−50
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
−130
−130
−140
0
5
Frequency (MHz)
SNR = 75.8 dBFS
SINAD = 73.8 dBFS
SFDR = 77.5 dBc
THD = 76.9 dBc
4 Channels Averaged
−10
−140
10
0
10
20
Frequency (MHz)
30
40
G025
Figure 30. FFT FOR 5-MHz INPUT SIGNAL
(Sample Rate = 80 MSPS, Decimation Filter = 4)
G026
Figure 31. FFT FOR 5-MHz INPUT SIGNAL
(Sample Rate = 80 MSPS by Averaging Four Channels)(2)
(2)
3
0
0
−10
−3
−20
−6
HPF_DISABLED
HPF_ENABLED (K = 2)
−30
−40
−12
Amplitude (dBFS)
Input Signal Amplitude (dB)
−9
−15
−18
−21
−24
K=2
K=3
K= 4
K=5
K=6
K=7
K=8
K=9
K = 10
−27
−30
−33
−36
−39
−42
−45
0.02
0.1
1
Frequency (MHz)
−50
−60
−70
−80
−90
−100
−110
−120
−130
10 15
−140
0
0.5
1
1.5
2
2.5
3
3.5
Frequency (MHz)
4
4.5
G027
Figure 32. DIGITAL HIGH-PASS FILTER RESPONSE
(2)
5
G032
Figure 33. FFT WITH HPF ENABLED AND DISABLED
(No Signal)
14x serialization is used to capture data.
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TYPICAL CHARACTERISTICS:
Power Consumption (8-Channel, 12-Bit, Non-Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
330
275
One−Wire
One−Wire, Decimate−By−2
One−Wire, Decimate−By−4
300
250
225
Digital Power (mW)
Analog Power (mW)
270
240
210
200
175
180
150
150
125
120
One−Wire
One−Wire, Decimate−By−2
One−Wire, Decimate−By−4
10
20
30
40
50
60
Sampling Frequency (MHz)
70
100
80
10
20
30
40
50
60
Sampling Frequency (MHz)
70
G032
G033
Figure 34. ANALOG SUPPLY POWER
Figure 35. DIGITAL SUPPLY POWER
180
150
One−Wire
One−Wire, Decimate−By−2
One−Wire, Decimate−By−4
One−Wire
One−Wire, Decimate−By−2
One−Wire, Decimate−By−4
130
Digital Current (mA)
Analog Current (mA)
160
140
120
100
80
110
90
70
10
20
30
40
50
60
Sampling Frequency (MHz)
70
80
50
10
20
30
40
50
60
Sampling Frequency (MHz)
70
G034
Figure 36. ANALOG SUPPLY CURRENT
24
80
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80
G035
Figure 37. DIGITAL SUPPLY CURRENT
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TYPICAL CHARACTERISTICS:
Power Consumption (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
65
60
Power/Channel (mW)
55
50
45
40
35
30
10
20
30
40
50
60
Sampling Frequency (MHz)
70
80
G036
Figure 38. TOTAL POWER PER CHANNEL
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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Non-Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
Sampling Frequency, MSPS
80
70
70.4
70.3
69.7
70
69.4
69.1
60
50
70.5
70.3
70.4
70
69.7
69.4
40
69.1
30
70.6
20
10
68
70.5
20
70.4 70.3
30
68.5
70
69.7
69.4
40
50
60
Input Frequency, MHz
69
69.5
69.1
70
70
68.8
68.5 68.2
80
90
70.5
Figure 39. SIGNAL-TO-NOISE RATIO vs INPUT AND SAMPLING FREQUENCIES
26
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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
80
78
80
Sampling Frequency, MSPS
82
70
78
60
80
50
78
76
82
74
40
80
78
30
82
84
20
76
80
10
20
74
74
78
30
76
40
50
60
Input Frequency, MHz
78
80
70
80
82
90
84
Figure 40. SPURIOUS-FREE DYNAMIC RANGE vs INPUT AND SAMPLING FREQUENCIES
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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,
and –1-dBFS differential analog input, unless otherwise noted.
0
0
SNR = 61.5 dBFS
SINAD = 61.5 dBFS
SFDR = 86.6 dBc
THD = 85.4 dBc
−10
−20
−30
−30
−40
−40
−50
−50
Amplitude (dBFS)
Amplitude (dBFS)
−20
−60
−70
−80
−90
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
−130
−130
−140
0
10
20
30
40
50
60
Frequency (MHz)
70
80
90
SNR = 61.4 dBFS
SINAD = 61.3 dBFS
SFDR = 75.6 dBc
THD = 84.9 dBc
−10
−140
100
0
10
20
30
40
50
60
Frequency (MHz)
70
80
90
G037
100
G038
Figure 41. FFT FOR 5-MHz INPUT SIGNAL
Figure 42. FFT FOR 15-MHz INPUT SIGNAL
0
62
SNR = 61.1 dBFS
SINAD = 61.03 dBFS
SFDR = 74.1 dBc
THD = 77.2 dBc
−10
−20
61.75
−30
61.5
−50
61.25
SNR (dBFS)
Amplitude (dBFS)
−40
−60
−70
−80
61
60.75
−90
−100
60.5
−110
−120
60.25
−130
−140
0
10
20
30
40
50
60
Frequency (MHz)
70
80
90
100
60
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
G039
Figure 43. FFT FOR 70-MHz INPUT SIGNAL
28
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90
100
G040
Figure 44. SIGNAL-TO-NOISE RATIO vs
INPUT SIGNAL FREQUENCY
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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,
and –1-dBFS differential analog input, unless otherwise noted.
88
80
Normal Mode
Mux Mode
78
Interleaving Spur (dBc)
85
SFDR (dBc)
82
79
76
73
70
76
74
72
70
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
90
68
100
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
90
100
G041
G042
Figure 45. SPURIOUS-FREE DYNAMIC RANGE vs
INPUT SIGNAL FREQUENCY
Figure 46. INTERLEAVING SPUR (fS / 2 – fIN)
vs INPUT SIGNAL FREQUENCY
63
94
Input Frequency = 10 MHz
Input Frequency = 70 MHz
62
90
SFDR (dBc)
SNR (dBFS)
61
60
59
86
82
58
78
57
Input Frequency = 10 MHz
Input Frequency = 70 MHz
56
0
1
2
3
4
5
6
7
8
Digital Gain (dB)
9
10
11
12
74
0
1
2
3
4
5
6
7
8
Digital Gain (dB)
9
10
11
G043
Figure 47. SIGNAL-TO-NOISE RATIO vs
DIGITAL GAIN
12
G044
Figure 48. SPURIOUS-FREE DYNAMIC RANGE vs
DIGITAL GAIN
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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,
and –1-dBFS differential analog input, unless otherwise noted.
SNR
SFDR (dBc)
SFDR (dBFS)
90
SFDR (dBFS,dBc)
80
77.5
75
Input Frequency = 5 MHz
66
80
64
70
62
60
60
50
58
40
56
30
54
SNR (dBFS)
Normal Mode − Input Frequency = 10 MHz
Normal mode − Input Frequency = 70 MHz
Mux mode − Input Frequency = 10 MHz
Mux mode − Input Frequency = 70 MHz
82.5
Interleaving Spur (dBc)
68
100
85
72.5
70
67.5
20
−50
65
0
1
2
3
4
5
6
7
8
Digital Gain (dB)
9
10
11
−45
12
−40
−35 −30 −25 −20 −15
Input amplitude (dBFS)
−10
−5
0
52
G046
G045
Figure 49. INTERLEAVING SPUR (fS / 2 – fIN)
vs DIGITAL GAIN
Figure 50. PERFORMANCE vs INPUT AMPLITUDE
84
62
Input Frequency = 5 MHz
61.9
AVDD = 1.7 V
AVDD = 1.8 V
AVDD = 1.9 V
Input Frequency = 5 MHz
83
61.8
82
61.7
81
61.6
SFDR (dBc)
SNR (dBFS)
AVDD = 1.7 V
AVDD = 1.8 V
AVDD = 1.9 V
61.5
61.4
80
79
78
61.3
77
61.2
76
61.1
61
−40 −27.5 −15 −2.5
10 22.5 35 47.5
Temperature (°C)
60
72.5
85
75
−40 −27.5 −15 −2.5
10 22.5 35 47.5
Temperature (°C)
60
72.5
G047
Figure 51. SIGNAL-TO-NOISE RATIO vs
AVDD AND TEMPERATURE
30
85
G048
Figure 52. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD AND TEMPERATURE
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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,
and –1-dBFS differential analog input, unless otherwise noted.
82
INTERLEAVING SPUR (dBc)
81
80
Normal Mode − AVDD = 1.7 V
Normal mode − AVDD = 1.8 V
Normal Mode − AVDD = 1.9 V
Mux Mode − AVDD = 1.7V
Mux Mode − AVDD = 1.8V
Mux Mode − AVDD = 1.9V
79
78
77
76
Input Frequency = 5 MHz
75
−40 −27.5 −15 −2.5 10 22.5 35 47.5
Temperature (°C)
60
72.5
85
G049
Figure 53. INTERLEAVING SPUR (fS / 2 – fIN) vs
AVDD AND TEMPERATURE
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TYPICAL CHARACTERISTICS:
Power Consumption (4-Channel, 10-Bit, Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
390
240
360
220
330
Digital Power (mW)
Analog Power (mW)
200
300
270
240
210
180
160
140
180
120
150
120
20
40
60
80
100 120 140 160
Sampling Frequency (MHz)
180
100
200
20
40
60
80
100 120 140 160
Sampling Frequency (MHz)
180
G050
200
G051
Figure 54. ANALOG SUPPLY POWER
Figure 55. DIGITAL SUPPLY POWER
220
125
200
110
Digital Current (mA)
Analog Current (mA)
180
160
140
95
80
120
65
100
80
20
40
60
80
100 120 140 160
Sampling Frequency (MHz)
180
200
50
20
40
60
80
100 120 140 160
Sampling Frequency (MHz)
180
G052
Figure 56. ANALOG SUPPLY CURRENT
32
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200
G053
Figure 57. DIGITAL SUPPLY CURRENT
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TYPICAL CHARACTERISTICS:
Power Consumption (4-Channel, 10-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
150
140
Power/Channel (mW)
130
120
110
100
90
80
70
60
20
40
60
80
100 120 140 160
Sampling Frequency (MHz)
180
200
G054
Figure 58. TOTAL POWER PER CHANNEL
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TYPICAL CHARACTERISTICS: Contour (4-Channel, 10-Bit, Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
200
61
Sampling Frequency, MSPS
61.1
61.4
180
61.3
60.9
61.2
160
61.1
61.4
61.3
61.2
140
120
61.1
61.4
100
10
60.9
20
30
61
61.3
40
50
60
Input Frequency, MHz
61.1
61.2
61.2
70
80
61.3
90
61.4
Figure 59. SIGNAL-TO-NOISE RATIO vs INPUT AND SAMPLING FREQUENCIES
34
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TYPICAL CHARACTERISTICS: Contour (4-Channel, 10-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
200
76
80
Sampling Frequency, MSPS
82
78
74
180
76
80
160
72
78
82
78
78
74
140
76
80
78
120
78
78
76
76
100
10
20
72
74
80
30
74
40
50
60
Input Frequency, MHz
76
78
70
80
80
90
82
Figure 60. SPURIOUS-FREE DYNAMIC RANGE vs INPUT AND SAMPLING FREQUENCIES
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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Interleaving Mode)
70
94
69.5
90
69
86
SFDR (dBc)
SNR (dBFS)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 160 MSPS, 50% clock duty cycle,
and –1-dBFS differential analog input, unless otherwise noted.
68.5
82
68
78
67.5
74
67
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
90
70
100
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
90
100
G058
G059
Figure 61. SIGNAL-TO-NOISE RATIO vs
INPUT SIGNAL FREQUENCY
Figure 62. SPURIOUS-FREE DYNAMIC RANGE vs
INPUT SIGNAL FREQUENCY
82
0.2
80
0.1
78
0
INL (LSB)
Interleaving Spur (dBc)
Normal Mode
Mux Mode
76
−0.1
74
−0.2
72
0
10
20
30
40
50
60
70
80
Input Signal Frequency (MHz)
90
100
−0.3
0
500
1000
1500 2000 2500
Output Codes (LSB)
3000
3500
G060
Figure 63. INTERLEAVING SPUR (fS / 2 – fIN)
vs INPUT SIGNAL FREQUENCY
36
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4000
G061
Figure 64. INTEGRAL NONLINEARITY
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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 160 MSPS, 50% clock duty cycle,
and –1-dBFS differential analog input, unless otherwise noted.
0.4
0.3
0.2
DNL (LSB)
0.1
0
−0.1
−0.2
−0.3
−0.4
0
500
1000
1500 2000 2500
Output Codes (LSB)
3000
3500
4000
G062
Figure 65. DEFERENTIAL NONLINEARITY
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TYPICAL CHARACTERISTICS:
Power Consumption (8-Channel, 12-Bit, Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
220
330
300
200
Digital Power (mW)
Analog Power (mW)
270
240
210
180
160
140
180
120
150
120
20
40
60
80
100
120
Sampling Frequency (MHz)
140
100
160
20
40
60
80
100
120
Sampling Frequency (MHz)
140
G063
G064
Figure 66. ANALOG SUPPLY POWER
Figure 67. DIGITAL SUPPLY POWER
120
180
110
Digital Current (mA)
Analog Current (mA)
160
140
120
100
80
100
90
80
70
20
40
60
80
100
120
Sampling Frequency (MHz)
140
160
60
20
40
60
80
100
120
Sampling Frequency (MHz)
140
G065
Figure 68. ANALOG SUPPLY CURRENT
38
160
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160
G066
Figure 69. DIGITAL SUPPLY CURRENT
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TYPICAL CHARACTERISTICS:
Power Consumption (8-Channel, 12-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
140
130
Power/Channel (mW)
120
110
100
90
80
70
60
20
40
60
80
100
120
Sampling Frequency (MHz)
140
160
G067
Figure 70. TOTAL POWER PER CHANNEL
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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Interleaving Mode)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
Sampling Frequency, MSPS
160
68.8
69
69.1
150
68.4
68.6
68.2
140
68
130
69.1
68.4
68.6
68.8
69
68.2
120
110
69.2
100
10
68
69.1
20
30
68.2
69
68.8
68.6
40
50
60
Input Frequency, MHz
68.4
68.6
68.4
70
68.8
68.2
80
69
90
69.2
Figure 71. SIGNAL-TO-NOISE RATIO vs INPUT AND SAMPLING FREQUENCIES
40
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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Interleaving Mode) (continued)
Typical values are at TA = +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,
unless otherwise noted.
160
79
Sampling Frequency, MSPS
80
78
75
150
74
73
76
78
77
140 79
130
77
78
75
74
75
74
76
120
110
77
100
76
78
10
73
20
74
30
75
40
50
60
Input Frequency, MHz
76
77
70
78
80
79
90
80
Figure 72. SPURIOUS-FREE DYNAMIC RANGE vs INPUT AND SAMPLING FREQUENCIES
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DEVICE CONFIGURATION
SERIAL INTERFACE
The device has a set of internal registers that can be accessed by the serial interface formed by the CS (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins.
Register Initialization
After power-up, the internal registers must be initialized to default values. This initialization can be accomplished
in one of two ways:
1. Either through a hardware reset by applying a low pulse on the RESET pin (of widths greater than 50 ns), as
shown in Figure 74; or
2. By applying a software reset. When using the serial interface, set the RST bit (register 00h, bit D0) high. This
setting initializes the internal registers to default values and then self-resets the RST bit low. In this case, the
RESET pin is kept high (inactive).
Reset Timing
Figure 73 shows a timing diagram for the reset function.
Power Supply
AVDD, LVDD
t1
RESET
t2
t3
SEN
Figure 73. Reset Timing Diagram
Table 6. Timing Characteristics for Figure 73 (1) (2)
PARAMETER
TEST CONDITIONS
t1
Power-on delay
Delay from AVDD and LVDD power-up to active
RESET pulse
t2
Reset pulse width
Pulse width of active RESET signal
t3
Register write delay
Delay from RESET disable to CS active
(1)
(2)
MIN
TYP
MAX
1
50
UNIT
ms
ns
100
ns
Typical values are at TA = +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to
TMAX = +85°C, unless otherwise noted.
A low pulse on the RESET pin is required when initialization is done via a hardware reset.
Serial Interface Write Operation
Serial shifting of bits into the device is enabled when CS is low. Serial data (on the SDATA pin) are latched at
every SCLK rising edge when CS is active (low). Serial data are loaded into the register at every 24th SCLK
rising edge when CS is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored (the
excess bits being the last bits clocked). Data can be loaded in multiples of 24-bit words within a single active CS
pulse. The first eight bits form the register address and the remaining 16 bits are the register data.
42
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CS
tCS_SU
tSCLK_L
Data Latched On
Rising Edge of SCLK
tSCLK
tCS_HO
SCLK
tSCLK_H
tDH
tDSU
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESET
Figure 74. Serial Interface Write Timing Diagram
Table 7. Timing Characteristics for Figure 74 and Figure 76 (1)
PARAMETER
MIN
TYP
UNIT
20
MHz
SCLK frequency (equal to 1 / tSCLK)
tSCLK
SCLK period
50
ns
tSCLK_H
SCLK high time
20
ns
tSCLK_L
SCLK low time
20
ns
tDSU
SDATA setup time
25
ns
tDHO
SDATA hold time
25
ns
tCS_SU
CS fall to SCLK rise
25
ns
tCS_HO
Time between last SCLK rising edge to CS rising edge
25
tOUT_DV (2)
Delay from SCLK falling edge to SDOUT valid
15
(1)
(2)
> dc
MAX
fSCLK
ns
19
23
ns
Typical values are at TA = +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX =
+85°C, unless otherwise noted.
See Figure 76
Serial Interface Read Operation
The device includes a mode where the contents of the internal registers can be read back on the SDOUT pin.
This readback mode may be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC.
By default, the SDOUT pin is in 3-state after a device power-up or reset. When the readout mode is enabled
using the EN_READOUT register bit, SDOUT serially outputs the contents of the selected register. The following
steps describe how to achieve this functionality:
1. Set the EN_READOUT register bit to '1' See Figure 75(a). This setting puts the device in serial readout
mode. This mode prevents any further writes to the internal registers, except for at register 01h. Note that the
EN_READOUT bit is also located in register 01h. The device can exit readout mode by setting the
EN_READOUT bit to '0'. Note that only the contents of register 01h are unable to be read in register readout
mode.
2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.
3. The device serially outputs the contents (D[15:0]) of the selected register on the SDOUT pin See
Figure 75(b).
4. The external controller can latch the contents at the SCLK rising edge.
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To exit serial readout mode, reset the EN_READOUT register bit to '0', which enables writes to all device
registers. At this point, the SDOUT pin is in 3-state. A detailed timing diagram for the serial readout mode is
shown in Figure 76.
Register Address (A[7:0]) = 01h
SDATA
0
0
0
0
0
0
Register Data (D[15:0]) = 0001
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
SCLK
The SDOUT pin becomes active and is forced low.
CS
SDOUT
The SDOUT Pin is in 3-State
a) Enable Serial Readout (READOUT = 1)
Register Address (A[7:0]) = 0Fh
SDATA
Register Data (D[15:0]) = XXXX (don’t care)
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
SCLK
CS
SDOUT
SDOUT outputs the contents of register 0Fh in the same cycle, MSB first.
b) Read contents of register 0Fh. This register is initialized with 0200 (the device was previously put in global power-down).
Figure 75. Serial Readout Functional Diagram
CS
SCLK
tOUT_DV
SDOUT
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Figure 76. Serial Interface Read Timing Diagram
44
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SERIAL INTERFACE REGISTERS MAP
Table 8 lists the ADS5296 registers.
Table 8. Register Map
REGISTER
ADDRESS
(Hex)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RST (1)
01
0
0
0
0
0
0
0
0
0
0
0
EN_HIGH_
ADDRS
0
0
0
EN_
READOUT
07
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN_MUX_R
EG
EN_INTER
LEAVE
PDN_
COMPLETE
PDN_
PARTIAL
0
0
0A
RAMP_PAT_RESET_VAL
0
0
0
0
PDN_PIN_
CFG
0
0
0
0
0
0
0
EN_FRAME
_PAT
0
0
0F
0
14
1C
PRBS_SEED[15:0]
24
TP_HARD_
SYNC
PRBS_
SEED_
FROM_REG
PRBS_SEED[22:16]
0
PRBS_
TP_EN
TP_SOFT_
SYNC
PRBS_
MODE_2
0
0
0
INVERT_CH[8:1]
0
TEST_PATT[2:0]
BITS_CUSTOM2[11:10]
BITS_CUSTOM1[11:10]
26
BITS_CUSTOM1[9:0]
0
0
0
0
0
27
BITS_CUSTOM2[9:0]
0
0
0
0
0
0
0
GLOBAL_E
N_
FILTER
EN_
CHANNEL_
AVG
29
(1)
LFNS_CH[8:1]
ADCLKOUT[11:0]
23
25
PDN_CH[8:1]
0
0
0
0
0
0
0
0
0
0
0
2A
GAIN_CH4[3:0]
GAIN_CH3[3:0]
GAIN_CH2[3:0]
2B
GAIN_CH5[3:0]
GAIN_CH6[3:0]
GAIN_CH7[3:0]
0
0
0
GAIN_CH1[3:0]
GAIN_CH8[3:0]
2C
0
0
0
0
0
AVG_OUT4[1:0]
0
AVG_OUT3[1:0]
0
AVG_OUT2[1:0]
0
AVG_OUT1[1:0]
2D
0
0
0
0
0
AVG_OUT8[1:0]
0
AVG_OUT7[1:0]
0
AVG_OUT6[1:0]
0
AVG_OUT5[1:0]
Shaded cells indicate used bits.
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Table 8. Register Map (continued)
REGISTER
ADDRESS
(Hex)
46
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
2E
0
HPF_EN_
CH1
HPF_CORNER_CH1[3:0]
FILTER_TYPE_CH1[2:0]
DEC_RATE_CH1
0
SEL_ODD_
TAP_CH1
0
USE_
FILTER_
CH1
2F
0
HPF_EN_
CH2
HPF_CORNER_CH2[3:0]
FILTER_TYPE_CH2[2:0]
DEC_RATE_CH2
0
SEL_ODD_
TAP_CH2
0
USE_
FILTER_
CH2
30
0
HPF_EN_
CH3
HPF_CORNER_CH3[3:0]
FILTER_TYPE_CH3[2:0]
DEC_RATE_CH3
0
SEL_ODD_
TAP_CH3
0
USE_
FILTER_
CH3
31
0
HPF_EN_
CH4
HPF_CORNER_CH4[3:0]
FILTER_TYPE_CH4[2:0]
DEC_RATE_CH4
0
SEL_ODD_
TAP_CH4
0
USE_
FILTER_
CH4
32
0
HPF_EN_
CH5
HPF_CORNER_CH5[3:0]
FILTER_TYPE_CH5[2:0]
DEC_RATE_CH5
0
SEL_ODD_
TAP_CH5
0
USE_
FILTER_
CH5
33
0
HPF_EN_
CH6
HPF_CORNER_CH6[3:0]
FILTER_TYPE_CH6[2:0]
DEC_RATE_CH6
0
SEL_ODD_
TAP_CH6
0
USE_
FILTER_
CH6
34
0
HPF_EN_
CH7
HPF_CORNER_CH7[3:0]
FILTER_TYPE_CH7[2:0]
DEC_RATE_CH7
0
SEL_ODD_
TAP_CH7
0
USE_
FILTER_
CH7
35
0
HPF_EN_
CH8
HPF_CORNER_CH8[3:0]
FILTER_TYPE_CH8[2:0]
DEC_RATE_CH8
0
SEL_ODD_
TAP_CH8
0
USE_
FILTER_
CH8
38
0
0
0
0
DATA_RATE[1:0]
40
ENABLE 40
42
EN_PHASE
DDR
0
0
0
45
0
46
ENABLE 46
50
51
0
0
0
0
0
0
0
0
0
0
ODD_EVEN_SEL
0
0
0
PHASE_
DDR1
PHASE_
DDR0
0
0
0
0
0
0
0
0
0
0
0
EN_SDR
EN_MSB_
FIRST
BTC_MODE
0
0
0
0
0
0
0
0
0
0
0
0
0
FALL_SDR
0
ENABLE 50
0
0
0
ENABLE 51
0
0
0
0
0
0
0
52
ENABLE 52
0
0
0
0
0
0
0
53
ENABLE 53
0
0
0
0
0
0
0
54
ENABLE 54
0
0
0
55
ENABLE 55
0
0
0
EN_BIT_SER
MAP_Ch1234_to_OUT2
0
0
MAP_Ch1234_to_OUT3
0
0
0
MAP_Ch5678_to_OUT5
0
0
0
PAT_DESKEW_SYNC[1:0]
0
0
MAP_Ch1234_to_OUT1
0
0
0
0
0
MAP_Ch1234_to_OUT4
0
MAP_Ch5678_to_OUT7
0
0
0
0
0
MAP_Ch5678_to_OUT6
0
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MAP_Ch5678_to_OUT8
0
0
0
0
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Table 8. Register Map (continued)
REGISTER
ADDRESS
(Hex)
D15
D14
D13
D12
5A to 65
EN_
CUSTOM_
FILT_CH1
0
0
0
COEFFn_SET_CH1 (2)
66 to 71
EN_
CUSTOM_
FILT_CH2
0
0
0
COEFFn_SET_CH2 (2)
72 to 7D
EN_
CUSTOM_
FILT_CH3
0
0
0
COEFFn_SET_CH3 (2)
7E to 89
EN_
CUSTOM_
FILT_CH4
0
0
0
COEFFn_SET_CH4 (2)
8A to 95
EN_
CUSTOM_
FILT_CH5
0
0
0
COEFFn_SET_CH5 (2)
96 to A1
EN_
CUSTOM_
FILT_CH6
0
0
0
COEFFn_SET_CH6 (2)
A2 to AD
EN_
CUSTOM_
FILT_CH7
0
0
0
COEFFn_SET_CH7 (2)
AE to B9
EN_
CUSTOM_
FILT_CH8
0
0
0
COEFFn_SET_CH8 (2)
BE
EN_LVDS
_PROG
0
0
0
0
0
DELAY_DATA_R
F0
EN_EXT_
REF
0
0
0
0
0
0
(2)
D11
D10
D9
D8
0
D7
D6
D5
DELAY_LCLK_R
0
0
D4
D3
D2
DELAY_DATA_F
0
0
0
D1
D0
DELAY_LCLK_F
0
0
0
n = 0 to 11.
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DESCRIPTION OF SERIAL INTERFACE REGISTERS
Table 9. Register 00h
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
RST
All bits default to '0' after reset.
Bits D[15:1]
Must write '0'
Bit D0
RST
0 = Normal operation (default)
1 = Self-clearing software RESET; after reset, this bit is set to '0'
Table 10. Register 01h
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
EN_HIGH_
ADDRS
0
0
0
EN_READOUT
0
0
All bits default to '0' after reset.
Bits D[15:5]
Must write '0'
Bit D4
EN_HIGH_ADDRS
0 = Access to register F0h disabled (default)
1 = Access to register F0h enabled
Bits D[3:1]
Must write '0'
Bit D0
EN_READOUT
0 = Normal operation (default)
1 = READOUT of registers mode using the SDOUT pin enabled
48
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Table 11. Register 07h
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
EN_MUX_REG
EN_
INTERLEAVE
0
0
0
0
0
0
All bits default to '0' after reset.
Bits D[15:2]
Must write '0'
Bit D1
EN_MUX_REG
Enables mux mode interleaving using register bit.
0 = Enables mux mode interleaving using the ODD_EVEN_SEL register bits (default)
1 = Enables mux mode interleaving using the INTERLEAVE_MUX pin.
For more details on this bit, see the Interleaving Mode section.
Bit D0
EN_INTERLEAVE
Enables interleaving of adjacent channel pairs.
0 = Interleaving disabled (default)
1 = Interleaving enabled
For more details on this bit, see the Interleaving Mode section.
Table 12. Register 0Ah
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
RAMP_PAT_RESET_VAL
D7
D6
D5
D4
D3
RAMP_PAT_RESET_VAL
All bits default to '0' after reset.
Bits D[15:0]
RAMP_PAT_RESET_VAL
The starting value of the digital ramp test pattern can be programmed using these register
bits. By default, the starting value is 0000h after reset.
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Table 13. Register 0Fh
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
PDN_PIN_CFG
PDN_
COMPLETE
PDN_PARTIAL
D7
D6
D5
D4
D3
D2
D1
D0
PDN_CH[8:1]
All bits default to '0' after reset.
Bits D[15:11]
Must write '0'
Bit D10
PDN_PIN_CFG
0 = PD pin configured for complete power-down mode
1 = PD pin configured for partial power-down mode
Bit D9
PDN_COMPLETE
0 = Normal operation
1 = Register mode for complete power-down; slow recovery from power-down
Bit D8
PDN_PARTIAL
0 = Normal operation
1 = Partial power-down mode; fast recovery from power-down
Bits D[7:0]
PDN_CH[8:1]
0 = Normal operation
1 = Individual channel ADC power-down mode
Table 14. Register 14h
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
LFNS_CH[8:1]
All bits default to '0' after reset.
Bits D[15:8]
Must write '0'
Bits D[7:0]
LFNS_CH[8:1]
0 = Low-frequency noise suppression (LFNS) mode disabled (default)
1 = LFNS mode enabled for individual channels
50
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Table 15. Register 1Ch
D15
D14
D13
D12
0
EN_FRAME_
PAT
0
0
D7
D6
D5
D4
D11
D10
D9
D8
ADCLKOUT[11:0]
D3
D2
D1
D0
ADCLKOUT[11:0]
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
EN_FRAME_PAT
0 = Normal operation on frame clock (default)
1 = Enables output frame clock to be programmed through a pattern specified by the
ADCCLKOUT register bits
Bits D[13:12]
Must write '0'
Bits D[11:0]
ADCLKOUT[11:0]
These bits create the 12-bit pattern for the frame clock on the ADCLKP, ADCLKN pins.
Table 16. Register 23h
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
PRBS_SEED[15:0]
D7
D6
D5
D4
D3
PRBS_SEED[15:0]
All bits default to '0' after reset.
Bits D[15:0]
PRBS_SEED[15:0]
These bits are the lower 16 bits of the PRBS pattern starting seed value.
The starting seed value of the PRBS test pattern can be specified using these register bits.
Table 17. Register 24h
D15
D14
D13
D12
D11
D10
D9
PRBS_SEED[22:16]
D7
D6
D5
D4
D8
0
D3
D2
D1
D0
INVERT_CH[8:1]
All bits default to '0' after reset.
Bits D[15:9]
PRBS_SEED[22:16]
These bits are the seven upper bits of the PRBS seed starting value.
Bit D8
Must write '0'
Bits D[7:0]
INVERT_CH[8:1]
0 = Normal configuration
Normally, the IN_p pin represents the positive analog input pin and IN_n represents the
complementary negative input.
1 = The polarity of the analog input pins is electrically swapped
Setting the INVERT_CH[8:1] bits causes the inputs to be swapped. IN_n now represents the
positive input and IN_p represents the negative input.
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Table 18. Register 25h
D15
D14
D13
TP_HARD_
SYNC
PRBS_SEED_
FROM_REG
PRBS_
MODE_2
PRBS_TP_EN
D7
D6
D5
D4
0
D12
TEST_PATT[2:0]
D11
D10
0
0
D3
D2
BITS_CUSTOM2[11:10]
D9
D8
0
TP_SOFT_
SYNC
D1
D0
BITS_CUSTOM1[11:10]
All bits default to '0' after reset.
Bit D15
TP_HARD_SYNC
0 = Inactive
1 = The external SYNC feature is enabled for syncing test patterns
Bit D14
PRBS_SEED_FROM_REG
0 = Disabled
1 = The PRBS seed can be chosen from registers 23h and 24h
Bit D13
PRBS_MODE_2
The PRBS 9-bit LFSR (23-bit LFSR) is the default mode.
Bit D12
PRBS_TP_EN
0 = PRBS test pattern disabled
1 = PRBS test pattern enabled
Bits D[11:9]
Must write '0'
Bit D8
TP_SOFT_SYNC
0 = No sync
1 = Software sync bit for the test patterns on all eight channels
Bit D7
Must write '0'
Bit D6
TEST_PATT2
0 = Normal operation
1 = A repeating full-scale ramp pattern is enabled on the outputs; ensure that bits D4 and
D5 are '0'
Bit D5
TEST_PATT1
0 = Normal operation
1 = Enables a mode where the output toggles between two defined codes; ensure that bits
D4 and D6 are '0'
Bit D4
TEST_PATT0
0 = Normal operation
1 = Enables a mode where the output is a constant specified code; ensure that bits D5 and
D6 are '0'
Bits D[3:2]
BITS_CUSTOM2[11:10]
These bits are the two MSBs for the second code of the dual custom patterns.
Bits D[1:0]
BITS_CUSTOM1[11:10]
These bits are the two MSBs for the single custom pattern (and for the first code of the dual
custom patterns).
52
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Table 19. Register 26h
D15
D14
D13
D12
D11
D10
D9
D8
BITS_CUSTOM1[9:0]
D7
D6
BITS_CUSTOM1[9:0]
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
All bits default to '0' after reset.
Bits D[15:6]
BITS_CUSTOM1[9:0]
These bits are the 10 lower bits for the single custom pattern (and for the first code of the
dual custom pattern).
Bits D[5:0]
Must write '0'
Table 20. Register 27h
D15
D14
D13
D12
D11
D10
D9
D8
BITS_CUSTOM2[9:0]
D7
D6
BITS_CUSTOM2[9:0]
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
All bits default to '0' after reset.
Bits D[15:6]
BITS_CUSTOM2[9:0]
These bits are the 10 lower bits for the second code of the dual custom pattern.
Bits D[5:0]
Must write '0'
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Table 21. Register 29h
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
GLOBAL_EN
FILTER
EN_CHANNEL
_AVG
0
0
0
0
0
All bits default to '0' after reset.
Bits D[15:2]
Must write '0'
Bit D1
GLOBAL_EN_FILTER
0 = Global control digital filter disabled(default)
1 = Global control digital filter enabled
Bit D0
EN_CHANNEL_AVG
0 = Channel averaging disabled (default)
1 = Channel averaging enabled and specified by the AVG_OUTn register bits
Table 22. Register 2Ah
D15
D14
D13
D12
D11
GAIN_CH4[3:0]
D7
D6
D5
D10
D9
D8
GAIN_CH3[3:0]
D4
D3
GAIN_CH2[3:0]
D2
D1
D0
GAIN_CH1[3:0]
All bits default to '0' after reset.
Bits D[15:12]
GAIN_CH4[3:0]
These bits set the programmable gain for channel 4.
Bits D[11:8]
GAIN_CH3[3:0]
These bits set the programmable gain for channel 3.
Bits D[7:4]
GAIN_CH2[3:0]
These bits set the programmable gain for channel 2.
Bits D[3:0]
GAIN_CH1[3:0]
These bits set the programmable gain for channel 1.
Table 23. Register 2Bh
D15
D14
D13
D12
D11
GAIN_CH5[3:0]
D7
D6
D5
D10
D9
D8
GAIN_CH6[3:0]
D4
D3
GAIN_CH7[3:0]
D2
D1
D0
GAIN_CH8[3:0]
All bits default to '0' after reset.
Bits D[15:12]
GAIN_CH5[3:0]
These bits set the programmable gain for channel 4.
Bits D[11:8]
GAIN_CH6[3:0]
These bits set the programmable gain for channel 5.
Bits D[7:4]
54
GAIN_CH7[3:0]
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These bits set the programmable gain for channel 6.
Bits D[3:0]
GAIN_CH8[3:0]
These bits set the programmable gain for channel 7.
Table 24. Register 2Ch
D15
D14
D13
D12
D11
0
0
0
0
0
D6
D5
D4
D7
AVG_OUT3[1:0]
0
D3
AVG_OUT2[1:0]
D10
D9
D8
AVG_OUT4[1:0]
D2
0
D1
0
D0
AVG_OUT1[1:0]
All bits default to '0' after reset.
Bits D[15:11]
Must write '0'
Bits D[10:9]
AVG_OUT4[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT4.
Bit D8
Must write '0'
Bits D[7:6]
AVG_OUT3[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT3.
Bit D5
Must write '0'
Bits D[4:3]
AVG_OUT2[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT2.
Bit D2
Must write '0'
Bits D[1:0]
AVG_OUT1[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT1.
Table 25. Register 2Dh
D15
D14
D13
D12
D11
0
0
0
0
0
D6
D5
D4
D7
AVG_OUT7[1:0]
0
D3
AVG_OUT6[1:0]
D10
D9
D8
AVG_OUT8[1:0]
D2
0
0
D1
D0
AVG_OUT5[1:0]
All bits default to '0' after reset.
Bits D[15:11]
Must write '0'
Bits D[10:9]
AVG_OUT8[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT8.
Bit D8
Must write '0'
Bits D[7:6]
AVG_OUT7[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT7.
Bit D5
Must write '0'
Bits D[4:3]
AVG_OUT6[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT6.
Bit D2
Must write '0'
Bits D[1:0]
AVG_OUT5[1:0]
These bits set the averaging control for data transmitted on the LVDS output OUT5.
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Table 26. Register 2Eh
D15
D14
0
HPF_EN_CH1
D7
D6
FILTER_TYPE
_CH1[2:0]
D13
D12
D11
D10
HPF_CORNER _CH1[3:0]
D5
D4
DEC_RATE_CH1[2:0]
D9
D8
FILTER_TYPE_CH1[2:0]
D3
D2
0
SEL_ODD_
TAP_CH1
D1
D0
0
USE_FILTER_
CH1
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH1
This bit enables the HPF filter for channel 1.
Bits D[13:10]
HPF_CORNER _CH1[3:0]
These bits program the HPF corner for channel 1.
Bits D[9:7]
FILTER_TYPE_CH1[2:0]
These bits select the type of filter on channel 1.
Bits D[6:4]
DEC_RATE_CH1[2:0]
These bits set the decimation factor for the filter on channel 1.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH1
This bit enables the odd tap filter for channel 1.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH1
This bit enables the filter for channel 1.
56
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Table 27. Register 2Fh
D15
D14
0
HPF_EN_CH2
D7
D6
FILTER_TYPE
_CH2[2:0]
D13
D12
D11
D10
D9
HPF_CORNER _CH2[3:0]
D5
D4
DEC_RATE_CH2[2:0]
D8
FILTER_TYPE_CH2[2:0]
D3
D2
0
SEL_ODD_
TAP_CH2
D1
D0
0
USE_FILTER_
CH2
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH2
This bit enables the HPF filter for channel 2.
Bits D[13:10]
HPF_CORNER _CH2[3:0]
These bits program the HPF corner for channel 2.
Bits D[9:7]
FILTER_TYPE_CH2[2:0]
These bits select the type of filter on channel 2.
Bits D[6:4]
DEC_RATE_CH2[2:0]
These bits set the decimation factor for the filter on channel 2.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH2
This bit enables the odd tap filter for channel 2.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH2
This bit enables the filter for channel 2.
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Table 28. Register 30h
D15
D14
0
HPF_EN_CH3
D7
D6
FILTER_TYPE
_CH3[2:0]
D13
D12
D11
D10
HPF_CORNER _CH3[3:0]
D5
D4
DEC_RATE_CH3[2:0]
D9
D8
FILTER_TYPE_CH3[2:0]
D3
D2
0
SEL_ODD_
TAP_CH3
D1
D0
0
USE_FILTER_
CH3
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH3
This bit enables the HPF filter for channel 3.
Bits D[13:10]
HPF_CORNER _CH3[3:0]
These bits program the HPF corner for channel 3.
Bits D[9:7]
FILTER_TYPE_CH3[2:0]
These bits select the type of filter on channel 3.
Bits D[6:4]
DEC_RATE_CH3[2:0]
These bits set the decimation factor for the filter on channel 3.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH3
This bit enables the odd tap filter for channel 3.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH3
This bit enables the filter for channel 3.
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Table 29. Register 31h
D15
D14
0
HPF_EN_CH4
D7
D6
FILTER_TYPE
_CH4[2:0]
D13
D12
D11
D10
D9
HPF_CORNER _CH4[3:0]
D5
D4
DEC_RATE_CH4[2:0]
D8
FILTER_TYPE_CH4[2:0]
D3
D2
0
SEL_ODD_
TAP_CH4
D1
D0
0
USE_FILTER_
CH4
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH4
This bit enables the HPF filter for channel 4.
Bits D[13:10]
HPF_CORNER _CH4[3:0]
These bits program the HPF corner for channel 4.
Bits D[9:7]
FILTER_TYPE_CH4[2:0]
These bits select the type of filter on channel 4.
Bits D[6:4]
DEC_RATE_CH4[2:0]
These bits set the decimation factor for the filter on channel 4.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH4
This bit enables the odd tap filter for channel 4.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH4
This bit enables the filter for channel 4.
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Table 30. Register 32h
D15
D14
0
HPF_EN_CH5
D7
D6
FILTER_TYPE
_CH5[2:0]
D13
D12
D11
D10
HPF_CORNER _CH5[3:0]
D5
D4
DEC_RATE_CH5[2:0]
D9
D8
FILTER_TYPE_CH5[2:0]
D3
D2
0
SEL_ODD_
TAP_CH5
D1
D0
0
USE_FILTER_
CH5
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH5
This bit enables the HPF filter for channel 5.
Bits D[13:10]
HPF_CORNER _CH5[3:0]
These bits program the HPF corner for channel 5.
Bits D[9:7]
FILTER_TYPE_CH5[2:0]
These bits select the type of filter on channel 5.
Bits D[6:4]
DEC_RATE_CH5[2:0]
These bits set the decimation factor for the filter on channel 5.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH5
This bit enables the odd tap filter for channel 5.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH5
This bit enables the filter for channel 5.
60
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Table 31. Register 33h
D15
D14
0
HPF_EN_CH6
D7
D6
FILTER_TYPE
_CH6[2:0]
D13
D12
D11
D10
D9
HPF_CORNER _CH6[3:0]
D5
D4
DEC_RATE_CH6[2:0]
D8
FILTER_TYPE_CH6[2:0]
D3
D2
0
SEL_ODD_
TAP_CH6
D1
D0
0
USE_FILTER_
CH6
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH6
This bit enables the HPF filter for channel 6.
Bits D[13:10]
HPF_CORNER _CH6[3:0]
These bits program the HPF corner for channel 6.
Bits D[9:7]
FILTER_TYPE_CH6[2:0]
These bits select the type of filter on channel 6.
Bits D[6:4]
DEC_RATE_CH6[2:0]
These bits set the decimation factor for the filter on channel 6.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH6
This bit enables the odd tap filter for channel 6.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH6
This bit enables the filter for channel 6.
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Table 32. Register 34h
D15
D14
0
HPF_EN_CH7
D7
D6
FILTER_TYPE
_CH7[2:0]
D13
D12
D11
D10
HPF_CORNER _CH7[3:0]
D5
D4
DEC_RATE_CH7[2:0]
D9
D8
FILTER_TYPE_CH7[2:0]
D3
D2
0
SEL_ODD_
TAP_CH7
D1
D0
0
USE_FILTER_
CH7
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH7
This bit enables the HPF filter for channel 7.
Bits D[13:10]
HPF_CORNER _CH7[3:0]
These bits program the HPF corner for channel 7.
Bits D[9:7]
FILTER_TYPE_CH7[2:0]
These bits select the type of filter on channel 7.
Bits D[6:4]
DEC_RATE_CH7[2:0]
These bits set the decimation factor for the filter on channel 7.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH7
This bit enables the odd tap filter for channel 7.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH7
This bit enables the filter for channel 7.
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Table 33. Register 35h
D15
D14
0
HPF_EN_CH8
D7
D6
FILTER_TYPE
_CH8[2:0]
D13
D12
D11
D10
D9
HPF_CORNER _CH8[3:0]
D5
D4
DEC_RATE_CH8[2:0]
D8
FILTER_TYPE_CH8[2:0]
D3
D2
0
SEL_ODD_
TAP_CH8
D1
D0
0
USE_FILTER_
CH8
All bits default to '0' after reset.
Bit D15
Must write '0'
Bit D14
HPF_EN_CH8
This bit enables the HPF filter for channel 8.
Bits D[13:10]
HPF_CORNER _CH8[3:0]
These bits program the HPF corner for channel 8.
Bits D[9:7]
FILTER_TYPE_CH8[2:0]
These bits select the type of filter on channel 8.
Bits D[6:4]
DEC_RATE_CH8[2:0]
These bits set the decimation factor for the filter on channel 8.
Bit D3
Must write '0'
Bit D2
SEL_ODD_TAP_CH8
This bit enables the odd tap filter for channel 8.
Bit D1
Must write '0'
Bit D0
USE_FILTER_CH8
This bit enables the filter for channel 8.
Table 34. Register 38h
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
DATA_RATE[1:0]
All bits default to '0' after reset.
Bits D[15:2]
Must write '0'
Bits D[1:0]
DATA_RATE[1:0]
Bits D1 and D0 select the output data rate depending on the type of filter.
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Table 35. Register 40h
D15
D14
D13
D12
D11
D10
D9
D8
ENABLE 40
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
ODD_EVEN_SEL
All bits default to '0' after reset.
Bits D15
Enable 40
0 = Disable bits D[7:0] of register 40h
1 = Enable bits D[7:0] of register 40h
Bits D[14:8]
Must write '0'
Bits D[:0]
ODD_EVEN_SEL[7:0]
8000 = Input pins IN1, IN3, IN5, and IN7 are interleaved
80FF = Input pins IN2, IN4, IN6, and IN8 are interleaved
For more details on this bit, see the Interleaving Mode section.
Table 36. Register 42h
D15
D14
D13
D12
D11
D10
D9
D8
EN_PHASE_
DDR
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
PHASE_DDR1
PHASE_DDR0
0
0
0
0
0
All bits default to '0' after reset.
Bit D15
EN_PHASE_DDR
This bit enables LCLK phase programmability.
0 = Disable bits D[6:5] of register 42h
1 = Enable bits D[6:5] of register 42h
Bits D[14:7]
Must write '0'
Bits D[6:5]
PHASE_DDR[1:0]
These bits control the LCLK output phase relative to data.
Refer to the Programmable LCLK Phase section.
Bits D[4:0]
Must write '0'
Table 37. Register 45h
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
PAT_DESKEW_SYNC[1:0]
All bits default to '0' after reset.
Bits D[15:2]
Must write '0'
Bit D1
PAT_DESKEW_SYNC1
0 = Inactive
1 = Sync pattern mode enabled; ensure that D0 is '0'
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Bit D0
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PAT_DESKEW_SYNC0
0 = Inactive
1 = Deskew pattern mode enabled; ensure that D1 is '0'
Table 38. Register 46h
D15
D14
D13
D12
ENABLE 46
0
FALL_SDR
0
D7
D6
D5
D4
D3
EN_SDR
EN_MSB_
FIRST
0
0
0
D11
D10
D9
D8
D2
D1
D0
BTC_MODE
0
0
EN_BIT_SER
All bits default to '0' after reset. Note that bit D15 must be set to '1' to enable bits D[13:0].
Bit D15
ENABLE 46
0 = Disable bits D13, D[11:8] and D[4:2] of register 46h
1 = Enable bits D13, D[11:8] and D[4:2] of register 46h
Bit D14
Must write '0'
Bit D13
FALL_SDR
0 = The LCLK rising or falling edge comes at the edge of the data window when operating in
SDR output mode
1 = The LCLK rising or falling edge comes in the middle of the data window when operating
in SDR output mode
Bit D12
Must write '0'
Bits D[11:8]
EN_BIT_SER
0001 = 10-bit serialization mode enabled
0010 = 12-bit serialization mode enabled
0100 = 14-bit serialization mode enabled
Do not use any other bit combinations.
Bits D[7:5]
Must write '0'
Bit D4
EN_SDR
0 = DDR bit clock
1 = SDR bit clock
Bit D3
EN_MSB_FIRST
0 = LSB first
1 = MSB first
Bit D2
BTC_MODE
0 = Binary offset (ADC data output format)
1 = Twos complement (ADC data output format)
Bit D[1:0]
Must write '0'
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Programmable LVDS Mapping Mode Registers
Table 39. Register 50h
D15
D14
D13
D12
ENABLE 50
0
0
0
D7
D6
D5
D4
0
0
0
0
D11
D10
D9
D8
MAP_Ch1234_to_OUT2
D3
D2
D1
D0
MAP_Ch1234_to_OUT1
All bits default to '0' after reset.
Bit D15
ENABLE 50
0 = Disable bits D[11:8] and D[3:0] of register 50h.
1 = Enable bits D[11:8] and D[3:0] of register 50h.
Bits D[14:12], D[7:4]
Must write '0'
Bits D[11:8]
MAP_Ch1234_to_OUT2
These bits set the OUT2 pin pair to the channel data mapping selection.
Bits D[3:0]
MAP_Ch1234_to_OUT1
These bits set the OUT1 pin pair to the channel data mapping selection.
Table 40. Register 51h
D15
D14
D13
D12
D11
D10
D9
D8
ENABLE 51
0
0
0
0
0
0
0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D7
MAP_Ch1234_to_OUT3
All bits default to '0' after reset.
Bit D15
ENABLE 51
0 = Disable bits D[7:4] of register 51h
1 = Enable bits D[7:4] of register 51h.
Bits D[14:8], D[3:0]
Must write '0'
Bits D[7:4]
MAP_Ch1234_to_OUT3
These bits set the OUT3 pin pair to the channel data mapping selection.
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Table 41. Register 52h
D15
D14
D13
D12
D11
D10
D9
D8
ENABLE 52
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
MAP_Ch1234_to_OUT4
All bits default to '0' after reset.
Bit D15
ENABLE 52
0 = Disable bits D[3:0] of register 52h
1 = Enable bits D[3:0] of register 52h
Bits D[14:4]
Must write '0'
Bits D[3:0]
MAP_Ch1234_to_OUT4
These bits set the OUT4 pin pair to the channel data mapping selection.
Table 42. Register 53h
D15
D14
D13
D12
D11
D10
D9
D8
ENABLE 53
0
0
0
0
0
0
0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D7
MAP_Ch5678_to_OUT5
All bits default to '0' after reset.
Bit D15
ENABLE 53
0 = Disable bits D[7:4] of register 53h.
1 = Enable bits D[7:4] of register 53h.
Bits D[14:8], D[3:0]
Must write '0'
Bits D[7:4]
MAP_Ch5678_to_OUT5
These bits set the OUT5 pin pair to the channel data mapping selection.
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Table 43. Register 54h
D15
D14
D13
D12
ENABLE 54
0
0
0
D7
D6
D5
D4
0
0
0
0
D11
D10
D9
D8
MAP_Ch5678_to_OUT7
D3
D2
D1
D0
MAP_Ch5678_to_OUT6
All bits default to '0' after reset.
Bit D15
ENABLE 54
0 = Disable bits D[11:8] and D[3:0] of register 54h.
1 = Enable bits D[11:8] and D[3:0] of register 54h.
Bits D[14:12], D[7:4]
Must write '0'
Bits D[11:8]
MAP_Ch5678_to_OUT7
These bits set the OUT7 pin pair to the channel data mapping selection.
Bits D[3:0]
MAP_Ch5678_to_OUT6
These bits set the OUT6 pin pair to the channel data mapping selection.
Table 44. Register 55h
D15
D14
D13
D12
D11
D10
D9
D8
ENABLE 55
0
0
0
0
0
0
0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D7
MAP_Ch5678_to_OUT8
All bits default to '0' after reset.
Bit D15
ENABLE 55
0 = Disable bits D[7:4] of register 55h.
1 = Enable bits D[7:4] of register 55h.
Bits D[14:8], D[3:0]
Must write '0'
Bits D[7:4]
MAP_Ch5678_to_OUT8
These bits set the OUT8 pin pair to the channel data mapping selection.
68
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Custom Coefficient Registers
Table 45. Registers 5Ah to 65h (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH1
0
0
0
D7
D6
D5
D4
D11
D10
D9
D8
COEFFn_SET_CH1[11:0]
D3
D2
D1
D0
D9
D8
COEFFn_SET_CH1[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 1.
Bit D15
EN_CUSTOM_FILT_CH1
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH1[11:0]
These bits set the custom coefficient n for the channel 1 digital filter.
Table 46. Registers 66h to 71h (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH2
0
0
0
D7
D6
D5
D4
D11
D10
COEFFn_SET_CH2[11:0]
D3
D2
D1
D0
COEFFn_SET_CH2[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 2.
Bit D15
EN_CUSTOM_FILT_CH2
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH2[11:0]
These bits set the custom coefficient n for the channel 2 digital filter.
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Table 47. Registers 72h to 7Dh (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH3
0
0
0
D7
D6
D5
D4
D11
D10
D9
D8
COEFFn_SET_CH3[11:0]
D3
D2
D1
D0
D9
D8
COEFFn_SET_CH3[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 3.
Bit D15
EN_CUSTOM_FILT_CH3
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH3[11:0]
These bits set the custom coefficient n for the channel 3 digital filter.
Table 48. Registers 7Eh to 89h (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH4
0
0
0
D7
D6
D5
D4
D11
D10
COEFFn_SET_CH4[11:0]
D3
D2
D1
D0
COEFFn_SET_CH4[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 4.
Bit D15
EN_CUSTOM_FILT_CH4
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH4[11:0]
These bits set the custom coefficient n for the channel 4 digital filter.
70
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Table 49. Registers 8Ah to 95h (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH5
0
0
0
D7
D6
D5
D4
D11
D10
D9
D8
COEFFn_SET_CH5[11:0]
D3
D2
D1
D0
D9
D8
COEFFn_SET_CH5[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 5.
Bit D15
EN_CUSTOM_FILT_CH5
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH5[11:0]
These bits set the custom coefficient n for the channel 5 digital filter.
Table 50. Registers 96h to A1h (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH6
0
0
0
D7
D6
D5
D4
D11
D10
COEFFn_SET_CH6[11:0]
D3
D2
D1
D0
COEFFn_SET_CH6[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 6.
Bit D15
EN_CUSTOM_FILT_CH6
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH6[11:0]
These bits set the custom coefficient n for the channel 6 digital filter.
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Table 51. Registers A2h to ADh (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH7
0
0
0
D7
D6
D5
D4
D11
D10
D9
D8
COEFFn_SET_CH7[11:0]
D3
D2
D1
D0
D9
D8
COEFFn_SET_CH7[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 7.
Bit D15
EN_CUSTOM_FILT_CH7
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH7[11:0]
These bits set the custom coefficient n for the channel 7 digital filter.
Table 52. Registers AEh to B9h (1)
D15
D14
D13
D12
EN_CUSTOM_
FILT_CH8
0
0
0
D7
D6
D5
D4
D11
D10
COEFFn_SET_CH8[11:0]
D3
D2
D1
D0
COEFFn_SET_CH8[11:0]
(1)
n = 0 to 11.
All bits default to '0' after reset.
These registers are the custom coefficient registers for channel 8.
Bit D15
EN_CUSTOM_FILT_CH8
0 = Built-in coefficients are used
1 = Enables custom coefficients to be used
Bits D[14:12]
Must write '0'
Bits D[11:0]
COEFFn_SET_CH8[11:0]
These bits set the custom coefficient n for the channel 8 digital filter.
72
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Table 53. Register BEh
D15
D14
D13
D12
D11
D10
EN_LVDS_
PROG
0
0
0
0
0
D6
D5
D4
D3
D2
D7
DELAY_LCLK_R[2:0]
DELAY_DATA_F[1:0]
D9
D8
DELAY_DATA_R[1:0]
D1
D0
DELAY_LCLK_F[2:0]
All bits default to '0' after reset.
Bit D15
This bit enables LVDS edge delay programmability.
Bits D[14:10]
Must write '0'
Bits D[9:8]
Refer to Table 68 for settings.
Bits D[7:5]
Refer to Table 69 for settings.
Bits D[4:3]
Refer to Table 68 for settings.
Bits D[2:0]
Refer to Table 69 for settings.
Table 54. Register F0h
D15
D14
D13
D12
D11
D10
D9
D8
EN_EXT_REF
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
All bits default to '0' after reset.
The EN_HIGH_ADDRS register bit (register 01h, bit D4) must be set to '1' to allow access to this register.
Bit D15
EN_EXT_REF
0 = Internal reference mode (default)
1 = External reference mode enabled; apply the reference voltages on the REFT and REFB
pins
Bits D[14:0]
Must write '0'
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5296 is a low-power, multichannel, analog-to-digital converter (ADC) that can be operated at sample
rates up to 200 MSPS from a single 1.8-V supply. At the core, the device consists of eight 12-bit ADCs with
sample rates up to 80 MSPS. By interleaving every pair of 12-bit ADCs, the effective sample rate can be doubled
to 160 MSPS. A mode exists to operate the device as a 10-bit ADC, in which the effective sample rate can be
increased to 200 MSPS with interleaving. In both the interleaving modes (12-bit and 10-bit), the device operates
as a 4-channel ADC.
When interleaving is disabled, the device can also be operated as an 8-channel 10-bit ADC up to 100 MSPS for
systems where the SNR of the 10-bit ADC is sufficient. To summarize, the device can be configured as:
• An 8-channel, 12-bit ADC without interleaving, with sample rates up to 80 MSPS
• An 8-channel, 10-bit ADC without interleaving, with sample rates up to 100 MSPS
• A 4-channel, 12-bit ADC with interleaving, with sample rates up to 160 MSPS
• A 4-channel, 10-bit ADC with interleaving, with sample rates up to 200 MSPS
ANALOG INPUT
The analog input consists of a switched-capacitor-based, differential sample-and-hold architecture, as shown in
Figure 77. This differential topology results in very good ac performance even for high input frequencies at high
sampling rates. The INP and INM pins must be externally biased around a common-mode voltage of 0.95 V,
available on the VCM pin. For a full-scale differential input, each input pin (IN_p, IN_n) must swing symmetrically
between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The input sampling circuit
has a high 3-dB bandwidth that extends up to 500 MHz (measured from the input pins to the sampled voltage).
SZ
S
RON
25 W
LPKG
2 nH
S
CPAR3
0.3 pF
Sampling
Switch
Sampling
Capacitor
15 W
INP
RON
10 W
CBOND
0.5 pF
RESR
200 W
LPKG
2 nH
RON
40 W
CSAMP
2.6 pF
RON
10 W
CBOND
0.5 pF
RESR
200 W
CSAMP
2.6 pF
CPAR1
1.5 pF
1 kW
15 W
INN
CPAR2
1 pF
1 kW
VCM
RON
100 W
S
CPAR2
1 pF
Sampling
Switch
RON
25 W
S
Sampling
Capacitor
RON
100 W
CPAR3
0.3 pF
SZ
Figure 77. Analog Input Equivalent Circuit
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Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This architecture improves the
common-mode noise immunity and even-order harmonic rejection. A small resistor (10 Ω to 20 Ω) in series with
each input pin is recommended to damp out ringing caused by package parasitics. The drive circuits in Figure 78
and Figure 79 show an R-C filter across the analog input pins. The purpose of the filter is to absorb the glitches
caused by the opening and closing of the sampling capacitors. Figure 78 is recommended for driving the analog
inputs in interleaving mode and Figure 79 can be used for non-interleaving mode .
The analog input pins of the ADC have an internal 1k-Ω termination resistance connected to VCM voltage (see
Figure 77 ) which allows external signals to be ac-coupled to the ADC input pins. During the sampling process, a
common-mode current is drawn from VCM through the 1-kΩ termination. This current scales with sampling
frequency (approximately 1 µA per MSPS) and results in a drop in the common-mode voltage of the input pins.
The recommended range of input common-mode voltage is VCM ± 50 mV. Therefore, at higher sample rates, TI
recommends connecting an external 25-Ω to 100-Ω termination resistor to VCM. Figure 80 and Figure 81 show
the differential input resistance and capacitance across frequency.
20
0.1 PF
10
5
INP
INP
100
25
6.8 pF
VCM
25
Device
3.3 pF
Device
100
0.1 PF
INN
INN
20
10
Figure 78. DC-Coupled Drive Circuit with RCR
5
Figure 79. AC-Coupled Drive Circuit
4
2
3.5
1.5
CIN (pF)
RIN (kΩ)
3
1
2.5
2
0.5
1.5
0
0
100
200
300
400 500 600 700
Frequency (MHz)
800
900 1000
1
0
100
200
300
400 500 600 700
Frequency (MHz)
800
900 1000
G043
Figure 80. ADC Differential Input Resistance (RIN)
vs Frequency
G044
Figure 81. ADC Differential Input Capacitance (CIN)
vs Frequency
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Large- and Small-Signal Input Bandwidth
The small-signal bandwidth of the analog input circuit is high, approximately 500 MHz. When using an amplifier
to drive the ADS5296, the total amplifier noise up to the small-signal bandwidth must be considered. The largesignal bandwidth of the device depends on the amplitude of the input signal. The ADS5296 supports a 2-VPP
amplitude for input signal frequencies up to 90 MHz. For higher frequencies, the amplitude of the input signal
must be decreased proportionally. For example, at 180 MHz, the device supports a maximum 1-VPP signal.
INTERLEAVING MODE
The interleaving mode in the device can be used to sample analog inputs at frequencies greater than 100 MSPS.
A pair of ADCs are used in interleaving mode, both of which sample the same analog input signal. The sampling
instants of the two ADCs are interleaved in such a way that while one ADC samples the input at every odd edge
of the device input clock, the second ADC samples the input at every even edge of the input clock, as shown in
Figure 82.
Sample
N
Sample
N+2
Sample
N+1
Sample
N+4
Sample
N+3
Sample
N + 15
Sample
N + 14
Sample
N + 13
Sample
N + 12
Sample
N + 16
Sample
N + 17
Sample
N + 18
INP
CLKP
Sampling Clock
ADCn
Internal
Signals
Sampling Clock
ADCn+1
N
N+2
N+4
OUTn
…………
D9
D0
…………
D9
D0
…………
……
D0
…………
D9
D0
…………
D9
D0
…………
D9
D0
D1
OUTn+1
…………
D9
D0
…………
D9
D0
…………
……
D0
…………
D9
D0
…………
D9
D0
…………
D9
D0
D1
N+1
N+3
N+5
NOTE: n = 1, 3, 5, or 7.
Figure 82. Interleaving Mode Latency Timing Diagram
Note that in this mode, device input clock frequency is actually 2x times the sampling rate of each ADC. For
example, when a 200-MHz clock input is applied, each ADC in the pair samples at 100 MHz, but the sampling
instants of both ADCs are staggered (or offset) by one 200-MHz clock cycle. Each ADC converts the sampled
values and outputs the data over separate LVDS pairs. The receiver used to capture the data from the device
[either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA)] must combine
the data from the two LVDS pairs and reconstruct the data stream at 200 MSPS (see Figure 83). In this mode,
the device operates as a 4-channel ADC because the interleaving operation requires two ADCs per channel.
After applying a reset and enabling interleaving mode (EN_INTERLEAVE = 1), the four interleaved ADC
channels sample the analog inputs at the odd pins (IN1, IN3, IN5, and IN7). A mode exists where the analog
inputs at the even pins can be sampled by using the ODD_EVEN_SEL register bits. Instead of using the register
bits, the INTERLEAVE_MUX pin can be used to select between the odd and even input pins (see Table 55).
As Figure 82 shows, in the interleaving mode, the device input clock is divided by two to generate two sampling
clocks which are 180° out of phase with each other. The odd ADC (ADC1, ADC3, ADC5, ADC7) in each
interleaving pair uses one sampling clock while the even ADC (ADC2, ADC4, ADC6, ADC8) in the pair uses the
other sampling clock. When using multiple ADS5296 chips, it is necessary to ensure that the sampling clock for
the odd (and even) ADCs in every chip are synchronized. This can be achieved by using the SYNC input signal.
See SYNCHRONIZATION USING THE SYNC PIN for description of the SYNC functionality.
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Table 55. Interleaving Mode
PIN (1)
MODE
REGISTER BITS
INTERLEAVE_
MUX
EN_
INTERLEAVE
EN_MUX_REG
ODD_EVEN_SEL
Don't care
0
0
8000h
Low
0
1
Don't care
Don't care
0
0
80FFh
High
0
1
Don't care
Don't care
1
0
8000h
Low
1
1
Don't care
Don't care
1
0
80FFh
High
1
1
Don't care
No interleaving
•
•
8-channel ADC mode
IN1 ↔ OUT1, IN2 ↔ OUT2
•
•
•
IN3 ↔ OUT3, IN4 ↔ OUT4
IN5 ↔ OUT5, IN6 ↔ OUT6
IN7 ↔ OUT7, IN8 ↔ OUT8
No interleaving
•
•
8-channel ADC mode
IN1 ↔ OUT2, IN2 ↔ OUT1
•
•
•
IN3 ↔ OUT4, IN4 ↔ OUT3
IN5 ↔ OUT6, IN6 ↔ OUT5
IN7 ↔ OUT8, IN8 ↔ OUT7
Interleaving enabled
•
•
4-channel ADC Mode
IN1 ↔ OUT1, OUT2
•
•
•
IN3 ↔ OUT3, OUT4
IN5 ↔ OUT5, OUT6
IN7 ↔ OUT7, OUT8
Interleaving enabled
•
•
4-channel ADC Mode
IN2 ↔ OUT1, OUT2
•
•
•
IN4 ↔ OUT3, OUT4
IN6 ↔ OUT5, OUT6
IN8 ↔ OUT7, OUT8
(1)
INTERLEAVE_MUX has an internal pull-up resistor to supply.
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The block diagrams for interleaving even input pins and interleaving odd input pins are shown in Figure 83 and
Figure 84.
EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 0, and ODD_EVEN_SEL = 8000h,
or
EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 1, and INTERLEAVE_MUX Pin Low
OUT1
10 BIT
ADC 1
ADAC
IN1
Sample N
IN1
Sample N+2
IN1
Sample N+1
IN1
Sample N+3
OUT3
IN3
Sample N
IN3
Sample N+2
OUT4
IN3
Sample N+1
IN3
Sample N+3
OUT5
IN5
Sample N
IN5
Sample N+2
OUT6
IN5
Sample N+1
IN5
Sample N+3
OUT7
IN7
Sample N
IN7
Sample N+2
OUT8
IN7
Sample N+1
IN7
Sample N+3
IN1_p, IN1_n
IN2_p, IN2_n
OUT2
10 BIT
ADC 2
ADAC
IN3_p, IN3_n
IN4_p, IN4_n
IN5_p, IN5_n
IN6_p, IN6_n
IN7_p, IN7_n
IN8_p, IN8_n
Figure 83. Odd Input Pins, Interleaved
EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 0, and ODD_EVEN_SEL = 80FFh,
or
EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 1, and INTERLEAVE_MUX Pin High
OUT1
10 BIT
ADC 1
ADAC
IN2
Sample N
IN2
Sample N+2
IN1_p, IN1_n
IN2_p, IN2_n
OUT2
10 BIT
ADC 2
ADAC
IN2
Sample N+1
IN2
Sample N+3
OUT3
IN4
Sample N
IN4
Sample N+2
OUT4
IN4
Sample N+1
IN4
Sample N+3
OUT5
IN6
Sample N
IN6
Sample N+2
OUT6
IN6
Sample N+1
IN6
Sample N+3
OUT7
IN8
Sample N
IN8
Sample N+2
OUT8
IN8
Sample N+1
IN8
Sample N+3
IN3_p, IN3_n
IN4_p, IN4_n
IN5_p, IN5_n
IN6_p, IN6_n
IN7_p, IN7_n
IN8_p, IN8_n
Figure 84. Even Input Pins, Interleaved
78
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CLOCK INPUT
The device can operate with both single-ended (CMOS) and differential input clocks (such as sine wave,
LVPECL, and LVDS). Operating with a low-jitter differential clock is recommended for good SNR performance,
especially at input frequencies greater than 30 MHz. In differential mode, the clock inputs are internally biased to
a 0.95-V common-mode voltage. While driving with an external LVPECL or LVDS driver, TI recommends accoupling the clock signals so that the clock pins are correctly biased to the common-mode voltage (0.95 V). To
operate using a single-ended clock, connect a CMOS clock source to CLKP and tie CLKN to GND. The device
automatically detects the presence of a single-ended clock without requiring any configuration and disables
internal biasing. Typical clock termination schemes are shown in Figure 85, Figure 86, Figure 87, and Figure 88.
Figure 89 and Figure 90 show the equivalent circuit of the clock pins in both single-ended and differential modes.
0.1 mF
0.1 mF
CLKP
CLKP
RTERM
Differential
LVPECL
Clock Input
Differential
Sine-Wave
Clock Input
0.1 mF
0.1 mF
CLKN
CLKN
RTERM
Figure 85. Differential Sine-Wave Clock
Driving Circuit
Figure 86. Differential LVPECL Clock
Driving Circuit
0.1 mF
CMOS
Clock Input
CLKP
Differential
LVDS
Clock Input
CLKP
RTERM
0.1 mF
CLKN
CLKN
Figure 87. Differential LVDS Clock Driving Circuit
Figure 88. Single-Ended Clock Driving Circuit
Sampling clock
CLKP
CLKP
22kQ
Internal single ended
clock buffer
4kQ
Sampling clock
VCM_Internal
VCM_Internal
4kQ
Internal differential
clock buffer
22kQ
CLKN
CLKN
Device
Device
Figure 89. Input Clock Equivalent Circuit:
Single-Ended Mode
Figure 90. Input Clock Equivalent Circuit:
Differential Mode
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EXTERNAL REFERENCE MODE OF OPERATION
For normal operation, the device requires two reference voltages (REFT and REFB) that are generated internally
by default, as shown in Figure 91. The value of the reference voltage determines the actual ADC full-scale input
voltage, as shown in Equation 1:
Full-Scale Input Voltage = 2 ´ (VREFT - VREFB)
(1)
Device
EN_EXT_REF
Internal
Reference
REFT
REF Amp
REFB
EN_EXT_REF
ADC
Figure 91. Reference Equivalent Circuit
Any error in the reference results in a deviation of the full-scale input range from its ideal value of 2.0 VPP, as
shown in Equation 2:
Error in Full-Scale Voltage = 2x [Error in (VREFT – VREFB)]
(2)
The reference inaccuracy results in a gain error, which is defined as Equation 3:
100
Gain Error (%) = Error in Full-Scale Voltage ´
Ideal Full-Scale Voltage
= 2x [Error in (VREFT - VREFB)] ´
100
2.0
(3)
To minimize gain error, the internal reference voltages are trimmed to an accuracy of ±1.5%. To obtain even
lower gain error, the device supports an external reference mode of operation. In this mode, the internal
reference amplifiers are powered down and an external amplifier must force the reference voltages on the REFT
and REFB pins. For example, this mode can be used to ensure that multiple ADS5296 devices in the system
have nearly the same full-scale voltage.
To enable external reference mode, set the register bits as shown in Table 56. These settings power-down the
internal reference amplifier and the two reference voltages can be forced directly on the REFT and REFB pins as
VREFT = 1.45 V and VREFB = 0.45 V, respectively.
Table 56. External Reference Function
FUNCTION
EN_HIGH_ADDRS
EN_EXT_REF
1
1
External reference using the REFT, REFB pins
Because the internal reference amplifiers are powered down, the accuracy of the full-scale voltage is determined
by the accuracy of (VREFT – VREFB), where VREFT is the voltage forced on REFT and VREFB is the voltage forced
on REFB. Note that although the nominal value of (VREFT – VREFB) = 1.0 V, ensure that Equation 4 is met:
[(VREFT + VREFB) / 2 = 0.950 V ± 50 mV]
80
(4)
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Figure 92 shows an example of driving the reference pins. The 1-µF bypass capacitor helps provide the
switching current drawn by the REFT and REFB pins. The external amplifier must provide an average current of
5 mA or less at the maximum sample rate. Performance in the external reference mode depends on sampling
speed. At low sampling speeds (for instance, 20 MSPS), performance is the same as that of an internal
reference. At higher speeds, performance degrades because of the effect of parasitic bond-wire inductance of
the REF pins. Figure 93 highlights the difference in SNR between the external and internal reference modes.
RS
+
REFT
VT
1 mF
VB
Precision
Reference
Device
+
RS
REFB
1 mF
Figure 92. Driving Reference Inputs in External Reference Mode
73
SNR in External Reference
SNR in Internal Reference
72
71
SNR (dBFS)
70
69
68
67
66
65
20
30
40
50
60
Sampling Frequency (MSPS)
70
80
G045
Figure 93. SNR in Internal and External Reference Mode
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LOW-FREQUENCY NOISE SUPPRESSION
The low-frequency noise suppression (LFNS) mode is particularly useful in applications where good noise
performance is desired in the low-frequency band of dc to 1 MHz. By setting this mode, the low-frequency noise
spectrum band around dc is shifted to a similar band around fS / 2 (or the Nyquist frequency). As a result, the
noise spectrum from dc to approximately 1 MHz improves significantly, as shown in Figure 94, Figure 95, and
Figure 96.
This function can be selectively enabled in each channel using the LFNS_CH register bits. Figure 94, Figure 95,
and Figure 96 show the effect of this mode on the spectrum.
0
0
SNR = 70.3 dBFS
SINAD = 70.1 dBFS
SFDR = 82.7 dBc
THD = 82.2 dBc
−10
−20
LF Noise Suppression Enabled
LF Noise Suppression Disabled
−10
−20
−30
−30
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−50
−60
−70
−80
−50
−60
−70
−80
−90
−100
−90
−110
−100
−120
−110
−120
−130
0
10
20
Frequency (MHz)
30
40
−140
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Frequency (MHz)
0.8
0.9
G029
Figure 94. Full-Band FFT, 5-MHz Input
(80-MHz FS with LFNS Enabled)
1
G030
Figure 95. 0-MHz to 1-MHz FFT, 5-MHz Input
(80-MHz FS with LFNS Enabled)
0
LF Noise Suppression Enabled
LF Noise Suppression Disabled
−10
−20
−30
Amplitude (dBFS)
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
39
39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 39.9
Frequency (MHz)
40
G031
Figure 96. 39-MHz to 40-MHz FFT, 5-MHz Input
(80-MHz FS with LFNS Enabled)
82
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DIGITAL PROCESSING BLOCKS
The device integrates a set of commonly-used digital functions that can be used to ease system design. These
functions are shown in Figure 97 and are described in the following sections.
LVDS Outputs
Test
Patterns,
Ramp
Channel 1 ADC Data
12-Bit
ADC
Average of
2 Channels
Serializer
Wire 1
Channel 2
23-Tap Tilter
(Odd Tap)
Channel 2
Average of
4 Channels
Channel 4
OUT1
Decimate
By 2 or 4
24-Tap Filter
(Even Tap)
ADC Data:
Channel 3
Channel 1
Built-In Coefficients
Serializer
Wire 1
OUT2
Mapper
Custom Coefficients
24-Tap Filter
(Even Tap)
Decimate
By 2, 4,
or 8
Channel 3
Gain
(0 dB to 12 dB,
in 1-dB steps)
23-Tap Filter
(Odd Tap)
4:4
Multiplexer
Serializer
Wire 1
OUT3
12-Tap Filter
Channel 4
Serializer
Wire 1
Digital Processing Block for Channel 1
12-Bit
ADC
Channel 2 ADC Data
Digital Processing Block for Channel 2
12-Bit
ADC
Channel 3 ADC Data
Digital Processing Block for Channel 3
12-Bit
ADC
Channel 4 ADC Data
Digital Processing Block for Channel 4
OUT4
1/2 ADS5296
Figure 97. Digital Processing Block Diagram
Digital Gain
The device includes programmable digital gain settings from 0 dB to 12 dB, in 1-dB steps. The benefit of digital
gain is obtaining improved SFDR performance. However, SFDR improvement is achieved at the expense of
SNR; for each gain setting, SNR degrades by approximately 1 dB. Therefore, gain can be used to trade-off
between SFDR and SNR.
For each gain setting, the supported analog input full-scale range scales proportionally, as shown in Table 57.
After reset, the device comes up in 0-dB gain mode. To use other gain settings, program the GAIN_CHn[3:0]
register bits.
Table 57. Analog Full-Scale Range Across Gains
GAIN_CHn[3:0]
DIGITAL GAIN (dB)
ANALOG FULL-SCALE INPUT (VPP)
0000
0
2
0001
1
1.78
0010
2
1.59
0011
3
1.42
0100
4
1.26
0101
5
1.12
0110
6
1
0111
7
0.89
1000
8
0.8
1001
9
0.71
1010
10
0.63
1011
11
0.56
1100
12
0.5
Other combinations
Do not use
—
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Digital Filter
The digital processing block includes the option to filter and decimate the ADC data outputs digitally. Various
filters and decimation rates are supported: decimation rates of 2, 4, and 8, and low-pass, high-pass, and bandpass filters are available.
The filters are internally implemented as 24-tap symmetric finite impulse response (FIR) filters (even-tap) using
the predefined coefficients of Equation 5:
y(n) =
1
211
´ [h0.x(n) + h1.x(n-1) + h2.x(n-2) + ... + h11.x(n-11) + h12.x(n-12) + ... + h1.x (n-22) + h0.x(n-23)]
(5)
Alternatively, some filters can be configured as 23-tap symmetric FIR filters (odd-tap), as described in
Equation 6:
y(n) =
1
211
´ [h0.x(n) + h1.x(n-1) + h2.x(n-2) + ... + h10.x(n-10) + h11.x(n-11) + h10.x(n-12) + ... + h1.x (n-21) + h0.x(n-22)]
(6)
In Equation 5 and Equation 6, h0 through h11 are 12-bit, signed, twos complement representations of the
coefficients (–2048 to +2047). x(n) is the filter input data sequence and y(n) is the filter output sequence.
Details of the registers used for configuring the digital filters are described in the digital filter registers (registers
29h, 2Eh, 2Fh, 30h, 31h, and 38h) and Table 58. Table 58 gives a summary of the register bits to be used for
each filter type.
Table 58. Digital Filters
DATA_
RATE
DEC_RATE
_CHn (1)
FILTER_
TYPE_CHn
ODD_
TAP_CHn
USE_
FILTER_
CHn
EN_
CUSTOM_
FILT_CHn
EN_DIG_
FILTER
Built-in, low-pass, odd-tap filter
(pass band = 0 to fS / 4)
01
000
000
1
1
0
1
Built-in, high-pass, odd-tap filter
(pass band = 0 to fS / 4)
01
000
001
1
1
0
1
Built-in, low-pass, even-tap filter
(pass band = 0 to fS / 8)
10
001
010
0
1
0
1
Built-in, first band-pass, even-tap filter
(pass band = fS / 8 to fS / 4)
10
001
011
0
1
0
1
Built-in, second band-pass,
even-tap filter
(pass band = fS / 4 to 3 fS / 8)
10
001
100
0
1
0
1
Built-in, high-pass, odd-tap filter
(pass band = 3 fS / 8 to fS / 2)
10
001
101
1
1
0
1
Decimate-by-2
Custom filter
(user-programmable coefficients)
01
000
000
0 or 1
1
1
1
Decimate-by-4
Custom filter
(user-programmable coefficients)
10
001
000
0 or 1
1
1
1
Decimate-by-8
Custom filter
(user-programmable coefficients)
11
100
000
0 or 1
1
1
1
12-tap filter, no
decimation
Custom filter
(user-programmable coefficients)
00
011
000
0
1
1
1
DECIMATION
Decimate-by-2
Decimate-by-4
(1)
84
TYPE OF FILTER
The DEC_RATE_CHn value must be the same for all channels.
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Predefined Coefficients
The built-in filter types (low pass, high pass, and band pass) use predefined coefficients. The frequency
response of the built-in filters is shown in Figure 98 and Figure 99.
The predefined coefficients for the decimate-by-2 and decimate-by-4 filters are listed in Table 59 and Table 60,
respectively.
40
20
Low-Pass
High-Pass
10
Low-Pass
Band-Pass 1
Band-Pass 2
High-Pass
30
20
0
Normalized Amplitude (dB)
Normalized Amplitude (dB)
10
−10
−20
−30
−40
−50
0
−10
−20
−30
−40
−50
−60
−60
−70
−80
−70
0
0.1
0.2
0.3
0.4
Normalized Frequency (fIN/fS)
−80
0.5
0
0.1
0.2
0.3
0.4
Normalized Frequency (fIN/fS)
G024
0.5
G025
Figure 98. Filter Response (Decimate-by-2)
Figure 99. Filter Response (Decimate-by-4)
Table 59. Predefined Coefficients for Decimate-by-2 Filters
COEFFICIENTS
DECIMATE-BY-2 FILTERS
LOW-PASS
HIGH-PASS
h0
3
–22
h1
0
–65
h2
5
–52
h3
1
30
h4
–27
66
h5
–2
–35
h6
73
–107
h7
3
38
h8
–178
202
h9
–4
–41
h10
636
–644
h11
1024
1061
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Table 60. Predefined Coefficients for Decimate-by-4 Filters
COEFFICIENTS
DECIMATE-BY-4 FILTERS
LOW-PASS
1st BAND-PASS
2nd BAND-PASS
HIGH-PASS
h0
–17
–7
–34
40
h1
–50
19
–34
–15
h2
71
–47
–101
–95
h3
46
127
43
22
h4
24
73
58
–8
h5
–42
0
–28
–81
h6
–100
86
–5
106
h7
–97
117
–179
–62
h8
8
–190
294
–97
h9
202
–464
86
310
h10
414
–113
–563
–501
h11
554
526
352
575
Custom Filter Coefficients
In addition to the built-in filters described in the Predefined Coefficients section, customers also have the option
of using their own custom, 12-bit, signed coefficients. Because of the symmetric FIR implementation of the filters,
only 12 coefficients can be specified with the configurations in Equation 5 or Equation 6. These coefficients (h0
to h11) must be configured in the custom coefficient registers, as shown in Equation 7:
Register Content = 12-Bit Signed Representation of (Real Coefficient Value × 211)
(7)
The 12 custom coefficients must be loaded into 12 separate registers for each channel (refer to the custom
coefficient registers, 5Ah to B9h). The MSB bit of each coefficient register determines whether built-in filters or
custom filters are used. If the EN_CUSTOM_FILT MSB bit is reset to '0', then built-in filter coefficients are used.
Otherwise, custom coefficients are used.
Custom Filter without Decimation
Another mode is available that enables the use of the digital filter without decimation. In this mode, the filter
behaves similar to a 12-tap symmetric FIR filter, as shown in Equation 8:
y(n) =
1
211
´ [h6.x(n) + h7.x(n-1) + h8.x(n-2) + h9.x(n-3) + h10.x(n-4) + h11.x(n-5) +
+ h11.x(n-6) + h10.x(n-7) + h9.x(n-8) + h8.x(n-9) + h7.x(n-10) + h6.x (n-11)]
(8)
In Equation 8, h6 through h11 are 12-bit, signed, twos complement representations of the coefficients (–2048 to
+2047). x(n) is the filter input data sequence and y(n) is the filter output sequence.
In this mode, because the filter is implemented as a 12-tap symmetric FIR, only six custom coefficients must be
specified and loaded in registers h6 to h11 (refer to the custom coefficient registers, 5Ah to B9h). To enable this
mode, use the register setting specified in bit 15 of registers AEh to B9h.
Digital High-Pass Filter
In addition to the 12 tap filters described previously, the digital processing block also includes a separate highpass filter for each channel. The high-pass corner frequency can be programmed using bits D[14:10] in register
2Eh.
86
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Digital Averaging
The device includes an averaging function where the ADC digital data from two (or four) channels can be
averaged. The averaged data are output on specific LVDS channels. Table 61 shows the combinations of the
input channels that can be averaged and the LVDS channels on which the averaged data are available.
Table 61. Using Channel Averaging
AVERAGED CHANNELS
OUTPUT WHERE
AVERAGED DATA ARE
AVAILABLE AT
REGISTER SETTINGS
1, 2
OUT1
Set AVG_OUT1 = 10 and EN_CHANNEL_AVG = 1
1, 2
OUT3
Set AVG_OUT3 = 11 and EN_CHANNEL_AVG = 1
3, 4
OUT4
Set AVG_OUT4 = 10 and EN_CHANNEL_AVG = 1
3, 4
OUT2
Set AVG_OUT2 = 11 and EN_CHANNEL_AVG = 1
1, 2, 3, 4
OUT1
Set AVG_OUT1 = 11 and EN_CHANNEL_AVG = 1
1, 2, 3, 4
OUT4
Set AVG_OUT4 = 11 and EN_CHANNEL_AVG = 1
5, 6
OUT5
Set AVG_OUT5 = 10 and EN_CHANNEL_AVG = 1
5, 6
OUT7
Set AVG_OUT7 = 11 and EN_CHANNEL_AVG = 1
7, 8
OUT8
Set AVG_OUT8 = 10 and EN_CHANNEL_AVG = 1
7, 8
OUT6
Set AVG_OUT6 = 11 and EN_CHANNEL_AVG = 1
5, 6, 7, 8
OUT5
Set AVG_OUT5 = 11 and EN_CHANNEL_AVG = 1
5, 6, 7, 8
OUT8
Set AVG_OUT8 = 11 and EN_CHANNEL_AVG = 1
Performance with Digital Processing Blocks
In applications where higher SNR performance is desired, digital processing blocks (such as averaging and
decimation filters) can be used advantageously to achieve higher performance. Table 62 shows the improvement
in SNR that can be achieved compared to the default value, using these modes.
Table 62. SNR Improvement Using Digital Processing
TYPICAL SNR (dB) (1)
TYPICAL IMPROVEMENT IN
SNR (dB)
Default
70.4
NA
With decimate-by-2 filter enabled
75.4
5
With decimate-by-4 filter enabled
76.7
6.3
With two channels averaged
75
4.6
With four channels averaged
75.8
5.4
MODE
(1)
In all modes (except default), 14x serialization is used to capture data.
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PROGRAMMABLE MAPPING BETWEEN INPUT CHANNELS AND OUTPUT PINS
The device has eight pairs of LVDS channel outputs. The mapping of ADC channels to LVDS output channels is
programmable to allow for flexibility in board layout. Control register mapping is shown in Table 63. The eight
LVDS channel outputs are split into two groups of four LVDS pairs. Within each group, four ADC input channels
can be multiplexed to the four LVDS pairs.
Table 63. Mapping Control Registers
ADDRESS
(Hex)
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
D7
D6
D5
D4
1
D3
D2
D1
D0
NAME
X
X
X
X
MAP_Ch1234_to_OUT1
50
1
51
1
52
1
53
1
MAP_Ch1234_to_OUT2
X
X
X
X
X
X
X
MAP_Ch1234_to_OUT3
X
X
X
X
X
X
X
X
X
1
MAP_Ch1234_to_OUT4
MAP_Ch5678_to_OUT5
MAP_Ch5678_to_OUT6
54
1
55
X
X
1
X
X
MAP_Ch5678_to_OUT7
X
X
X
X
MAP_Ch5678_to_OUT8
Input channels 1 to 4 can be mapped to any LVDS output (OUT1 to OUT4) using the MAP_CH1234_TO_OUTn
bits, as shown in Table 64.
Table 64. Mapping Analog Inputs IN1-IN4 to LVDS Outputs OUT1-4
MAP_CH1234_TO_OUTN[3:0] (1)
(1)
88
MAPPING
0000
ADC input channel IN1 to OUTn
0010
ADC input channel IN2 to OUTn
0100
ADC input channel IN3 to OUTn
0110
ADC input channel IN4 to OUTn
1xxx
LVDS output buffer OUTn powered down
n = 1, 2, 3, or 4.
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Similarly, input channels 5 to 8 can be mapped to any LVDS output (OUT5 to OUT8) using the
MAP_CH5678_TO_OUTn bits, as shown in Table 65. Both multiplexing options are controlled by registers 50h to
55h. The channel mapping block diagram is illustrated in Figure 100.
Table 65. Mapping analog inputs IN8-IN8 to LVDS outputs OUT5-8
MAP_CH5678_TO_OUTN[3:0] (1)
(1)
MAPPING
0000
ADC input channel IN8 to OUTn
0010
ADC input channel IN7 to OUTn
0100
ADC input channel IN6 to OUTn
0110
ADC input channel IN5 to OUTn
1xxx
LVDS output buffer OUTn powered down
n = 5, 6, 7, or 8.
Channel 8 Data
MAP_CH5678_to_OUTn[3:0] = 0000
Channel 7 Data
MAP_CH5678_to_OUTn[3:0] = 0010
OUTn
(1)
Channel 6 Data
MAP_CH5678_to_OUTn[3:0] = 0100
MAP_CH5678_to_OUTn[3:0] = 1xxx,
the unused OUTn LVDS buffer is powered down.
Channel 5 Data
MAP_CH5678_to_OUTn[3:0] = 0110
Channel 4 Data
MAP_CH1234_to_OUTn[3:0] = 0110
Channel 3 Data
MAP_CH1234_to_OUTn[3:0] = 0100
OUTn
(1)
Channel 2 Data
MAP_CH1234_to_OUTn[3:0] = 0010
MAP_CH1234_to_OUTn[3:0] = 1xxx,
the unused OUTn LVDS buffer is powered down.
Channel 1 Data
MAP_CH1234_to_OUTn[3:0] = 0000
(1) For channels 1 to 4, n = 1, 2, 3, 4. For channels 5 to 8, n = 5, 6, 7, 8.
Figure 100. Channel Mapping
The default mapping is shown in Table 66.
Table 66. Default Mapping After Reset
ANALOG INPUT CHANNEL
LVDS OUTPUT
Channel IN1
OUT1
Channel IN2
OUT2
Channel IN3
OUT3
Channel IN4
OUT4
Channel IN5
OUT5
Channel IN6
OUT6
Channel IN7
OUT7
Channel IN8
OUT8
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SYNCHRONIZATION USING THE SYNC PIN
The SYNC pin can be used to synchronize:
• The data output across channels within the same device or
• The data from channels across multiple devices when decimation filters are used
• The odd and even ADC sampling instants across multiple devices in interleaving mode
When decimation filters are used (if the decimate-by-2 filter is enabled, for example), then effectively the device
outputs one digital code for every two analog input samples. If the SYNC pulse is not used, then the filters are
not synchronized (even within a device). When the filters are not synchronized, one channel may be transmitting
codes corresponding to input samples N, N+1, and so on, while another channel may be transmitting codes
corresponding to N+1, N+2, and so on.
To achieve synchronization across multiple devices, the SYNC pulse must arrive at all ADS5296 devices at the
same time (as shown in Figure 101). The ADS5296 generates an internal synchronization signal that resets the
internal clock dividers used by the decimation filter and in the interleaving mode. Using the SYNC signal in this
manner ensures that all channels output digital codes corresponding to the same set of input samples.
Synchronizing the filters using the SYNC pin is enabled by default. No register bits are required to be written.
The TP_HARD_SYNC register bit must be reset to '0' for this mode to function properly. As shown in Figure 101,
the SYNC rising edge can be positioned anywhere within the window. SYNC width must be at least one clock
cycle.
In addition, SYNC can also be used to synchronize the RAMP test patterns across channels. In order to
synchronize the test patterns, TP_HARD_SYNC must be set to '1'. Setting TP_HARD_SYNC to '1' actually
disables the sync of the filters.
0 ns
tCLK / 2
ADC Input
Clock
-1 ns
tCLK / 2
tD = -1 ns < tD < tCLK / 2
SYNC
tWIDTH ³ 1 Clock Cycle
Figure 101. SYNC Timing Diagram
Synchronizing ADC Sampling Instants (Non-Interleaving mode)
Note that in the non-interleaved mode, the SYNC cannot be used to synchronize the ADC sampling instants
across devices. All channels within a single device sample the analog inputs simultaneously. To ensure that
channels across two devices sample the analog inputs simultaneously, the input clock must be routed to both
devices with an identical length. This layout ensures that the input clocks arrive at both devices at the same time.
90
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DIGITAL OUTPUT INTERFACE
SERIAL LVDS INTERFACE
The ADS5296 offers several flexible output options, making the device easy to interface to an application-specific
integrated circuit (ASIC) or a field-programmable gate array (FPGA). Each option can be easily programmed
using the serial interface. A summary of all available options is listed in Table 67 along with the default values
after power-up and reset. Following Table 67, each option is described in detail.
Table 67. Summary of Output Interface Options
FEATURE
Serialization factor
OPTIONS
DEFAULT AFTER POWERUP AND RESET
12x
12x
10x
12x
BRIEF DESCRIPTION
To be used with digital processing functions, such as
averaging and decimation filers.
14x
DDR bit clock frequency
6x, 5x, 7x
6x
Frame clock frequency
1x sample rate
1x
For 12x, 10x, and 14x serialization factors respectively.
12x Serialization with DDR Bit Clock and 1x Frame Clock
The 12-bit ADC data are serialized and output over one LVDS pair per channel along with a 6x bit clock and a 1x
frame clock, as shown in Figure 102. The output data rate is a 12x sample rate, and maximum data rates up to
960 Mbps are supported.
Input Clock
(CLK Frequency = fS)
Frame Clock
(ADCLK Frequency = 1x fS)
Bit Clock
(LCLK Frequency = 6x fS)
Output Data(1)
(OUTA Data rate = 12x fS)
D11
(D0)
D10
(D1)
D9
(D2)
D8
(D3)
D7
(D4)
D6
(D5)
D5
(D6)
D4
(D7)
D3
(D8)
D2
(D9)
D1
(D10)
D0
(D11)
D11
(D0)
D10
(D1)
Sample N
Sample N+1
(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.
Figure 102. LVDS Output Interface Timing Diagram (12x Serialization)
10x Serialization with DDR Bit Clock and 1x Frame Clock
The 10 upper bits of the 12-bit ADC data are serialized and output over one LVDS pair per channel along with a
5x bit clock and a 1x frame clock, as shown in Figure 103. The output data rate is a 10x sample rate, and
maximum data rate ups to 1 Gbps are supported.
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Input Clock
(CLK Frequency = fS)
Frame Clock
(ADCLK Frequency = 1x fS)
Bit Clock
(LCLK Frequency = 5x fS)
Output Data(1)
(OUTA Data rate = 10x fS)
D9
(D0)
D8
(D1)
D7
(D2)
D6
(D3)
D5
(D4)
D4
(D5)
D3
(D6)
D2
(D7)
D1
(D8)
D0
(D9)
D9
(D0)
D8
(D1)
D7
(D2)
Sample N
Sample N+1
(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.
Figure 103. LVDS Output Interface Timing Diagram (10x Serialization)
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PROGRAMMABLE LCLK PHASE
The device enables the edge of the output bit clock (LCLK) to be programmed with the PHASE_DDR register
bits. The default value of PHASE_DDR after reset is '10'. The default phase is shown in Figure 104.
The phase can also be changed by changing the value of the PHASE_DDR[1:0] bits, as shown in Figure 105.
ADCLKP
LCLKP
DATA
OUT
PHASE_DDR[1:0] = 10
Figure 104. Default LCLK Phase
ADCLKP
ADCLKP
LCLKP
LCLKP
DATA
OUT
DATA
OUT
PHASE_DDR[1:0] = 10
PHASE_DDR[1:0] = 00
ADCLKP
ADCLKP
LCLKP
LCLKP
DATA
OUT
DATA
OUT
PHASE_DDR[1:0] = 11
PHASE_DDR[1:0] = 01
Figure 105. Programmable LCLK Phases
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PROGRAMMABLE LVDS OUTPUT CLOCK AND DATA DELAYS
The device enables the edges of the output data and output bit clock to be delayed with the DELAY_DATA and
DELAY_LCLK register bits.
Figure 106 details the timing of the output data and clock edge movements. Table 68 and Table 69 show the
register settings and corresponding delay values for the data and clock edge movements.
tDF
tDR
DATA
LCLKN
tCR
tCF
LCLKP
Figure 106. LVDS Interface Output Data and Clock Edge Movement
Table 68. LVDS Interface Output Data Delay Settings (1)
DELAY_DATA_R[1:0]
(1)
(2)
DATA DELAY,
RISING CLOCK EDGE (2)
(tDR, typical, ps)
DELAY_DATA_F[1:0]
DATA DELAY,
FALLING CLOCK EDGE (2)
(tDF, typical, ps)
0
0
0
0
0
0
0
1
33
0
1
33
1
0
72
1
0
72
1
1
120
1
1
120
Delay settings are the same for both 10x and 12x serialization modes.
Positive value indicates that the data edge is delayed with respect to the clock, resulting in lower setup time and higher hold time
Table 69. LVDS Interface Output Clock Delay Settings (1)
DELAY_LCLK_R[2:0]
(1)
(2)
94
CLOCK RISING EDGE DELAY (2)
(tCR, typical, ps)
DELAY_LCLK_F[2:0]
CLOCK FALLING EDGE DELAY (2)
(tCF, typical, ps)
0
0
0
-106
0
0
0
-120
0
0
1
-73
0
0
1
-87
0
1
0
-34
0
1
0
-48
0
1
1
14
0
1
1
0
1
0
0
0
1
0
0
-14
1
0
1
53
1
0
1
39
1
1
0
96
1
1
0
82
1
1
1
138
1
1
1
124
Delay settings are the same for both 10x and 12x serialization modes.
Negative value indicates that the clock edge is advanced with respect to the data edge, resulting in lower setup time and higher hold
time. Positive value indicates that the clock edge is delayed with respect to the data edge, resulting in higher setup time and lower hold
time
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LVDS OUTPUT DATA AND CLOCK BUFFERS
The equivalent circuit of each LVDS output buffer is shown in Figure 107. After reset, the buffer presents an
output impedance of 100 Ω to match with the external 100-Ω termination.
The VDIFF voltage is nominally 400 mV, resulting in an output swing of ±400 mV with a 100-Ω external
termination. The buffer output impedance behaves in the same way as a source-side series termination. By
absorbing reflections from the receiver end, this impedance helps improve signal integrity.
VDIFF
High
Low
OUTP
External
100-W Load
OUTM
VOCM
ROUT
VDIFF
Low
(1)
High
(1) ROUT = 100 Ω.
Figure 107. LVDS Buffer Equivalent Circuit
OUTPUT DATA FORMAT
Two output data formats are supported: twos complement and offset binary. These formats can be selected by
the BTC_MODE serial interface register bit. In the event of an input voltage overdrive, the digital outputs go to
the appropriate full-scale level. For a positive overload, the 12-bit output data (D[11:0]) is FFFh in offset binary
output format and 7FFh in twos complement output format. For a negative input overload, the output data is 000h
in offset binary output format and 800h in twos complement output format.
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. Refer to the EVM User Guide, ADS5295, 8-Channel ADC Evaluation Module,
(SLAU442) for details on layout and grounding.
Supply Decoupling
Minimal external decoupling can be used without loss in performance because the device already includes
internal decoupling. Note that decoupling capacitors can help filter external power-supply noise; thus, the
optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed as
close as possible to the converter supply pins.
Exposed Pad
In addition to providing a path for heat dissipation, the pad is also electrically connected to the digital ground
internally. Therefore, the exposed pad must be soldered to the ground plane for best thermal and electrical
performance.
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (jitter): The sample-to-sample variation in aperture delay.
Clock Pulse Width (duty cycle): The duty cycle of a clock signal is the ratio of the time that the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate, unless otherwise noted.
Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a
least-squares curve fit of that transfer function, measured in units of LSBs.
Gain Error: Gain error is the deviation of the actual ADC input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as
EGREF and EGCHAN, respectively. To a first-order approximation, the total gain error is (ETOTAL ~ EGREF + EGCHAN).
For example, if ETOTAL = ±0.5%, then the full-scale input varies from [(1 – 0.5 / 100) × FSIDEAL] to [(1 + 0.5 / 100)
× FSIDEAL].
Offset Error: Offset error is the difference, given in number of LSBs, between the actual average ADC idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. Drift is calculated by dividing the maximum
deviation of the parameter across the TMIN to TMAX range by the difference of TMAX – TMIN.
Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first nine harmonics. SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power
of the fundamental is extrapolated to the converter full-scale range.
PS
SNR = 10 Log10
PN
(9)
Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components, including noise (PN) and distortion (PD), but excluding dc. SINAD is either
given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or
dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
PS
SINAD = 10 Log10
PN + PD
(10)
Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(11)
Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first
nine harmonics (PD). THD is typically given in units of dBc (dB to carrier).
PS
THD = 10 Log10
PN
(12)
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Spurious-Free Dynamic Range (SFDR): SFDR is the ratio of power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies
f1 and f2) to the power of the worst spectral component at either frequency 2 f1 – f2 or 2 f2 – f1. IMD3 is either
given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or
dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply
voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC
output code (referred to the input), then:
DVOUT
(Expressed in dBc)
PSRR = 20 Log10
DVSUP
(13)
Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This recovery is tested by separately applying a sine-wave signal with 6-dB
positive and negative overload. The deviation of the first few samples after the overload (from the expected
values) is noted.
Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
(Expressed in dBc)
CMRR = 20 Log10
DVCM
(14)
CROSSTALK: (only for multichannel ADCs) Crosstalk is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from a channel across the package (far-channel). Crosstalk
is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of
the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. Crosstalk is typically expressed in dBc.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
ADS5296RGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5296
ADS5296RGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5296
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS5296RGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS5296RGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5296RGCR
VQFN
RGC
64
2000
336.6
336.6
28.6
ADS5296RGCT
VQFN
RGC
64
250
336.6
336.6
28.6
Pack Materials-Page 2
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