ADS5424-EP
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SGLS331C – JUNE 2006 – REVISED OCTOBER 2006
14-Bit 105-MSPS Analog-to-Digital Converter
FEATURES
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly
– Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
14-Bit Resolution
105-MSPS Maximum Sample Rate
SNR = 74 dBc at 105 MSPS and 50-MHz IF
SFDR = 93 dBc at 105 MSPS and 50-MHz IF
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
•
•
•
•
•
•
•
•
•
2.2-VPP Differential Input Range
5-V Supply Operation
3.3-V CMOS-Compatible Outputs
1.9-W Total Power Dissipation
2s-Complement Output Format
On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
52-Pin PowerPAD™ Thermally-Enhanced
Thin Quad Flat Pack (HTQFP) With Exposed
Heatsink
Pin Compatible to the AD6644/45
Military Temperature Range –55°C to 125°C
APPLICATIONS
•
•
•
•
Single and Multichannel Digital Receivers
Base Station Infrastructure
Instrumentation
Video and Imaging Related Devices
RELATED DEVICES
•
•
Clocking: CDC7005
Amplifiers: OPA695, THS4509
DESCRIPTION
The ADS5424 is a 14-bit 105-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, while
providing 3.3-V CMOS-compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the
on-chip track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided
to further simplify the system design. The ADS5424 has outstanding low noise and linearity over input
frequency. With only a 2.2-VPP input range, simplifies the design of multicarrier applications, where the carriers
are selected on the digital domain.
The ADS5424 is available in a 52-pin thermally-enhanced thin quad flat pack (HTQFP) with heatsink and is pin
compatible to the AD6645. The ADS5424 is built on state-of-the-art Texas Instruments complementary bipolar
process (BiCom3) and is specified over the full military temperature range (–55°C to 125°C).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
ADS5424-EP
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SGLS331C – JUNE 2006 – REVISED OCTOBER 2006
FUNCTIONAL BLOCK DIAGRAM
AVDD
AIN
AIN
TH1
A1
+
TH2
Σ
A2
+
TH3
ADC1
A3
ADC3
−
−
VREF
Σ
DRVDD
DAC1
ADC2
DAC2
Reference
5
5
6
C1
C2
Digital Error Correction
CLK+
CLK−
Timing
DMID OVR
DRY
GND
D[13:0]
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5424
HTQFP-52 (1)
PowerPAD™
PJY
–55°C to 125°C
ADS5424MEP
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS5424MPJYREP
Tape and reel, 1000
ADS5424MPJYEP
Tray, 160
Thermal pad size: Octagonal 2,5 mm side
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
ADS5424
Supply voltage
AVDD to GND
6
DRVDD to GND
5
UNIT
V
Analog input to GND
–0.3 V to AVDD + 0.3
V
Clock input to GND
–0.3 V to AVDD + 0.3
V
±2.5
V
–0.3 V to DRVDD + 0.3
V
–55 to 125
°C
150
°C
–65 to 150
°C
CLK to CLK
Digital data output to GND
Operating free-air temperature range
Maximum junction temperature
Storage temperature range
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Thermal Characteristics (1)
PARAMETER
θJA
θJC
(1)
2
TEST CONDITIONS
TYP
Soldered slug, no airflow
22.5
Soldered slug, 200-LFPM airflow
15.8
Unsoldered slug, no airflow
33.3
Unsoldered slug, 200-LFPM airflow
25.9
Bottom of package (heatslug)
Using 25 thermal vias (5 × 5 array). See the Application Section.
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2
UNIT
°C/W
°C/W
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SGLS331C – JUNE 2006 – REVISED OCTOBER 2006
Recommended Operating Conditions
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
3
3.3
3.6
V
Supply Voltage
AVDD
Analog supply voltage
DRVDD
Output driver supply voltage
Analog Input
VCM
Differential input range
2.2
VPP
Input common mode voltage
2.4
V
10
pF
Digital Output
Maximum output load
Clock Input
ADCLK input sample rate (sine wave) 1/tC
Clock amplitude, sine wave,
30
differential (1)
3
Clock duty cycle (2)
(1)
(2)
MSPS
VPP
50%
Operating free-air temperature
–55
125
°C
See Figure 23 and Figure 24 for more information.
See Figure 22 for more information.
10000
1000
Wirebond Voiding Fail Mode
Years Estimated Life
TA
105
100
10
Electromigration Fail Mode
1
0.1
80
90
100
110
120
130
140
150
160
170
180
Continuous TJ − 5C
Figure 1. ADS5424MPJYEP Operating Life Derating Chart
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Electrical Characteristics
over full operating temperature range (TMIN = –55°C to TMAX = 125°C), sampling rate = 105 MSPS, 50% clock duty cycle,
AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential sinusoidal clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
14
Bits
2.2
VPP
kΩ
Analog Inputs
Differential input range
Differential input resistance
See Figure 33
1
Differential input capacitance
See Figure 33
1.5
pF
570
MHz
2.4
V
Analog input bandwidth
Internal Reference Voltages
VREF
Reference voltage
Dynamic Accuracy
No missing codes
Tested
DNL
Differential linearity error
fIN = 10 MHz
INL
Integral linearity error
fIN = 10 MHz
–1
±0.5
1.5
LSB
0.33
%FS
±1.5
Offset error
–0.33
Offset temperature coefficient
0
LSB
1.7
Gain error
–5
PSRR
Gain temperature coefficient
0.9
ppm/°C
5
%FS
1
mV/V
77
ppm/°C
Power Supply
IAVDD
Analog supply current
VIN = full scale,
fIN = 70 MHz
FS = 92.16 MSPS
355
FS = 105 MSPS
355
IDRVDD
Output buffer supply current
VIN = full scale,
fIN = 70 MHz
FS = 92.16 MSPS
38
FS = 105 MSPS
40
FS = 92.16 MSPS
1.9
Power dissipation
Total power with 10-pF load
on each digital output to
ground,
fIN = 70 MHz
FS = 105 MSPS
1.9
Power-up time
FS = 105 MSPS
20
410
47
2.2
mA
mA
W
ms
Dynamic AC Characteristics
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
SNR
Signal-to-noise ratio
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
4
FS = 92.16 MSPS
74.5
FS = 105 MSPS
74.4
FS = 92.16 MSPS
FS = 105 MSPS
74.4
73
74.3
FS = 92.16 MSPS
74.2
FS = 105 MSPS
74.2
FS = 92.16 MSPS
FS = 105 MSPS
74
72
74
FS = 92.16 MSPS
73.5
FS = 105 MSPS
73.5
FS = 92.16 MSPS
72
FS = 105 MSPS
72
FS = 92.16 MSPS
71.5
FS = 105 MSPS
71.5
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dBc
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SGLS331C – JUNE 2006 – REVISED OCTOBER 2006
Electrical Characteristics (continued)
over full operating temperature range (TMIN = –55°C to TMAX = 125°C), sampling rate = 105 MSPS, 50% clock duty cycle,
AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential sinusoidal clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
SFDR
Spurious-free dynamic range
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
SINAD
Signal-to-noise + distortion
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
HD2
HD3
Second harmonic
Third harmonic
MIN
TYP
FS = 92.16 MSPS
94
FS = 105 MSPS
93
FS = 92.16 MSPS
FS = 105 MSPS
95
94
FS = 105 MSPS
93
FS = 92.16 MSPS
89
FS = 105 MSPS
88
FS = 92.16 MSPS
88
FS = 105 MSPS
87
FS = 92.16 MSPS
73
FS = 105 MSPS
73
FS = 92.16 MSPS
64
FS = 105 MSPS
74.4
FS = 105 MSPS
74.3
FS = 92.16 MSPS
74.3
71.7
74.3
74.1
FS = 105 MSPS
74
FS = 92.16 MSPS
74
FS = 105 MSPS
73.9
FS = 92.16 MSPS
73.3
FS = 105 MSPS
73.3
FS = 92.16 MSPS
69.3
FS = 105 MSPS
69.1
FS = 92.16 MSPS
63.4
FS = 105 MSPS
63.4
fIN = 10 MHz
100
fIN = 30 MHz
105
fIN = 50 MHz
98
fIN = 70 MHz
98
fIN = 100 MHz
98
fIN = 170 MHz
98
fIN = 230 MHz
96
fIN = 10 MHz
93
fIN = 30 MHz
95
fIN = 50 MHz
93
fIN = 100 MHz
87
fIN = 170 MHz
73
fIN = 230 MHz
64
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dBc
64
FS = 92.16 MSPS
FS = 92.16 MSPS
UNIT
95
83
FS = 92.16 MSPS
FS = 105 MSPS
MAX
dBc
dBc
dBc
5
ADS5424-EP
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SGLS331C – JUNE 2006 – REVISED OCTOBER 2006
Electrical Characteristics (continued)
over full operating temperature range (TMIN = –55°C to TMAX = 125°C), sampling rate = 105 MSPS, 50% clock duty cycle,
AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential sinusoidal clock (unless otherwise noted)
PARAMETER
Worst harmonic/spur
(other than HD2 and HD3)
RMS idle channel noise
TEST CONDITIONS
MIN
TYP
fIN = 10 MHz
93
fIN = 30 MHz
95
fIN = 50 MHz
93
fIN = 70 MHz
88
fIN = 100 MHz
88
fIN = 170 MHz
88
fIN = 230 MHz
88
Input pins tied together
0.9
MAX
UNIT
dBc
LSB
Digital Characteristics
over full operating temperature range (TMIN = –55°C to TMAX = 125°C), AVDD = 5 V, DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.1
0.6
UNIT
Digital Outputs
Low-level output voltage
CLOAD = 10 pF (1)
High-level output voltage
CLOAD = 10 pF (1)
Output capacitance
DMID
(1)
6
Equivalent capacitance to ground of (load + parasitics of transmission lines)
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2.6
V
3.2
V
3
pF
DRVDD/2
V
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SGLS331C – JUNE 2006 – REVISED OCTOBER 2006
Timing Characteristics
(1)
over full operating temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Aperture Time
tA
Aperture delay
500
ps
tJ
Clock slope independent aperture uncertainty (jitter)
150
fs
kJ
Clock slope dependent jitter factor
50
µV
Clock Input
tCLK
Clock period
9.5
ns
tCLKH (2)
Clock pulse width high
4.75
ns
tCLKL (2)
Clock pulse width low
4.75
ns
Clock to DataReady (DRY)
tDR
Clock rising 50% to DRY falling 50%
tC_DR
Clock rising 50% to DRY rising 50%
tC_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
Clock to DATA,
OVR (3)
tr
Data VOL to data VOH (rise time)
2
ns
tf
Data VOH to data VOL (fall time)
2
ns
L
Latency
3
Cycles
tSU(C)
Valid DATA (4) to clock 50% with 50% duty cycle clock (setup time)
1.8
3.4
ns
tH(C)
Clock 50% to invalid DATA (4) (hold time)
2.6
3.6
ns
DataReady (DRY)/DATA,
2.8
3.9
4.7
tDR + tCLKH
7.6
8.7
ns
ns
9.5
ns
OVR (3)
tsu(DR)_50%
Valid DATA (4) to DRY 50% with 50% duty cycle clock (setup time)
1.8
2.6
ns
th(DR)_50%
DRY 50% to invalid DATA (4) with 50% duty cycle clock (hold time)
3.9
4.4
ns
(1)
(2)
(3)
(4)
All values are obtained from design and characterization and are not production tested.
See Figure 22 for more information.
Data is updated with clock rising edge or DRY falling edge.
See VOH and VOL levels.
tA
N+3
N
AIN
N+1
N+2
tCLKH
tCLK
CLK, CLK
N+1
N
N+4
tCLKL
N+2
N+3
tC_DR
D[13:0], OVR
DRY
N−3
tr
N−2
tf
tsu(C)
N−1
tsu(DR)
N+4
th(C)
N
th(DR)
tDR
Figure 2. Timing Diagram
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PIN CONFIGURATION
DRY
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
DRVCC
GND
D5
D4
PJY PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
DRVDD
GND
VREF
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
1
39
2
3
38
37
4
36
5
6
35
34
7
33
GND
8
9
32
31
10
30
11
12
29
28
13
27
D3
D2
D1
D0 (LSB)
DMID
GND
DRVDD
OVR
DNC
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
C1
GND
AVDD
GND
C2
GND
AVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN ASSIGNMENTS
TERMINAL
NAME
DRVDD
GND
1, 33, 43
3.3 V power supply, digital output stage only
2, 4, 7, 10, 13, 15, 17, 19, 21,
Ground
23, 25, 27, 29, 34, 42
VREF
3
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
CLK
5
Clock input. Conversion initiated on rising edge
CLK
6
Complement of CLK, differential input
AVDD
8, 9, 14, 16, 18, 22, 26, 28, 30 5-V analog power supply
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
C2
24
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
DNC
31
Do not connect
OVR
32
Overrange bit. A logic-level high indicates the analog input exceeds full scale.
DMID
35
Output data voltage midpoint. Approximately equal to (DVCC)/2
D0 (LSB)
36
Digital output bit (least significant bit); twos complement
D1–D5, D6–D12
8
DESCRIPTION
NO.
37–41, 44–50
Digital output bits in twos complement
D13 (MSB)
51
Digital output bit (most significant bit); twos complement
DRY
52
Data ready output
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB, with respect
to the low frequency value
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which
the sampling occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high
(clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified operation is given. All parametric testing is
performed at this sampling rate, unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC functions
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly one LSB apart. The
DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL)
The INL is the deviation of the ADC transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of LSB.
Gain Error
The gain error is the deviation of the ADC actual input full-scale range from its ideal value. The
gain error is given as a percentage of the ideal input full-scale range.
Offset Error
The offset error is the difference, given in number of LSBs, between the ADC actual value average
idle channel output code and the ideal average idle channel output code. This quantity is often
mapped into mV
Power-Supply Rejection Ration (PSRR)
The maximum change in offset voltage divided by the total change in supply voltage, in units of
mV/V
Power-Up Time
The difference in time from the point where the supplies are stable at ±5% of the final value, to the
time the ac test is past
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the
power at dc and the first five harmonics.
SNR + 10Log 10
PS
PN
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is
used as the reference, or dBFS (dB to full scale) when the power of the fundamental is
extrapolated to the converter's full-scale range.
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DEFINITION OF SPECIFICATIONS (continued)
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral
components including noise (PN) and distortion (PD), but excluding dc.
SINAD + 10Log 10
PS
PN ) PD
SINAD is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is
used as the reference, or dBFS (dB to full scale) when the power of the fundamental is
extrapolated to the converter's full-scale range.
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB to carrier).
Temperature Drift
The temperature drift coefficient (with respect to gain error and offset error) specifies the change
per degree Celsius of the parameter from TMIN or TMAX. It is computed as the maximum variation of
that parameter over the whole temperature range divided by TMAX – TMIN.
Total Harmonic Distortion (THD)
THD is the ratio of the fundamental power (PS) to the power of the first five harmonics (PD).
THD + 10Log 10
PS
PD
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst
spectral component at either frequency (2f1 – f2 or 2f2 – f1). IMD3 is either given in units of dBc (dB
to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to
full scale) when it is referred to the full-scale range.
10
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TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3-V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3-VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted).
SPECTRAL PERFORMANCE
1
0
fS = 105 MSPS
fIN = 2 MHz
SNR = 74.4 dBc
SINAD = 74.4 dBc
SFDR = 93 dBc
THD = 95 dBc
--40
--60
--80
--40
--60
--80
X
5
--100
6
2
X 5
3
3
--100
fS = 105 MSPS
fIN = 30 MHz
SNR = 74.4 dBc
SINAD = 74.3 dBc
SFDR = 94 dBc
THD = 93 dBc
--20
Amplitude -- dBFS
--20
Amplitude -- dBFS
SPECTRAL PERFORMANCE
1
0
4
--120
--120
0
10
20
30
40
50
0
10
20
f -- Frequency -- MHz
SPECTRAL PERFORMANCE
fS = 105 MSPS
fIN = 100 MHz
SNR = 73.5 dBc
SINAD = 73.3 dBc
SFDR = 87 dBc
THD = 86 dBc
Amplitude -- dBFS
--20
--60
--80
--100
1
0
fS = 105 MSPS
fIN = 70 MHz
SNR = 74 dBc
SINAD = 73.9 dBc
SFDR = 92 dBc
THD = 91 dBc
3
X
50
SPECTRAL PERFORMANCE
1
--40
40
Figure 4.
0
--20
30
f -- Frequency -- MHz
Figure 3.
Amplitude -- dBFS
2
6
4
--60
--80
3
X
5
2
--100
5
6
--40
4
2
6
--120
--120
0
10
20
30
40
50
0
10
20
f -- Frequency -- MHz
Figure 5.
Amplitude -- dBFS
Amplitude -- dBFS
fS = 105 MSPS
fIN = 230 MHz
SNR = 71 dBc
SINAD = 64.2 dBc
SFDR = 65 dBc
THD = 65 dBc
--20
--60
3
X
--80
5
--100
1
0
fS = 105 MSPS
fIN = 170 MHz
SNR = 71.9 dBc
SINAD = 69.1 dBc
SFDR = 72 dBc
THD = 72 dBc
--40
2
50
SPECTRAL PERFORMANCE
1
--20
40
Figure 6.
SPECTRAL PERFORMANCE
0
30
f -- Frequency -- MHz
--40
--60
3
--80
5
4
6
--120
X
4
--100
2
6
--120
0
10
20
30
40
50
0
f -- Frequency -- MHz
10
20
30
40
50
f -- Frequency -- MHz
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3-V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3-VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted).
SPECTRAL PERFORMANCE
--60
--80
--40
--60
3
--80
X
--100
2
6
--120
5
6
--120
0
10
20
30
40
0
10
f -- Frequency -- MHz
SPECTRAL PERFORMANCE
40
SPECTRAL PERFORMANCE
0
fS = 92.16 MSPS
fIN1 = 69.2 MHz, --7 dBFS
fIN2 = 70.7 MHz, --7 dBFS
IMD3 = --93 dBFS
--40
fS = 92.16 MSPS
fIN1 = 169.6 MHz, --7 dBFS
fIN2 = 170.4 MHz, --7 dBFS
IMD3 = --82 dBFS
--20
Amplitude -- dBFS
--20
Amplitude -- dBFS
30
Figure 10.
0
--60
--80
--100
--120
--40
--60
--80
--100
--120
--140
--140
0
10
20
30
40
0
10
f -- Frequency -- MHz
20
30
40
f -- Frequency -- MHz
Figure 11.
Figure 12.
WCDMA CARRIER
WCDMA CARRIER
0
0
fS = 92.16 MSPS
fIN = 70 MHz
PAR = 5 dB
ACPR Adj Top = 79.2 dB
ACPR Adj Low = 79.7 dB
−40
fS = 92.16 MSPS
fIN = 170 MHz
PAR = 5 dB
ACPR Adj Top = 73.3 dB
ACPR Adj Low = 74 dB
−20
Amplitude − dBFS
−20
Amplitude − dBFS
20
f -- Frequency -- MHz
Figure 9.
−60
−80
−100
−40
−60
−80
−100
−120
−120
−140
−140
0
10
20
30
40
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
Figure 13.
12
4
2
X
5
4
--100
fS = 92.16 MSPS
fIN = 170 MHz
SNR = 71.6 dBc
SINAD = 69 dBc
SFDR = 73 dBc
THD = 73 dBc
--20
Amplitude -- dBFS
--40
1
0
fS = 92.16 MSPS
fIN = 70 MHz
SNR = 73.9 dBc
SINAD = 73.8 dBc
SFDR = 96 dBc
THD = 95 dBc
--20
Amplitude -- dBFS
SPECTRAL PERFORMANCE
1
0
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3-V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3-VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted).
AC PERFORMANCE
vs
INPUT AMPLITUDE
AC PERFORMANCE
vs
INPUT AMPLITUDE
120
120
100
SFDR (dBFS)
AC Performance − dB
AC Performance − dB
100
80
SNR (dBFS)
60
SFDR (dBc)
40
20
SNR (dBc)
0
fS = 92.16 MSPS
fIN = 70 MHz
−80
−70
−60
−50
−40
−30
−20
−10
SNR (dBFS)
60
SFDR (dBc)
40
20
SNR (dBc)
fS = 92.16 MSPS
fIN = 170 MHz
0
−20
−90
0
−80
−70
−60
−50
−40
−30
−20
AIN − Input Amplitude − dB
AIN − Input Amplitude − dBFS
Figure 15.
Figure 16.
−10
0
NOISE HISTOGRAM WITH INPUTS SHORTED
TWO-TONE SPURIOUS-FREE DYNAMIC RANGE
vs
INPUT AMPLITUDE
40
35
120
30
100
Percentage − %
SFDR − Two-Tone Spurious-Free Dynamic Range − dB
−20
−90
SFDR (dBFS)
80
SFDR (dBFS)
80
60
40
25
20
15
10
SFDR (dBc)
5
20
90 dBFS Line
0
fIN1 = 69 MHz
fIN2 = 71 MHz
fS = 92.16 MSPS
−20
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
8174
8175
8176
8177
8178
8179
Code Number
0
AIN − Input Amplitude − dBFS
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3-V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3-VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted).
INPUT BANDWIDTH
TOTAL POWER
vs
SAMPLING FREQUENCY
2
1.90
0
PT − Total Power − W
Power Output − dB
fIN= 70 MHz
1.89
1.88
1.87
1.86
1.85
1.84
−2
−4
−6
−8
fS = 105 MSPS
AIN = −1 dBFS
1.83
−10
1.82
1
10
1.81
0
20
40
60
80
100
120
100
1k
f − Frequency − MHz
140
fS − Sampling Frequency − MSPS
Figure 20.
AC PERFORMANCE
vs
CLOCK COMMON MODE
100
fS = 105 MSPS
fIN = 69.6 MHz
AC Performance − dB
95
SFDR (dBc)
90
85
80
SNR (dBc)
75
70
65
60
0
14
1
2
3
4
5
SFDR − Spurious-Free Dynamic Range − dBc
Figure 19.
SPURIOUS-FREE DYNAMIC RANGE
vs
DUTY CYCLE
100
fIN = 2 MHz
95
90
85
fIN = 50 MHz
80
fIN = 70 MHz
75
70
65
40
45
50
Clock Common Mode − V
Duty Cycle − %
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3-V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3-VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted).
AC PERFORMANCE
vs
CLOCK LEVEL
AC PERFORMANCE
vs
CLOCK LEVEL
95
75
SFDR (dBc)
SFDR (dBc)
85
70
AC Performance − dB
AC Performance − dB
90
80
75
70
SNR (dBc)
65
60
fS = 105 MSPS
fIN = 70 MHz
55
50
0
1
2
3
SNR (dBc)
65
60
55
fS = 105 MSPS
fIN = 170 MHz
50
4
0
1
Differential Clock Level − VPP
2
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
94
74.8
fS = 105 MSPS
fIN = 69.6 MHz
100°C
SNR − Signal-to-Noise Ratio − dBc
93
92
91
60°C
85°C
−20°C
90
89
88
87
86
20°C
−40°C
2.8
3.0
3.2
3.4
3.6
74.6
3.8
fS = 105 MSPS
fIN = 69.6 MHz
−40°C
74.4
−20°C
74.2
20°C
74.0
73.8
60°C
73.6
85°C
73.4
100°C
73.2
73.0
2.6
2.8
3.0
3.2
3.4
3.6
DRVDD − Supply Voltage − V
DRVDD − Supply Voltage − V
Figure 25.
Figure 26.
SPURIOUS-FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
3.8
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
74.6
91.0
90.5
fS = 105 MSPS
fIN = 69.6 MHz
60°C
SNR − Signal-to-Noise Ratio − dBc
SFDR − Spurious-Free Dynamic Range − dBc
SFDR − Spurious-Free Dynamic Range − dBc
Figure 24.
SPURIOUS-FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
90.0
89.5
−20°C
85°C
89.0
88.5
88.0
87.5
87.0
20°C
86.5
86.0
4.6
4
Differential Clock Level − VPP
Figure 23.
85
2.6
3
−40°C
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
fS = 105 MSPS
fIN = 69.6 MHz
74.4
−40°C
74.2
0°C
74.0
40°C
73.8
73.6
73.4
60°C
100°C
85°C
73.2
73.0
4.6
4.8
5.0
5.2
AVDD − Supply Voltage − V
AVDD − Supply Voltage − V
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3-V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3-VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted).
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
1.5
0.8
INL − Integral Nonlinearity − LSB
DNL − Differential Nonlinearity − LSB
1.0
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
1.0
0.5
0.0
−0.5
−1.0
−1.5
−1.0
0
5000
10000
0
15000
5000
10000
15000
Code
Code
Figure 29.
Figure 30.
73
120
71
74
fS − Sampling Frequency − MHz
110
74
100
72
90
73
71
80
70
74
72
73
70
60
71
74
69
50
72
74
40
73
69
71
70
30
72
20
73
71
70
10
0
20
40
60
68
70
68
69
80
100
67
120
68
69
66
64
65
140
160
180
67
64
66
68
SNR − dBc
Figure 31.
16
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72
65
62
63
200
fIN − Input Frequency − MHz
62
66
74
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3-V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3-VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted).
120
88
91
76
88
110
fS − Sampling Frequency − MHz
79
82
85
91
94
100
73
67
79
85
91
90
94
91
94
80
94
94
94
70
73
76
70
67
88
82
94
85
94
60
64
70
82
85
79
91
94
94
94
94
91
94
91
85
82
79
94
91
40
60
64
80
100
120
140
61
70
73
76
85
10
20
67
70
91
94
20
0
73
94
40
30
76
88
50
160
180
200
220
fIN − Input Frequency − MHz
60
65
70
75
80
85
90
SFDR − dBc
Figure 32.
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EQUIVALENT CIRCUITS
DRVDD
AVDD
AIN
BUF
T/H
500 Ω
BUF
VREF
AVDD
500 Ω
AIN
BUF
T/H
Figure 33. Analog Input
Figure 34. Digital Output
AVDD
AVDD
+
CLK
Bandgap
1 kΩ
Clock Buffer
25 Ω
−
1.2 kΩ
1.2 kΩ
Bandgap
AVDD
1 kΩ
CLK
Figure 35. Clock Input
18
Figure 36. Reference
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EQUIVALENT CIRCUITS (continued)
AVDD
DRVDD
10 kΩ
−
DAC
Bandgap
+
IOUTP
DMID
IOUTM
C1, C2
10 kΩ
Figure 37. Decoupling Pin
Figure 38. DMID Generation
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APPLICATION INFORMATION
Theory of Operation
The ADS5424 is a 14-bit, 105-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from a 5-V
supply, while the output uses 3.3-V supply for compatibility with the CMOS family. The conversion process is
initiated by the rising edge of the external input clock. At that instant, the differential input signal is captured by
the input track and hold (T&H) and the input sample is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline every half clock cycle. This process results in a data
latency of three clock cycles, after which the output data is available as a 14-bit parallel word, coded in binary
twos-complement format.
Input Configuration
The analog input for the ADS5424 (see Figure 33) consists of an analog differential buffer followed by a bipolar
T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching. The input
common mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs. This results
in a differential input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings
symmetrically between 2.4 + 0.55 V and 2.4 – 0.55 V. This means that each input is driven with a signal of up to
2.4 ± 0.55 V, so that each input has a maximum signal swing of 1.1 VPP for a total differential input signal swing
of 2.2 VPP. The maximum swing is determined by the internal reference voltage generator eliminating any
external circuitry for this purpose.
The ADS5424 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 39 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. If voltage gain is required, a step-up transformer can be used. For higher
gains that would require impractical higher turn ratios on the transformer, a single-ended amplifier driving the
transformer can be used (see Figure 40). Another circuit optimized for performance is the one shown in
Figure 41, using the THS4304 or the OPA695. TI has shown excellent performance on this configuration up to
10-dB gain with the THS4304, and at 14-dB gain with the OPA695. For the best performance, they need to be
configured differentially after the transformer (as shown) or in inverting mode for the OPA695 (see SBAA113);
otherwise, HD2 from the operational amplifiers limits the useful frequency.
R0
50W
Z0
50W
AIN
1:1
R
50W
AC Signal
Source
ADS5424
AIN
ADT1−1WT
Figure 39. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
5V
VIN
−5 V
RS
100 Ω
+
OPA695
−
0.1 µF
1000 µF
RIN
1:1
RT
100 Ω
RIN
R1
400 Ω
R2
57.5 Ω
AV = 8V/V
(18 dB)
Figure 40. Using the OPA695 With the ADS5424
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APPLICATION INFORMATION (continued)
RG
RF
CM
5V
−
THS4304
+
1:1
VIN
49.9 Ω
CM
AIN
ADS5424
VREF
AIN
5V
From
50 Ω
Source
+
THS4304
−
RG
CM
RF
CM
Figure 41. Using the THS4304 With the ADS5424
Besides these, TI offers a wide selection of single-ended operational amplifiers (including the THS3201,
THS3202, and OPA847) that can be selected, depending on the application. An RF gain block amplifier, such as
the TI THS9001, can also be used with an RF transformer for high input frequency applications. For applications
requiring dc coupling with the signal source, instead of using a topology with three single-ended amplifiers, a
differential input/differential output amplifier, such as the THS4509 (see Figure 42), can be used, which
minimizes board space and reduce number of components.
Figure 43 shows their combined SNR and SFDR performance versus frequency, with –1-dBFS input signal level
and sampling at 80 MSPS.
VI
From
50 Ω
Source
100 Ω
69.8 W
348 Ω
+5V
225 Ω
0.22 mF
100 Ω
THS 4509
2.7 pF
225 Ω
CM
49.9 Ω
0.22 mF
69.8 Ω
14-Bit
105
AIN
MSPS
ADS5424
AIN VREF
49.9 Ω
0.22 mF
0.1mF
0.1mF
348 Ω
Figure 42. Using the THS4509 With the ADS5424
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APPLICATION INFORMATION (continued)
95
Performance -- dB
90
SFDR (dBc)
85
80
SNR (dBFS)
75
70
10
20
30
40
50
60
70
fIN -- Input Frequency -- MHz
Figure 43. Performance vs Input Frequency for the THS4509 + ADS5424 Configuration
On this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5424.
The 225-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5424 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz (–3 dB).
For this test, an Agilent signal generator is used for the signal source. The generator is an ac-coupled 50-Ω
source. A band-pass filter is inserted in series with the input to reduce harmonics and noise from the signal
source.
Input termination is accomplished via the 69.8-Ω resistor and 0.22-µF capacitor to ground, in conjunction with
the input impedance of the amplifier circuit. A 0.22-µF capacitor and 49.9-Ω resistor is inserted to ground across
the 69.8-Ω resistor and 0.22-µF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. See the THS4509 data
sheet for further component values to set proper 50-Ω termination for other common gains.
Since the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single
power-supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the internal
transistors of the THS4509.
Clock Inputs
The ADS5424 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low input frequency applications, where
jitter may not be a big concern, the use of single-ended clock (see Figure 44) could save some cost and board
space without any trade-off in performance. When driven on this configuration, it is best to connect CLKM
(pin 11) to ground with a 0.01-µF capacitor, while CLKP is ac coupled with a 0.01-µF capacitor to the clock
source (see Figure 45).
Square Wave or
Sine Wave
CLK
0.01 µF
ADS5424
CLK
0.01 µF
Figure 44. Single-Ended Clock
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APPLICATION INFORMATION (continued)
0.1 µF
Clock
Source
1:4
CLK
MA3X71600LCT−ND
ADS5424
CLK
Figure 45. Differential Clock
Nevertheless, for jitter-sensitive applications, the use of a differential clock has some advantages (as with any
other ADCs) at the system level. The first advantage is that it allows for common-mode noise rejection at the
PCB level. A further analysis (see Clocking High Speed Data Converters, literature number SLYT075) reveals
one more advantage. The following formula describes the different contributions to clock jitter:
(Jittertotal)2 = (EXT_jitter)2 + (ADC_jitter)2 = (EXT_jitter)2 + (ADC_int)2 + (K/clock_slope)2
The first term would represent the external jitter coming from the clock source, plus noise added by the system
on the clock distribution, up to the ADC. The second term is the ADC contribution, which can be divided in two
portions. The first does not depend directly on any external factor. The second contribution is a term inversely
proportional to the clock slope. The faster the slope, the smaller this term will be. For example, compute the
ADC jitter contribution from a sinusoidal input clock of 3-VPP amplitude and FS = 80 MSPS:
ADC_jitter = sqrt ((150 fs)2 + (5 × 10–5/(1.5 × 2 × PI × 80 × 106))2) = 164 fs
The use of differential clock allows for the use of bigger clock amplitudes without exceeding the absolute
maximum ratings. This, in the case of sinusoidal clock, results in higher slew rates that minimize the impact of
the jitter factor inversely proportional to the clock slope.
Figure 46 shows this approach. The back-to-back Schottky can be added to limit the clock amplitude in cases
where this would exceed the absolute maximum ratings, even when using a differential clock. Figure 23 and
Figure 24 show the performance versus input clock amplitude for a sinusoidal clock.
100 nF
MC100EP16DT
100 nF
D
D
CLK
Q
VBB Q
499 W
100 nF
100 nF
ADS5424
CLK
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 46. Differential Clock Using PECL Logic
Another possibility is the use of a logic-based clock as PECL. In this case, the slew rate of the edges most likely
are much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This solution
minimizes the effect of the slope-dependent ADC jitter. Nevertheless, observe that for the ADS5424, this term is
small and has been optimized. Using logic gates to square a sinusoidal clock may not produce the best results,
as logic gates may not have been optimized to act as comparators, adding too much jitter while squaring the
inputs.
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APPLICATION INFORMATION (continued)
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use an ac coupling, but if for any reason this scheme is not possible due to, for instance,
asynchronous clocking, the ADS5424 presents a good tolerance to clock common-mode variation (see
Figure 21).
Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that,
ideally, a 50% duty cycle should be provided. Figure 22 shows the performance variation of the ADC versus
clock duty cycle.
Digital Outputs
The ADC provides 14 data outputs (D13–D0, with D13 being the MSB and D0 the LSB), a data-ready signal
(DRY, pin 52), and an out-of-range indicator (OVR, pin 32) that equals 1 when the output reaches the full-scale
limits.
The output format is twos complement. When the input voltage is at negative full scale (around –1.1-V
differential), the output is, from MSB to LSB, 10 0000 0000 0000. Then, as the input voltage is increased, the
output switches to 10 0000 0000 0001, 10 0000 0000 0010, and so on until 11 1111 1111 1111 right before
mid-scale (when both inputs are tight together if we neglect offset errors). Further increases on input voltage
outputs the word 00 0000 0000 0000, to be followed by 00 0000 0000 0001, 00 0000 0000 0010, and so on until
reaching 01 1111 1111 1111 at full-scale input (1.1-V differential).
Although the output circuitry of the ADS5424 has been designed to minimize the noise produced by the
transients of the data switching, care must be taken when designing the circuitry reading the ADS5424 outputs.
Output load capacitance should be minimized by minimizing the load on the output traces, reducing their length
and the number of gates connected to them, and by the use of a series resistor with each pin. Typical numbers
on the data-sheet tables and graphs are obtained with 100-Ω series resistor on each digital output pin, followed
by an SN74AVC16244 digital buffer like the one used in the evaluation board.
Power Supplies
The use of low-noise power supplies with adequate decoupling is recommended, being the linear supplies the
first choice versus switched ones, which tend to generate more noise components that can be coupled to the
ADS5424.
The ADS5424 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for the
digital outputs supply (DRVDD), the use of 3.3 V is recommended. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied together inside the package. Customers willing to experiment
with different grounding schemes should know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and
29, while DRGND pins are 2, 34, and 42. Nevertheless, it is recommended that both grounds are tied together
externally, using a common ground plane. That is the case on the production test boards and modules provided
to customer for evaluation. In order to obtain the best performance, the user should layout the board to ensure
that the digital return currents do not flow under the analog portion of the board. This can be achieved without
the need to split the board and just with careful component placing and increasing the number of vias and
ground planes.
Finally, notice that the metallic heatsink under the package is also connected to analog ground.
Layout Information
The evaluation board represents a good guideline of how to layout the board to obtain maximum performance
from the ADS5424. General design rules, such as the use of multilayer boards, single ground plane for both
analog and digital ADC ground connections, and local decoupling ceramic chip capacitors should be applied.
The input traces should be isolated from any external source of interference or noise, including the digital
outputs as well as the clock traces. Clock should also be isolated from other signals, particularly on applications
where low jitter is required, as high IF sampling.
Besides performance-oriented rules, special care must be taken when considering the heat dissipation out of the
device. The thermal heatsink (octagonal, with 2,5 mm on each side) should be soldered to the board, and
provision for more than 16 ground vias should be made. The thermal package information describes the TJA
values obtained on the different configurations.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
ADS5424MPJYEP
ACTIVE
QFP
PJY
52
TBD
Call TI
Call TI
ADS5424MPJYREP
ACTIVE
QFP
PJY
52
TBD
Call TI
Call TI
V62/06647-01XE
ACTIVE
QFP
PJY
52
TBD
Call TI
Call TI
V62/06647-02XE
ACTIVE
QFP
PJY
52
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5424-EP :
ADS5424
• Catalog:
• Space: ADS5424-SP
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Mar-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS5424MPJYREP
Package Package Pins
Type Drawing
QFP
PJY
52
SPQ
0
Reel
Reel
Diameter Width
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
12.3
12.3
2.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Mar-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5424MPJYREP
QFP
PJY
52
0
346.0
346.0
41.0
Pack Materials-Page 2
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