ADS5484
ADS5485
www.ti.com ............................................................................................................................................... SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009
16-Bit, 170/200-MSPS Analog-to-Digital Converters
Check for Samples: ADS5484 ADS5485
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
23
•
•
170/200-MSPS Sample Rates
16-Bit Resolution, 78 dBFS Noise Floor
SFDR = 95 dBc
On-Chip High Impedance Analog Buffer
Efficient DDR LVDS-Compatible Outputs
Power-Down Mode: 70 mW
Pin-for-Pin with ADS5483/5482/5481,
135/105/80-MSPS ADCs
QFN-64 PowerPAD™ Package
(9 mm × 9 mm footprint)
Industrial Temperature Range:
–40°C to 85°C
Wireless Infrastructure
Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Radar
Medical Imaging
DESCRIPTION
The ADS5484/ADS5485 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that operate from
both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x integrated
analog input buffer isolates the internal switching of the onboard track and hold (T & H) from disturbing the signal
source while providing a high-impedance input. An internal reference generator is provided to simplify the system
design. Internal dither is available to improve SFDR. These devices are drop-in compatible to the
ADS5483/5482/5481, creating a pin-compatible family from 80 – 200 MSPS. Designed for highest total ENOB,
the ADS548x family has outstanding low noise performance and spurious-free dynamic range.
The ADS548x family is available in a QFN-64 PowerPAD package. The devices are built on Texas Instruments
complementary bipolar process (BiCom3) and are specified over the full industrial temperature range (–40°C to
85°C).
SFDR
vs
INPUT FREQUENCY
SNR
vs
INPUT FREQUENCY
100
78
170 MSPS, Dither Enabled
90
170 MSPS, Dither Enabled
76
170 MSPS, No Dither
SNR − dBFS
SFDR − dBc
170 MSPS, No Dither
77
80
200 MSPS, Dither Enabled
70
75
74
200 MSPS, No Dither
73
72
200 MSPS, No Dither
200 MSPS, Dither Enabled
71
60
70
0
50
100
150
200
fIN − Input Frequency − MHz
250
300
G001
0
50
100
150
200
250
300
fIN − Input Frequency − MHz
G002
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
ADS5484
ADS5485
SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009 ............................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5484
QFN-64
RGC
–40°C to 85°C
AZ5484
ADS5485
(1)
2
QFN-64
RGC
–40°C to 85°C
AZ5485
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5484IRGCT
Tape and reel, 250
ADS5484IRGCR
Tape and reel, 2000
ADS5485IRGCT
Tape and reel, 250
ADS5485IRGCR
Tape and reel, 2000
For the most current product and ordering information see the Package Option Addendum located at the end of this document, or see
the TI website at www.ti.com..
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ADS5484
ADS5485
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ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage
ADS5484, ADS5485
UNIT
AVDD5 to GND
6
V
AVDD3 to GND
5
V
DVDD3 to GND
5
V
–0.3 to (AVDD5 + 0.3)
V
±4
V
–0.3 to (AVDD3 + 0.3)
V
Analog input to GND
AC signal. Valid when AVDD5 is within normal operating range. When
AVDD5 is off, analog inputs should be < 0.5 V. If not, the protection
diode between the inputs and AVDD5 becomes forward-biased and
could be damaged or shorten device lifetime (see Figure 30). Short
transient conditions during power on/off are not a concern.
Analog INP to INM
DC signal
Clock input to GND
Valid when AVDD3 is within normal operating range. When AVDD3 is
off, clock inputs should be < 0.5 V. If not, the protection diode between
the inputs and AVDD3 becomes forward-biased and could be
damaged or shorten device lifetime (see Figure 37). Short transient
conditions during power on/off are not a concern.
CLKP to CLKM
Digital data output to GND
±2.5
V
–0.3 to (DVDD3 + 0.3)
V
Digital data output plus-to-minus
Operating temperature range
Maximum junction temperature
Storage temperature range
ESD, human-body model (HBM)
(1)
±1
V
–40 to 85
°C
150
°C
–65 to 150
°C
2
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime are available upon
request.
THERMAL CHARACTERISTICS (1)
PARAMETER
RθJA
(1)
TEST CONDITIONS
TYP
Soldered thermal pad, no airflow
20
Soldered thermal pad, 150-LFM airflow
16
RθJC
Thermal resistance from the junction to the package case (top)
RθJP
Thermal resistance from the junction to the thermal pad (bottom)
7
UNIT
°C/W
0.2
Using 49 thermal vias ( 7 × 7 array). See PowerPAD Package in the Application Information section.
Copyright © 2008–2009, Texas Instruments Incorporated
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ADS5484
ADS5485
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RECOMMENDED OPERATING CONDITIONS
ADS5484, ADS5485
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD5
Analog supply voltage
4.75
5
5.25
V
AVDD3
Analog supply voltage
3.15
3.3
3.45
V
DVDD3
Output driver supply voltage
3
3.3
3.6
V
ANALOG INPUT
Differential input voltage range
VCM
3
Input common-mode voltage
VPP
3.1
V
5
pF
100
Ω
DIGITAL OUTPUT (DRY, DATA)
Maximum differential output load (parasitic or intentional)
Differential output resistance
CLOCK INPUT (CLK)
CLK input sample rate (sine wave)
10
Max
Rated
Clock
Clock amplitude, differential sine wave (see Figure 39)
1.5
5
Clock duty cycle (see Figure 44)
TA
45%
Operating free-air temperature
50%
MSPS
VPP
55%
–40
+85
°C
ELECTRICAL CHARACTERISTICS (ADS5484, ADS5485)
Typical values at TA = 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ADS5484
MIN
TYP
ADS5485
MAX
MIN
TYP
MAX
UNIT
Clock rate
170
200
MSPS
Resolution
16
16
Bits
ANALOG INPUTS
Differential input voltage range
Analog input common-mode voltage
Self-biased; see VCM
specification below
Input resistance (dc)
Each input to VCM
Input capacitance
Each input to GND (unsoldered
package)
Analog input bandwidth (–3dB)
CMRR
Common-mode rejection ratio
Common-mode signal
70 MHz (see Figure 26)
3
3
VPP
3.1
3.1
V
1000
1000
Ω
3.5
3.5
pF
730
730
MHz
65
65
dB
1.2
1.2
V
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
VCM
Analog input common-mode voltage
reference output
VCM temperature coefficient
4
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With internal voltage reference
2.9
3.1
3.3
-1
2.9
3.1
-1
3.3
V
mV/°C
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5484 ADS5485
ADS5484
ADS5485
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ELECTRICAL CHARACTERISTICS (ADS5484, ADS5485) (continued)
Typical values at TA = 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ADS5484
ADS5485
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
-0.99
±0.5
1.0
-0.99
±0.5
1.0
LSB
-10
±3
+10
-10
±3
+10
LSB
15
-15
DYNAMIC ACCURACY
DNL
INL
Differential nonlinearity error
No missing codes,
fIN = 30 MHz
Integral nonlinearity error
fIN = 30 MHz
Offset error
-15
Offset temperature coefficient
-0.02
Gain error
-6
Gain temperature coefficient
±2
15
-0.02
6
-6
-0.01
±2
mV
mV/°C
6
-0.01
%FS
mV/°C
POWER SUPPLY
IAVDD5
5-V analog current
IAVDD3
3.3-V analog current
IDVDD3
3.3-V digital/LVDS current
VIN = Full-scale, fIN = 30 MHz,
fS = Max rated, Normal operation
Total power dissipation
IAVDD5
5-V analog current
IAVDD3
3.3-V analog current
IDVDD3
3.3-V digital/LVDS current
5-V analog current
IAVDD3
3.3-V analog current
IDVDD3
3.3-V digital/LVDS current
Light sleep mode (PDWNF = H,
PDWNS = L)
PSRR
Deep sleep mode (PDWNF = L,
PDWNS = H)
From PDWNF disabled
From PDWNS disabled
AVDD5 supply
Power-supply rejection ratio,
Without 0.1-μF board supply
capacitors, with 1-MHz supply
noise (see Figure 46)
DVDD3 supply
330
mA
126
150
mA
60
65
60
65
mA
2.16
2.35
2.16
2.35
W
98
mA
35
35
mA
0.07
0.07
680
600
mA
680
mW
13
13
mA
1
1
mA
0.07
0.07
70
Slow wake-up time (deep sleep)
AVDD3 supply
310
150
600
Total power dissipation
Fast wake-up time (light sleep)
330
126
98
Total power dissipation
IAVDD5
310
100
70
600
mA
100
mW
600
μS
6
6
mS
60
60
dB
80
80
dB
95
95
dB
DYNAMIC AC CHARACTERISTICS
SNR
SFDR
HD2
Signal-to-noise ratio, dither disabled
Spurious-free dynamic range, dither
disabled
Second-harmonic, dither disabled
fIN = 10 MHz
75
76.8
73.5
fIN = 30 MHz
74.5
75.9
73
fIN = 70 MHz
fIN = 130 MHz
75.7
73.5
75.7
fIN = 170 MHz
75.6
fIN = 230 MHz
74.9
72
84
fIN = 30 MHz
84
91
82
87
86
fIN = 170 MHz
81
fIN = 230 MHz
73
fIN = 10 MHz
84
fIN = 30 MHz
84
fIN = 70 MHz
fIN = 130 MHz
78
90
85
73
84
95
82
100
95
95
78
85
fIN = 170 MHz
81
78
fIN = 230 MHz
73
73
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dBc
78
100
87
93
87
95
78
dBFS
74.4
95
78
74.8
74.8
84
fIN = 130 MHz
75
75
fIN = 10 MHz
fIN = 70 MHz
75.8
dBc
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ADS5484
ADS5485
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ELECTRICAL CHARACTERISTICS (ADS5484, ADS5485) (continued)
Typical values at TA = 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
PARAMETER
HD3
Third-harmonic, dither disabled
Worst harmonic/spur
(other than HD2 and HD3), dither
disabled
THD
SINAD
IMD
ENOB
Noise
Total harmonic distortion, dither
disabled
Signal-to-noise and distortion, dither
disabled
Two-tone SFDR (worst spurious or
IMD)
TEST CONDITIONS
ADS5484
MIN
TYP
fIN = 10 MHz
84
fIN = 30 MHz
84
fIN = 70 MHz
fIN = 130 MHz
MIN
TYP
97
84
99
91
82
87
78
82
fIN = 230 MHz
73
fIN = 10 MHz
84
fIN = 30 MHz
84
fIN = 70 MHz
78
84
91
82
90
87
78
92
81
fIN = 30 MHz
81
86
79
86
75
78
fIN = 230 MHz
70
fIN = 10 MHz
73.5
fIN = 30 MHz
73
fIN = 70 MHz
fIN = 130 MHz
75
92
85
70
75.8
71.5
74.6
75
71
73.8
70
72.9
73.7
73.8
fIN = 170 MHz
72.9
71.7
fIN = 230 MHz
68.7
68.4
fIN1 = 29.5 MHz, fIN2 = 30.5 MHz,
Each at –7 dBFS
99.1
95.9
fIN1 = 69.5 MHz, fIN2 = 70.5 MHz,
Each at –10 dBFS
95.3
95.2
Effective number of bits
fIN = 10 MHz (from SINAD in dBc
at -1dBFS)
RMS idle-channel noise
Analog inputs shorted together
dBc
81
76
74.3
71.5
dBc
90
85
84
fIN = 170 MHz
90
87
81
fIN = 130 MHz
93
90
fIN = 10 MHz
fIN = 70 MHz
dBc
85
90
91
fIN = 230 MHz
87
73
96
fIN = 170 MHz
UNIT
81
90
78
MAX
87
86
fIN = 170 MHz
fIN = 130 MHz
ADS5485
MAX
dBc
dBFS
11.92
12.3
11.58
12.1
Bits
2.9
2.9
LSB rms
78
78
dBFS
LVDS DIGITAL OUTPUTS
VOD
Differential output voltage (±)
VOC
Common-mode output voltage
Assumes a 100-Ω differential
load on each LVDS pair and
LVDS bias = 3.5 mA
247
350
454
247
350
454
mV
1.125
1.25
1.375
1.125
1.25
1.375
V
0.8
V
1
μA
DIGITAL INPUTS
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
IIL
Low-level input current
Input capacitance
6
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2
2
V
0.8
PDWNF, PDWNS, DITHER
1
-1
μA
-1
2
2
pF
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ADS5485
www.ti.com ............................................................................................................................................... SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009
TIMING INFORMATION
Sample
N
N+5
N+3
Aperture
Delay
ta
N+1
N+2
N+4
tCLKL
N+6
tCLKH
CLKP
Sampling
Clock Input
CLKM
tDRY
DRY_P
Data Clock
Output
DRY_M
Latency = 5 Clock Cycles
tDATA
Dx_y_P
Output Data
O
E
E
O
O
E
O
E
O
E
E
O
E
O
Dx_y_M
N–1
N
E = Even Bits = B0, B2, B4, B6, B8, B10, B12, B14
O = Odd Bits = B1, B3, B5, B7, B9, B11, B13, B15
Dx_y_P/M are LVDS outputs that have two bits per pair (EVEN and ODD). The values for x and y are 0_1, 2_3, 4_5, ... 14_15.
T0158-02
Figure 1. Timing Diagram
TIMING CHARACTERISTICS (1)
Typical values at TA = 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock,
unless otherwise noted.
PARAMETER
ta
TEST CONDITIONS
MIN
Aperture delay
Aperture jitter, rms
Clock period
tCLKH
Clock pulse duration, high
tCLKL
MAX
UNIT
200
Internal jitter of the ADC
Latency
tCLK
TYP
ps
80
fs
5
cycles
1e9/CLK
100
ns
0.5e9/CLK
50
ns
Clock pulse duration, low
0.5e9/CLK
50
ns
tDRY
CLK to DRY delay time (2)
1500
1900
2300
ps
tDATA
CLK to DATA delay time (2)
1400
1900
2400
ps
tSKEW
DATA to DRY skew
–500
0
500
ps
tRISE
DRY/DATA rise time
tFALL
DRY/DATA fall time
(1)
(2)
CLK = max rated clock for that part
number
Zero crossing, 5-pF parasitic to GND
tDATA – tDRY, 5-pF parasitic to GND
5-pF parasitic to GND
500
ps
500
ps
Timing parameters are assured by design or characterization, but not production tested.
DRY and DATA are updated on the rising edge of CLK input. The latency must be added to tDATA to determine the overall propagation
delay.
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ADS5485
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PIN CONFIGURATION
D14_15_P
D14_15_M
D12_13_P
D12_13_M
D10_11_P
D10_11_M
D8_9_P
D8_9_M
DRY_P
DRY_M
DVDD3
DGND
63
62
61 60
59
58
57
56
55
54
53
52
51 50
D6_7_M
DVDD3
64
D6_7_P
DGND
ADS548x
RGC Package
(Top View)
49
48
D4_5_P
2
47
D4_5_M
AGND
3
46
D2_3_P
REF
4
45
D2_3_M
NC
5
44
D0_1_P
NC
6
43
D0_1_M
AGND
7
42
DVDD3
AVDD5
8
41
DGND
AVDD5
1
AVDD5
AGND
NC
AGND
13
36
DITHER
AVDD5
14
35
PDWNS
AVDD3
15
34
PDWNF
16
17
18
19
20
21 22
23
24
25
26
27
28
29
30
33
31 32
LVDSB
AGND
VCM
AVDD3
37
AVDD5
12
AGND
INM
AVDD3
NC
AVDD5
38
AGND
11
AVDD3
INP
AVDD5
NC
AGND
39
CLKP
10
CLKM
AGND
AGND
NC
AVDD3
40
AVDD5
9
AGND
AVDD3
P0056-08
8
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Table 2. PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
AVDD5
1, 2, 8, 14, 18,
24, 27, 30
5-V analog supply
AVDD3
9, 15, 19, 25,
28, 31
3.3-V analog supply
AGND
3, 7, 10, 13, 17,
20, 23, 26, 29, Analog ground
32
DVDD3
42, 52, 63
3.3-V digital supply
DGND
41, 51, 64
Digital ground
NC
5, 6, 37-40
INP, INM
11, 12
CLKM, CLKP
21, 22
No connect - leave floating
Differential analog inputs (P = plus = true, M = minus = complement)
Differential clock inputs (P = plus = true, M = minus = complement)
REF
4
Reference voltage input/output (1.2 V nominal). To use an external reference and to turn the internal
reference off, pull both PDWNF and PDWNS to logic high (DVDD3). A 0.1-μF capacitor to ground on
REF is recommended but not required.
VCM
16
Analog input common mode, output (3.1V), for use in applications that require use of the internally
generated common-mode. See the Applications section for more information on using VCM. A 0.1-μF
capacitor to ground on VCM is recommended but not required.
LVDSB
33
External bias resistor for LVDS bias current, normally 10 kΩ to GND to provide nominal 3.5-mA LVDS
current.
PDWNF
34
Light sleep power down, fast wake-up, logic high (DVDD3) = light sleep enabled (bandgap reference
remains on)
PDWNS
35
Deep sleep power down, slow wake-up, logic high (DVDD3) = deep sleep enabled (bandgap reference
is off)
DITHER
36
Dither enable, logic high (DVDD3) = dither enabled
DRY_P,
DRY_M
54, 53
Data ready signal (LVDS clock out) (P = plus = true, M = minus = complement)
D14_15_P,
D14_15_M
62, 61
DDR LVDS output bits 14 then 15 (15 is MSB) (P = plus = true, M = minus = complement)
DE_O_P,
DE_O_M
43-50, 55-62
DDR LVDS output bits E (even) then O (odd) (P = plus = true, M = minus = complement)
D0_1_P,
D0_1_M
44, 43
PowerPAD
65
DDR LVDS output bits 0 then 1 (0 is LSB) (P = plus = true, M = minus = complement)
Analog ground (exposed pad on bottom of package)
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TYPICAL CHARACTERISTICS
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5484 - 170-MSPS Typical Data
Plots in this section are with a clock of 170 MSPS, unless otherwise specified.
ADS5484 SPECTRAL PERFORMANCE
vs
FFT for 10-MHz INPUT SIGNAL
0
−10
Amplitude − dB
−60
−70
−80
−40
−50
−60
−70
−80
−90
−100
−90
−100
−110
−120
−110
−120
8.5
17
25.5
34
42.5
51
59.5
68
76.5
f − Frequency − MHz
85
0
8.5
17
34
42.5
51
59.5
68
ADS5484 SPECTRAL PERFORMANCE
vs
FFT for 230-MHz INPUT SIGNAL
0
−10
SFDR = 80 dBc
SINAD = 74.4 dBFS
SNR = 75.6 dBFS
THD = 79.6 dBc
Amplitude − dB
−70
−80
−40
−50
−60
−70
−80
−90
−100
−90
−100
−110
−120
−110
−120
8.5
17
25.5
34
42.5
51
59.5
f − Frequency − MHz
68
76.5
SFDR = 73 dBc
SINAD = 69.7 dBFS
SNR = 74.9 dBFS
THD = 70.3 dBc
−20
−30
−60
85
0
8.5
17
25.5
34
42.5
51
59.5
f − Frequency − MHz
G005
Figure 4.
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85
G004
ADS5484 SPECTRAL PERFORMANCE
vs
FFT for 130-MHz INPUT SIGNAL
−40
−50
76.5
f − Frequency − MHz
G003
Figure 3.
−20
−30
10
25.5
Figure 2.
0
−10
0
SFDR = 87 dBc
SINAD = 75.3 dBFS
SNR = 75.5 dBFS
THD = 87.2 dBc
−20
−30
−40
−50
0
Amplitude − dB
0
−10
SFDR = 97 dBc
SINAD = 76.7 dBFS
SNR = 76.8 dBFS
THD = 96.3 dBc
−20
−30
Amplitude − dB
ADS5484 SPECTRAL PERFORMANCE
vs
FFT for 70-MHz INPUT SIGNAL
68
76.5
85
G006
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5484 DIFFERENTIAL NONLINEARITY
ADS5484 INTEGRAL NONLINEARITY
1.0
4
0.8
3
0.6
2
INL − LSB
DNL − LSB
0.4
0.2
0.0
−0.2
−0.4
0
−1
−2
−0.6
−3
fS = 170 MSPS
fIN = 10 MHz, –1 dBFS
−0.8
−1.0
fS = 170 MSPS
fIN = 10 MHz, –1 dBFS
−4
16384
32768
49152
Code
0
65536
16384
32768
49152
65536
Code
G007
G008
Figure 6.
Figure 7.
ADS5484 AC PERFORMANCE
vs
INPUT AMPLITUDE (130-MHz Input Signal)
ADS5484 AC PERFORMANCE
vs
INPUT AMPLITUDE (130-MHz Input Signal)
130
SFDR (dBFS,
120
Dither ON)
110
SFDR
(dBFS,
100
SNR (dBFS,
Dither OFF)
Dither ON)
90
80
70
SFDR (dBc,
Dither OFF)
60
50
SFDR (dBc,
40
Dither ON)
30
fS = 170 MSPS
fIN = 130 MHz
20
SNR (dBc,
AIN = 0 to −100 dBFS
10
Dither ON)
256k Point FFT
0
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
AIN − Input Amplitude − dBFS
90
SFDR (dBc,
Dither ON)
85
AC Performance − dB
0
AC Performance − dB
1
80
SFDR (dBc,
Dither OFF)
75
70
fS = 170 MSPS
fIN = 130 MHz
AIN = 0 to −40 dBFS
256k Point FFT
65
60
−40 −36 −32 −28 −24 −20 −16 −12
G009
Figure 8.
−8
−4
AIN − Input Amplitude − dBFS
0
G010
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5484 TWO-TONE PERFORMANCE
vs
INPUT AMPLITUDE (f1 = 69.5 MHz and f2 = 70.5 MHz)
ADS5484 30-MHz SFDR
vs
AVDD5 and AVDD3 OVER TEMPERATURE
−70
94
No Dither, Dominant Spur (dBFS)
−90
−100
−110
−120
89
−140
87
Dither, 2F1−F2 (dBFS)
−80
−70
−60
−50
−40
−30
−20
−10
Input Amplitude − dBFS
AVDD5 = 4.75 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.15 V
86
−40
0
AVDD5 = 5.25 V,
AVDD3 = 3.15 V
90
88
Dither, 2F2−F1 (dBFS)
AVDD5 = 5 V,
AVDD3 = 3.45 V
91
−130
−150
−90
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
92
Dither, Dominant Spur (dBFS)
AVDD5 = 5 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.45 V
93
SFDR − dBc
Performance − dBFS
−80
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
fS = 170 MSPS,
fIN = 30 MHz
−20
0
20
40
T − Temperature − °C
G011
Figure 10.
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
60
80
G012
Figure 11.
ADS5484 30-MHz SNR
vs
AVDD5 and AVDD3 OVER TEMPERATURE
77.0
76.8
SNR − dBFS
76.6
76.4
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.15 V
AVDD5 = 5.25 V,
AVDD3 = 3.45 V
AVDD5 = 5 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
76.2
76.0
75.8
75.6
75.4
75.2
75.0
−40
AVDD5 = 4.75 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.3 V
AVDD5 = 5 V,
AVDD3 = 3.15 V
fS = 170 MSPS,
fIN = 30 MHz
−20
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
0
20
40
60
80
T − Temperature − °C
G013
Figure 12.
12
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5485 - 200-MSPS Typical Data
Plots in this section are with a clock of 200 MSPS, unless otherwise specified.
ADS5485 SPECTRAL PERFORMANCE
vs
FFT for 10-MHz INPUT SIGNAL
0
−10
Amplitude − dB
−60
−70
−80
−40
−50
−60
−70
−80
−90
−100
−90
−100
−110
−120
−110
−120
10
20
30
40
50
60
70
80
90
f − Frequency − MHz
0
−10
0
100
20
30
40
50
60
70
80
G018
Figure 14.
ADS5485 SPECTRAL PERFORMANCE
vs
FFT for 130-MHz INPUT SIGNAL
ADS5485 SPECTRAL PERFORMANCE
vs
FFT for 230-MHz INPUT SIGNAL
0
−10
Amplitude − dB
−70
−80
−40
−50
−60
−70
−80
−90
−100
−90
−100
−110
−120
−110
−120
10
20
30
40
50
60
70
f − Frequency − MHz
80
90
100
100
SFDR = 73 dBc
SINAD = 69.5 dBFS
SNR = 74.5 dBFS
THD = 70.2 dBc
−20
−30
−60
90
G019
Figure 13.
−40
−50
0
10
f − Frequency − MHz
SFDR = 84 dBc
SINAD = 74.1 dBFS
SNR = 75 dBFS
THD = 80.8 dBc
−20
−30
SFDR = 88 dBc
SINAD = 74.7 dBFS
SNR = 75 dBFS
THD = 86 dBc
−20
−30
−40
−50
0
Amplitude − dB
0
−10
SFDR = 93 dBc
SINAD = 75.7 dBFS
SNR = 75.8 dBFS
THD = 97 dBc
−20
−30
Amplitude − dB
ADS5485 SPECTRAL PERFORMANCE
vs
FFT for 70-MHz INPUT SIGNAL
0
10
20
G020
Figure 15.
30
40
50
60
70
80
90
f − Frequency − MHz
100
G021
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5485 DIFFERENTIAL NONLINEARITY
ADS5485 INTEGRAL NONLINEARITY
1.0
4
0.8
3
0.6
2
INL − LSB
DNL − LSB
0.4
0.2
0.0
−0.2
−0.4
0
−1
−2
−0.6
−3
fS = 200 MSPS
fIN = 10 MHz, –1 dBFS
−0.8
−1.0
fS = 200 MSPS
fIN = 10 MHz, –1 dBFS
−4
16384
32768
49152
Code
0
65536
16384
49152
65536
G022
G023
Figure 17.
Figure 18.
ADS5485 AC PERFORMANCE
vs
INPUT AMPLITUDE (130-MHz Input Signal)
ADS5485 AC PERFORMANCE
vs
INPUT AMPLITUDE (130-MHz Input Signal)
130
SNR (dBFS,
120
SFDR (dBFS,
Dither ON)
Dither ON)
110
SFDR (dBFS,
100
Dither OFF)
90
80
70
SFDR (dBc,
Dither ON)
60
50
SFDR (dBc,
40
Dither OFF)
30
fS = 200 MSPS
fIN = 130 MHz
20
SNR (dBc,
AIN = 0 to −100 dBFS
10
Dither ON)
256k Point FFT
0
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
AIN − Input Amplitude − dBFS
90
85
fS = 200 MSPS
fIN = 130 MHz
AIN = 0 to −40 dBFS
256k Point FFT
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SFDR (dBc,
Dither ON)
80
SFDR (dBc,
Dither OFF)
75
70
65
60
−40 −36 −32 −28 −24 −20 −16 −12
AIN − Input Amplitude − dBFS
G024
Figure 19.
14
32768
Code
AC Performance − dB
0
AC Performance − dB
1
−8
−4
0
G025
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5485 TWO-TONE PERFORMANCE
vs
INPUT AMPLITUDE (f1 = 69.5 MHz and f2 = 70.5 MHz)
ADS5485 30-MHz SFDR
vs
AVDD5 and AVDD3 OVER TEMPERATURE
−70
90
No Dither, Dominant Spur (dBFS)
SFDR − dBc
Performance − dBFS
89
Dither, Dominant Spur (dBFS)
−90
−100
−110
−120
−130
−80
−70
−60
−50
−40
−30
−20
−10
87
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
Input Amplitude − dBFS
85
−40
0
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.15 V
88
Dither, 2F1−F2 (dBFS)
−150
−90
AVDD5 = 5.25 V,
AVDD3 = 3.45 V
AVDD5 = 5 V,
AVDD3 = 3.15 V
86
Dither, 2F2−F1 (dBFS)
−140
AVDD5 = 5 V,
AVDD3 = 3.3 V
fS = 200 MSPS,
fIN = 30 MHz
−80
AVDD5 = 4.75 V,
AVDD3 = 3.15 V
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
−20
AVDD5 = 5 V,
AVDD3 = 3.45 V
0
20
40
60
80
T − Temperature − °C
G026
Figure 21.
G027
Figure 22.
ADS5485 30-MHz SNR
vs
AVDD5 and AVDD3 OVER TEMPERATURE
76.0
75.5
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.45 V
SNR − dBFS
75.0
74.5
74.0
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
73.5
73.0
72.5
72.0
−40
AVDD5 = 5 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.15 V
fS = 200 MSPS,
fIN = 30 MHz
−20
0
20
40
60
T − Temperature − °C
80
G028
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
Typical Data, Valid for Both ADS5484/5485
Plots in this section are valid for either device or otherwise have combined plots.
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY
NOISE HISTOGRAM WITH INPUTS SHORTED
3
18
ADS5484
0
14
ADS5481
−6
ADS5485
10
8
6
2
ADS5482
G033
32706
32704
32702
32700
32698
32696
32694
32692
Output Code
Figure 24.
G034
Figure 25.
CMRR
vs
COMMON-MODE INPUT FREQUENCY
ADC WAKE-UP TIME
0
90
−10
80
−20
70
SNR − dBFS
CMRR − dB
32690
32688
fIN − Input Frequency − Hz
32686
1G
32684
0
100M
32680
−12
10M
−30
−40
−50
PDWNF
60
PDWNS
50
40
30
−60
fS = 135 MSPS
fIN = 10 MHz
PDWNF and PDWNS Tested Independently
PDWNx Disabled at 0 ms
PDWNx Enabled at ≈ 8 ms
20
−70
10
0
1
10
100
fIN − Input Frequency − MHz
1k
0
1
2
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3
4
5
6
t − time − ms
G054
Figure 26.
16
ADS5485
4
−9
−80
0.1
ADS5484
12
32682
−3
fs = 170 MSPS for ADS5484
fs = 200 MSPS for ADS5485
Analog Inputs Shorted to VCM
16
Percentage − %
Normalized Gain Response − dB
ADS5483
7
8
9
10
G066
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
210
200
74
75
74
75
73
75
fS - Sampling Frequency - MSPS
180
160
74
76
140
75
120
73
74
100
80
76
75
75
60
40
20
10
10
74
73
75
73
74
73
72
74
72
72
70
70
50
66
68
150
100
70
68
200
250
64
300
fIN - Input Frequency - MHz
62
64
66
68
70
72
SNR - dBFS
74
76
78
M0048-08
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SFDR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
210
200
85
80
70
90
fS - Sampling Frequency - MSPS
180
75
85
160
80
140
90
120
85
100
75
80
80
70
60
40
85
90
75
80
85
20
10
10
50
150
100
65
70
60
200
250
300
fIN - Input Frequency - MHz
55
60
65
70
75
80
85
SFDR - dBc
90
95
100
M0049-08
Figure 29.
18
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APPLICATIONS INFORMATION
Theory of Operation
The ADS5484/ADS5485 (ADS548x) is a 16-bit, 170/200-MSPS family of monolithic pipeline ADCs. The bipolar
analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide
LVDS-compatible outputs. Prior to the track-and-hold, the analog input signal passes through a high-performance
bipolar buffer. The buffer presents a high and consistent impedance to the analog inputs. The buffer isolates the
board circuitry external to the ADC from the sampling glitches caused by the track-and-hold in the ADC. The
conversion process is initiated by the falling edge of the external input clock. At that instant, the differential input
signal is captured by the input track-and-hold, and the input sample is converted sequentially by a series of lower
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in
a data latency of 4.5 clock cycles, after which the output data are available as a 16-bit parallel word, coded in
offset binary format.
Input Configuration
The analog input for the ADS548x consists of an analog pseudo-differential buffer followed by a bipolar transistor
T & H. The analog buffer isolates the source driving the input of the ADC from any internal switching and
presents a high impedance to drive at high input frequencies, as compared to an ADC without a buffered input.
The input common-mode is set internally through a 1000-Ω resistor connected from 3.1 V to each of the inputs.
This configuration results in a differential input impedance of 2 kΩ at 0 Hz. Figure 30 estimates the package
parasitics before soldering to a board. Each board is different, but soldering to the board will likely add 1 – 2 pF
to the input capacitance.
ADS548x
Bipolar
Transistor
Buffer
AVDD5
~ 2 nH Bond Wire
10 W
INP
~ 200 fF
Bond Pad
~ 200 fF
Package
Analog
Inputs
3 pF
1000 W
AGND
AVDD5
1000 W
~ 2 nH Bond Wire
Track and Hold,
VCM
st
1 Pipeline Stage
3 pF
AGND
INM
~ 200 fF
Package
~ 200 fF
Bond Pad
10 W
AGND
Bipolar
Transistor
Buffer
S0293-02
Figure 30. Analog Input Circuit (unsoldered package)
For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings
symmetrically between (3.1 V + 0.75 V) and (3.1 V – 0.75 V). This range means that each input has a maximum
signal swing of 1.5 VPP for a total differential input signal swing of 3 VPP. Operation below 3 VPP is allowable, with
the characteristics of performance versus input amplitude demonstrated in Figure 8 through Figure 10. For
instance, for performance at 2 VPP rather than 3 VPP, refer to the SNR and SFDR at –3.5 dBFS (0 dBFS =
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3 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for
any external circuitry for this purpose. The primary degradation visible if the maximum amplitude is kept to 2 VPP
is ~3 dBc of SNR compared to using 3 VPP, while SFDR is the same or even improved. The smaller input signal
also possibly helps any components in the signal chain prior to the ADC to be more linear and provide better
distortion.
The ADS548x performs optimally when the analog inputs are driven differentially. The circuit in Figure 31 shows
one possible configuration using an RF transformer with termination either on the primary or on the secondary of
the transformer. If voltage gain is required, a step-up transformer can be used.
R0
50 W
Z0
50 W
INP
R
200 W
AC Signal
Source
ADS548x
INM
n = 2:1
S0176-04
Figure 31. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
Dither
The ADS548x family of devices contain a dither option that is enabled via the DITHEREN pin. Dither is a
technique applied to convert small static errors in the converter to dynamic errors, which look similar to white
noise in the output. It improves the harmonics that are a function of the static errors. The dither is a low level and
is only indicated in the output waveform as wideband noise that may slightly degrade the SNR. It is
recommended that users should allow the capability to enable/disable it in the event they would like to compare
the results during their evaluation. In addition to the plots on the first page of the data sheet, Figure 8 through
Figure 10 and Figure 19 through Figure 21 show the minor differences of dither on/off when studied.
External Voltage Reference
For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an
external reference. The dependency on the signal amplitude to the value of the external reference voltage is
characterized typically by Figure 32 (VREF = 1.2 V is normalized to 0 dB as this is the internal reference
voltage). As can be seen in the linear fit, this equates to approximately ~1 dB of signal adjustment per 100 mV of
reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied to
the inputs and the desired spectral performance, as can be seen in the performance versus external reference
graphs in Figure 33 and Figure 34.
For dc-coupled applications that use the VCM pin of the ADS548x as the common mode of the signal in the
analog signal gain path prior to the ADC inputs, Figure 36 indicates little change in VCM output as VREF is
externally adjusted. The VCM output is buffered with a 2-kΩ series output resistor.
The method for disabling the internal reference for use with an external reference is described in Table 5 . The
following VREF adjustment graphs were collected using the ADS5483, but are indicative of the behavior of the
ADS5484/5485. The absolute performance may differ from device to device, but the relative characteristics are
valid.
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100
fS = 135 MSPS
fIN = 30 MHz
AIN ≤ −1 dBFS
Normalized to 1.2 VREF
8
6
AIN = −2 dBFS
95
Linear Fit: y = −9.8x + 11.8
4
2
AIN = −1 dBFS
90
SFDR − dBc
Normalized Gain Adjustment − dB
10
AIN = −10 dBFS
85
AIN = −4 dBFS
AIN = −6 dBFS
80
0
−2
75
−4
0.5
70
0.5
fS = 135 MSPS
fIN = 30 MHz
Dither Enabled
Signal Amplitude Relative
to Adjusted Fullscale
AIN = −3 dBFS
AIN = −7 dBFS
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Applied External VREF − V
1.4
G057
76
AIN = −1 dBFS
1.0
1.1
1.2
1.3
1.4
G058
2.2
fS = 135 MSPS
fIN = 30 MHz
Signal Adjusted to −1 dBFS
AIN = −6 dBFS
P − Power − W
SNR − dBc
0.9
2.3
AIN = −3 dBFS
AIN = −2 dBFS
AIN = −4 dBFS
78
AIN = −7 dBFS
70
68
66
64
62
60
0.5
0.8
Figure 33. SFDR versus External VREF and AIN
80
72
0.7
Applied External VREF − V
Figure 32. Signal Gain Adjustment versus External
Reference (VREF)
74
0.6
AIN = −10 dBFS
0.6
0.7
0.8
0.9
1.0
2.1
2.0
1.9
fS = 135 MSPS
fIN = 30 MHz
Dither Enabled
Signal Amplitude Relative
to Adjusted Fullscale
1.1
1.2
1.3
Applied External VREF − V
1.8
1.7
0.5
1.4
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Applied External VREF − V
G059
Figure 34. SNR versus External VREF and AIN
1.4
G060
Figure 35. Total Power Consumption versus
External VREF
3.20
VCM Pin Output Voltage − V
3.19
3.18
3.17
3.16
3.15
3.14
3.13
3.12
3.11
3.10
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Applied External VREF − V
1.4
G061
Figure 36. VCM Pin Output versus External VREF
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Clock Inputs
The ADS548x equivalent clock input circuit is shown in Figure 37. The clock inputs can be driven with either a
differential clock signal or a single-ended clock input, but differential is highly recommended. The characterization
of the ADS548x is typically performed with a 3-VPP differential clock, but the ADC performs well with a differential
clock amplitude down to ~1 VPP, as shown in Figure 39 and Figure 40 . The performance is optimized when the
clock amplitude is kept above 2 VPP. The clock amplitude becomes more of a factor in performance as the
analog input frequency increases. When single-ended clocking is a necessity, it is best to connect CLKM to
ground with a 0.01-μF capacitor, while CLKP is ac-coupled with a 0.01-μF capacitor to the clock source, as
shown in Figure 38.
Figure 37. Clock Input Circuit
Square Wave or
Sine Wave
CLKP
0.01 mF
ADS548x
CLKM
0.01 mF
S0168-08
Figure 38. Single-Ended Clock
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SFDR
vs
CLOCK AMPLITUDE
SNR
vs
CLOCK AMPLITUDE
110
81
fIN = 100.33 MHz
fIN = 9.97 MHz
fIN = 30.13 MHz
fIN = 30.13 MHz
79
100
fIN = 9.97 MHz
fIN = 69.59 MHz
SNR − dBFS
SFDR − dBc
77
90
80
70
73
fIN = 130.13 MHz
71
fIN = 170.13 MHz
fIN = 69.59 MHz
fIN = 100.33 MHz
69
fIN = 130.13 MHz
60
75
67
fIN = 170.13 MHz
fS = 170 MSPS
50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Clock Amplitude − VPP
4.5
5.0
65
0.0
0.5
1.0
1.5
fS = 170 MSPS
2.0
2.5
3.0
3.5
4.0
4.5
Clock Amplitude − VPP
G035
Figure 39.
5.0
G036
Figure 40.
For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications
because the board level clock jitter is superior.
The sampling process is more sensitive to jitter using high analog input frequencies or slow clock frequencies.
Large clock amplitude levels are recommended when possible to reduce the indecision (jitter) in the ADC clock
input buffer. Whenever possible, the ideal combination is a differential clock with large signal swing (~1 – 3 VPP).
Figure 41 demonstrates a recommended method for converting a single-ended clock source into a differential
clock; it is similar to the configuration found on the evaluation board and was used for much of the
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.
Clock
Source
0.1 mF
CLKP
ADS548x
CLKM
S0194-03
Figure 41. Differential Clock
The common-mode voltage of the clock inputs is set internally to ~2 V using internal 0.5-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS548x features good tolerance to
clock common-mode variation (as shown in Figure 42 and Figure 43). The internal ADC core uses both edges of
the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Performance
degradation as a result of duty cycle can be seen in Figure 44.
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100
76
30.13 MHz
75
69.59 MHz
74
SNR − dBFS
SFDR − dBc
90
80
70
100.33 MHz
1.0
1.5
71
30.13 MHz
69.59 MHz
70
68
67
CLK = 200 MSPS
50
0.5
230.53 MHz
72
69
230.53 MHz
60
73
2.0
2.5
3.0
3.5
Clock Common-Mode Voltage − V
100.33 MHz
CLK = 200 MSPS
66
0.5
1.0
1.5
2.0
2.5
3.0
Clock Common-Mode Voltage − V
G037
Figure 42. SFDR versus Clock Common-Mode
Voltage
3.5
G038
Figure 43. SNR versus Clock Common-Mode
Voltage
95
30 MHz
90
SFDR − dBc
85
80
75
70
130 MHz
65
230 MHz
60
170 MSPS (ADS5484)
200 MSPS (ADS5485)
55
50
30
35
40
45
50
55
60
65
Clock Duty Cycle − %
70
G039
Figure 44. SFDR vs Clock Duty Cycle
The ADS5484 is capable of achieving 75.7 dBFS SNR at 130 MHz of analog input frequency. In order to achieve
the SNR at 130 MHz the clock source rms jitter (at the ADC clock input pins) must be at most 184 fsec in order
for the total rms jitter to be 201 fsec due to internal ADC aperture jitter of ~80 fsec. A summary of maximum
recommended rms clock jitter as a function of analog input frequency for the ADS5484 is provided in Table 3.
The equations used to create the table are presented and can be used to estimate required clock jitter for
virtually any pipeline ADC, but in particular, the ADS5481/5482/5483/5484/5485 family.
Table 3. Recommended Approximate RMS Clock Jitter for ADS5484
ANALOG INPUT FREQUENCY
(MHz)
24
MEASURED SNR
(dBc)
TOTAL JITTER
(fsec rms)
MAXIMUM CLOCK JITTER
(fsec rms)
10
76.8
2301
2299
30
75.9
851
847
70
75.7
373
364
130
75.7
201
184
170
75.6
155
133
230
74.9
124
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Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 ´ LOG10 (2 ´ p ´ fIN ´ jTOTAL)
2
(1)
2 1/2
jTOTAL = (jADC + jCLOCK )
(2)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI
CDCE72010 and CDCM7005. Depending on the jitter requirements, a band pass filter (BPF) is sometimes
required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too
low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed
between the CDC and the BPF, as its harmonics and wide-band noise are reduced by the BPF.
Figure 45 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCE72010
with the clock signal path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult
to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCE72010 output depends largely on the phase
noise of the VCXO/VCO selected, as well as from the CDCE72010 itself.
Board Master
Reference Clock
(High or Low Jitter)
10 MHz
AMP and/or BPF Optional
REF
LVCMOS
100 MHz
AMP
BPF
XFMR
400 MHz (To Transmit DAC)
CLKP
CLKM
ADC
TI ADS548x
100 MHz (To DSP)
Low Jitter Oscillator
LVPECL
or
LVCMOS
100 MHz (To FPGA)
400 MHz
VCO/
VCXO
CDC
(Clock Distribution Chip)
Ex: TI CDCE72010
To Other
B0268-01
Consult the CDCE72010 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 45. Optimum Jitter Clock Circuit
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Digital Outputs
The ADC provides eight LVDS-compatible, offset binary, DDR data outputs (2 bits per LVDS output driver) and a
data-ready LVDS signal (DRY). It is recommended to use the DRY signal to capture the output data of the
ADS548x (use as a clock output). DRY is source-synchronous to the DATA outputs and operates at the same
frequency, creating a full-rate DDR interface that updates data on both the rising and falling edges of DRY. It is
recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance shortens the
data-valid timing window. The values given for timing (see Figure 1) were obtained with a 5-pF parasitic board
capacitance to ground on each LVDS line. When setting the time relationship between DRY and DATA at the
receiving device, it is generally recommended that setup time be maximized, but this partially depends on the
setup and hold times of the device receiving the digital data. Since DRY and DATA are coincident, it will likely be
necessary to delay either DRY such that DATA setup time is maximized.
The LVDS outputs all require an external 100-Ω load between each output pair in order to meet the expected
LVDS voltage levels. For long trace lengths, it may be necessary to place a 100-Ω load on each digital output as
close to the ADS548x as possible and another 100-Ω differential load at the end of the LVDS transmission line to
terminate the transmission line and avoid signal reflections. The effective load in this case reduces the LVDS
voltage levels by half. The current of all LVDS drivers is set externally with a resistor connected between the
LVDSB (LVDS bias) pin and ground. Normal LVDS current is 3.5 mA per LVDS pair, set with a 10-kΩ external
resistor. For systems with excessive load capacitance on the LVDS lines, reducing the resistor value in order to
increase the LVDS bias current is allowed to create a stronger LVDS drive capability. For systems with short
traces and minimal loading, increasing the resistor in order to decrease the LVDS current is allowable in order to
save power. Table 4 provides a sampling of LVDSB resistor values should deviation from the recommended
LVDS output current of 3.5 mA be considered. It is not recommended to exceed the range listed in the table. If
the LVDS bias current is adjusted, the differential load resistance should also be adjusted to maintain voltage
levels within the specification for the LVDS outputs. The signal integrity of the LVDS lines on the board layout
should be scrutinized to ensure proper LVDS signal integrity exists.
Table 4. Setting the LVDS Current Drive
26
LVDSB RESISTOR TO GND, Ω
LVDS NOMINAL CURRENT, mA
6k
5.6
8k
4.3
10k (value for normal recommended operation)
3.5
12k
2.8
14k
2.3
16k
2.0
18k
1.7
20k
1.5
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Power Supplies and Sleep Modes
The ADS548x uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies generate more noise that can be coupled to the ADS548x. However, the PSRR value and plot shown in
Figure 46 were obtained without bulk supply decoupling capacitors. When bulk (0.1-μF) decoupling capacitors
are used near the supply pins, the board-level PSRR is much higher than the stated value for the ADC. The user
may be able to supply power to the device with a less-than-ideal supply and still achieve good performance. It is
not possible to make a single recommendation for every type of supply and level of decoupling for all systems. If
the noise characteristics of the available supplies are understood, a study of the PSRR data for the ADS548x
may provide the user with enough information to select noisy supplies if the performance is still acceptable within
the frequency range of interest. The power consumption of the ADS548x does not change substantially over
clock rate or input frequency.
0
PSRR − dB
−20
−40
AVDD3V
−60
AVDD5V
−80
−100
DVDD3V
−120
0.1
1
10
100
fIN − Input Frequency − MHz
1k
G067
Figure 46. PSRR versus Supply Injected Frequency
Two separate sleep modes are offered. They are differentiated by the amount of power consumed and the time it
takes for the ADC to wake-up from sleep. The light sleep mode consumes 605 mW and can be used when
wake-up of less than 600 μs is required. Deep sleep consumes 70 mW and requires 6 ms to wake-up. See the
wake-up characteristic in Figure 27. For directions on enabling these modes, see Table 5. The input clock can be
in either state when the power-down modes are enabled. The device can enter power-down mode whether using
an internal or external reference. However, the wake-up time from light sleep enabled to external reference mode
is dependent on the external reference voltage and is not necessarily 0.6 ms, but should be noticeably faster
than deep sleep wake-up. No specific power sequences are required.
Table 5. Power-Down and Reference Modes
MODE
PDWNF PIN
PDWNS PIN
POWER CONSUMPTION
WAKE-UP TIME
On
ADC On - Internal reference
Low
Low
2.16 W
ADC On - External reference
High
High
2.16 W
On
Light sleep
High
Low
600 mW when enabled
0.6 ms
Deep sleep
Low
High
70 mW when enabled
6 ms
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Layout Information
The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the
maximum performance from the ADS548x. Follow general design rules, such as the use of multilayer boards, a
single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The analog input
traces should be isolated from any external source of interference or noise, including the digital outputs as well
as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications
such as high IF sampling where low jitter is required. Besides performance-oriented rules, care must be taken
when considering the heat dissipation of the device. The thermal heat sink included on the bottom of the
package should be soldered to the board as described in the PowerPad Package section. See the ADS548x
EVM User Guide on the TI web site for the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally-enhanced, standard-size IC package designed to eliminate the use of
bulky heat sink and slugs traditionally used in thermal packages. This package can be easily mounted using
standard PCB assembly techniques and can be removed and replaced using standard repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This pad design provides an extremely low thermal resistance path between the die and the exterior of
the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB
as a heat sink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section (at the end of this data sheet).
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils (0.013 in or
0.3302 mm) in diameter. The small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25 mil (0.025 in or 0.635 mm) diameter holes under the
package, but outside the thermal pad area, to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002), both available for download at www.ti.com.
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value.
The injected frequency level is translated into dBFS,
the spur in the output FFT is measured in dBFS, and
the difference is the PSRR in dB. The measurement
calibrates out the benefit of the board supply
decoupling capacitors.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
P
SNR + 10log 10 S
PN
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed
as a percentage.
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
PS
SINAD + 10log 10
PN ) PD
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are
presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated
into dBFS, the spur in the output FFT is measured in
dBFS, and the difference is the CMRR in dB.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of converter
performance as compared to the theoretical limit
based on quantization noise:
ENOB = (SINAD – 1.76)/6.02
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range.
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input
value is the difference between the actual transfer
function and this best-fit line, measured in units of
LSB.
Offset Error
Offset error is the deviation of output code from
mid-code when both inputs are tied to
common-mode.
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of the ability to reject frequencies
present on the power supply.
(4)
(5)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Temperature Drift
Temperature drift (with respect to gain error and
offset error) specifies the change from the value at
the nominal temperature to the value at TMIN or TMAX.
It is computed as the maximum variation the
parameters over the whole temperature range divided
by TMIN – TMAX.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
P
THD + 10log 10 S
PD
(6)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
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REVISION HISTORY
Changes from Revision B (July 2009) to Revision C ..................................................................................................... Page
•
Changed pin PDWNF from 35 to 34 ..................................................................................................................................... 9
•
Changed pin PDWNS from 34 to 35 ..................................................................................................................................... 9
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS5484IRGCT
ACTIVE
VQFN
RGC
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ5484
ADS5485IRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ5485
ADS5485IRGCT
ACTIVE
VQFN
RGC
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ5485
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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