ADS54J69IRMP

Product Folder Order Now Support & Community Tools & Software Technical Documents ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter 1 Features 3 Description • • • The ADS54J69 is a low-power, wide-bandwidth, 16bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. 1 • • • • • • • • • 16-Bit Resolution, Dual-Channel, 500-MSPS ADC Idle Channel Noise Floor: –159 dBFS/Hz Spectral Performance (fIN = 170 MHz at –1 dBFS): – SNR: 73 dBFS – NSD: –157 dBFS/Hz – SFDR: 93 dBc – SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone) Spectral Performance (fIN = 310 MHz at –1 dBFS): – SNR: 71.7 dBFS – NSD: –155.7 dBFS/Hz – SFDR: 81 dBc – SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone) Channel Isolation: 100 dBc at fIN = 170 MHz Input Full-Scale: 1.9 VPP Input Bandwidth (3 dB): 1.2 GHz On-Chip Dither Integrated Decimate-by-2 Filter JESD204B Interface with Subclass 1 Support: – 1 Lane per ADC at 10.0 Gbps – 2 Lanes per ADC at 5.0 Gbps – Support for Multi-Chip Synchronization Power Dissipation: 1.35 W/ch at 500 MSPS 72-Pin VQFNP Package (10 mm × 10 mm) The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel. Device Information PART NUMBER BODY SIZE (NOM) 10.00 mm × 10.00 mm Spectrum at 170-MHz IF 0 SNR = 73 dBFS SFDR = 93 dBc Non HD2, HD3 Spur = 94 dBc -20 Amplitude (dBFS) Radar and Antenna Arrays Broadband Wireless Cable CMTS, DOCSIS 3.1 Receivers Communications Test Equipment Microwave Receivers Software Defined Radio (SDR) Digitizers Medical Imaging and Diagnostics VQFNP (72) (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • • • • • PACKAGE ADS54J69 -40 -60 -80 -100 -120 0 50 100 150 Input Frequency (MHz) 200 250 D003 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 1 1 1 2 4 5 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 Electrical Characteristics........................................... 8 AC Characteristics .................................................... 9 Digital Characteristics ............................................. 11 Timing Characteristics............................................. 12 Typical Characteristics ............................................ 14 Detailed Description ............................................ 24 8.1 Overview ................................................................. 24 8.2 Functional Block Diagram ....................................... 24 8.3 Feature Description................................................. 25 8.4 Device Functional Modes........................................ 30 8.5 Register Maps ......................................................... 39 9 Application and Implementation ........................ 63 9.1 Application Information............................................ 63 9.2 Typical Application .................................................. 68 10 Power Supply Recommendations ..................... 70 10.1 Power Sequencing and Initialization ..................... 71 11 Layout................................................................... 72 11.1 Layout Guidelines ................................................. 72 11.2 Layout Example .................................................... 73 12 Device and Documentation Support ................. 74 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 74 74 74 74 74 74 13 Mechanical, Packaging, and Orderable Information ........................................................... 74 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February 2016) to Revision C Page • Added Device Comparison Table........................................................................................................................................... 5 • Added the FOVR latency parameter to the Timing Characteristics table............................................................................. 12 • Added SYSREF Not Present (Subclass 0, 2) section .......................................................................................................... 27 • Changed the number of clock cycles in the Fast OVR section ............................................................................................ 28 • Changed the Register Map................................................................................................................................................... 40 • Deleted register 39h, 3Ah, and 56h ..................................................................................................................................... 40 • Changed the SNR versus Input Frequency and External Clock Jitter figure ....................................................................... 67 • Changed Power Supply Recommendations section ........................................................................................................... 70 • Added the Power Sequencing and Initialization section....................................................................................................... 71 • Added Documentation Support and Receiving Notification of Documentation Updates sections........................................ 74 • Added the Receiving Notification of Documentation Updates section ................................................................................. 74 Changes from Revision A (January 2016) to Revision B Page • Changed Sample Timing, Aperture jitter parameter in Timing Characteristics table .......................................................... 12 • Changed Table 35 ................................................................................................................................................................ 51 • Changed Table 42 ................................................................................................................................................................ 54 • Changed Table 44 ................................................................................................................................................................ 55 • Changed SNR and Clock Jitter section: changed Figure 130 and last sentence of section................................................ 67 • Changed Application Curves section ................................................................................................................................... 70 2 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Changes from Original (May 2015) to Revision A • Page Released to production .......................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 3 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 5 Device Comparison Table 4 PART NUMBER SPEED GRADE (MSPS) RESOLUTION (Bits) CHANNEL ADS54J20 1000 12 2 ADS54J42 625 14 2 ADS54J40 1000 14 2 ADS54J60 1000 16 2 ADS54J66 500 14 4 ADS54J69 500 16 2 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 6 Pin Configuration and Functions DB2P DB2M IOVDD DB1P DB1M DGND DB0P DB0M IOVDD SYNC DA0M DA0P DGND DA1M DA1P IOVDD DA2M DA2P RMP Package 72-Pin VQFNP Top View 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DB3M 1 54 DA3M DB3P 2 53 DA3P DGND 3 52 DGND IOVDD 4 51 IOVDD SDIN 5 50 PDN SCLK 6 49 RES SEN 7 48 RESET DVDD 8 47 DVDD AVDD 9 46 AVDD AVDD3V 10 45 AVDD3V SDOUT 11 44 AVDD AVDD 12 43 AVDD INBP 13 42 INAP INBM 14 41 INAM AVDD 15 40 AVDD AVDD3V 16 39 AVDD3V AVDD 17 38 AVDD AGND 18 37 AGND 22 23 24 25 26 27 28 29 30 31 32 33 NC NC VCM AGND AVDD3V AVDD AGND CLKINP CLKINM AGND AVDD AVDD3V AGND SYSREFP 34 35 36 AGND 21 AVDD 20 SYSREFM 19 NC GND Pad (Back Side) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 5 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Pin Functions PIN NAME NO. I/O DESCRIPTION CLOCK, SYSREF CLKINM 28 I Negative differential clock input for the ADC CLKINP 27 I Positive differential clock input for the ADC SYSREFM 34 I Negative external SYSREF input SYSREFP 33 I Positive external SYSREF input CONTROL, SERIAL INTERFACE Power-down. Can be configured via an SPI register setting. Can be configured to fast overrange output for channel A via the SPI. PDN 50 I/O RESET 48 I Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor. SCLK 6 I Serial interface clock input SDIN 5 I Serial interface data input SDOUT 11 O Serial interface data output. Can be configured to fast overrange output for channel B via the SPI. SEN 7 I Serial interface enable O JESD204B serial data negative outputs for channel A O JESD204B serial data positive outputs for channel A O JESD204B serial data negative outputs for channel B O JESD204B serial data positive outputs for channel B DATA INTERFACE DA0M 62 DA1M 59 DA2M 56 DA3M 54 DA0P 61 DA1P 58 DA2P 55 DA3P 53 DB0M 65 DB1M 68 DB2M 71 DB3M 1 DB0P 66 DB1P 69 DB2P 72 DB3P 2 SYNC 63 I Synchronization input for JESD204B port INAM 41 I Differential analog negative input for channel A INAP 42 I Differential analog positive input for channel A INBM 14 I Differential analog negative input for channel B INBP 13 I Differential analog positive input for channel B VCM 22 O Common-mode voltage, 2.1 V. Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external connection from the VCM pin to the INxP or INxM pin is required. AGND 18, 23, 26, 29, 32, 36, 37 I Analog ground AVDD 9, 12, 15, 17, 25, 30, 35, 38, 40, 43, 44, 46 I Analog 1.9-V power supply INPUT, COMMON MODE POWER SUPPLY AVDD3V 10, 16, 24, 31, 39, 45 I Analog 3.0-V power supply for the analog buffer DGND 3, 52, 60, 67 I Digital ground DVDD 8, 47 I Digital 1.9-V power supply IOVDD 4, 51, 57, 64, 70 I Digital 1.15-V power supply for the JESD204B transmitter 19, 20, 21 — 49 I NC, RES NC RES 6 Unused pins, do not connect Reserved pin. Connect to DGND. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range MIN MAX AVDD3V –0.3 3.6 AVDD –0.3 2.1 DVDD –0.3 2.1 IOVDD –0.2 1.4 Voltage between AGND and DGND Voltage applied to input pins V –0.3 0.3 INAP, INBP, INAM, INBM –0.3 3 CLKINP, CLKINM –0.3 AVDD + 0.3 SYSREFP, SYSREFM –0.3 AVDD + 0.3 SCLK, SEN, SDIN, RESET, SYNC, PDN –0.2 2.1 –65 150 Storage temperature, Tstg (1) UNIT V V °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) MIN NOM MAX 2.85 3.0 3.6 AVDD 1.8 1.9 2.0 DVDD 1.7 1.9 2.0 IOVDD 1.1 1.15 1.2 AVDD3V Supply voltage range Analog inputs 1.9 VPP Input common-mode voltage 2.0 V (3) (4) Input clock frequency, device clock frequency Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) LVPECL, ac-coupled 400 500 Input device clock duty cycle 1.5 0.8 1.6 (1) (2) (3) (4) (5) 50% –40 Operating junction, TJ MHz VPP 0.7 45% Operating free-air, TA MHz 1000 0.75 LVDS, ac-coupled Temperature V Differential input voltage range Maximum analog input frequency for 1.9-VPP input amplitude Clock inputs UNIT 55% 85 105 (5) 125 ºC SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details. After power-up, always use a hardware reset to reset the device for the first time; see Table 60 for details. Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs. At high frequencies, the maximum supported input amplitude reduces; see Figure 51 for details. Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 7 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 7.4 Thermal Information ADS54J69 THERMAL METRIC (1) RMP (VQFNP) UNIT 72 PINS RθJA Junction-to-ambient thermal resistance 22.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.1 °C/W RθJB Junction-to-board thermal resistance 2.4 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 2.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Electrical Characteristics typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1000 MSPS 500 MSPS GENERAL Device clock frequency Output sample rate Resolution 16 Bits POWER SUPPLIES AVDD3V 3.0-V analog supply 2.85 3.0 3.6 V AVDD 1.9-V analog supply 1.8 1.9 2.0 V DVDD 1.9-V digital supply 1.7 1.9 2.0 V IOVDD 1.15-V SERDES supply 1.1 1.15 1.2 V IAVDD3V 3.0-V analog supply current VIN = full-scale on both channels 293 360 mA IAVDD 1.9-V analog supply current VIN = full-scale on both channels 354 510 mA IDVDD 1.9-V digital supply current 188 260 mA IIOVDD 1.15-V SERDES supply current 512 920 mA Pdis Total power dissipation 2.66 3.1 IDVDD 1.9-V digital supply current 195 mA IIOVDD 1.15-V SERDES supply current 559 mA Pdis Total power dissipation 2.73 W Four-lane output mode (default after reset) Two-lane output mode Global power-down power dissipation 8 Using the GLOBAL PDN register bit in the master page Submit Documentation Feedback 204 315 W mW Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 7.6 AC Characteristics typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS Signal-to-noise ratio fIN = 140 MHz, AIN = –1 dBFS 73.4 Noise spectral density 71.3 72.7 fIN = 310 MHz, AIN = –1 dBFS 71.7 fIN = 370 MHz, AIN = –1 dBFS 70.3 fIN = 470 MHz, AIN = –3 dBFS 70.5 fIN = 10 MHz, AIN = –1 dBFS 158.2 fIN = 140 MHz, AIN = –1 dBFS 157.4 155.3 156.7 fIN = 310 MHz, AIN = –1 dBFS 155.7 fIN = 370 MHz, AIN = –1 dBFS 154.3 fIN = 470 MHz, AIN = –3 dBFS 154.5 fIN = 10 MHz, AIN = –1 dBFS 73.8 fIN = 170 MHz, AIN = –1 dBFS SINAD Signal-to-noise and distortion ratio 72.5 71.2 fIN = 370 MHz, AIN = –1 dBFS 70.2 fIN = 470 MHz, AIN = –3 dBFS 69.4 95 79 89 fIN = 310 MHz, AIN = –1 dBFS 81 fIN = 370 MHz, AIN = –1 dBFS 87 fIN = 470 MHz, AIN = –3 dBFS 73 fIN = 10 MHz, AIN = –1 dBFS 86 fIN = 140 MHz, AIN = –1 dBFS HD2 Second-order harmonic distortion Third-order harmonic distortion 102 95 fIN = 310 MHz, AIN = –1 dBFS 81 fIN = 370 MHz, AIN = –1 dBFS 87 fIN = 470 MHz, AIN = –3 dBFS 96 fIN = 10 MHz, AIN = –1 dBFS 89 fIN = 140 MHz, AIN = –1 dBFS 103 86 100 fIN = 310 MHz, AIN = –1 dBFS 98 fIN = 370 MHz, AIN = –1 dBFS 95 fIN = 470 MHz, AIN = –3 dBFS 73 Submit Documentation Feedback Product Folder Links: ADS54J69 dBc 101 fIN = 210 MHz, AIN = –1 dBFS Copyright © 2015–2017, Texas Instruments Incorporated dBc 104 85 fIN = 210 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS HD3 94 fIN = 210 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS dBFS 86 fIN = 140 MHz, AIN = –1 dBFS Spurious free dynamic range (excluding IL spurs) dBFS/Hz 72.9 fIN = 310 MHz, AIN = –1 dBFS fIN = 10 MHz, AIN = –1 dBFS SFDR dBFS 73.3 69.8 fIN = 210 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS UNIT 157.0 fIN = 210 MHz, AIN = –1 dBFS fIN = 140 MHz, AIN = –1 dBFS MAX 73 fIN = 210 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS NSD TYP 74.2 fIN = 170 MHz, AIN = –1 dBFS SNR MIN fIN = 10 MHz, AIN = –1 dBFS dBc 9 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com AC Characteristics (continued) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS Spurious-free dynamic range (excluding HD2, HD3, and IL spur) fIN = 140 MHz, AIN = –1 dBFS 95 84 89 fIN = 310 MHz, AIN = –1 dBFS 92 fIN = 370 MHz, AIN = –1 dBFS 97 fIN = 470 MHz, AIN = –3 dBFS 92 fIN = 10 MHz, AIN = –1 dBFS 12 fIN = 170 MHz, AIN = –1 dBFS Effective number of bits 11.8 11.5 fIN = 370 MHz, AIN = –1 dBFS 11.4 fIN = 470 MHz, AIN = –3 dBFS 11.2 95 79 85 fIN = 310 MHz, AIN = –1 dBFS 80 fIN = 370 MHz, AIN = –1 dBFS 85 fIN = 470 MHz, AIN = –3 dBFS 72 fIN = 10 MHz, AIN = –1 dBFS 90 fIN = 140 MHz, AIN = –1 dBFS SFDR_IL IMD3 10 Interleaving spur Two-tone, third-order intermodulation distortion 89 fIN = 210 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS dBc 90 75 87 fIN = 210 MHz, AIN = –1 dBFS 85 fIN = 310 MHz, AIN = –1 dBFS 85 fIN = 370 MHz, AIN = –1 dBFS 86 fIN = 470 MHz, AIN = –3 dBFS 82 fIN1 = 185 MHz, fIN2 = 190 MHz, AIN = –7 dBFS 86 fIN1 = 365 MHz, fIN2 = 370 MHz, AIN = –7 dBFS 79 fIN1 = 465 MHz, fIN2 = 470 MHz, AIN = –10 dBFS 78 Submit Documentation Feedback Bits 84 fIN = 140 MHz, AIN = –1 dBFS Total harmonic distortion dBc 11.9 fIN = 310 MHz, AIN = –1 dBFS fIN = 10 MHz, AIN = –1 dBFS THD UNIT 11.9 11.3 fIN = 210 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS MAX 94 fIN = 210 MHz, AIN = –1 dBFS fIN = 140 MHz, AIN = –1 dBFS ENOB TYP 98 fIN = 170 MHz, AIN = –1 dBFS Non HD2, HD3 MIN fIN = 10 MHz, AIN = –1 dBFS dBc dBFS Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 7.7 Digital Characteristics typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN) TEST CONDITIONS MIN 0.8 VIH High-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels VIL Low-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels IIH High-level input current IIL Low-level input current TYP MAX UNITS (1) V 0.4 SEN 0 RESET, SCLK, SDIN, PDN, SYNC 50 SEN 50 RESET, SCLK, SDIN, PDN, SYNC V µA µA 0 DIGITAL INPUTS (SYSREFP, SYSREFM) VD Differential input voltage V(CM_DIG) Common-mode voltage for SYSREF (2) 0.35 0.45 1.4 V 1.3 V DVDD V DIGITAL OUTPUTS (SDOUT, PDN (3)) VOH High-level output voltage VOL Low-level output voltage DVDD – 0.1 0.1 V DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM) (4) VOD Output differential voltage VOC Output common-mode voltage Transmitter short-circuit current zos (2) (3) (4) Transmitter pins shorted to any voltage between –0.25 V and 1.45 V Single-ended output impedance Output capacitance (1) With default swing setting Output capacitance inside the device, from either output to ground 700 mVPP 450 mV –100 100 mA 50 Ω 2 pF The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ (typical) pullup resistor to IOVDD. The SYSREFP and SYSREFM pins are internally biased to the 1.3-V common-mode voltage through a 5-kΩ resistor. When functioning as an OVR pin for channel B. 100-Ω differential termination. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 11 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 7.8 Timing Characteristics typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) MIN TYP MAX UNITS SAMPLE TIMING Aperture delay 0.75 Aperture delay matching between two channels on the same device Aperture delay matching between two devices at the same temperature and supply voltage Aperture jitter 1.6 ns ±70 ps ±270 ps Actual jitter of sampling clock buffer 145 Effective jitter after decimation filtering 102 fS rms WAKE-UP TIMING Wake-up time to valid data after coming out of global power-down 150 µs LATENCY Data latency (1): ADC sample to digital output OVR latency: ADC sample to OVR bit FOVR latency: ADC sample to FOVR signal on pin tPD Propagation delay: logic gates and output buffers delay (does not change with fS) 134 (2) Input clock cycles 62 Input clock cycles 18 + 4 ns Input clock cycles 4 ns SYSREF TIMING tSU_SYSREF Setup time for SYSREF, referenced to the input clock falling edge 300 tH_SYSREF Hold time for SYSREF, referenced to the input clock falling edge 100 900 ps ps JESD OUTPUT INTERFACE TIMING CHARACTERISTICS Unit interval 100 400 ps Serial output data rate 2.5 10 Gbps Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 Random jitter for BER of 1E-15 and lane rate = 10 Gbps tR, tF (1) (2) 0.75 ps ps rms Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk Data rise time, data fall time: rise and fall times are measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps 35 ps Overall latency = data latency + decimation filter delay + tPDI. Decimation filter latency is not included in this specification. Sample N ts_min ts_max CLKIN 1.0 GSPS SYSREF Figure 1. SYSREF Timing 12 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 N+1 N+2 N N+3 Sample tPD Data Latency: 134 Clock Cycles CLKINM CLKINP DA0P, DA0M, DB0P, DB0M D20 Sample N-1 DA1P, DA1M, DB1P, DB1M Sample N-1 D11 D20 Sample N D10 D11 D20 Sample N+1 D1 D10 Sample N Sample N+2 D1 Sample N+1 D10 Sample N+2 Figure 2. Sample Timing Requirements Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 13 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 7.9 Typical Characteristics 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 50 100 150 Input Frequency (MHz) 200 0 250 SNR = 74.2 dBFS; SFDR = 86 dBc; SINAD = 73.8 dBFS; THD = 83 dBc; HD2 = 86 dBc; HD3 = 89 dBc; IL spur = 99 dBc; non HD2, HD3 spur = 98 dBc 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) 200 250 D002 Figure 4. FFT for 140-MHz Input Signal 0 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 50 100 150 Input Frequency (MHz) 200 250 0 50 D003 SNR = 73 dBFS; SFDR = 93 dBc; SINAD = 73.18 dBFS; THD = 89 dBc; HD2 = 93 dBc; HD3 = 103 dBc; IL spur = 99 dBc; non HD2, HD3 spur = 94 dBc -20 -20 Amplitude (dBFS) 0 -60 -80 -100 200 250 D004 Figure 6. FFT for 210-MHz Input Signal 0 -40 100 150 Input Frequency (MHz) SNR = 72.8 dBFS; SFDR = 89 dBc; SINAD = 72.63 dBFS; THD = 86 dBc; HD2 = 97 dBc; HD3 = 99 dBc; IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc Figure 5. FFT for 170-MHz Input Signal Amplitude (dBFS) 100 150 Input Frequency (MHz) SNR = 73.3 dBFS; SFDR = 94 dBc; SINAD = 73.25 dBFS; THD = 93 dBc; HD2 = 104 dBc; HD3 = 111 dBc; IL spur = 95 dBc; non HD2, HD3 spur = 94 dBc Figure 3. FFT for 10-MHz Input Signal -40 -60 -80 -100 -120 -120 0 50 100 150 Input Frequency (MHz) 200 250 0 D005 SNR = 71.6 dBFS; SFDR = 80 dBc; SINAD = 71 dBFS; THD = 79 dBc; HD2 = –80 dBc; HD3 = –96 dBc; IL spur = 85 dBc; non HD2, HD3 spur = 92 dBc 50 100 150 Input Frequency (MHz) 200 250 D007 SNR = 70.5 dBFS; SFDR = 86 dBc; SINAD = 70.4 dBFS; THD = 85 dBc; HD2 = –86 dBc; HD3 = –96 dBc; IL spur = 98 dBc; non HD2, HD3 spur = 98 dBc Figure 7. FFT for 310-MHz Input Signal 14 50 D001 Submit Documentation Feedback Figure 8. FFT for 370-MHz Input Signal Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Typical Characteristics (continued) 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) -40 -60 -80 -100 -80 -120 0 50 100 150 Input Frequency (MHz) 200 250 0 50 D007 SNR = 70.6 dBFS; SFDR = 86 dBc; SINAD = 70.55 dBFS; THD = 85 dBc; tone at –3 dBFS; HD2 = 102 dBc; HD3 = 86 dBc; IL spur = 97 dBc; non HD2, HD3 spur = 96 dBc Figure 9. FFT for 470-MHz Input Signal 0 -20 -20 -60 -80 200 250 D008 Figure 10. FFT for Two-Tone Input Signal (–7 dBFS) 0 -40 100 150 Input Frequency (MHz) fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS, IMD = 86 dBFS Amplitude (dBFS) Amplitude (dBFS) -60 -100 -120 -100 -40 -60 -80 -100 -120 -120 0 50 100 150 Input Frequency (MHz) 200 250 0 50 D009 fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS, IMD = 101 dBFS Figure 11. FFT for Two-Tone Input Signal (–36 dBFS) 0 -20 -20 -60 -80 200 250 D010 Figure 12. FFT for Two-Tone Input Signal (–7 dBFS) 0 -40 100 150 Input Frequency (MHz) fIN1 = 300 MHz, fIN2 = 310 MHz, each tone at –7 dBFS, IMD = 79 dBFS Amplitude (dBFS) Amplitude (dBFS) -40 -40 -60 -80 -100 -100 -120 -120 0 50 100 150 Input Frequency (MHz) 200 250 0 D011 fIN1 = 300 MHz, fIN2 = 310 MHz, each tone at –36 dBFS, IMD3 = 102 dBFS Figure 13. FFT for Two-Tone Input Signal (–36 dBFS) 50 100 150 Input Frequency (MHz) 200 250 D012 fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –10 dBFS, IMD = 78 dBFS Figure 14. FFT for Two-Tone Input Signal (–10 dBFS) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 15 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) 0 -80 -20 -85 -40 -90 IMD (dBFS) Amplitude (dBFS) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) -60 -95 -80 -100 -100 -105 -110 -35 -120 0 50 100 150 Input Frequency (MHz) 200 250 D013 -75 -50 -80 -60 -85 -7 D014 -70 IMD (dBFS) IMD (dBFS) -11 Figure 16. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) Figure 15. FFT for Two-Tone Input Signal (–36 dBFS) -90 -95 -80 -90 -100 -100 -105 -110 -35 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -30 D015 fIN1 = 300 MHz, fIN2 = 310 MHz -25 -20 -15 Each Tone Amplitude (dBFS) -10 D016 fIN1 = 465 MHz, fIN2 = 470 MHz Figure 17. Intermodulation Distortion vs Input Amplitude (365 MHz and 370 MHz) Figure 18. Intermodulation Distortion vs Input Amplitude (465 MHz and 470 MHz) 100 100 AIN = -6 dBFS AIN = -3 dBFS AIN = -1 dBFS 95 fS/4 - fIN fS/2 - fIN 3fS/4 - fIN 95 Interleaving Spur (dBc) 90 SFDR (dBc) -27 -23 -19 -15 Each Tone Amplitude (dBFS) fIN1 = 185 MHz, fIN2 = 190 MHz fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –36 dBFS, IMD3 = 104 dBFS 85 80 75 70 90 85 80 75 65 70 60 0 100 200 300 400 500 Input Frequency (MHz) 600 700 0 D017 Figure 19. Spurious-Free Dynamic Range vs Input Frequency 16 -31 Submit Documentation Feedback 100 200 300 400 500 Input Frequency (MHz) 600 700 D018 Figure 20. IL Spur vs Input Frequency Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Typical Characteristics (continued) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) 75 75 AIN = -6 dBFS AIN = -3 dBFS AIN = -1 dBFS 74 AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 74.5 AVDD = 1.95 V AVDD = 2 V SNR (dBFS) SNR (dBFS) 74 73 72 71 73.5 73 72.5 72 70 71.5 71 -40 69 0 100 200 300 400 500 Input Frequency (MHz) 600 700 -15 D019 10 35 Temperature (°C) 60 85 D020 fIN = 185 MHz Figure 21. Signal-to-Noise Ratio vs Input Frequency Figure 22. Signal-to-Noise Ratio vs AVDD Supply and Temperature 74 98 AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 96 AVDD = 1.95 V AVDD = 2 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 73.5 AVDD = 1.95 V AVDD = 2 V SNR (dBFS) SFDR (dBc) 73 94 92 90 72.5 72 71.5 71 88 86 -40 70.5 -15 10 35 Temperature (°C) 60 70 -40 85 -15 D021 fIN = 185 MHz 10 35 Temperature (°C) 60 85 D022 fIN = 300 MHz Figure 23. Spurious-Free Dynamic Range vs AVDD Supply and Temperature Figure 24. Signal-to-Noise Ratio vs AVDD Supply and Temperature 75 85 AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 84 AVDD = 1.95 V AVDD = 2 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V 74.5 DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V SNR (dBFS) SFDR (dBc) 74 83 82 81 73.5 73 72.5 72 80 79 -40 71.5 -15 10 35 Temperature (°C) 60 85 71 -40 D023 fIN = 300 MHz -15 10 35 Temperature (°C) 60 85 D024 fIN = 185 MHz Figure 25. Spurious-Free Dynamic Range vs AVDD Supply and Temperature Figure 26. Signal-to-Noise Ratio vs DVDD Supply and Temperature Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 17 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) 75 96 DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V 74.5 74 DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V 94 SNR (dBFS) SFDR (dBc) 73.5 92 73 72.5 72 71.5 90 71 70.5 88 -40 -15 10 35 Temperature (°C) 60 70 -40 85 -15 D025 fIN = 185 MHz 60 85 D026 fIN = 300 MHz Figure 27. Spurious-Free Dynamic Range vs DVDD Supply and Temperature Figure 28. Signal-to-Noise Ratio vs DVDD Supply and Temperature 75.5 86 DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V 75 74.5 SNR (dBFS) 84 SFDR (dBc) 10 35 Temperature (°C) 82 AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V 74 73.5 73 72.5 80 72 78 -40 -15 10 35 Temperature (°C) 60 71.5 -40 85 -15 D027 fIN = 300 MHz 60 85 D028 fIN = 185 MHz Figure 29. Spurious-Free Dynamic Range vs DVDD Supply and Temperature Figure 30. Signal-to-Noise Ratio vs AVDD3V Supply and Temperature 74 96 AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V 73.5 73 SNR (dBFS) 94 SFDR (dBc) 10 35 Temperature (°C) 92 AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V 72.5 72 71.5 71 90 70.5 88 -40 -15 10 35 Temperature (°C) 60 85 70 -40 D029 10 35 Temperature (°C) 60 85 D030 fIN = 300 MHz fIN = 185 MHz Figure 31. Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature 18 -15 Submit Documentation Feedback Figure 32. Signal-to-Noise Ratio vs AVDD3V Supply and Temperature Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Typical Characteristics (continued) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) 83 84 AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V Gain = 0 dB Gain = 2 dB Gain = 4 dB 80 Gain = 6 dB Gain = 8 dB Gain = 10 dB Gain = 12 dB 77 SNR (dBFS) SFDR (dBc) 83 AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V 82 74 71 68 65 81 62 80 -40 59 -15 10 35 Temperature (°C) 60 0 85 80 D031 160 240 320 Input Frequency (MHz) 400 480 D032 fIN = 300 MHz Figure 33. Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature Figure 34. Signal-to-Noise Ratio vs Gain and Input Frequency 110 120 Gain = 0 dB Gain = 2 dB Gain = 4 dB 105 Gain = 12 dB 110 95 Gain = 6 dB Gain = 8 dB Gain = 10 dB Gain = 12 dB 105 90 85 100 95 80 90 75 85 70 80 65 75 0 80 160 240 320 Input Frequency (MHz) 400 480 0 80 D033 Figure 35. Spurious-Free Dynamic Range vs Gain and Input Frequency 160 240 320 Input Frequency (MHz) 400 480 D034 Figure 36. Second-Order Harmonic Distortion vs Gain and Input Frequency 125 115 Gain = 0 dB Gain = 2 dB Gain = 4 dB Gain = 6 dB Gain = 8 dB Gain = 10 dB Gain = 12 dB Gain = 0 dB Gain = 2 dB Gain = 4 dB 110 Interleaving Spur (dBc) 115 105 HD3 (dBc) Gain = 0 dB Gain = 2 dB Gain = 4 dB 115 HD2 (dBc) SFDR (dBc) 100 Gain = 6 dB Gain = 8 dB Gain = 10 dB 95 85 75 Gain = 6 dB Gain = 8 dB Gain = 10 dB Gain = 12 dB 105 100 95 90 85 65 80 0 80 160 240 320 Input Frequency (MHz) 400 480 0 D035 Figure 37. Third-Order Harmonic Distortion vs Gain and Input Frequency 80 160 240 320 Input Frequency (MHz) 400 480 D036 Figure 38. IL Spur vs Gain and Input Frequency Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 19 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) 74 120 72 80 70 77 SNR (dBFS) 76 200 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 160 SFDR (dBc,dBFS) 40 68 -70 75.5 180 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 150 74 120 72.5 90 71 60 69.5 30 0 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 68 -70 0 0 -60 -40 -30 Amplitude (dBFS) D037 fIN = 185 MHz -20 Figure 39. Performance vs Amplitude D038 Figure 40. Performance vs Amplitude fS / 4 - fIN fS / 2 - fIN 3fS / 4 - fIN Interleaving Spur (dBc) 100 90 80 70 60 50 100 90 80 70 60 50 40 40 30 -70 30 -70 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 fS / 4 - fIN fS / 2 - fIN 3fS / 4 - fIN 110 0 -60 D039 fIN = 185 MHz -50 -40 -30 Amplitude (dBFS) -20 Figure 41. IL Spur vs Amplitude 120 76 100 74 90 72 80 70 70 60 2.2 SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) D040 80 SNR SFDR 1 1.4 1.8 Differential Clock Amplitude (VPP) 0 Figure 42. IL Spur vs Amplitude 110 0.6 -10 fIN = 310 MHz 78 77 100 74 80 71 60 68 40 65 0.2 D041 fIN = 185 MHz 0.6 1 1.4 1.8 Differential Clock Amplitude (VPP) 20 2.2 D042 fIN = 310 MHz Figure 43. Performance vs Differential Clock Amplitude 20 0 120 110 68 0.2 -10 fIN = 310 MHz 120 Interleaving Spur (dBc) -50 SFDR (dBc) SNR (dBFS) 78 SFDR (dBc,dBFS) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) Figure 44. Performance vs Differential Clock Amplitude Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Typical Characteristics (continued) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) 100 75 90 75 95 74 90 73 85 72 80 71 35 40 45 50 55 Input Clock Duty Cycle (%) 60 75 65 SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 74 85 73 80 72 75 71 70 70 30 35 D043 fIN = 185 MHz 55 65 60 D044 fIN = 300 MHz Figure 45. Performance vs Input Clock Duty Cycle Figure 46. Performance vs Input Clock Duty Cycle 0 -10 -20 -20 -40 -30 PSRR (dB) Amplitude (dBFS) 40 45 50 Input Clock Duty Cycle (%) SFDR (dBc) 76 -60 PSRR with 50-mVPP Signal on AVDD PSRR with 50-mVPP Signal on AVDD3V -40 -50 -80 -60 -100 -70 -120 0 50 100 150 Input Frequency (MHz) 200 0 250 D045 50 100 150 200 250 Frequency of Signal on Supply (MHz) 300 D046 fIN = 185 MHz AIN = –1 dBFS, SFDR = 84 dBc, SINAD = 70 dBFS, fPSRR = 5 MHz, APSRR = 50 mVPP, fIN = 185 MHz, amplitude: fIN – fPSRR = 85 dBc, fIN + fPSRR = 84 dBc Figure 48. Power-Supply Rejection Ratio vs Noise Signal Frequency Figure 47. Power-Supply Rejection Ratio FFT for AVDD Supply -20 0 -25 -20 CMRR (dB) Amplitude (dBFS) -30 -40 -60 -35 -40 -45 -80 -50 -100 -55 -60 -120 0 50 100 150 Input Frequency (MHz) 200 250 0 D047 300 D048 fIN = 185 MHz AIN = –1 dBFS, SFDR = 78 dBc, SINAD = 71 dBFS, fCMRR = 5 MHz, ACMRR = 50 mVPP, fIN = 185 MHz, amplitude: fIN – fCMRR = 79 dBc, fIN + fCMRR = 80 dBc Figure 49. Common-Mode Rejection Ratio FFT 50 100 150 200 250 Frequency of Input Common-Mode Signal (MHz) Figure 50. Common-Mode Rejection Ratio vs Common-Mode Signal Frequency Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 21 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) 4 0 Power Consumption (W) Fundamental Amplitude (dBFS) 2 -2 -4 -6 -8 -10 0 100 200 300 400 500 600 700 Input Frequency (MHz) 800 AVDD DVDD AVDD3V 3.2 2.4 1.6 0.8 0 250 900 1000 300 D049 Figure 51. Maximum-Supported Amplitude vs Input Frequency IOVDD TOTAL POWER 350 400 450 Output Sample Rate (MSPS) 500 D050 Figure 52. Power Consumption vs Sampling Speed 76 105 AIN = -3 dBFS AIN = -1 dBFS 75 AIN = -3 dBFS AIN = -1 dBFS 100 SFDR (dBc) SNR (dBFS) 95 74 73 72 90 85 80 75 71 70 70 65 0 100 200 300 400 Input Frequency (MHz) 500 600 0 100 D051 Figure 53. Signal-to-Noise Ratio vs Input Frequency (Output Sample Rate = 300 MSPS) 200 300 400 Input Frequency (MHz) 500 600 D052 Figure 54. Spurious-Free Dynamic Range vs Input Frequency (Output Sample Rate = 300 MSPS) 105 76 AIN = -3 dBFS AIN = -1 dBFS 75 AIN = -3 dBFS AIN = -1 dBFS 100 SFDR (dBc) SNR (dBFS) 95 74 73 72 90 85 80 75 71 70 65 70 0 100 200 300 400 Input Frequency (MHz) 500 600 Figure 55. Signal-to-Noise Ratio vs Input Frequency (Output Sample Rate = 350 MSPS) 22 0 D053 100 200 300 400 Input Frequency (MHz) 500 600 D054 Figure 56. Spurious-Free Dynamic Range vs Input Frequency (Output Sample Rate = 350 MSPS) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Typical Characteristics (continued) typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency = 1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted) 105 76 75 101 74 SFDR (dBc) SNR (dBFS) AIN = -3 dBFS AIN = -1 dBFS AIN = -3 dBFS AIN = -1 dBFS 73 97 93 72 89 71 85 70 0 100 200 300 Input Frequency (MHz) 400 500 0 D055 Figure 57. Signal-to-Noise Ratio vs Input Frequency (Output Sample Rate = 400 MSPS) 100 200 300 Input Frequency (MHz) 400 500 D056 Figure 58. Spurious-Free Dynamic Range vs Input Frequency (Output Sample Rate = 400 MSPS) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 23 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8 Detailed Description 8.1 Overview The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). The ADS54J69 employs four interleaving ADCs for each channel to achieve a noise floor of –159 dBFS/Hz. The ADS54J69 uses TI's proprietary interleaving and dither algorithms to achieve a clean spectrum with high spurious-free dynamic range (SFDR). Built-in, half-band, decimate-by-2 filters further enhance the capability of the ADS54J69 to deliver excellent signal-to-noise ratio (SNR) and SFDR over a wide range of frequencies. Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby simplify the driving network on-board. The JESD204B interface reduces the number of interface lines with two-lane and four-lane options, allowing a high system integration density. The JESD204B interface operates in subclass-1, enabling multi-chip synchronization with the SYSREF input. 8.2 Functional Block Diagram DDC Block DA0P, DA0M, DA1P, DA1M Buffer PLL: x20 x40 Divideby-4 CLKINP, CLKINM DA2P, DA2M, DA3P, DA3M 2 SYSREFP, SYSREFM JESD204B Interface ADC ADC ADC ADC INAP, INAM 2 Interleaving Correction, Digital Gain SYNC DDC Block Buffer ADC ADC ADC ADC INBP, INBM 2 Interleaving Correction, Digital Gain 2 DB0P, DB0M, DB1P, DB1M DB2P, DB2M, DB3P, DB3M FOVR 24 SCLK SEN SDIN RESET PDN CommonMode SDOUT VCM Control and SPI Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.3 Feature Description 8.3.1 Analog Inputs The ADS54J69 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source that enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more constant SFDR performance across input frequencies. The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for accoupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in Figure 59. 0.77 : 2 nH 0.6 : 500 fF 150 fF 150 fF 1: 200 fF 3.3 : 3 pF 375 fF INP 40 : 0.77 : 1: 150 fF 200 fF 3.3 : 600 : 3 pF 375 fF VCM 40 : 600 : 0.77 : 150 fF 2 nH 0.6 : 500 fF 150 fF 1: 200 fF 3.3 : 3 pF 375 fF INM 40 : 0.77 : 1: 150 fF 200 fF 3.3 : 3 pF 375 fF 40 : Figure 59. Analog Input Network Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 25 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Feature Description (continued) The input bandwidth shown in Figure 60 is measured with respect to a 50-Ω differential input termination at the ADC input pins. 0 Transfer Function (dB) -3 -6 -9 -12 -15 -18 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Input Frequency (MHz) D057 Figure 60. Transfer Function versus Frequency 8.3.2 DDC Block The ADS54J69 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is followed by a DDC block consisting of a decimate-by-2, half-band, finite impulse response (FIR) filter with lowpass and high-pass options programmable via the SPI interface. 8.3.2.1 Decimate-by-2 Filter This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 1 shows corner frequencies for the low-pass and high-pass filter options. Table 1. Corner Frequencies for the Decimate-by-2 Filter CORNERS (dB) LOW PASS HIGH PASS –0.1 0.202 × fS 0.298 × fS –0.5 0.210 × fS 0.290 × fS –1 0.215 × fS 0.285 × fS –3 0.227 × fS 0.273 × fS Figure 61 and Figure 62 show the frequency response of the decimate-by-2 filter from dc to fS / 2. 5 0.5 0 -20 Magnitude (dB) Magnitude (dB) -0.5 -45 -70 -1 -1.5 -2 -95 -2.5 -120 -3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency Response 0.4 0.45 0.5 Figure 61. Decimate-by-2 Filter Response 26 0 D013 0.05 0.1 0.15 Frequency Response 0.2 0.25 D014 Figure 62. Decimate-by-2 Filter Response (Zoomed) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.3.3 SYSREF Signal The SYSREF signal is a periodic signal that is sampled by the ADS54J69 device clock and used to align the boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of the local multi-frame clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and frames per multi-frame settings. The SYSREF signal is recommended be a low-frequency signal in the range of 1 MHz to 5 MHz in order to reduce coupling to the signal path both on the printed circuit board (PCB) as well as internal in the device. The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and Table 2. SYSREF = LMFC / 2N where • N = 0, 1, 2, and so forth (1) Table 2. LMFC Clock Frequency (1) (2) LMFS CONFIGURATION DECIMATION LMFC CLOCK (1) (2) 4222 2X (fS / 4) / k 2242 2X (fS / 4) / k K = Number of frames per multi-frame (JESD digital page 6900h, address 06h, bits 4-0). fS = sampling (device) clock frequency. 8.3.3.1 SYSREF Not Present (Subclass 0, 2) A SYSREF pulse is required by the ADS54J69 to reset internal counters. If SYSREF is not present, as can be the case in subclass 0 or 2, this pulse can be done by doing the following register writes shown in Table 3. Table 3. Internally Pulsing SYSREF Twice Using Register Writes ADDRESS (Hex) DATA (Hex) COMMENT 0-011h 80h Set the master page 0-054h 80h Enable manual SYSREF 0-053h 01h Set SYSREF high 0-053h 00h Set SYSREF low 0-053h 01h Set SYSREF high 0-053h 00h Set SYSREF low 8.3.4 Overrange Indication The ADS54J69 provides a fast overrange indication that can be presented in the digital output data stream via an SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured via the SPI to output the fast overrange (FOVR) indicator. When the FOVR indication is embedded in the output data stream, the FOVR replaces the LSB of the 16-bit data stream going to the 8b/10b encoder, as shown in Figure 63. 16-Bit Data Output D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0/ OVR 16-Bit Data Going to 8b/10b Encoder Figure 63. Overrange Indication in a Data Stream Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 27 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.3.4.1 Fast OVR The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after only 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns), thus enabling a quicker reaction to an overrange event. The input voltage level at which the overload is detected is referred to as the threshold. The threshold is programmable using the FOVR THRESHOLD bits, as shown in Figure 64. The FOVR is triggered 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns) after the overload condition occurs. 0 FOVR Threshold (dBFS) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0 32 64 96 128 160 192 Threshold Decimal Value 224 255 D055 Figure 64. Programming Fast OVR Thresholds The input voltage level at which the fast OVR is triggered is defined by Equation 2: Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255) (2) The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS. In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3: 20log (FOVR Threshold / 255) 28 (3) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.3.5 Power-Down Mode The ADS54J69 provides a highly-configurable power-down mode. Power-down can be enabled by using the PDN pin or via SPI register writes. A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in Table 4. See the master page registers in Table 10 for further details. Table 4. Register Address for Power-Down Modes REGISTER ADDRESS REGISTER DATA COMMENT A[7:0] (Hex) 7 6 5 4 3 2 0 0 1 0 MASTER PAGE (80h) 20 21 23 24 MASK 1 MASK 2 PDN ADC CHA PDN BUFFER CHB PDN ADC CHA PDN BUFFER CHB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDN MASK 0 0 0 0 OVERRIDE PDN PIN PDN MASK SEL 53 0 MASK SYSREF 55 0 0 CONFIG 0 PDN ADC CHB PDN BUFFER CHA GLOBAL PDN 26 PDN ADC CHB PDN BUFFER CHA To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However, when the JESD link is required to be active during power-down, the ADC and analog buffer can be selectively powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 5 shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx register bits. Table 5. Power Consumption in Different Power-Down Settings REGISTER BIT COMMENT IAVDD3V (mA) IAVDD (mA) IDVDD (mA) IIOVDD (mA) TOTAL POWER (W) Default After reset, with a full-scale input signal to both channels 346 354 188 512 2.66 GBL PDN = 1 The device is in a complete power-down state 3 6 21 127 0.2 GBL PDN = 0, PDN ADC CHx = 1 (x = A or B) The ADC of one channel is powered down 284 221 130 461 2.05 GBL PDN = 0, PDN BUFF CHx = 1 (x = A or B) The input buffer of one channel is powered down 270 352 188 516 2.43 GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = A or B) The ADC and input buffer of one channel are powered down 206 220 129 465 1.82 GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = A and B) The ADC and input buffer of both channels are powered down 64 84 67 389 0.93 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 29 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.4 Device Functional Modes 8.4.1 Device Configuration The ADS54J69 can be configured by using a serial programming interface, as described in the Serial Interface section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode. The ADS54J69 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register Maps section) to access all register bits. 8.4.1.1 Serial Interface The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 65. Legends used in Figure 65 are explained in Table 6. Serially shifting bits into the device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with SCLK frequencies from 2 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle. Register Address[11:0] SDIN R/W M P CH A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 65. SPI Timing Diagram Table 6. SPI Timing Diagram Legend SPI BITS BIT SETTINGS Read/write bit 0 = SPI write 1 = SPI read back M SPI bank access 0 = Analog SPI bank (master and ADC pages) 1 = JESD SPI bank (main digital, analog JESD, and digital JESD pages) P JESD page selection bit 0 = Page access 1 = Register access SPI access for a specific channel of the JESD SPI bank 0 = Channel A 1 = Channel B By default, both channels are being addressed. A[11:0] SPI address bits — D[7:0] SPI data bits — R/W CH 30 DESCRIPTION Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Table 7 shows the timing requirements for the serial interface signals in Figure 65. Table 7. SPI Timing Requirements MIN TYP MAX UNIT 2 MHz fSCLK SCLK frequency (equal to 1 / tSCLK) > dc tSLOADS SEN to SCLK setup time 100 ns tSLOADH SCLK to SEN hold time 100 ns tDSU SDIN setup time 100 ns tDH SDIN hold time 100 ns 8.4.1.2 Serial Register Write: Analog Bank The analog SPI bank contains two pages (the master and ADC page). The internal register of the ADS54J69 analog SPI bank can be programmed by: 1. Driving the SEN pin low. 2. Initiating a serial interface cycle specifying the page address of the register whose content must be written. – Master page: write address 0011h with 80h. – ADC page: write address 0011h with 0Fh. 3. Writing the register content, as shown in Figure 66. When a page is selected, multiple writes into the same page can be done. SDIN 0 0 0 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET Figure 66. Serial Register Write Timing Diagram Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 31 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.4.1.3 Serial Register Readout: Analog Bank The content from one of the two analog banks can be read out by: 1. Driving the SEN pin low. 2. Selecting the page address of the register whose content must be read. – Master page: write address 0011h with 80h. – ADC page: write address 0011h with 0Fh. 3. Setting the R/W bit to 1 and writing the address to be read back. 4. Reading back the register content on the SDOUT pin, as shown in Figure 67. When a page is selected, multiple read backs from the same page can be done. SDIN 1 0 0 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] = XX A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET SDOUT SDOUT[7:0] Figure 67. Serial Register Read Timing Diagram 8.4.1.4 JESD Bank SPI Page Selection The JESD SPI bank contains four pages (main digital, digital, and analog JESD pages). The individual pages can be selected by: 1. Driving the SEN pin low. 2. Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as shown in Figure 68. – Write address 4003h with 00h (LSB byte of page address). – Write address 4004h with the MSB byte of the page address. – For the main digital page: write address 4004h with 68h. – For the digital JESD page: write address 4004h with 69h. – For the analog JESD page: write address 4004h with 6Ah. SDIN 0 1 0 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET Figure 68. SPI Page Selection 32 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.4.1.5 Serial Register Write: JESD Bank The ADS54J69 is a dual-channel device and the JESD204B portion is configured individually for each channel by using the CH bit. Note that the P bit must be set to 1 for register writes. 1. Drive the SEN pin low. 2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0. – Write address 4003h with 00h. – If separate control for both channels is desired, write address 4005h with 01h. – For the main digital page: write address 4004h with 68h. – For the digital JESD page: write address 4004h with 69h. – For the analog JESD page: write address 4004h with 6Ah. 3. Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as shown in Figure 69. When a page is selected, multiple writes into the same page can be done. SDIN 0 1 1 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET Figure 69. JESD Serial Register Write Timing Diagram 8.4.1.5.1 Individual Channel Programming By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h with 01h (default is 00h). 8.4.1.6 Serial Register Readout: JESD Bank The content from one of the pages of the JESD bank can be read out by: 1. Driving the SEN pin low. 2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0. – Write address 4003h with 00h. – If separate control for both channels is desired, write address 4005h with 01h. – For the main digital page: write address 4004h with 68h. – For the digital JESD page: write address 4004h with 69h. – For the analog JESD page: write address 4004h with 6Ah. 3. Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read back. 4. Reading back the register content on the SDOUT pin; see Figure 70. When a page is selected, multiple read backs from the same page can be done. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 33 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 SDIN 1 1 1 0 R/W M P CH www.ti.com Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] = XX A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET SDOUT SDOUT[7:0] Figure 70. JESD Serial Register Read Timing Diagram 8.4.2 JESD204B Interface The ADS54J69 supports device subclass 1 with a maximum output data rate of 10.0 Gbps for each serial transmitter. An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and alignment uncertainty. The SYNC input is used to control the JESD204B SERDES blocks. Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four active lanes (out of total 8 lanes), as shown in Figure 71. The JESD204B setup and configuration of the frame assembly parameters is controlled via the SPI interface. SYSREF SYNC INA JESD204B JESD204B DA[3:0] INB JESD204B JESD204B DB[3:0] Sample Clock Figure 71. ADS54J69 Block Diagram 34 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 The JESD204B transmitter block shown in Figure 72 consists of the transport layer, the data scrambler, and the link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport layer can be scrambled. JESD204B Block Transport Layer Link Layer 8b, 10b Encoding Frame Data Mapping Scrambler 1 + x14 + x15 D[3:0] Comma Characters, Initial Lane Alignment SYNC Figure 72. JESD204B Transmitter Block 8.4.2.1 JESD204B Initial Lane Alignment (ILA) The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in Figure 73. When a logic low is detected on the SYNC input pin, the ADS54J69 starts transmitting comma (K28.5) characters to establish a code group synchronization. When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J69 starts the initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J69 transmits four multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data. SYSREF LMFC Clock LMFC Boundary Multi Frame SYNC Transmit Data xxx K28.5 Code Group Synchronization K28.5 ILA Initial Lane Alignment ILA DATA DATA Data Transmission Figure 73. Lane Alignment Sequence 8.4.2.2 JESD204B Test Patterns There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J69 supports a clock output, encoded, and a PRBS (215 – 1) pattern. These test patterns can be enabled via an SPI register write and are located in the JESD digital page of the JESD bank. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 35 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.4.2.3 JESD204B Frame The JESD204B standard defines the following parameters: • L is the number of lanes per link • M is the number of converters per device • F is the number of octets per frame clock period, per lane • S is the number of samples per frame per converter 8.4.2.4 JESD204B Frame Assembly with Decimation Table 8 lists the available JESD204B formats and interface rate at maximum sampling frequency. At lower sampling frequencies, interface rates scale down proportionally. Figure 74 shows the detailed frame assembly for the decimated output. Table 8. Interface Rates with Decimation Filter L M F S JESD MODE REGISTER BIT JESD PLL MODE SETTING DECIMATION MAX ADC OUTPUT RATE (MSPS) MAX fSERDES (Gbps) 4 2 2 2 001 20x 2X 500 5.0 2 2 4 2 010 40x 2X 500 10.0 Channel Output Sample Clock (Chip Clock / 2 = 500 MSPS) Frame Clock (250 MHz) One Frame Period PIN One Frame Period LMFS = 4222, 2X DECIMATION LMFS = 2242, 2X DECIMATION DA0 A1[15:8] A1[7:0] A3[15:8] A3[7:0] DA1 A0[15:8] A0[7:0] A2[15:8] A2[7:0] Lane DA0 is Unused A0[15:8] A0[7:0] A1[15:8] A1[7:0] DA2 Lane DA2 is Unused Lane DA2 is Unused DA3 Lane DA3 is Unused Lane DA3 is Unused DB0 B1[15:8] B1[7:0] B3[15:8] B3[7:0] DB1 B0[15:8] B0[7:0] B2[15:8] B2[7:0] Lane DB0 is Unused B0[15:8] B0[7:0] B1[15:8] B1[7:0] DB2 Lane DB2 is Unused Lane DB2 is Unused DB3 Lane DB3 is Unused Lane DB3 is Unused Figure 74. Frame Assembly with Decimation Filter 36 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Note that after power-up, the JESD output bus must be reordered to obtain correct link parameters in the ILA sequence. Table 9 shows the required register writes to reorder the JESD output bus. Table 9. Configuring LMFS for the JESD Link L M F S DECIMATION JESD PLL MODE (In JESD Analog Page) JESD MODE REGISTER BIT (In JESD Digital Page) DA_BUS_REORDER REGISTER BIT (In JESD Digital Page) DB_BUS_REORDER REGISTER BIT (In JESD Digital Page) REGISTER 52 (In Main Digital Page) REGISTER 72 (In Main Digital Page) 4 2 2 2 2X 00h 01h 0Ah 0Ah 80h 08h 2 2 4 2 2X 10h 02h 0Ah 0Ah 80h 08h 8.4.2.4.1 JESD Transmitter Interface Each of the 10.0-Gbps SERDES JESD transmitter outputs requires ac-coupling between the transmitter and receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as possible to avoid unwanted reflections and signal degradation, as shown in Figure 75. 0.1 PF DA[3:0]P, DB[3:0]P R t = ZO Transmission Line, Zo VCM Receiver R t = ZO DA[3:0]M, DB[3:0]M 0.1 PF Figure 75. Output Connection to Receiver Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 37 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.4.2.4.2 Eye Diagrams Figure 76 to Figure 79 show the serial output eye diagrams of the ADS54J69 at 5.0 Gbps and 10 Gbps with default and increased output voltage swing against the JESD204B mask. 38 Figure 76. Eye Diagram at 5-Gbps Bit Rate with Default Output Swing Figure 77. Eye Diagram at 5-Gbps Bit Rate with Increased Output Swing Figure 78. Eye Diagram at 10-Gbps Bit Rate with Default Output Swing Figure 79. Eye Diagram at 10-Gbps Bit Rate with Increased Output Swing Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5 Register Maps Figure 80 shows a conceptual diagram of the serial registers. Initiate an SPI Cycle R/W, M, P, CH, Bits Decoder(1) M=0 Analog Bank M=1 JESD Bank General Register (Address 00h, Keep M = 0, P = 0) Analog Bank Page Selection (Address 011h, Keep M = 0, P = 0) Value 80h Addr 20h Keep M = 0, P = 0 Addr 59h Value 6800h Value 0Fh Addr 0h Addr 5Fh Master Page (PDN, OVR, DC Coupling) JESD Bank Page Selection (Address 003h and Address 004h, Keep M = 1, P = 0) General Register (Address 005h, Keep M = 1, P = 0) Keep M = 0, P = 0 Addr F7h Value 6A00h Value 6900h Addr 0h Main Digital Page ADC Page (Fast OVR) Unused Registers (Address 01h, Address 02h. Keep M = 1, P = 0) Addr 12h (Nyquist Zone, Gain, OVR, Filter) (JESD Configuration) JESD Analog Page (PLL Configuration, Output Swing, Pre-Emphasis) Keep M = 1, P=1 Keep M = 1, P=1 Keep M = 1, P=1 JESD Digital Page Addr 32h Addr 1Bh Figure 80. Serial Interface Registers 8.5.1 Detailed Register Info The ADS54J69 contains two main SPI banks: the analog SPI bank and the digital SPI bank. The analog SPI bank gives access to the ADC analog blocks and the JESD SPI bank controls the digital features and anything related to the JESD204B serial interface. The analog SPI bank is divided into two pages (master and ADC) and the JESD SPI bank is divided into three pages (main digital, JESD digital, and JESD analog). Table 10 lists a register map for the ADS54J69. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 39 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Register Maps (continued) Table 10. Register Map REGISTER ADDRESS REGISTER DATA A[11:0] (Hex) 7 6 5 RESET 0 0 4 3 2 1 0 0 0 0 0 RESET 0 0 DISABLE BROADCAST 0 0 GENERAL REGISTERS 0 3 JESD BANK PAGE SEL[7:0] 4 JESD BANK PAGE SEL[15:8] 5 0 0 0 0 11 0 ANALOG BANK PAGE SEL MASTER PAGE (80h) 20 PDN ADC CHA 21 PDN ADC CHB PDN BUFFER CHB 23 PDN BUFFER CHA 0 0 PDN BUFFER CHA 0 0 0 0 PDN ADC CHA 24 PDN ADC CHB PDN BUFFER CHB 26 GLOBAL PDN OVERRIDE PDN PIN 4F 0 0 0 0 0 0 0 EN INPUT DC COUPLING 53 0 MASK SYSREF 0 0 0 0 EN SYSREF DC COUPLING SET SYSREF 54 ENABLE MANUAL SYSREF 0 0 0 0 0 0 0 55 0 0 0 PDN MASK 0 0 0 0 59 FOVR CHB 0 ALWAYS WRITE 1 0 0 0 0 0 0 PULSE RESET PDN MASK SEL 0 0 0 0 0 ADC PAGE (0Fh) 5F FOVR THRESHOLD PROG MAIN DIGITAL PAGE (6800h) 0 0 0 0 0 0 41 0 0 0 DECFIL MODE[3] 0 42 0 0 0 0 0 43 0 0 0 0 0 44 0 4B 0 0 DECFIL MODE[2:0] NYQUIST ZONE 0 0 FORMAT SEL 0 0 0 DIGITAL GAIN 0 FORMAT EN 0 0 MAIN DIGITAL PAGE (6800h) (continued) 40 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Register Maps (continued) Table 10. Register Map (continued) REGISTER ADDRESS REGISTER DATA A[11:0] (Hex) 7 6 5 4 3 2 1 0 4D 0 0 0 0 DEC MODE EN 0 0 0 4E CTRL NYQUIST 0 0 0 0 0 0 0 52 ALWAYS WRITE 1 0 0 0 0 0 0 DIG GAIN EN 72 0 0 0 0 ALWAYS WRITE 1 0 0 0 AB 0 0 0 0 0 0 0 LSB SEL EN AD 0 0 0 0 0 0 F7 0 0 0 0 0 0 0 DIG RESET TESTMODE EN FLIP ADC DATA LANE ALIGN FRAME ALIGN TX LINK DIS LSB SELECT JESD DIGITAL PAGE (6900h) 0 CTRL K 0 0 1 SYNC REG SYNC REG EN 0 2 LINK LAYER TESTMODE 3 FORCE LMFC COUNT 5 SCRAMBLE EN 0 0 6 0 0 0 7 0 0 0 0 0 LINK LAYER RPAT LMFC MASK RESET JESD MODE 0 0 LMFC COUNT INIT 0 RELEASE ILANE SEQ 0 0 0 0 0 0 0 FRAMES PER MULTI FRAME (K) 0 SUBCLASS 31 DA_BUS_REORDER[7:0] 32 DB_BUS_REORDER[7:0] 0 JESD ANALOG PAGE (6A00h) 12 SEL EMP LANE 1 0 0 13 SEL EMP LANE 0 0 0 14 SEL EMP LANE 2 0 0 15 SEL EMP LANE 3 0 0 16 0 0 0 0 0 0 1A 0 0 0 0 0 0 FOVR CHA 0 0 FOVR CHA EN 0 0 0 1B JESD SWING JESD PLL MODE Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 41 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.2 Example Register Writes This section provides three different example register writes. Table 11 describes a global power-down register write, Table 12 describes the register writes to enable the high-pass filter in the default four-lane output mode (LMFS = 4222), and Table 13 describes the register writes to enable the high-pass filter in the two-lane output mode (LMFS = 2242). Note that by default after reset, the low-pass filter and four-lane output mode are enabled and register writes are applied to both channels together. Table 11. Global Power-Down ADDRESS (Hex) DATA (Hex) 11h 80h Set the master page COMMENT 26h C0h Set the global power-down Table 12. Selecting 2X Decimation with Four-Lane Mode (LMFS = 4222) ADDRESS (Hex) DATA (Hex) 4-004h 68h 4-003h 00h COMMENT Select the main digital page (6800h) 6-041h 16h Set decimate-by-2 (high-pass filter) 6-04Dh 08h Enable decimation filter control 6-072h 08h Enable the ALWAYS WRITE 1 register bit (for output bus reorder) 6-052h 80h Enable the ALWAYS WRITE 1 register bit (for output bus reorder) 6-000h 01h 6-000h 00h Pulse the PULSE RESET register bit so that registers programmed in the main digital page (6800h) become effective. 4-004h 69h 4-003h 00h 6-031h 0Ah Output bus reorder for channel A 6-032h 0Ah Output bus reorder for channel B 6-001h 01h JESD filter mode + 4-lanes output selection Select the JESD digital page (6900h) Table 13. Selecting 2X Decimation with Two-Lane Mode (LMFS = 2242) 42 ADDRESS (Hex) DATA (Hex) 4-004h 68h 4-003h 00h COMMENT Select the main digital page (6800h) 6-041h 16h Set decimate-by-2 (high-pass filter) 6-04Dh 08h Enable decimation filter control 6-072h 08h Set the ALWAYS WRITE 1 register bit (for output bus reorder) 6-052h 80h Set the ALWAYS WRITE 1 register bit (for output bus reorder) 6-000h 01h 6-000h 00h Pulse the PULSE RESET register bit so that registers programmed in the main digital page (6800h) become effective. 4-004h 69h 4-003h 00h 6-031h 0Ah Output bus reorder for channel A 6-032h 0Ah Output bus reorder for channel B 6-001h 02h JESD filter mode + 2-lanes output selection 4-004h 6Ah 4-003h 00h 6-016h 02h Select the JESD digital page (6900h) Select the JESD analog page (6A00h) JESD PLL MODE 40x selection in the analog page Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3 Register Descriptions 8.5.3.1 General Registers 8.5.3.1.1 Register 0h (address = 0h) Figure 81. Register 0h 7 RESET W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 RESET W-0h LEGEND: W = Write only; -n = value after reset Table 14. Register 0h Field Descriptions Bit 7 6-1 0 Field Type Reset Description RESET W 0h 0 = Normal operation 1 = Internal software reset, clears back to 0 0 W 0h Must write 0 RESET W 0h 0 = Normal operation 1 = Internal software reset, clears back to 0 8.5.3.1.2 Register 3h (address = 3h) Figure 82. Register 3h 7 6 5 4 3 JESD BANK PAGE SEL[7:0] R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 15. Register 3h Field Descriptions Bit Field Type Reset Description 7-0 JESD BANK PAGE SEL[7:0] R/W 0h Program these bits to access the desired page in the JESD bank. 6800h = Main digital page selected 6900h = JESD digital page selected 6A00h = JESD analog page selected 8.5.3.1.3 Register 4h (address = 4h) Figure 83. Register 4h 7 6 5 4 3 JESD BANK PAGE SEL[15:8] R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 16. Register 4h Field Descriptions Bit Field Type Reset Description 7-0 JESD BANK PAGE SEL[15:8] R/W 0h Program these bits to access the desired page in the JESD bank. 6800h = Main digital page selected 6900h = JESD digital page selected 6A00h = JESD analog page selected Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 43 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.1.4 Register 5h (address = 5h) Figure 84. Register 5h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 DISABLE BROADCAST R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 17. Register 5h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 DISABLE BROADCAST R/W 0h 0 = Normal operation; channel A and B are programmed as a pair 1 = Channel A and B can be individually programmed based on the CH bit (keep CH = 0 for channel A, CH = 1 for channel B). 0 8.5.3.1.5 Register 11h (address = 11h) Figure 85. Register 11h 7 6 5 4 3 ANALOG PAGE SELECTION R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 18. Register 11h Field Descriptions Bit Field Type Reset Description 7-0 ANALOG BANK PAGE SEL R/W 0h Program these bits to access the desired page in the analog bank. Master page = 80h ADC page = 0Fh 8.5.3.2 Master Page (080h) Registers 8.5.3.2.1 Register 20h (address = 20h), Master Page (080h) Figure 86. Register 20h 7 6 5 4 3 PDN ADC CHA R/W-0h 2 1 0 PDN ADC CHB R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 19. Registers 20h Field Descriptions 44 Bit Field Type Reset Description 7-4 PDN ADC CHA R/W 0h 3-0 PDN ADC CHB R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. Power-down mask 1 or mask 2 are selected via register bit 5 in address 26h. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. 0Fh = Power-down CHB only. F0h = Power-down CHA only. FFh = Power-down both. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.2.2 Register 21h (address = 21h), Master Page (080h) Figure 87. Register 21h 7 6 PDN BUFFER CHB R/W-0h 5 4 PDN BUFFER CHA R/W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 20. Register 21h Field Descriptions Bit Field Type Reset Description 7-6 PDN BUFFER CHB R/W 0h 5-4 PDN BUFFER CHA R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. Power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. There are two buffers per channel. One buffer drives two ADC cores. PDN BUFFER CHx: 00 = Both buffers of a channel are active. 11 = Both buffers are powered down. 01–10 = Do not use. 3-0 0 W 0h Must write 0 8.5.3.2.3 Register 23h (address = 23h), Master Page (080h) Figure 88. Register 23h 7 6 5 4 3 2 PDN ADC CHA R/W-0h 1 0 PDN ADC CHB R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 21. Register 23h Field Descriptions Bit Field Type Reset Description 7-4 PDN ADC CHA R/W 0h 3-0 PDN ADC CHB R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. Power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. 0Fh = Power-down CHB only. F0h = Power-down CHA only. FFh = Power-down both. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 45 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.2.4 Register 24h (address = 24h), Master Page (080h) Figure 89. Register 24h 7 6 PDN BUFFER CHB R/W-0h 5 4 PDN BUFFER CHA R/W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 22. Register 24h Field Descriptions 46 Bit Field Type Reset Description 7-6 PDN BUFFER CHB R/W 0h 5-4 PDN BUFFER CHA R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. Power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. Power-down mask 2: addresses 23h and 24h. There are two buffers per channel. One buffer drives two ADC cores. PDN BUFFER CHx: 00 = Both buffers of a channel are active. 11 = Both buffers are powered down. 01–10 = Do not use. 3-0 0 W 0h Must write 0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.2.5 Register 26h (address = 26h), Master Page (080h) Figure 90. Register 26h 7 6 OVERRIDE PDN PIN R/W-0h GLOBAL PDN R/W-0h 5 PDN MASK SEL R/W-0h 4 3 2 1 0 0 0 0 0 0 W-0h W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 23. Register 26h Field Descriptions Bit Field Type Reset Description 7 GLOBAL PDN R/W 0h Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be programmed. 0 = Normal operation 1 = Global power-down via the SPI 6 OVERRIDE PDN PIN R/W 0h This bit ignores the power-down pin control. 0 = Normal operation 1 = Ignores inputs on the power-down pin 5 PDN MASK SEL R/W 0h This bit selects power-down mask 1 or mask 2. 0 = Power-down mask 1 1 = Power-down mask 2 0 W 0h Must write 0 4-0 8.5.3.2.6 Register 39h (address = 39h), Master Page (080h) Figure 91. Register 39h 7 6 PERF MODE[1:0] R/W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 24. Register 39h Field Descriptions Bit Field Type Reset Description 7-6 PERF MODE[1:0] R/W 0h Set all four PERF MODE[3:0] bits together. Bits are located in register address 39h, 3Ah, and 56h in the master page. 5-0 0 W 0h Must write 0 8.5.3.2.7 Register 3Ah (address = 3Ah), Master Page (080h) Figure 92. Register 3Ah 7 0 W-0h 6 PERF MODE[2] R/W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 25. Register 3Ah Field Descriptions Bit Field Type Reset Description 7 0 W 0h Must write 0 6 PERF MODE[2] R/W 0h Set all four PERF MODE[3:0] bits together. Bits are located in register address 39h, 3Ah, and 56h in the master page. 0 W 0h Must write 0 5-0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 47 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.2.8 Register 4Fh (address = 4Fh), Master Page (080h) Figure 93. Register 4Fh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 EN INPUT DC COUPLING R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 26. Register 4Fh Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 EN INPUT DC COUPLING R/W 0h Enables dc-coupling between the analog inputs and driver by changing the internal biasing resistor between the analog inputs and VCM from 600 Ω to 5 kΩ. 0 = Disable dc-coupling support 1 = Enable dc-coupling support 0 8.5.3.2.9 Register 53h (address = 53h), Master Page (080h) Figure 94. Register 53h 7 6 MASK SYSREF R/W-0h 0 W-0h 5 4 3 2 0 0 0 0 W-0h W-0h W-0h W-0h 1 EN SYSREF DC COUPLING R/W-0h 0 SET SYSREF R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 27. Register 53h Field Descriptions Bit Field Type Reset Description 7 0 W 0h Must write 0 6 MASK SYSREF R/W 0h 0 = Normal operation 1 = Ignores the SYSREF input 5-2 0 W 0h Must write 0 1 EN SYSREF DC COUPLING R/W 0h Enables a higher common-mode voltage input on the SYSREF signal (up to 1.6 V). 0 = Normal operation 1 = Enables a higher SYSREF common-mode voltage support 0 SET SYSREF R/W 0h 0 = Set SYSREF low 1 = Set SYSREF high 8.5.3.2.10 Register 54h (address = 54h), Master Page (080h) Figure 95. Register 54h 7 ENABLE MANUAL SYSREF R/W-0h 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W-0h W-0h W-0h W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 28. Register 54h Field Descriptions Bit 7 6-0 48 Field Type Reset Description ENABLE MANUAL SYSREF R/W 0h This bit enables manual SYSREF 0 W 0h Must write 0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.2.11 Register 55h (address = 55h), Master Page (080h) Figure 96. Register 55h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 PDN MASK R/W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 29. Register 55h Field Descriptions Bit Field Type Reset Description 7-5 0 W 0h Must write 0 PDN MASK R/W 0h This bit enables power-down via a register bit. 0 = Normal operation 1 = Power-down is enabled by powering down internal blocks as specified in the selected power-down mask 0 W 0h Must write 0 4 3-0 8.5.3.2.12 Register 56h (address = 56h), Master Page (080h) Figure 97. Register 56h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 R/W-0h 3 0 W-0h 2 PERF MODE[3] W-0h 1 0 W-0h 0 0 W-0h LEGEND: W = Write only; -n = value after reset Table 30. Register 56h Field Descriptions Bit Field Type Reset Description 7-3 0 W 0h Must write 0 PERF MODE[3] W 0h Set all four PERF MODE[3:0] bits together. Bits are located in register address 39h, 3Ah, and 56h in the master page. 0 W 0h Must write 0 2 1-0 8.5.3.2.13 Register 59h (address = 59h), Master Page (080h) Figure 98. Register 59h 7 FOVR CHB W-0h 6 0 W-0h 5 ALWAYS WRITE 1 R/W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 31. Register 59h Field Descriptions Bit Field Type Reset Description 7 FOVR CHB W 0h Outputs the FOVR signal for channel B on the SDOUT pin. 0 = Normal operation 1 = Outputs FOVR on the SDOUT pin 6 0 W 0h Must write 0 5 ALWAYS WRITE 1 R/W 0h Must write 1 0 W 0h Must write 0 4-0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 49 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.3 ADC Page (0Fh) Registers 8.5.3.3.1 Registers 5F (addresses = 5F), ADC Page (0Fh) Figure 99. Register 5F 7 6 5 4 3 FOVR THRESHOLD PROG R/W-E3h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 32. Registers 5F Field Descriptions 50 Bit Field Type Reset Description 7-0 FOVR THRESHOLD PROG R/W E3h Program the fast OVR thresholds together for channel A and B, as described in the Overrange Indication section. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.4 Main Digital Page (6800h) Registers 8.5.3.4.1 Register 0h (address = 0h), Main Digital Page (6800h) Figure 100. Register 0h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 PULSE RESET R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 33. Register 0h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 PULSE RESET R/W 0h Must be pulsed after power-up or after configuring registers in the main digital page of the JESD bank. Any register bits in the main digital page (6800h) take effect only after this bit is pulsed; see the Start-Up Sequence section for the correct sequence. 0 = Normal operation 0 → 1 → 0 = Bit is pulsed 0 8.5.3.4.2 Register 41h (address = 41h), Main Digital Page (6800h) Figure 101. Register 41h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 DECFIL MODE[3] R/W-0h 3 0 W-0h 2 1 DECFIL MODE[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 34. Register 41h Field Descriptions Bit Field Type Reset Description 7-5 0 W 0h Must write 0 4 DECFIL MODE[3] R/W 0h Refer Table 35. 3 0 W 0h Must write 0 DECFIL MODE[2:0] R/W 2h These bits select the decimation filter mode. Table 35 lists the bit settings. Register bit DEC MODE EN (register 4Dh, bit 3) must also be enabled. 2-0 Table 35. DECFIL MODE Bit Settings DEC MODE EN (REGISTER 4Dh, BIT 3) BITS (4, 2-0) FILTER MODE DECIMATION 0 XXXX Low-pass filter 2X 1 1010 Low-pass filter 2X 1 1110 High-pass filter 2X 1 Others Do not use — Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 51 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.4.3 Register 42h (address = 42h), Main Digital Page (6800h) Figure 102. Register 42h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 1 NYQUIST ZONE R/W-0h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 36. Register 42h Field Descriptions Bit Field Type Reset Description 7-3 0 W 0h Must write 0 2-0 NYQUIST ZONE R/W 0h The Nyquist zone must be selected for proper interleaving correction. Here Nyquist refers to Device Clock/2. For 1 GSPS Device clock, Nyquist frequency is 500 MHz. Also set register bit CTRL NYQUIST (4Eh, bit 7). 000 = 1st Nyquist zone (0 MHz to 500 MHz) 001 = 2nd Nyquist zone (500 MHz to 1000 MHz) 010 = 3rd Nyquist zone (1000 MHz to 1500 MHz) All others = Not used 8.5.3.4.4 Register 43h (address = 43h), Main Digital Page (6800h) Figure 103. Register 43h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 FORMAT SEL R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 37. Register 43h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 FORMAT SEL R/W 0h Changes the output format. Set the FORMAT EN bit (register 4Bh, bit 5) to enable control using this bit. 0 = Twos complement 1 = Offset binary 0 8.5.3.4.5 Register 44h (address = 44h), Main Digital Page (6800h) Figure 104. Register 44h 7 0 R/W-0h 6 5 4 3 DIGITAL GAIN R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 38. Register 44h Field Descriptions Bit 7 6-0 52 Field Type Reset Description 0 R/W 0h Must write 0 DIGITAL GAIN R/W 0h Digital gain setting. Digital gain must be enabled (register 52h, bit 0). Gain in dB = 20log (digital gain / 32). 7Fh = 127, equals digital gain of 9.5 dB. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h) Figure 105. Register 4Bh 7 0 W-0h 6 0 W-0h 5 FORMAT EN R/W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 39. Register 4Bh Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0 FORMAT EN R/W 0h This bit enables control for data format selection using the FORMAT SEL register bit. 0 = Default, output is in twos complement format 1 = Output is in offset binary format after the FORMAT SEL bit is set 0 W 0h Must write 0 5 4-0 8.5.3.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h) Figure 106. Register 4Dh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 DEC MOD EN R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 40. Register 4Dh Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0 DEC MOD EN R/W 0h This bit enables control of decimation filter mode via the DECFIL MODE[3:0] register bits. 0 = Default 1 = Decimation modes control is enabled 0 W 0h Must write 0 3 2-0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 53 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h) Figure 107. Register 4Eh 7 CTRL NYQUIST R/W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 41. Register 4Eh Field Descriptions Bit 7 6-0 Field Type Reset Description CTRL NYQUIST R/W 0h This bit enables selecting the Nyquist zone using register 42h, bits 2-0. 0 = Selection disabled 1 = Selection enabled 0 W 0h Must write 0 8.5.3.4.9 Register 52h (address = 52h), Main Digital Page (6800h) Figure 108. Register 52h 7 ALWAYS WRITE 1 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 DIG GAIN EN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 42. Register 52h Field Descriptions Bit 7 6-1 0 Field Type Reset Description ALWAYS WRITE 1 W 0h This bit enables output bus reorder using the Dx_BUS_REORDER[7:0] bits. Set this bit along with register 72h, bit 3 in the main digital page. 0 W 0h Must write 0 DIG GAIN EN R/W 0h Enables selecting the digital gain for register 44h. 0 = Digital gain disabled 1 = Digital gain enabled 8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h) Figure 109. Register 72h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 ALWAYS WRITE 1 W-0h 2 0 W-0h 1 0 W-0h 0 0 R/W-0h LEGEND: W = Write only; -n = value after reset Table 43. Register 72h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0 ALWAYS WRITE 1 W 0h This bit enables output bus reorder using the Dx_BUS_REORDER[7:0] bits. Set this bit along with register 52h, bit 7 in the main digital page. 0 W 0h Must write 0 3 2-0 54 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h) Figure 110. Register ABh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 LSB SEL EN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 44. Register ABh Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 LSB SEL EN R/W 0h Enables control for the LSB SELECT register bit. 0 = Default 1 = The LSB of the 16-bit ADC data can be programmed as fast OVR using the LSB SELECT bit 0 8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h) Figure 111. Register ADh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 LSB SELECT R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 45. Register ADh Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1-0 LSB SELECT R/W 0h Enables output of the FOVR flag instead of the output data LSB. 00 = Output is 16-bit data 11 = Output data LSB is replaced by the FOVR information for each channel 8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h) Figure 112. Register F7h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 DIG RESET W-0h LEGEND: W = Write only; -n = value after reset Table 46. Register F7h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 DIG RESET W 0h Self-clearing reset for the digital block. Does not include the interleaving correction. 0 = Normal operation 1 = Digital reset 0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 55 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.5 JESD Digital Page (6900h) Registers 8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h) Figure 113. Register 0h 7 6 5 CTRL K 0 0 R/W-0h W-0h W-0h 4 TESTMODE EN R/W-0h 3 FLIP ADC DATA R/W-0h 2 1 0 LANE ALIGN FRAME ALIGN TX LINK DIS R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 47. Register 0h Field Descriptions Bit 7 6-5 56 Field Type Reset Description CTRL K R/W 0h Enable bit for a number of frames per multi-frame. 0 = Default is five frames per multi-frame 1 = Frames per multi-frame can be set in register 06h 0 W 0h Must write 0 4 TESTMODE EN R/W 0h This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of the JESD204B specification. 0 = Test mode disabled 1 = Test mode enabled 3 FLIP ADC DATA R/W 0h 0 = Normal operation 1 = Output data order is reversed: MSB to LSB 2 LANE ALIGN R/W 0h This bit inserts the lane alignment character (K28.3) for the receiver to align to the lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts lane alignment characters 1 FRAME ALIGN R/W 0h This bit inserts the lane alignment character (K28.7) for the receiver to align to the lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts frame alignment characters 0 TX LINK DIS R/W 0h This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-asserted. 0 = Normal operation 1 = ILA disabled Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h) Figure 114. Register 1h 7 SYNC REG R/W-0h 6 SYNC REG EN R/W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 1 JESD MODE R/W-1h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 48. Register 1h Field Descriptions Bit Field Type Reset Description 7 SYNC REG R/W 0h Register control for sync request. 0 = Normal operation 1 = ADC output data are replaced with K28.5 characters; the SYNC REG EN register bit must also be set to 1 6 SYNC REG EN R/W 0h Enables register control for sync request. 0 = Use the SYNC pin for sync requests 1 = Use the SYNC REG register bit for sync requests 5-3 0 W 0h Must write 0 2-0 JESD MODE R/W 1h These bits select the number of active output lanes. The JESD PLL MODE register bit located in the JESD analog page must also be set accordingly. Active lanes carry serial JESD data whereas inactive lanes don't carry any data. 001 = 20X mode, four active lanes per device (default) 010 = 40X mode, two active lanes per device All others = Not used 8.5.3.5.3 Register 2h (address = 2h), JESD Digital Page (6900h) Figure 115. Register 2h 7 6 5 LINK LAYER TESTMODE R/W-0h 4 LINK LAYER RPAT R/W-0h 3 LMFC MASK RESET R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 49. Register 2h Field Descriptions Bit Field Type Reset Description 7-5 LINK LAYER TESTMODE R/W 0h These bits generate a pattern according to section 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high-frequency jitter pattern) 010 = K28.5 (mixed-frequency jitter pattern) 011 = Repeat initial lane alignment (generates a K28.5 character and continuously repeats lane alignment sequences) 100 = 12-octet RPAT jitter pattern All others = Not used 4 LINK LAYER RPAT R/W 0h This bit changes the running disparity in the modified RPAT pattern test mode (only when the link layer test mode = 100). 0 = Normal operation 1 = Changes disparity 3 LMFC MASK RESET R/W 0h Masks the LMFC reset coming to the digital block. 0 = LMFC reset is not masked 1 = Ignore the LMFC reset request 0 W 0h Must write 0 2-0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 57 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h) Figure 116. Register 3h 7 FORCE LMFC COUNT R/W-0h 6 5 4 3 2 1 0 LMFC COUNT INIT RELEASE ILANE SEQ R/W-0h R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 50. Register 3h Field Descriptions Bit Field Type Reset Description FORCE LMFC COUNT R/W 0h This bit forces the LMFC count. 0 = Normal operation 1 = Enables using a different starting value for the LMFC counter 6-2 MASK SYSREF R/W 0h When SYSREF transmits to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the receiver can be synchronized early because the LANE ALIGNMENT SEQUENCE is received early. The FORCE LMFC COUNT register bit must be enabled. 1-0 RELEASE ILANE SEQ R/W 0h These bits delay the generation of the lane alignment sequence by 0, 1, 2 or 3 multi-frames after the code group synchronization. 00 = 0 01 = 1 10 = 2 11 = 3 7 8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h) Figure 117. Register 5h 7 SCRAMBLE EN R/W-Undefined 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 51. Register 5h Field Descriptions Bit 7 6-0 58 Field Type Reset Description SCRAMBLE EN R/W Undefined Scrambles the enable bit in the JESD204B interface. 0 = Scrambling disabled 1 = Scrambling enabled 0 W 0h Must write 0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.5.6 Register 6h (address = 6h), JESD Digital Page (6900h) Figure 118. Register 6h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 3 2 1 FRAMES PER MULTI FRAME (K) R/W-8h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 52. Register 6h Field Descriptions Bit Field Type Reset Description 7-5 0 W 0h Must write 0 4-0 FRAMES PER MULTI FRAME (K) R/W 8h These bits set the number of multi-frames. Actual K is the value in hex + 1 (that is, 0Fh is K = 16). 8.5.3.5.7 Register 7h (address = 7h), JESD Digital Page (6900h) Figure 119. Register 7h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 SUBCLASS R/W-1h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 53. Register 7h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0 SUBCLASS R/W 1h This bit sets the JESD204B subclass. 000 = Subclass 0 is backward compatible with JESD204A 001 = Subclass 1 deterministic latency using the SYSREF signal 0 W 0h Must write 0 3 2-0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 59 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.5.8 Register 31h (address = 31h), JESD Digital Page (6900h) Figure 120. Register 31h 7 6 5 4 3 DA_BUS_REORDER[7:0] R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 54. Register 31h Field Descriptions Bit Field Type Reset Description 7-0 DA_BUS_REORDER[7:0] R/W 0h Use these bits to program output connections between data streams and output lanes in decimate-by-2 mode. Table 12 lists the supported combinations of these bits. 8.5.3.5.9 Register 32h (address = 32h), JESD Digital Page (6900h) Figure 121. Register 32h 7 6 5 4 3 DB_BUS_REORDER[7:0] R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 55. Register 32h Field Descriptions 60 Bit Field Type Reset Description 7-0 DB_BUS_REORDER[7:0] R/W 0h Use these bits to program output connections between data streams and output lanes in decimate-by-2 mode. Table 12 lists the supported combinations of these bits. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.6 JESD Analog Page (6A00h) Register 8.5.3.6.1 Registers 12h-5h (address = 12h-5h), JESD Analog Page (6A00h) Figure 122. Register 12h 7 6 5 4 SEL EMP LANE 1 R/W-0h 3 2 1 0 W-0h 0 0 W-0h 2 1 0 W-0h 0 0 W-0h 2 1 0 W-0h 0 0 W-0h 2 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Figure 123. Register 13h 7 6 5 4 SEL EMP LANE 0 R/W-0h 3 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Figure 124. Register 14h 7 6 5 4 SEL EMP LANE 2 R/W-0h 3 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Figure 125. Register 15h 7 6 5 4 SEL EMP LANE 3 R/W-0h 3 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 56. Registers 12h-15h Field Descriptions Bit Field Type Reset Description 7-2 SEL EMP LANE 1, 0, 2, or 3 R/W 0h Selects the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period. 000000 = 0 dB 000001 = –1 dB 000011 = –2 dB 000111 = –4.1 dB 001111 = –6.2 dB 011111 = –8.2 dB 111111 = –11.5 dB 1-0 0 W-0h 0h Must write 0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 61 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h) Figure 126. Register 16h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 JESD PLL MODE R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 57. Register 16h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1-0 JESD PLL MODE R/W 0h These bits select the JESD PLL multiplication factor and must match the JESD MODE setting. 00 = 20X mode, four active lanes per device 01 = Not used 10 = 40X mode, two active lanes per device 11 = Not used 8.5.3.6.3 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h) Figure 127. Register 1Ah 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 FOVR CHA R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 58. Register 1Ah Field Descriptions 62 Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 FOVR CHA R/W 0h Outputs the FOVR signal for channel A on the PDN pin. FOVR CHA EN (register 1Bh, bit 3) must be enabled. 0 = Normal operation 1 = FOVR on the PDN pin 0 0 W 0h Must write 0 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 8.5.3.6.4 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h) Figure 128. Register 1Bh 7 6 JESD SWING R/W-0h 5 4 0 W-0h 3 FOVR CHA EN R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 59. Register 1Bh Field Descriptions Bit Field Type Reset Description 7-5 JESD SWING R/W 0h Selects the output differential amplitude VOD (mVPP) of the JESD transmitter (for all lanes). 0 = 860 mVPP 1 = 810 mVPP 2 = 770 mVPP 3 = 745 mVPP 4 = 960 mVPP 5 = 930 mVPP 6 = 905 mVPP 7 = 880 mVPP 4 0 W 0h Must write 0 3 FOVR CHA EN R/W 0h Enables overwriting the PDN pin with the FOVR signal from channel A. 0 = Normal operation 1 = PDN is overwritten JESD PLL MODE R/W 0h Must write 0 2-0 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Start-Up Sequence The steps described in Table 60 are the recommended power-up sequence with the ADS54J69 in 20X or 40X mode. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 63 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Table 60. Initialization Sequence STEP 1 SEQUENCE Power-up the device PAGE BEING PROGRAMMED DESCRIPTION Bring up IOVDD to 1.15 V before applying power to DVDD. Bring up DVDD to 1.9 V, AVDD to 1.9 V, and AVDD3V to 3.0 V. COMMENT — See the Power Sequencing and Initialization section for power sequence requirements. — A hardware reset clears all registers to their default values. Hardware reset Apply a hardware reset by pulsing pin 48 (low->high->low). Software reset: Register writes equivalent to a hardware reset are: Write address 0-000h with 81h. 2 General register This bit is a self-clearing bit. Reset the device Write address 4-001h with 00h and address 4-002h with 00h. Unused page Write address 4-003h with 00h and address 4-004h with 68h. — Write address 6-0F7h with 01h for channel A. Performance modes Clear any unwanted content from the unused pages of the JESD bank. Select the main digital page of the JESD bank. Use the DIG RESET register bit to reset all pages in the JESD bank. Main digital page (JESD bank) Write address 6-000h with 01h, then address 6-000h with 00h. 3 Reset registers in the ADC page and master page of the analog bank This bit is a self-clearing bit. This bit is a self-clearing bit. Pulse the PULSE RESET register bit for both channels. Write address 0-011h with 80h. — Write address 0-059h with 20h. Master page (analog bank) Select the master page of the analog bank. Set the ALWAYS WRITE 1 bit. The JESD mode (in the JESD digital page) and JESD PLL mode (in the JESD analog page) register bits control 20X or 40X serialization. By default after reset, the device is in 20X serialization mode (4-lanes output). Write address 4-003h with 00h and address 4-004h with 69h. Write address 6-000h with 80h. — JESD digital page (JESD bank) Write address 6-001h with 01h. Write address 6-001h with 02h. 4 Program registers for 20X or 40X serialization and program the HPF or LPF filter Set the CTRL K bit for both channels to program K for the SYSREF signal frequency in step 5. Enable 20X serialization (4-lane output, default setting after reset). Enable 40X serialization (2-lane output). Write address 4-003h with 00h and address 4-004h with 6Ah. Write address 6-016h with 00h Write address 6-016h with 02h JESD analog page (JESD bank) Select the JESD analog page. Enable 20X serialization (4-lane output, default setting after reset). To enable 40X serialization (2-lane output). Write address 4-003h with 00h and address 4-004h with 68h. Select the main digital page. Write address 6-052h with 80h and address 6-072h with 08h. Set the ALWAYS WRITE 1 bit (enables correct order of the JESD output lanes). Write address 6-04Dh with 08h Main digital page (JESD bank) Write address 6-041h with 12h 64 Select the JESD digital page. Enable the decimation filter programming. Enable the low-pass filter (default setting after reset). Write address 6-041h with 16h Enable the high-pass filter. Write address 6-000h with 01h and address 6-000h with 00h. Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Table 60. Initialization Sequence (continued) STEP SEQUENCE PAGE BEING PROGRAMMED DESCRIPTION Write address 4-003h with 00h and address 4-004h with 69h. 5 Set the value of K and the SYSREF signal frequency accordingly 6 JESD lane alignment Write address 6-006h with XXh (choose the value of K). — JESD digital page (JESD bank) Pull the SYNC pin (pin 63) low. Pull the SYNC pin high. COMMENT Select the JESD digital page. Default value of K is 8 for 20X (4-lane) mode and 4 for 40X (2-lane) mode. However, K can be programmed for higher values than the default by using bits 4-0 of address 6-006 in the JESD digital page. For example, if K = 31 by writing address 6-006h with 1Fh in the JESD digital page, then the SYSREF signal frequency must be kept less than or equal to 250 MHz / 32 = 7.8125 MHz. Transmit K28.5 characters. — After the receiver is synchronized, initiate an ILA phase and subsequent transmissions of ADC data. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 65 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 9.1.2 Hardware Reset Figure 129 and Table 61 show the timing for a hardware reset. Power Supplies t1 RESET t2 t3 SEN Figure 129. Hardware Reset Timing Diagram Table 61. Timing Requirements for Figure 129 MIN t1 Power-on delay from power-up to active high RESET pulse t2 Reset pulse duration: active high RESET pulse duration t3 Register write delay: delay from RESET disable to SEN active TYP MAX UNIT 1 ms 10 ns 100 ns 9.1.3 SNR and Clock Jitter The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is 98 dB for a 16-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies. The decimation-by-2 process gives approximately an additional 3-dB improvement in SNR. 504#&% >@$?? = F3 F 20HKC¨l10F 504 3Q=JPEV=PEKJ 20 0KEOA p + l10 2 F 504 6D ANI=H 0KEOA 20 p + l 10 2 F 504 ,EPPAN 20 p 2 (4) The SNR limitation resulting from the sample clock jitter can be calculated by Equation 5: (5) The total clock jitter (TJitter) has two components: the internal aperture jitter (145 fS) is set by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6: (6) External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter. 66 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 The ADS54J69 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 130. 75 SNR (dBFS) 73 35 fS 50 fS 100 fS 150 fS 200 fS 71 69 67 65 10 100 Input Frequency (MHz) D052 Figure 130. SNR versus Input Frequency and External Clock Jitter Half-band decimation filtering employed by the ADS54J69 reduces the affect of all contributors to SNR by 3 dB. Filtering makes the SNR curve in Figure 130 start at 74 dBFS despite a thermal noise of 71.1 dBFS. Decimation filtering also improves the affect of jitter noise by 3 dB, and is equivalent to having 102 fS as the effective aperture jitter instead of 120 fS. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 67 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 9.2 Typical Application The ADS54J69 is designed for wideband receiver applications demanding excellent dynamic range over a large input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 131. DVDD 10 k 5: 50 : Driver 0.1 PF 0.1 PF 2 pF 50 : SPI Master 5: GND GND 0.1 PF GND 0.1 PF IOVDD 0.1 PF 100 : SYSREFM AVDD AVDD AGND 3 DB3M AGND SYSREFP 4 DB3P 0.1 PF GND 5 DGND AVDD3V AVDD3V 6 IOVDD AVDD 7 SDIN GND 0.1 PF Low-Jitter Clock Generator 8 SCLK AGND 9 SEN CLKINM DVDD CLKINP 10 AVDD AGND 11 AVDD3V AVDD AVDD 0.1 PF GND 12 SDOUT 10 nF AVDD3V 13 AVDD GND 0.1 PF AVDD3V 14 INBP AGND 15 INBM 0.1 PF 16 AVDD VCM DVDD AVDD3V NC NC AVDD AGND NC 17 10nF AVDD AVDD3V 18 GND 0.1 PF AVDD3V AVDD 2 100-: Differential 1 10 nF DB2P 19 72 20 71 21 70 22 69 DB2M IOVDD IOVDD 10 nF DB1P 10 nF GND DB1M 23 68 24 67 25 66 DGND DB0P 10 nF GND DB0M 26 65 IOVDD 27 64 GND Pad (Back Side) 28 IOVDD 0.1 PF SYNC 63 GND DA0M 29 62 30 61 31 60 32 59 FPGA DA0P DGND DA1M 10 nF GND DA1P 33 58 34 57 IOVDD 35 IOVDD 10 nF 10 nF DA2M 56 GND DA2P 36 55 GND 37 38 39 40 42 43 44 45 46 47 49 51 52 53 10 nF 54 100-: Differential DA3M DA3P DGND IOVDD PDN RES RESET AVDD3V GND 50 10 nF DVDD AVDD AVDD 48 DVDD AVDD AVDD3V AVDD AVDD INAP INAM AVDD AVDD3V AVDD AGND AVDD3V 41 0.1 PF GND 0.1 PF GND 0.1 PF IOVDD GND 5: 50 : Driver 0.1 PF 0.1 PF 50 : GND 2 pF 5: NOTE: GND = AGND and DGND connected in the PCB layout. Figure 131. AC-Coupled Receiver 68 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 Typical Application (continued) 9.2.1 Design Requirements 9.2.1.1 Transformer-Coupled Circuits Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC inputs. When designing dc driving circuits, the ADC input impedance must be considered. Figure 132 and Figure 133 show the impedance (ZIN = RIN || CIN) across the ADC input pins. 5 Differential Input Capacitance (pF) Differential Input Resistance (k:) 1.4 1.2 1 0.8 0.6 0.4 0.2 4.75 4.5 4.25 4 3.75 3.5 3.25 3 2.75 2.5 2.25 0 0 100 200 300 400 500 600 700 Frequency (MHz) 800 0 900 1000 100 200 D103 Figure 132. RIN vs Input Frequency 300 400 500 600 700 Frequency (MHz) 800 900 1000 D102 Figure 133. CIN vs Input Frequency By using the simple drive circuit of Figure 134, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit. 0.1 F T1 T2 0.1 F 5 CHx_INP 25 0.1 F RIN 0.1 F 1:1 CIN 25 5 CHx_INM 1:1 Device Figure 134. Input Drive Circuit 9.2.2 Detailed Design Procedure For optimum performance, the analog inputs must be driven differentially. This architecture improves commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 134. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 69 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com Typical Application (continued) 9.2.3 Application Curves 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) Figure 135 and Figure 136 show the typical performance at 170 MHz and 230 MHz, respectively. -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 50 100 150 Input Frequency (MHz) 200 250 0 D003 SNR = 73 dBFS; SFDR = 93 dBc; SINAD = 73.18 dBFS; THD = 89 dBc; HD2 = 93 dBc; HD3 = 103 dBc; IL spur = 99 dBc; non HD2, HD3 spur = 94 dBc 50 100 150 Input Frequency (MHz) 200 250 D005 SNR = 71.6 dBFS; SFDR = 80 dBc; SINAD = 71 dBFS; THD = 79 dBc; HD2 = –80 dBc; HD3 = –96 dBc; IL spur = 85 dBc; non HD2, HD3 spur = 92 dBc Figure 135. FFT for 170-MHz Input Signal Figure 136. FFT for 310-MHz Input Signal 10 Power Supply Recommendations The device requires a 1.15-V nominal supply for IOVDD, a 1.9-V nominal supply for DVDD, a 1.9-V nominal supply for AVDD, and a 3.0-V nominal supply for AVDD3V. For detailed information regarding the operating voltage minimum and maximum specifications of different supplies, see the Recommended Operating Conditions table. 70 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 10.1 Power Sequencing and Initialization Figure 137 shows the suggested power-up sequencing for the device. Note that the 1.15-V IOVDD supply must rise before the 1.9-V DVDD supply. If the 1.9-V DVDD supply rises before the 1.15-V IOVDD supply, then the internal default register settings may not load properly. The other supplies (the 3-V AVDD3V and the 1.9-V AVDD), can come up in any order during the power sequence. The power supplies can ramp up at any rate and there is no hard requirement for the time delay between IOVDD ramp up to DVDD ramp-up (can be in orders of microseconds but is recommend to be a few milliseconds). IOVDD = 1.15 V DVDD = 1.9 V AVDD = 1.9 V AVDD = 3 V Figure 137. Power Sequencing for the ADS54Jxx Family of Devices Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 71 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 11 Layout 11.1 Layout Guidelines The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 138. A complete layout of the EVM is available from the ADS54J69EVM folder. Some important points to remember during board layout are: • Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as illustrated in the reference layout of Figure 138 as much as possible. • In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 138 as much as possible. • Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output traces must not be kept parallel to the analog input traces because this configuration can result in coupling from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be matched in length to avoid skew among outputs. • At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source. 72 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 ADS54J69 www.ti.com SBAS713C – MAY 2015 – REVISED JANUARY 2017 11.2 Layout Example Figure 138. ADS54J69EVM layout Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 73 ADS54J69 SBAS713C – MAY 2015 – REVISED JANUARY 2017 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • ADS54J20 Dual-Channel, 12-Bit, 1.0-GSPS, Analog-to-Digital Converter • ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter • ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter • ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter • ADS54J66 Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC • ADS54J69EVM User's Guide 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 74 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J69 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS54J69IRMP ACTIVE VQFN RMP 72 168 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ54J69 ADS54J69IRMPT ACTIVE VQFN RMP 72 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ54J69 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of