ADS54T01
SLAS918B – DECEMBER 2012 – REVISED APRIL 2022
ADS54T01 Single 12-Bit 750-Msps Receiver and Feedback IC
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The ADS54T01 is a high linearity, single channel,
12-bit, 750-Msps analog-to-digital converter (ADC)
easing front end filter design for wide bandwidth
receivers. The analog input buffer isolates the internal
switching of the on-chip track-and-hold from disturbing
the signal source as well as providing a highimpedance input.
•
•
•
Single channel
12-bit resolution
Maximum clock rate: 750 Msps
Low swing fullscale input: 1.0 Vpp
Analog input buffer with high impedance input
Input bandwidth (3 dB): > 1.2 GHz
Data output interface: DDR LVDS
196-Pin NFBGA package (12 mm × 12 mm)
Power dissipation: 1.2 W
Performance at fin = 230 MHz IF
– SNR: 60.7 dBFS
– SFDR: 73 dBc
Performance at fin = 700 MHz IF
– SNR: 58.6 dBFS
– SFDR: 64 dBc
Receive mode: 2x decimation with low-pass or
high-pass filter
Feedback mode: burst mode output for full
bandwidth DPD feedback
2 Applications
•
•
•
Telecommunications
Wireless infrastructure
Power amplifier linearization
Two output modes are available for the output data
—the data can be decimated by two or the data
can be output in burst mode. The burst mode
output is designed specifically for DPD feedback
applications where high-resolution output data is
available for a short period of time. Designed for
high SFDR, the ADC has low-noise performance and
outstanding spurious-free dynamic range over a large
input-frequency range. The device is available in a
196-pin NFBGA package and is specified over the full
industrial temperature range (–40°C to 85°C).
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
ADS54T01
NFBGA (196)
12.00 mm × 12.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Digital Block
12bit
750Msps
INA
Burst Mode
2x Decimation
DA[11:0]
DACLK
CLKIN
Clk
Buffer
SYNC
TRIGGER
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS54T01
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SLAS918B – DECEMBER 2012 – REVISED APRIL 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Electrical Characteristics.............................................9
7.7 Electrical Characteristics...........................................10
7.8 Electrical Characteristics...........................................11
7.9 Electrical Characteristics...........................................11
7.10 Typical Characteristics............................................ 13
8 Detailed Description......................................................22
8.1 Overview................................................................... 22
8.2 Functional Block Diagram......................................... 22
8.3 Feature Description...................................................22
8.4 Device Functional Modes..........................................29
8.5 Programming............................................................ 32
8.6 Register Maps...........................................................34
9 Power Supply Recommendations................................39
10 Device and Documentation Support..........................40
10.1 Receiving Notification of Documentation Updates..40
10.2 Support Resources................................................. 40
10.3 Trademarks............................................................. 40
10.4 Electrostatic Discharge Caution..............................40
10.5 Glossary..................................................................40
11 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
Changes from Revision A (January 2014) to Revision B (April 2022)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed Revision A History from "Deleted P7, N7" to "Deleted G4, G3".......................................................... 2
• Changed Pin Functions table to match TI Standards......................................................................................... 3
Changes from Revision * (December 2012) to Revision A (January 2014)
Page
• Deleted G4, G3 from TRDYP/N pin numbers..................................................................................................... 3
• Changed package from QFN to nFBGA in THERMAL INFORMATION............................................................. 7
• Added text and figure to TEST PATTERN OUTPUT section............................................................................ 22
• Deleted text from last paragraph in INTERLEAVING CORRECTION section.................................................. 26
• Changed second paragraph in MULTI DEVICE SYNCHRONIZATION section................................................28
• Deleted Register Initialization section and added Device Initialization section.................................................32
• Changed Register Address 2 Bit D13 from 0 to 1 in SERIAL REGISTER MAP...............................................34
• Changed Register Address E Bits D1 and D0 to 0 in SERIAL REGISTER MAP............................................. 34
• Changed Register Address 38 Bits D3 to D0 from 0 to 1 in SERIAL REGISTER MAP................................... 34
• Changed Register Address 2 Bit D13 from 0 to 1 and add D13 Read back 1..................................................34
• Changed Register Address E Bit D1 and D0 to 0.............................................................................................34
• Changed Register Address 38 Bits D3 to D0 from 0 to 1 and add D3 to D0 Read back 1...............................34
• Changed Register Address 66 D15-D10 to D15-D0 and D11-D10 to D11-D0..................................................34
2
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5 Device Comparison
Table 5-1. Device Comparison
PART NUMBER
NUMBER OF CHANNELS
SPEED GRADE
ADS54T02
2
750 Msps
ADS54T01
1
750 Msps
ADS54T04
2
500 Msps
6 Pin Configuration and Functions
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
VREF
VCM
GND
NC
NC
GND
AVDDC
AVDDC
GND
INA_P
INA_N
GND
GND
CLKINP
14
13
SDENB
TEST
MODE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CLKINN
13
12
SCLK
SRESET
GND
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
GND
AVDD33
AVDD33
12
11
SDIO
ENABLE
GND
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
GND
AVDD18
AVDD18
11
10
SDO
IOVDD
GND
AVDD18
GND
GND
GND
GND
GND
GND
AVDD18
GND
9
DVDD
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SYNCN
SYNCP
9
8
DVDD
DVDD
DVDD
DVDD
GND
GND
GND
GND
GND
GND
DVDD
DVDD
DVDD
DVDD
8
7
NC
NC
DVDD
LVDS
DVDD
LVDS
GND
GND
GND
GND
GND
GND
DVDD
LVDS
DVDD
LVDS
TRDYN
TRDYP
7
6
NC
NC
DVDD
LVDS
DVDD
LVDS
GND
GND
GND
GND
GND
GND
DVDD
LVDS
DVDD
LVDS
HRESN
HRESP
6
5
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
OVRAN
OVRAP
SYNC
OUTN
SYNC
OUTP
5
4
NC
NC
NC
NC
NC
NC
NC
DA0P
DA2P
DA4P
DA6P
DA8P
NC
NC
4
3
NC
NC
NC
NC
NC
NC
NC
DA0N
DA2N
DA4N
DA6N
DA8N
DA11N
DA11P
3
2
NC
NC
NC
NC
NC
NC
NC
DACLKP
DA1P
DA3P
DA5P
DA7P
DA10N
DA10P
2
1
NC
NC
NC
NC
NC
NC
NC
DACLKN
DA1N
DA3N
DA5N
DA7N
DA9N
DA9P
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
TRIGGER TRIGGER
N
P
10
Figure 6-1. ADS54T01 ZAY Package, 196-Pin NFBGA, Top View (DDR Output Mode)
Table 6-1. Pin Functions
PIN
NAME
NUMBER
I/O TYPE(1)
DESCRIPTION
INPUT/REFERENCE
INA_P/N
K14, L14
I
Analog ADC differential input signal.
VCM
B14
O
Output of the analog input common mode (nominally 1.9 V). A 0.1-μF capacitor to
AGND is recommended, but not required.
VREF
A14
I
Reference voltage input. A 0.1-μF capacitor to AGND is recommended.
P14, P13
I
Differential input clock
CLOCK/SYNC
CLKINP/N
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Table 6-1. Pin Functions (continued)
PIN
I/O TYPE(1)
DESCRIPTION
P9, N9
I
Synchronization input. Inactive if logic low. When clocked in a high state initially, this
is used for resetting internal clocks and digital logic and starting the SYNCOUT signal.
Internal 100-Ω termination.
SRESET
B12
I
Serial interface reset input. Active low. Initialized internal registers during high-to-low
transition. Asynchronous. Internal 50-kΩ pullup resistor to IOVDD.
ENABLE
B11
I
Chip enable – active high. Power-down function can be controlled through SPI
register assignment. Internal 50-kΩ pullup resistor to IOVDD.
SCLK
A12
I
Serial interface clock. Internal 50-kΩ pulldown resistor.
SDIO
A11
I/O
SDENB
A13
I
Serial interface enable. Internal 50-kΩ pulldown resistor.
SDO
A10
O
Uni-directional serial interface data in 4-pin mode (register x00, D16). The SDO pin is
tri-stated in 3-pin interface mode (default). Internal 50-kΩ pulldown resistor.
DA[11:0]P/N
P3, N3, P2, N2,
P1, N1, M4, M3,
M2, M1, L4, L3,
L2, L1, K4, K3,
K2, K1, J4, J3,
J2, J1, H4, H3
O
ADC A Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output.
DACLKP/N
H2, H1
O
DDR differential output data clock for Bus A. Register programmable to provide either
rising or falling edge to center of stable data nominal timing.
SYNCOUTP/N
P5, N5
O
Synchronization output signal for synchronizing multiple ADCs. Can be disabled
through the SPI.
OVRAP/N
M5, L5
O
Bus A, Overrange indicator, LVDS output. A logic high signals an analog input in
excess of the full-scale range. Optional SYNC output.
P10, N10
I
Trigger used for high-resolution output data in feedback mode. Internal 100-Ω
termination.
TRDYP/N
P7, N7
O
Trigger ready output indicator
HRESP/N
P6, N6
O
Indicator for high-resolution output data; logic high signals 12-bit output data.
A1, A2, A3, A4,
A5, A6, A7, B1,
B2, B3, B4, B5,
B6, B7, C1, C2,
C3, C4, C5, D1,
D2, D3, D4, D5,
D14, E1, E2, E3,
E4, E14, F1, F2,
F3, F4, G1, G2,
G3, G4, N4, P4
–
Do not connect to pin, leave floating.
B13
–
Used for factory internal test. Do not connect to pin, leave floating.
D12, E12, F12,
G12, H12, J12,
K12, L12, N12,
P12
P
3.3-V analog supply
AVDDC
G14, H14
P
1.8-V supply for clock input
AVDD18
D10, D11, E11,
F11, G11, H11,
J11, K11, L10,
L11, N11, P11
P
1.8-V analog supply
NAME
NUMBER
SYNCP/N
CONTROL/SERIAL
Bidirectional serial data in 3-pin mode (default). In 4-pin interface mode (register x00,
D16), the SDIO pin in an input only. Internal 50-kΩ pulldown resistor.
DATA INTERFACE
TRIGGERP/N
NO CONNECT
NC
TESTMODE
POWER SUPPLY
AVDD33
4
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Table 6-1. Pin Functions (continued)
PIN
I/O TYPE(1)
DESCRIPTION
NAME
NUMBER
DVDD
A8, A9, B8, B9,
C8, D8, L8, M8,
N8, P8
P
1.8-V supply for digital block
DVDDLVDS
C6, C7, D6, D7,
L6, L7, M6, M7
P
1.8-V supply for LVDS outputs
B10
P
1.8-V for digital I/Os
C9, C10, C11,
C12, C13, C14,
D9, D13, E5, E6,
E7, E8, E9, E10,
E13, F5, F6, F7,
F8, F9, F10, F13,
F14, G5, G6, G7,
G8, G9, G10,H5,
H6, H7, H8, H9,
H10, J5, J6, J7,
J8, J9, J10, K5,
K6, K7, K8, K9,
K10, L9, M9,
M10, M11, M12,
M13, M14,N13,
N14
GND
IOVDD
GND
(1)
Ground
The definitions below define the I/O type for each pin.
•
•
•
•
•
I = Input
O = Output
I/O = Input / Output
P = Power Supply
G = Ground
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Voltage applied to input pins
MIN
MAX
AVDD33
–0.5
4
V
AVDDC
–0.5
2.3
V
AVDD18
–0.5
2.3
V
DVDD
–0.5
2.3
V
DVDDLVDS
–0.5
2.3
V
IOVDD
–0.5
4
V
INA_P, INA_N
–0.5
AVDD33 + 0.5
V
CLKINP, CLKINN
–0.5
AVDDC + 0.5
V
SYNCP, SYNCN
–0.5
AVDD33 + 0.5
V
SRESET, SDENB, SCLK, SDIO, SDO, ENABLE
–0.5
IOVDD + 0.5
V
Operating free-air temperature, TA
–40
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
85
°C
150
°C
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
V (ESD)
(1)
6
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Recommended operating junction temperature
TJ
TA
(1)
NOM
MAX
105
Maximum rated operating junction temperature(1)
125
Recommended free-air temperature
–40
25
85
UNIT
°C
°C
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.
7.4 Thermal Information
ADS54T01
THERMAL
METRIC(1)
ZAY (NFBGA)
UNIT
196 PINS
Junction-to-ambient thermal resistance(2)
θJA
resistance(3)
θJCtop
Junction-to-case (top) thermal
θJB
Junction-to-board thermal resistance(4)
parameter(5)
ψJT
Junction-to-top characterization
ψJB
Junction-to-board characterization parameter(6)
(1)
(2)
(3)
(4)
(5)
(6)
37.6
°C/W
6.8
°C/W
16.8
°C/W
0.2
°C/W
16.4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
7.5 Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
ADC Clock Frequency
40
Resolution
12
TYP
MAX
UNITS
750
MSPS
Bits
SUPPLY
AVDD33
3.15
3.3
3.45
V
AVDDC, AVDD18, DVDD, DVDDLVDS
1.7
IOVDD
1.7
1.8
1.9
V
1.8
3.45
V
POWER SUPPLY
IAVDD33
3.3-V Analog supply current
154
170
mA
IAVDD18
1.8-V Analog supply current
66
80
mA
IAVDDC
1.8-V Clock supply current
42
60
mA
IDVDD
1.8-V Digital supply current
Auto Correction Enabled
250
280
mA
IDVDD
1.8-V Digital supply current
Auto Correction Disabled
215
IDVDD
1.8-V Digital supply current
Auto Correction Disabled, decimation filter enabled
234
IDVDDLVDS
1.8-V LVDS supply current
IIOVDD
1.8-V I/O Voltage supply current
mA
mA
66
90
mA
1
2
mA
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7.5 Electrical Characteristics (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
TYP
MAX
UNITS
1.75
W
Pdis
Total power dissipation
Auto Correction Enabled, decimation filter disabled
1.28
Pdis
Total power dissipation
Auto Correction Disabled, decimation filter disabled
1.2
PSRR
250 kHz to 500 MHz
Shutdown power dissipation
Standby power dissipation
Standby wake-up time
Deep-sleep mode power dissipation
W
dB
mW
2.5
ms
7
mW
100
µs
Auto correction disabled
350
mW
Auto correction enabled
475
mW
20
µs
Auto correction disabled
655
mW
Auto correction enabled
780
mW
Deep-sleep mode wake-up time
Light-sleep mode power dissipation
40
7
Shutdown wake-up time
Light-sleep mode wake-up time
8
MIN
2
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7.6 Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD3V = 3.3 V, AVDD/DRVDD/IOVDD = 1.8 V, –1-dBFS differential input (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNITS
Differential input full-scale
1.0 1.25
Vpp
Input common-mode voltage
1.9 ±0.1
V
ANALOG INPUTS
Input resistance
Differential at DC
1
kΩ
Input capacitance
Each input to GND
2
pF
VCM common-mode voltage output
1.9
Analog input bandwidth (3 dB)
V
1200
MHz
DYNAMIC ACCURACY
Offset Error
Auto Correction Disabled
–20
Auto Correction Enabled
–1
Offset temperature coefficient
–7.5
20
0
1
–6.5
Gain error
–5
Gain temperature coefficient
mV
mV
µV/°C
5
0.005
%FS
%FS/°C
Differential nonlinearity
fIN = 230 MHz
–1
±0.9
2
LSB
Integral nonlinearity
fIN = 230 MHz
–5
±1.5
5
LSB
40
750
MHz
40%
50% 60%
CLOCK INPUT
Input clock frequency
Input clock amplitude
2
Input clock duty cycle
Internal clock biasing
0.9
Vpp
V
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7.7 Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
Auto Correction
TYP MAX
Enabled
MIN
TYP MAX UNITS
Disabled
Vpp
DYNAMIC AC CHARACTERISTICS(1) – Burst Mode Enabled: 12-bit High Resolution Output Data
SNR
Signal to Noise Ratio
HD2,3
Second and third harmonic
distortion
fIN = 10 MHz
61.1
61.2
fIN = 100 MHz
61.1
61.1
fIN = 230 MHz
60.7
60.9
fIN = 450 MHz
59
59.9
60.5
fIN = 700 MHz
58.6
59.6
fIN = 10 MHz
81
83
fIN = 100 MHz
76
81
fIN = 230 MHz
78
79
fIN = 450 MHz
75
76
fIN = 700 MHz
74
76
78
79
75
77
fIN = 230 MHz
73
73
fIN = 450 MHz
68
69
fIN = 700 MHz
64
66
fIN = 10 MHz
90
87
84
82
79
76
fIN = 450 MHz
72
72
fIN = 700 MHz
66
69
fIN = 10 MHz
61.0
61.1
fIN = 100 MHz
60.8
61.0
fIN = 10 MHz
Non
HD2,3
Spur Free Dynamic Range
(excluding second and third
harmonic distortion)
fIN = 100 MHz
68
fIN = 100 MHz
IL
Fs/2-Fin interleaving spur
SINAD
Signal to noise and distortion
ratio
fIN = 230 MHz
fIN = 230 MHz
65
57.5
IMD3
Inter modulation distortion
(1)
10
Effective number of bits
dBc
60.8
59.8
60.3
fIN = 700 MHz
58.4
59.4
76
76
73
76
74
74
fIN = 450 MHz
74
73
fIN = 700 MHz
72
74
Fin = 184.5 and 185.5 MHz, –7
dBFS
82
83
Fin = 549.5 and 550.5 MHz, –7
dBFS
76
77
90
90
dB
9.8
9.8
LSB
fIN = 230 MHz
66
Crosstalk
ENOB
dBc
60.5
fIN = 100 MHz
Total Harmonic Distortion
dBc
fIN = 450 MHz
fIN = 10 MHz
THD
dBFS
fIN = 230 MHz
dBc
dBc
dBFS
SFDR and SNR calculations do not include the DC or Fs/2 bins when Auto Correction is disabled.
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7.8 Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OVER-DRIVE RECOVERY ERROR
Input overload recovery
Recovery to within 5% (of final value) for 6-dB
overload with sine wave input
2
ns
SAMPLE TIMING CHARACTERISTICS
rms
Aperture Jitter
Data Latency
Over-range Latency
Sample uncertainty
100
fs rms
ADC sample to digital output, Auto correction
disabled
38
ADC sample to digital output, Auto correction
enabled
50
ADC sample to digital output, Decimation filter
enabled, Auto correction disabled
74
Sampling
clock
Cycles
ADC sample to over-range output
12
Clock
Cycles
Clock
Cycles
7.9 Electrical Characteristics
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE
High-level input voltage
Low-level input voltage
All digital inputs support 1.8-V and 3.3-V
logic levels.
0.7 x
IOVDD
High-level input current
–50
Low-level input current
–50
Input capacitance
V
0.3 x
IOVDD
V
200
µA
50
µA
5
pF
DIGITAL OUTPUTS – SDO
Iload = -100 µA
High-level output voltage
Iload = -2 mA
IOVDD –
0.2
V
0.8 x
IOVDD
Iload = 100 µA
Low-level output voltage
0.2
0.22 x
IOVDD
Iload = 2 mA
V
DIGITAL INPUTS – SYNCP/N, TRIGGERP/N
VID
Differential input voltage
VCM
Input common-mode voltage
250
350
450
1.125
1.2
1.375
tSU
500
mV
V
ps
DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, TRDYP/N, HRESP/N
VOD
Output differential voltage
Iout = 3.5 mA
250
350
450
VOCM
Output common-mode voltage
Iout = 3.5 mA
1.125
1.25
1.375
tsu
Fs = 750 Msps
Data valid to zero-crossing of DACLK
320
400
ps
th
Fs = 750 Msps
Zero-crossing of DACLK to data becoming
invalid
250
320
ps
tPD
Fs = 750Msps
CLKIN falling edge to DACLK rising edge
3.36
3.69
3.92
mV
V
ns
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7.9 Electrical Characteristics (continued)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V
MIN
TYP
MAX
UNITS
tRISE
PARAMETER
10% - 90%
TEST CONDITIONS
100
150
200
ps
tFALL
90% - 10%
100
150
200
ps
Data Latency 38 Clock Cycles
SAMPLE N
CLKINP
tPD
DACLKP
DACLK edges are centered
within the data valid window
DA[11:0]P/N
OVRAP/N
TRDYP/N
HRESP/N
N-1
N
N+1
CLKIN, DACLK are differential:
Only the ‘P’ positive signal shown for clarity
tsu
th
Figure 7-1. Timing Diagram for 12-Bit DDR Output
12
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7.10 Typical Characteristics
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
Figure 7-2. FFT for 10-MHz Input Signal (Auto On)
Figure 7-3. FFT for 10-MHz Input Signal (Auto Off)
Figure 7-4. FFT for 230-MHz Input Signal (Auto On)
Figure 7-5. FFT for 230-MHz Input Signal (Auto Off)
Figure 7-6. FFT for 450-MHz Input Signal (Auto On)
Figure 7-7. FFT for 450-MHz Input Signal (Auto Off)
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
14
Figure 7-8. FFT for 700-MHz Input Signal (Auto On)
Figure 7-9. FFT for 700-MHz Input Signal (Auto Off)
Figure 7-10. SFDR vs. Input Frequency
Figure 7-11. SNR vs. Input Frequency
Figure 7-12. SFDR vs. Amplitude (fin = 230 MHz)
Figure 7-13. SNR vs. Amplitude (fin = 230 MHz)
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
Figure 7-14. Tow Tone Performance Across Input Amplitude (fin
= 185 MHz)
Figure 7-15. SFDR vs. Vref (Auto On)
Figure 7-16. SFDR vs. Vref (Auto Off)
Figure 7-17. SNR vs. Vref (Auto On)
Figure 7-18. SNR vs. Vref (Auto Off)
.
Figure 7-19. Performance Across Input Common-Mode Voltage
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
16
Figure 7-20. Performance Across Temperature (fin = 230 MHz)
Figure 7-21. Performance Across AVDD33 (fin = 230 MHz)
Figure 7-22. Performance Across AVDD18 (fin = 230 MHz)
Figure 7-23. Performance Across Clock Amplitude
Figure 7-24. INL
Figure 7-25. DNL
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
Figure 7-26. CMRR Across Frequency
Figure 7-27. PSRR Across Frequency
Figure 7-28. Power Across Sampling Frequency
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
Figure 7-29. SFDR Across Input and Sampling Frequencies (Auto On)
18
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
Figure 7-30. SFDR Across Input and Sampling Frequencies (Auto Off)
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
Figure 7-31. SNR Across Input and Sampling Frequencies (Auto On)
20
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7.10 Typical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750 Msps, 50%
clock duty cycle, AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V, –1-dBFS differential input, unless
otherwise noted.
Figure 7-32. SNR Across Input and Sampling Frequencies (Auto On)
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8 Detailed Description
8.1 Overview
The ADS54T01 is a 12-bit, single channel ADC that operates at sampling rates of up to 750 Msps. This
device has excellent SFDR over a large input frequency range and low noise performance. The ADC accepts
differential signals for the clock input and analog input buffers. The analog input buffer provides an isolated
signal from the source with a high-impedance input.
OVRAP/N
SRESET
8.2 Functional Block Diagram
SCLK
OVERRANGE
VREF
VCM
THRESHOLD
SDIO
CONTROL
SDO
VOLTAGE
REFERENCE
BUFFER
INA_P/N
PROGRAMMING
DATA
SDENB
INTERLEAVING
CORRECTION
ADC
Estimator
DC or
Fs/2
SYNCOUTP/M
FIR FILTER
Gain Correction
DEC
x2
SYNCOUTP/N
CLKOUT
GEN
DACLKP/N
SYNCP/N
MULTICHIP
SYNC
BURST MODE
PROCESSING
DDR LVDS
OUTPUT BUFFER
CLKINP/N
...
Offset Correction
CLOCK
DISTRIBUTION
DA[11:0]P/N
TRDYP/N
BURST MODE
TRIGGER
HRESP/N
TRIGGERP/N
Figure 8-1. Functional Block Diagram
8.3 Feature Description
8.3.1 Test Pattern Output
The ADS54T01 can be configured to output different test patterns that can be used to verify the digital interface
is connected and working properly.
To enable the test pattern mode, the high-performance mode 1 has to be disabled first through the SPI register
write. Then different test patterns can be selected by configuring registers x3C, x3D, and x3E. All three registers
must be configured for the test pattern to work properly.
First set HP1 = 0 (Addr 0x01, D01)
Internally the test pattern replaces the sampled data from the ADC. However at the LVDS outputs the output
data is still subject to burst mode operation. In low-resolution output, the LSBs of the test pattern are replaced
with 0 s.
22
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Test Pattern
LVDS Outputs
ADC Output Data
Burst Mode
Trigger
Figure 8-2. Test Pattern Selection
Table 8-1. Test Pattern Register Setting
Register Address
All 0s
All 1s
Toggle (0xAAA => 0x555)
Toggle (0xFFF => 0x000)
0x3C
0x8000
0xBFFC
0x9554
0xBFFC
0x3D
0x0000
0x3FFC
0x2AA8
0x0000
0x3E
0x0000
0x3FFC
0x1554
0x3FFC
Table 8-2. Custom Pattern Register Setting
Register
Address
Custom Pattern
D15
D14
x3C
1
0
x3D
0
0
x3E
0
0
D13
D11
D12
D10
D11
D9
D10
D8
D9
D7
D8
D6
D7
D5
D6
D4
D5
D3
D4
D3
D2
D1
D2
D0
D1
D0
0
0
0
0
0
0
For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, and 0x3E all to 0.
8.3.2 Clock Inputs
The ADS54T01 clock input can be driven differentially with a sine wave, LVPECL, or LVDS source with little or
no difference in performance. The common-mode voltage of the clock input is set to 0.9 V using internal 2-kΩ
resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close to
the clock inputs as possible to minimize signal reflections and jitter degradation.
0.1uF
CLKINP
CLKINP
2kΩ
RT
0.9V
0.1uF
2kΩ
RT
CLKINN
CLKINN
0.1uF
Recommended differential clock driving circuit
Figure 8-3. Recommended Differential Clock Driving Circuit
8.3.3 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors: the quantization noise is typically not
noticeable in pipeline converters and is 72 dB for a 12-bit ADC. The thermal noise limits the SNR at low input
frequencies while the clock jitter sets the SNR for higher input frequencies.
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SNRQuantization _ Noise
æ
SNR ADC [dBc] = -20 ´ log çç 10 20
è
2
2
2
ö æ
SNRThermalNoise ö æ
SNRJitter ö
+
10
+
10
÷÷ ç
÷ ç
÷
20
20
ø è
ø
ø è
(1)
Use Equation 2 to calculate the SNR limitation due to sample clock jitter.
SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter)
(2)
The total clock jitter (tJitter) has three components: the internal aperture jitter (100 fs for ADS54T01) which is set
by the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. Use
Equation 3 to calculate the total clock jitter.
TJitter =
(TJitter,Ext.Clock_Input)2 + (TAperture_ADC)2
(3)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as bandpass
filters at the clock input while a faster clock slew rate improves the ADC aperture jitter.
The ADS54T01 has a thermal noise of 61.2 dBFS and internal aperture jitter of 100 fs. Figure 8-4 shows the
SNR depending on amount of external jitter for different input frequencies.
Figure 8-4. SNR vs. Frequency and External Clock Jitter
8.3.4 Analog Inputs
The ADS54T01 analog signal input is designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source which enables great flexibility
in the external analog filter design as well as excellent 50 Ω matching for RF applications. The buffer also helps
isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a
more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 1.9 V using 500-Ω resistors which allows
for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM
+ 0.25 V) and (VCM – 0.25 V), resulting in a 1.0 Vpp (default) differential input swing. The input sampling circuit
has a 3-dB bandwidth that extends up to 1.2 GHz.
24
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2nH
0.5Ω
20Ω
INA_P
1.3pF
500Ω
0.5Ω
500Ω
1.4pF
Vcm= 1.9V
2nH
20Ω
INA_N
1.3pF
1.4pF
Figure 8-5. Analog Input Internal Circuitry
8.3.5 Over-Range Indication
The ADS54T01 provides a fast over-range indication on the OVRA/B pins. The fast OVR is triggered if the input
voltage exceeds the programmable overrange threshold and it gets presented after just 12 clock cycles enabling
a quicker reaction to an overrange event. The OVR threshold can be configured using SPI register writes.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the over-range threshold bits. The threshold at which fast OVR is triggered is (full-scale × [the decimal
value of the FAST OVR THRESH bits] /16). After reset, the default value of the over-range threshold is set to 15
(decimal) which corresponds to a threshold of 0.56 dB below full scale (20 × log(15/16)).
Figure 8-6. OVR Detection Threshold
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8.3.6 Interleaving Correction
The data converter channel consists of two interleaved ADCs each operating at half of the ADC sampling
rate but 180° out of phase from each other. The front end track and hold circuitry is operating at the full
ADC sampling rate which minimizes the timing mismatch between the two interleaved ADCs. In addition, the
ADS54T01 is equipped with internal interleaving correction logic that can be enabled through a SPI register
write.
ADC
ODD
Input
Track &
Hold
Fs
Interleaving
Correction
Fs/2
0 deg
ADC
EVEN
Estimator
Fs/2
180 deg
Figure 8-7. Interleaving Correction Block Diagram
The interleaving operation creates 2 distinct and interleaving products:
•
•
Fs/2 – Fin: this spur is created by gain timing mismatch between the ADCs. Since internally the front end
track and hold is operated at the full sampling rate, this component is greatly improved and mostly dependent
on gain mismatch.
Fs/2 Spur: due to offset mismatch between ADCs
Input
Signal
Fs/2 Spur
Fs/2 - Fin
Fs/2
Figure 8-8. Interleaving Correction Spurs
The auto correction loop can be enabled through a SPI register write in address 0x01. By default, the
auto correction function is disabled for lowest possible power consumption. The default settings for the auto
correction function should work for most applications. However please contact Texas Instruments if further fine
tuning of the algorithm is required.
The auto correction function yields best performance for input frequencies below 250 MHz.
8.3.7 High-Resolution Output Data
After trigger, the data outputs DA[11..0] are 12-bit resolution for 2N samples, where N is a programmable register
with a range 10 ≤ N ≤ 25 (corresponding to 1024 to 33554432 samples).
26
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M
Sample
M+1
M+2
...
INA_P/N
CLKINP/N
tPDI
Latency = X clock cycles
DACLKP/N
12-bit data
DA[11:0]
Sample #
M-6
M-5
M-4
M-3
M-2
M-1
M
M+1
M+2
M+3
Figure 8-9. High-Resolution Data Output Timing
After the high-resolution data, the data output returns to low-resolution mode, the logic level of the HRES flag
returns low and the trigger is locked out for 2(N+3) samples. N is the sample integer resulting in a maximum
output duty cycle of 1/9. During the trigger lockout time, a low to high transition on TRIGGERP/N will be ignored.
After the 2N+3 low-resolution samples, the TRIGGERP/N is re-enabled for the next valid data burst.
8.3.8 Low-Resolution Output Data
There are two different options for the low-resolution output data and the selection is made through SPI register
control. The data can either be output at full speed (ADC sampling rate) with the output resolution limited to 7 bit
(7 MSBs). Alternatively the output resolution can be selected to 11 bit (11 MSBs) but at a reduced effective data
rate where every 4th sample gets repeated four times.
8.3.9 Full Speed – 7 Bit
The output data rate and timing is exactly the same as the high-resolution data, only the output resolution is
limited to the 7 MSBs.
Full Speed Low Resolution
Sample
M
M+1
M+2
...
INA_P/N
CLKINP/N
tPDI
Latency = X clock cycles
DACLKP/N
7-bit data
DA[11:5]
Sample #
M-6
M-5
M-4
M-3
M-2
M-1
M
M+1
M+2
M+3
Figure 8-10. Full-Rate, Low-Resolution Output Data Timing
8.3.10 Decimated Low-Resolution Output Data
In decimated low-resolution mode, the output data is limited to 11 bits and every sample is repeated four times,
so the effective data rate is 1/4 of ADC sampling rate. The latency of the ADC sample to output sample is exactly
the same as for high-resolution data—there is no uncertainty in which conversion sample results in the valid
output data. This is because the output continues to run at the ADC sample rate in decimated low-resolution
mode where only the resolution is changed and three out of four samples are deleted.
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Decimated Low Resolution Mode
Sample
M
M+1
M+2
M+3
M+4 ...
INA_P/N
CLKINP/N
tPDI
Latency = X clock cycles
DACLKP/N
11-bit data
DA[11:1]]
Sample
M-8 M-4 M-4 M-4 M-4
M-8
repeat repeat
repeat repeat repeat
M
M
M
M
repeat repeat repeat
M+4
Figure 8-11. Decimated Low-Resolution Output Data Timing Diagram
8.3.11 Multi Device Synchronization
The ADS54T01 simplifies the synchronization of data from multiple ADCs in one common receiver. Upon
receiving the initial SYNC input signal, the ADS54T01 resets all the internal clocks and digital logic while also
starting a SYNCOUT signal which operates on a 5-bit counter (32 clock cycles). Therefore, by providing a
common SYNC signal to multiple ADCs, their output data can be synchronized as the SYNCOUT signal marks
a specific sample with the same latency in all ADCs. The SYNCOUT signal then can be used in the receiving
device to synchronize the FIFO pointers across the different input data streams. Thus the output data of multiple
ADCs can be aligned properly even if there are different trace lengths between the different ADCs.
ADS54T01
DxCLK
Sample x
SYNCOUT
Sample 1
DA[11:0]
ChA
FIFO
Pointer
Sample 2
Sample 3
Sample 4
Sample 5
Sample 6
...
FPGA
ASIC
SYNC
ADS54T01
ChA
DxCLK
Sample x
SYNCOUT
Sample 1
DA[11:0]
FIFO
Pointer
Sample 2
Sample 3
Sample 4
Sample 5
Sample 6
...
Figure 8-12. Multi Device SYNC
The SYNC input signal should be a one-time pulse to trigger the periodic 5-bit counter for SYNCOUT or a
periodic signal repeating every 32 CLKIN clock cycles. The signal is registered on the rising edge of the ADC
input clock (CLKIN). Upon registering the initial rising edge of the SYNC signal, the internal clocks and logic get
reset which results in invalid output data for 36 samples (1 complete sync cycle and 4 additional samples). The
SYNCOUT signal starts with the next output clock (DACLK) rising edge and operates on a 5-bit counter. If a
SYNCIN rising edge gets registered at a new position, the counter gets reset and SYNCOUT starts from the new
position.
The ADS54T01 output interface operates with a DDR clock, therefore the synchronization can happen on the
rising edge or falling edge sample. Synchronization on the falling edge sample will result in a half cycle clock
stretch of DACLK. For convenience, the SYNCOUT signal is available on the ChA output LVDS bus.
When using decimation, the SYNCOUT signal still operates on 32 clock cycles of CLKIN, but because the output
data is decimated by 2, only the first 18 samples should be discarded.
28
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CLKIN
16 clock cycles
SYNC
16 clock cycles
DACLK
16 clock cycles
SYNCOUT
16 clock cycles
DA[11:0]
Data invalid – 36 samples
SYNC
16 clock cycles
16 clock cycles
DACLK
SYNCOUT
16 clock cycles
16 clock cycles
DA[11:0]
Data invalid – 36 samples
Figure 8-13. SYNC Timing Diagram
8.4 Device Functional Modes
8.4.1 Power-Down Modes
The ADS54T01 can be configured through a SPI write (address x37) to a standby, light, or deep sleep power
mode which is controlled by the ENABLE pin. The sleep modes are active when the ENABLE pin goes low.
Different internal functions stay powered up which results in different power consumption and wake up time
between the two sleep modes.
Table 8-3. Sleep Mode Power Consumption
Sleep Mode
Wake-Up Time
Power Consumption With Auto
Correction Disabled
Power Consumption With
Auto Correction Enabled
Complete Shutdown
2.5 ms
7 mW
7 mW
Standby
100 µs
7 mW
7 mW
Deep Sleep
20 µs
350 mW
475 mW
Light Sleep
2 µs
655 mW
780 mW
8.4.2 Feedback Mode: Burst Mode
In burst mode, the output data is alternated between a high-resolution, 12-bit output of 2N samples and a lowresolution, 7-bit or 11-bit output of 2N+3 samples. Burst mode is enabled through a SPI register write and there
are two basic operating modes available: a manual trigger mode where the high-resolution output is initiated
through an external trigger and an auto-trigger mode where the internal logic transitions to a high-resolution
output immediately after transmitting the last low-resolution sample. After burst mode is enabled through a SPI
register write, the ADS54T01 transmits 213 low-resolution samples and the trigger command is locked out until
completion.
The parameter N can be changed through the SPI at any time. The change will go into effect with the next output
cycle, starting with the transmission of low-resolution samples. The default value for N after reset is N=10.
Table 8-4. Burst Mode Samples Per Cycle
N limit
Number of low resolution samples per cycle (2N+3)
Number of high resolution samples per cycle
(2N)
Total amount of samples per cycle
10 (minimum)
25 (maximum)
8,192
268,435,456
1,024
33,554,432
9,216
301,989,888
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Table 8-4. Burst Mode Samples Per Cycle (continued)
N limit
10 (minimum)
25 (maximum)
83.3M
83.3M
Maximum number of high resolution (12-bit) samples per 1 second
8.4.3 Receive Mode: Decimation Filter
Figure 8-14 shows that each channel has a digital filter in the data path.
750 MSPS
Lowpass/
Highpass
selection
Low Latency Filter
375 MSPS
ADC
2
Figure 8-14. Decimation Filter Block Diagram
The filter can be programmed as a low-pass or a high-pass filter and the normalized frequency response of
both filters. The decimation filter response has a 0.1-dB pass-band ripple with approximately 41% pass-band
bandwidth. The stop-band attenuation is approximately 40 dB.
Figure 8-15. Decimation Filter Response
Figure 8-16. Decimation Filter Response
8.4.4 Manual Trigger Mode
The control of the high-resolution output is shown below along with the two output flags (TRDY and HRES).
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Enable
Burst Mode
Manual Trigger
Trigger on rising
edge of TRIGGER
TRIGGER
tTRIG_DELAY
TRDY
DA[11..0]
High-Resolution
210 samples
Low Resolution
213 samples
Ready for
new trigger
High-Resolution
2N samples
Low Resolution
2(N+3) samples
Update value N
Ready for
new trigger
HRES
Figure 8-17. Triggering High Resolution Mode and Lockout Time
After enabling burst mode, the output data DA[11..0] are forced to low-resolution mode for 213 samples. During
that period, any trigger signal is ignored. The completion of the low-resolution sample cycle is signaled by a logic
high on the TRDY output pins indicating that a high-resolution (12-bit) data output burst can be triggered by a
low-to-high transition on the TRIGGER input. The ADC monitors the TRIGGER input at each rising edge of the
input clock.
The high-resolution output data starts with a delay of tTRIG_DELAY = 1-2 DACLK clock cycles and is indicated
through the HRES data flag which stays high for all 2N high-resolution samples. At completion the register value
for N is verified and transmission of 2(N+3) low-resolution data immediately follows. When the last low-resolution
sample is output on the output data bus, the flag TRDY is asserted high again indicating the end of the lockout
period and the next 2N high-resolution samples can be triggered again.
8.4.5 Auto Trigger Mode
This mode is enabled by setting the auto trigger bit through a SPI register write and the DA data outputs start
in low resolution for 213 samples. Immediately following completion of transmission of the last low resolution
sample, the outputs automatically start transmitting 210 high-resolution samples without the need for external
trigger ensuring maximum efficiency. Any input signal on the TRIGGER pins is ignored and the TRDY flag will go
high only for one clock cycle with the start of the high-resolution data.
The output flag HRES is aligned with the 2N high-resolution output samples and the parameter N can be
changed until the next output cycle starts again with low-resolution output data.
Enable
Burst Mode
Auto Trigger
High for one
clock cycle
TRDY
DA[11..0]
Low Resolution
213 samples
High-Resolution
210 samples
Low Resolution
2(N+3) samples
High-Resolution
2N samples
Update value N
HRES
Figure 8-18. Auto Trigger Mode Timing Diagram
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8.5 Programming
The serial interface (SIF) included in the ADS54T01 is a simple 3 or 4 pin interface. In normal mode, 3 pins are
used to communicate with the device. There is an enable (SDENB), a clock (SCLK) and a bidirectional IO port
(SDIO). If the user would like to use the 4-pin interface one write must be implemented in the 3-pin mode to
enable 4-pin communications. In this mode, the SDO pin becomes the dedicated output. The serial interface has
an 8-bit address word and a 16-bit data word. The first rising edge of SCLK after SDENB goes low will latch the
read/write bit. If a high is registered, then a read is requested. If it is low, then a write is requested. SDENB must
be brought high again before another transfer can be requested. The signal diagram is shown below:
8.5.1 Device Initialization
After power up, TI recommends to initialize the device through a hardware reset by applying a logic low pulse on
the SRESETb pin (of width greater than 20 ns), as shown in Figure 8-19. This resets all internal digital blocks
(including SPI registers) to their default condition.
Power
Supplies
t1
SRESETb
t2
t3
SDENb
Figure 8-19. Device Initialization Timing Diagram
Table 8-5. Reset Timing
PARAMETER
CONDITIONS
t1
Power-on delay
Delay from power up to active low RESET pulse
t2
Reset pulse width
t3
Register write delay
MIN
TYP
MAX UNIT
3
ms
Active low RESET pulse width
20
ns
Delay from RESET disable to SDENb active
100
ns
Recommended Device Initialization Sequence:
1.
2.
3.
4.
Power up
Reset ADS54T01 using hardware reset.
Apply clock and input signal.
Set register 0x01 bit D15 to "1" (ChA Corr EN) to enable gain/offset correction circuit and other desired
registers.
5. Set register 0x03 bit D14 to "1" (Start Auto Corr ChA). This clears and resets the accumulator values in the
DC and gain correction loop.
6. Set register 0x03 bit D14 to "0" (Start Auto Corr ChA). This starts the DC and gain auto-correction loop.
8.5.2 Serial Register Write
The internal register of the ADS54T01 can be programmed following these steps:
1. Drive SDENB pin low
2. Set the R/W bit to "0" (bit A7 of the 8-bit address)
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3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
written
4. Write 16-bit data which is latched on the rising edge of SCLK
SCLK
SDENB
SDIO
A6
RWB
A5
A4
Read = 1
Write = 0
A3
A2
A1
A0
D15
D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7 bit address space
16bit data: D15 is MSB, D0 is LSB
Figure 8-20. Serial Register Write Timing Diagram
Table 8-6. Timing Requirements
PARAMETER
TYP(1)
MIN
MAX UNIT
fSCLK
SCLK frequency (equal to 1/tSCLK)
tSLOADS
SDENB to SCLK setup time
25
ns
tSLOADH
SCLK to SDENB hold time
25
ns
tDSU
SDIO setup time
25
ns
tDH
SDIO hold time
25
ns
(1)
>DC
20
MHz
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD3V
= 3.3 V, AVDD, DRVDD = 1.9 V, unless otherwise noted.
8.5.3 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDO/SDIO
pins. This read-back mode may be useful as a diagnostic check to verify the serial interface communication
between the external controller and the ADC.
1. Drive SDENB pin low
2. Set the RW bit (A7) to "1". This setting disables any further writes to the registers
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
read.
4. The device outputs the contents (D15 to D0) of the selected register on the SDO/SDIO pin
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the RW register bit to "0".
SCLK
SDENB
SDIO
RWB
A6
Read = 1
Write = 0
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7 bit address space
16bit data: D15 is MSB, D0 is LSB
Figure 8-21. Serial Register Read Timing Diagram
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8.6 Register Maps
8.6.1 Serial Register Map
Table 8-7. Serial Registers
Register
Address
Register Data(1)
A7–A0 IN
HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
3/4 Wire
SPI
DecFil/
Burst
0
High/
Low
Pass
0
0
0
0
0
0
Burst
rate
0
0
Auto
Trigger
0
0
1
Corr EN
0
0
0
0
0
0
0
0
0
0
0
Data
Format
0
Hp
Mode1
0
2
0
1
1
0
0
0
0
0
0
0
0
0
0
DC
Offset
Corr
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
3
Over-range threshold
E
1
Sync Select
F
Sync Select
1A
0
0
0
0
1
0
1
2B
0
0
0
0
0
0
0
0
0
VREF Set
0
0
1
Temp Sensor
2C
Reset
34
Burst Mode N
37
Sleep Modes
38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LP Mode
TEMP
EN
BIAS EN
SYNC
EN
TRIGEN
1
1
1
1
0
0
0
0
DACLK
EN
DBCLK
EN
0
OVRA
EN
OVRB
EN
HP Mode2
3A
LVDS Current Strength
Internal LVDS
Termination
LVDS SW
66
(1)
0
LVDS Output Bus A EN
Multiple functions in a register can be programmed in a single write operation.
8.6.2 Description of Serial Interface Registers
Register Address
Register Data
A7-A0 in hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
3/4 Wire
SPI
Dec
Fil/
Burst
0
High/
Low
Pass
0
0
0
0
0
0
Burst
rate
0
0
Auto
Trigger
0
0
D15
3/4 Wire SPI
Default 0
0
3-wire SPI is used with SDIO pin operating as bidirectional I/O port
1
4-wire SPI is used with SDIO pin operating as data input and SDO pin as data output port.
D14
DecFil/ Burst
Default 0
0
Burst mode enable
1
2x decimation filter enabled
D12
High/Low Pass
Default 0
0
Low Pass
1
High Pass
D5
Burst Rate
Default 0
0
Low resolution (9-bit) full output rate
1
Decimated low resolution output (4x decimation, 11-bit resolution)
D2
Auto Trigger
Default 0
0
Manual trigger mode using the external trigger input pin
1
Auto trigger mode enabled
34
Enables 4-bit serial interface when set
2x decimation filter (Receive Mode) is enabled when bit is set
(Decimation filter must be enabled first: set bit D14)
Low resolution output data rate in burst mode
Enables auto trigger mode in burst mode without the need to control the trigger pin.
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Register Address
Register Data
A7-A0 in hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
Corr EN
0
0
0
0
0
0
0
0
0
0
0
Data
Format
0
HP
Mode1
0
D10
D9
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
D15
Corr EN (should be enabled for maximum performance)
Default 0
0
auto gain correction disabled
1
auto gain correction enabled
D3
Data Format
Default 0
0
Two's complement
1
Offset Binary
D1
HP Mode 1
Default 0
1
Must be set to 1 for optimum performance
Register Address
Register Data
A7-A0 in hex
D15
D14
D13
D12
D11
2
0
1
1
0
0
D14
Read back 1.
D13
Read back 1.
D10-D7
Over-range threshold
D8
D7
Over-range threshold
The over-range detection is triggered 12 output clock cycles after the overload condition occurs. The threshold at which the
OVR is triggered = 1.0V x [decimal value of ]/16. After power up or reset, the default value is 15
(decimal) which corresponds to a OVR threshold of 0.56dB below fullscale (20*log(15/16)). This OVR threshold is applicable
to both channels.
Default 1111
Figure 8-22. Over-range Threshold vs. Programmed Value
Register Address
Register Data
A7-A0 in hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3
0
DC
Offset
Coff
0
0
1
0
1
1
0
0
0
1
1
0
0
0
D14
DC Offset Corr
Default 1
Starts DC offset correction loop
0
Starts offset correction loop
1
DC offset correction loop is cleared
D11, 9, 8, 4, 3
Must be set to 1 for maximum performance
Default 1
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Register Address
A7-A0 in hex
Register Data
D15
D14
D13
D12
D11
D10
E
D9
D15-D2
Sync Select
Default 1010 1010 1010 10
0000 0000 0000 00
Sync is disabled
0101 0101 0101 01
Sync is set to one shot (one time synchronization only)
1010 1010 1010 10
Sync is derived from SYNC input pins
1111 1111 1111 11
not supported
D7
D6
D5
D4
D3
D2
A7-A0 in hex
D1
D0
0
0
Sync selection for the clock generator block (also need to see address
0x0F)
Register Address
Register Data
D15
D14
F
D13
D12
Sync Select
D11
D10
D9
D8
D7
0
0
0
0
0
D15-D12
Sync Select
Default 1010 1010 1010 10
0000
Sync is disabled
0101
Sync is set to one shot (one time synchronization only)
1010
Sync is derived from SYNC input pins
1111
not supported
D6-D4
VREF SEL
Default 000
000
1.0 V
001
1.25 V
010
0.9 V
011
0.8 V
100
1.15 V
Others
external reference
D6
D5
D4
VREF Sel
D3
D2
D1
D0
0
0
0
0
Sync selection for the clock generator block
Internal voltage reference selection
Register Address
Register Data
A7-A0 in hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1A
0
0
0
0
1
0
1
1
0
0
0
1
1
0
0
0
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
D0
D14, 11, 9, 8, 4, 3
Must be set to 1 for maximum performance
Default 1
Register Address
Register Data
A7-A0 in hex
D15
D14
D13
D12
D11
D10
D9
2B
0
0
0
0
0
0
0
D8-D0
Temp Sensor
A7-A0 in hex
D7
Temp Sensor
Register Data
D15
D14
D13
D12
2C
D15-D0
D8
Internal temperature sensor value – read only
Register Address
D11
D10
D9
D8
D7
D6
D5
D4
Reset
Reset
Default 0000
1101001011110000
36
D8
Sync Select
This is a software reset to reset all SPI registers to their default value. Self clears to 0.
Perform software reset
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Register Address
Register Data
A7-A0 in hex
D15
D14
34
0
0
D13-D10
Burst Mode N
Default 0000
0000
N = 10
0001
N = 11
...
...
1111
N = 25
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
Burst Mode N
This is the parameter that sets the amount of high resolution samples in burst mode
Register Address
A7-A0 in hex
Register Data
D15
D14
37
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
Sleep Modes
D15-D14
Sleep Modes
Default 00
Sleep mode selection which is controlled by the ENABLE pin. Sleep modes are active when ENABLE pin goes low.
000000
Complete shut down
Wake up time 2.5 ms
100000
Standby mode
Wake up time 100 µs
110000
Deep sleep mode
Wake up time 20 µs
110101
Light sleep mode
Wake up time 2 µs
Register Address
A7-A0 in hex
Register Data
D15
D14
D13
38
D12
D11
D10
D9
HP Mode 2
D15-D9
HP Mode 2
Default 111111111
1
Set to 1 for normal operation
D8
LP Mode
Default 1
0
Set to 0 to turn off unused output buffers
D7
TEMP EN
Default 1
1
Set to 1 to enable the temperature sensor
D6
FUSE BIAS EN
Default 1
0
Internal fuse bias powered down
1
Internal fuse bias enabled
D5
SYNC EN
Default 1
0
SYNC input buffer disabled
1
SYNC input bffer enabled
D4
TRIG EN
Default 1
0
TRIGGER input buffer disabled
1
TRIGGER input bffer enabled
D3-D0
Read back 1
D8
D7
D6
D5
D4
D3
D2
D1
D0
LP
Mode
TEMP
EN
FUSE
Bias EN
SYNC
EN
TRIG
EN
1
1
1
1
Low power mode
Temperature sensor enable
Enables internal bias voltages. Can be disabled after power up for power savings.
Enables the SYNC input buffer.
Enables the TRIGGER input buffer.
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Register Address
A7-A0 in hex
Register Data
D15
3A
D14
D13
D12
LVDS Current Strength
D11
LVDS SW
D10
D9
Internal LVDS
Termination
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
DACLK
EN
0
0
OVRA
EN
0
D3
D2
D1
D0
D15-D13
LVDS Current Strength
Default 000
LVDS output current strength.
000
2 mA
100
3 mA
001
2.25 mA
101
3.25 mA
010
2.5 mA
110
3.5 mA
011
2.75 mA
111
3.75 mA
D12-D11
LVDS SW
Default 01
LVDS driver internal switch setting – correct range must be set for setting in D15-D13
01
2 mA to 2.75 mA
11
3mA to 3.75mA
D10-D9
Internal LVDS Termination
Default 00
00
2 kΩ
01
200 Ω
10
200 Ω
11
100 Ω
D4
DACLK EN
Default 1
0
DACLK output buffer powered down
1
DACLK output buffer enabled
D1
OVRA EN
Default 1
0
OVRA output buffer powered down
1
OVRA output buffer enabled
Internal termination
Enable DACLK output buffer
Enable OVRA output buffer
Register Address
A7-A0 in hex
Register Data
D15
D14
D13
D12
66
D11
D10
D9
D8
D7
D15-D0
LVDS Output Bus EN
Default FFFF
0
Output is powered down
1
Output is enabled
D15
corresponds to TRDYP/N (pins N7, P7)
D14
corresponds to HRESP/N (pins N6, P6)
D13
SYNCOUTP/N (pins N5, P5)
D12
Pins N4, P4 (no connect pins) which are not used and should be powered down for power savings
D11-D0
corresponds to DA11-DA0
38
D6
D5
D4
LVDS Output Bus EN
Individual LVDS output pin power down
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9 Power Supply Recommendations
The device requires a 1.8-V nominal supply for AVDDC, AVDD18, DVDD, DVDDLVDS, and IOVDD. The device
also requires a 3.3-V supply for AVDD33. There are no specific sequence power-supply requirements during
device power-up. AVDDC, AVDD18, DVDD, DVDDLVDS, IOVDD and AVDD33 can power up in any order.
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Product Folder Links: ADS54T01
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ADS54T01
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SLAS918B – DECEMBER 2012 – REVISED APRIL 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
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14-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS54T01IZAY
ACTIVE
NFBGA
ZAY
196
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS54T01I
ADS54T01IZAYR
ACTIVE
NFBGA
ZAY
196
1000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS54T01I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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