ADS5500

ADS5521 SBAS309 − MAY 2004 12 Bit, 105MSPS Analog to Digital Converter FEATURES D D D D D D D D 12-Bit Resolution 105MSPS Sample Rate High SNR: 69.4dB at 100MHz fIN High SFDR: 85.0dB at 100MHz fIN 2.3VPP Differential Input Voltage Internal Voltage Reference 3.3V Single-Supply Voltage Analog Power Dissipation: 564mW − Total Power Dissipation: 700mW D Pin-Compatible with: − − − − − ADS5500 (14-Bit, 125MSPS) ADS5541 (14-Bit, 105MSPS) ADS5542 (14-Bit, 80MSPS) ADS5520 (12-Bit, 125MSPS) ADS5522 (12-Bit, 80MSPS) APPLICATIONS D Wireless Communication D D D D D D − Communication Receivers − Base Station Infrastructure Test and Measurement Instrumentation Single and Multichannel Digital Receivers Communication Instrumentation − Radar, Infrared Video and Imaging Medical Equipment Military Equipment D TQFP-64 PowerPADE Package D Recommended Op Amps: THS3202, THS3201, THS4503, OPA695, OPA847 DESCRIPTION The ADS5521 is a high-performance, 12-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in very little space, the ADS5521 has excellent power consumption of 700mW at 3.3V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS compatible output ensures seamless interfacing with common logic. The ADS5521 is available in a 64-pin TQFP PowerPAD package and is pin-compatible with the ADS5500, ADS5541, ADS5542, ADS5520, and ADS5522. This device is specified over the full temperature range of −40°C to +85°C. AVDD DRVDD CLK+ CLK− Timing Circuitry CLKOUT VIN+ S&H VIN− 12−Bit Pipeline ADC Core Digital Error Correction Output Control D0 . . . D11 OVR DFS CM Internal Reference Control Logic Serial Programming Register ADS5521 DRGND AGND SEN SDATA SCLK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright  2004, Texas Instruments Incorporated www.ti.com PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE−LEAD HTQFP-64(2) PowerPAD PACKAGE DESIGNATOR PAP SPECIFIED TEMPERATURE RANGE −40°C to +85°C PACKAGE MARKING ADS5521I ORDERING NUMBER ADS5521IPAP ADS5521IPAPR TRANSPORT MEDIA, QUANTITY Tray, 160 Tape and Reel, 1000 ADS5521 (1) For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet. (2) Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max). This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS5521 UNIT V V V V V mA °C °C °C RECOMMENDED OPERATING CONDITIONS PARAMETER Supplies Analog supply voltage, AVDD Output driver supply voltage, DRVDD Analog Input Differential input range Input common-mode voltage, VCM(1) Digital Output Maximum output load Clock Input ADCLK input sample rate (sine wave) 1/tC DLL ON DLL OFF 60 10 3 50 105 80 MSPS MSPS VPP % °C 1.5 10 2.3 1.6 VPP V pF 3.0 3.0 3.3 3.3 3.6 3.6 V V MIN TYP MAX UNIT PRODUCT PREVIEW Supply Voltage AVDD to AGND, DRVDD to DRGND AGND to DRGND −0.3 to +3.7 ±0.1 −0.15 to +2.5 −0.3 to DRVDD + 0.3 −0.3 to DRVDD + 0.3 30 −40 to +85 +105 −65 to +150 Analog input to AGND Logic input to DRGND Digital data output to DRGND Input current (any input) Operating temperature range Junction temperature Storage temperature range (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Clock amplitude, sine wave, differential(2) Clock duty cycle(3) Open free-air temperature range −40 +85 (1) Input common-mode should be connected to CM. (2) See Figure 13 for more information. (3) See Figure 12 for more information. 2 ADS5521 www.ti.com SBAS309 − MAY 2004 ELECTRICAL CHARACTERISTICS Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 105MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Resolution Analog Inputs Differential input range Differential input impedance Differential input capacitance Total analog input common-mode current Analog input bandwidth Conversion Characteristics Maximum sample rate Data latency Internal Reference Voltages Reference bottom voltage, VREFM Reference top voltage, VREFP Reference error Common-mode voltage output, VCM Dynamic DC Characteristics and Accuracy No missing codes Differential linearity error, DNL Integral linearity error, INL Offset error Offset temperature coefficient Gain error Gain temperature coefficient Dynamic AC Characteristics fIN = 10MHz 10MHz fIN = 30MHz fIN = 55MHz Signal-to-noise ratio, SNR fIN = 70MHz 70MHz fIN = 100MHz fIN = 150MHz RMS Output noise fIN = 225MHz Input tied to common-mode fIN = 10MHz 10MHz fIN = 30MHz fIN = 55MHz Spurious-free dynamic range, SFDR fIN = 70MHz 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz (1) 1.68mA per input. (2) See Recommended Operating Conditions on page 2. Room temp Full temp range Room temp Full temp range Room temp Full temp range Room temp Full temp range 70.6 70.5 70.4 70.1 69.8 69.7 69.4 68.8 67.4 1.1 85 85 84 83 80 80 85 75 76 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS LSB dBc dBc dBc dBc dBc dBc dBc dBc dBc fIN = 10MHz fIN = 10MHz −0.3 −1 Tested ±0.2 ±0.9 TBD TBD TBD TBD +0.3 +1.5 LSB LSB mV %/°C %FS ∆%/°C −4 0.97 2.11 ±0.9 1.55 ± 0.05 +4 V V % V See timing diagram, Figure 1 See Note 2 16.5 1.5 MSPS Clock Cycles Source impedance = 50Ω See Figure 4 See Figure 4 2.3 6.6 4 3.36(1) 750 VPP kΩ pF mA MHz CONDITIONS MIN TYP 12 (tested) MAX UNIT Bits 3 PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 ELECTRICAL CHARACTERISTICS (continued) Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 105MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER CONDITIONS fIN = 10MHz 10MHz fIN = 30MHz fIN = 55MHz Second-harmonic, HD2 fIN = 70MHz 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz fIN = 10MHz 10MHz fIN = 30MHz fIN = 55MHz Third-harmonic, HD3 Room temp Full temp range Room temp Full temp range Room temp Full temp range MIN TYP 102 101 93 88 82 82 86 80 78 85 85 84 83 Room temp Full temp range 80 80 91 76 78 92 89 70.4 70.3 70.1 69.8 Room temp Full temp range 69.2 69.2 69.2 67.8 66.6 Room temp Full temp range 83.7 83.6 81.5 80.7 Room temp Full temp range 77.2 77.2 82.5 74.1 74.3 MAX UNIT dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc PRODUCT PREVIEW fIN = 70MHz 70MHz fIN = 100MHz fIN = 150MHz Worst-harmonic/spur (other than HD2 and HD3) fIN = 225MHz fIN = 10MHz Room temp fIN = 70MHz fIN = 10MHz 10MHz fIN = 30MHz fIN = 55MHz Room temp Room temp Full temp range Signal-to-noise + distortion, SINAD fIN = 70MHz 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz fIN = 10MHz 10MHz fIN = 30MHz fIN = 55MHz Total harmonic distortion, THD fIN = 70MHz 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz 4 ADS5521 www.ti.com SBAS309 − MAY 2004 ELECTRICAL CHARACTERISTICS (continued) Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 105MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Effective number of bits, ENOB CONDITIONS fIN = 70MHz f = 10.1MHz, 15.1MHz (−7dBFS each tone) f = 30.1MHz, 35.1MHz (−7dBFS each tone) f = 50.1MHz, 55.1MHz (−7dBFS each tone) Power Supply Total supply current, ICC Analog supply current, IAVDD Output buffer supply current, IDRVDD VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V Analog only Total power with 10pF load on digital output to ground With clocks running 212 171 41 564 700 TBD TBD TBD TBD TBD TBD TBD mA mA mA mW mW mW MIN TYP 11.2 TBD TBD TBD MAX UNIT Bits dBc dBc dBc Two-tone intermodulation distortion, IMD Power dissipation Standby power DIGITAL CHARACTERISTICS Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 105MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Digital Inputs High-level input voltage Low-level input voltage High-level input current Low-level input current Input current for RESET Input capacitance Digital Outputs(1) Low-level output voltage High-level output voltage Output capacitance CLOAD = 10pF(2), fS = 105MSPS CLOAD = 10pF(2), fS = 105MSPS −20 4 0.3 3.0 3 2.4 0.8 10 10 V V µA µA µA pF V V pF CONDITIONS MIN TYP MAX UNIT (1) For optimal performance, all digital output lines (D0:D11), including the output clock, should see a similar load. (2) Equivalent capacitance to ground of (load + parasitics of transmission lines). 5 PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 TIMING CHARACTERISTCS N+2 N+3 N+4 N + 16 N + 17 tPDI Analog Input Signal Sample N N+1 N + 15 tA Input Clock t SETUP Output Clock N − 17 Data Out (D0− D11) N − 16 N − 15 N − 13 N−3 N−2 N−1 N tHOLD 16.5 Clock Cycles Data Invalid NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. PRODUCT PREVIEW Figure 1. Timing Diagram TIMING CHARACTERISTICS Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 105MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Switching Specification Aperture delay, tA Aperture jitter (uncertainty) Data setup time, tSETUP Data hold time, tHOLD Data latency, tD(Pipe) Propagation delay, tPDI Data rise time Data fall time Output enable (OE) to output stable delay Input CLK falling edge to data sampling point Uncertainty in sampling instant Data valid to 50% of CLKOUT rising edge CLKOUT rising edge to data becoming invalid Input clock falling edge (on which sampling takes place) to input clock rising edge (on which the corresponding data is given out) Input clock rising edge to data valid Data out 20% to 80% Data out 80% to 20% 1 300 TBD TBD 16.5 TBD 2.5 2.5 2 ns fs ns ns Clock Cycles ns ns ns ms DESCRIPTION MIN TYP MAX UNIT SERIAL PROGRAMMING INTERFACE CHARACTERISTICS The device has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of serial clock SCLK when SEN is active. D Data is loaded at every 16th SCLK falling edge while SEN is low. D Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at falling edge. D In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. D Minimum width of data stream for a valid loading is 16 clocks. D Data can be loaded in multiple of 16-bit words within a single active SEN pulse. 6 ADS5521 www.ti.com SBAS309 − MAY 2004 SDATA A3 A2 A1 A0 D11 D10 D9 DATA D0 ADDRESS MSB Figure 2. DATA Communication is 2-Byte, MSB First tSLOADS SEN tWSCLK tWSCLK tSCLK tSLOADH SCLK t OS SDATA t OH MSB LSB 16 x M MSB LSB Figure 3. Serial Programming Interface Timing Diagram Table 1. Serial Programming Interface Timing Characteristics SYMBOL tSCLK tWSCLK tSLOADS tSLOADH tDS tDH PARAMETER SCLK Period SCLK Duty Cycle SEN to SCLK setup time SCLK to SEN hold time Data Setup Time Data Hold Time MIN(1) 50 25 8 6 8 6 50 75 TYP(1) MAX(1) UNIT ns % ns ns ns ns (1) Typ, min, and max values are characterized, but not production tested. Table 2. Serial Register Table A3 1 A2 1 A1 0 A0 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 DLL OFF D0 0 DESCRIPTION DLL OFF = 0 : internal DLL is on, recommended for 60−105MSPS clock speed DLL OFF = 1 : internal DLL is off, recommended for 10−80MSPS clock speed TP − Test modes for output data capture TP = 0, TP = 0 : Normal mode of operation, TP = 0 TP = 1 : All output lines are pulled to ’0’, TP = 1 TP = 0 : All output lines are pulled to ’1’, TP = 1 TP = 1 : A continuous stream of ’10’ comes out on all output lines PDN = 0 : Normal mode of operation, PDN = 1 : Device is put in power down (low current) mode 1 1 1 0 0 TP TP 0 0 0 0 0 0 0 0 0 1 1 1 1 PDN 0 0 0 0 0 0 0 0 0 0 0 7 PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 Table 3. DATA FORMAT SELECT (DFS TABLE) DFS-PIN VOLTAGE (VDFS) V DFS t 5 12 2 3 1 6 AV DD AV DD AV DD DATA FORMAT Straight Binary Two’s Complement Straight Binary Two’s Complement CLOCK OUTPUT POLARITY Data valid on rising edge Data valid on rising edge Data valid on falling edge Data valid on falling edge 1 AV DD u V DFS u 3 7 AV DD u V DFS u 12 V DFS u 5 6 AV DD PIN CONFIGURATION D11 (MSB) PAP PACKAGE (TOP VIEW) DRVDD DRVDD 49 48 DRGND 47 D1 46 D0 (LSB) 45 NC 44 NC 43 CLKOUT 42 DRGND 41 OE 40 DFS 39 AVDD 38 AGND 37 AVDD 36 AGND 35 RESET 34 AVDD 33 AVDD 32 AGND DRGND DRGND DRGND 50 31 IREF D10 D9 D8 D7 D6 D5 D4 D3 52 29 REFP D2 51 30 REFM PRODUCT PREVIEW 64 DRGND Reserved Reserved Reserved AVDD AGND AVDD AGND AVDD 1 2 3 4 5 6 7 8 9 OVR 63 62 61 60 59 58 57 56 55 54 53 ADS5521 PowerPAD (Connected to Analog Ground) CLKP 10 CLKM 11 AGND 12 AGND 13 AGND 14 AVDD 15 AGND 16 17 CM 18 AGND 19 INP 20 INM 21 AGND 22 AVDD 23 AGND 24 AVDD 25 AGND 26 AVDD 27 AGND 28 AVDD 8 ADS5521 www.ti.com SBAS309 − MAY 2004 PIN ASSIGNMENTS TERMINAL NAME AVDD AGND DRVDD DRGND NC INP INM REFP REFM IREF CM RESET OE DFS CLKP CLKM SEN SDATA SCLK D0 (LSB)−D11 (MSB) OVR CLKOUT NO. 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 6, 8, 12, 13, 14, 16, 18, 21, 23, 25, 27, 32, 36, 38 49, 58 1, 42, 48, 50, 57, 59 44, 45 19 20 29 30 31 17 35 41 40 10 11 4 3 2 46, 47, 51−56, 60−63 64 43 NO. OF PINS 12 14 2 6 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 1 1 I/O I I I I — I I O O I O I I I I I I I I O O O Analog power supply Analog ground Output driver power supply Output driver ground Not connected Differential analog input (positive) Differential analog input (negative) Reference voltage (positive); 0.1µF capacitor in series with a 1Ω resistor to GND Reference voltage (negative); 0.1µF capacitor in series with a 1Ω resistor to GND Current set; 56kΩ resistor to GND; do not connect capacitors Common-mode output voltage Reset (active high), 200kΩ resistor to AVDD Output enable (active high) Data format and clock out polarity select(1) Data converter differential input clock (positive) Data converter differential input clock (negative) Serial interface chip select Serial interface data Serial interface clock Parallel data output Over-range indicator bit CMOS clock out in sync with data DESCRIPTION NOTE: PowerPAD is connected to analog ground. (1) The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are listed in Table 3 on page 8. 9 PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB. Aperture Delay The delay in time between the falling edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle A perfect differential sine wave clock results in a 50% clock duty cycle on the internal conversion clock. Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic ‘1’ state to achieve rated performance. Pulse width low is the minimum time that the ENCODE pulse should be left in a low state (logic ‘0’). At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation of any single LSB transition at the digital output from an ideal 1 LSB step at the analog input. If a device claims to have no missing codes, it means that all possible codes (for a 14-bit converter, 16384 codes) are present over the full operating range. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: Integral Nonlinearity (INL) INL is the deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” or “best fit” determined by a least square curve fit. INL is independent from effects of offset, gain or quantization errors. Maximum Conversion Rate The encode rate at which parametric testing is performed. This is the maximum sampling rate where certified operation is given. Minimum Conversion Rate This is the minimum sampling rate where the ADC still works. Nyquist Sampling When the sampled frequencies of the analog input signal are below fCLOCK/2, it is called Nyquist sampling. The Nyquist frequency is fCLOCK/2, which can vary depending on the sample rate (fCLOCK). Offset Error PRODUCT PREVIEW Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode. Propagation Delay This is the delay between the input clock rising edge and the time when all data bits are within valid logic levels. Signal-to-Noise and Distortion (SINAD) The RMS value of the sine wave fIN (input sine wave for an ADC) to the RMS value of the noise of the converter from DC to the Nyquist frequency, including harmonic content. It is typically expressed in decibels (dB). SINAD includes harmonics, but excludes DC. ENOB + SINAD * 1.76 6.02 If SINAD is not known, SNR can be used exceptionally to calculate ENOB (ENOBSNR). Effective Resolution Bandwidth SINAD + 20Log (10) Input(VS ) Noise ) Harmonics The highest input frequency where the SNR (dB) is dropped by 3dB for a full-scale input amplitude. Gain Error The amount of deviation between the ideal transfer function and the measured transfer function (with the offset error removed) when a full-scale analog input voltage is applied to the ADC, resulting in all 1s in the digital code. Gain error is usually given in LSB or as a percent of full-scale range (%FSR). 10 Signal-to-Noise Ratio (without harmonics) SNR is a measure of signal strength relative to background noise. The ratio is usually measured in dB. If the incoming signal strength in µV is VS, and the noise level (also in µV) is VN, then the SNR in dB is given by the formula: SNR + 20Log (10) VS VN This is the ratio of the RMS signal amplitude, VS (set 1dB below full-scale), to the RMS value of the sum of all other spectral components, VN, excluding harmonics and DC. ADS5521 www.ti.com SBAS309 − MAY 2004 Spurious-Free Dynamic Range (SFDR) The ratio of the RMS value of the analog input sine wave to the RMS value of the peak spur observed in the frequency domain. It may be reported in dBc (that is, it degrades as signal levels are lowered), or in dBFS (always related back to converter full-scale). The peak spurious component may or may not be a harmonic. Temperature Drift Temperature drift (for offset error and gain error) specifies the maximum change from the initial temperature value to the value at TMIN or TMAX. Total Harmonic Distortion (THD) THD is the ratio of the RMS signal amplitude of the input sine wave to the RMS value of distortion appearing at multiples (harmonics) of the input, typically given in dBc. Two-Tone Intermodulation Distortion Rejection The ratio of the RMS value of either input tone (f1, f2) to the RMS value of the worst third-order intermodulation product (2f1 − f2; 2f2 − f1). It is reported in dBc. 11 PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 APPLICATION INFORMATION THEORY OF OPERATION The ADS5521 is a low-power, 12-bit, 105MSPS, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3V supply. The conversion process is initiated by a falling edge of the external input clock. Once the signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 16.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in either straight offset binary or binary two’s complement format. INPUT CONFIGURATION The analog input for the ADS5521 consists of a differential sample-and-hold architecture implemented using a switched capacitor technique, shown in Figure 4. PRODUCT PREVIEW SAMPLE PHASE L1 W1a R1a SAMPLE W 3a PHASE C1a INP CP1 CACROSS SAMPLE W2 PHASE SWITCH CP3 R3 SWITCH L2 R1b C1b SWITCH INM CP2 W1b SAMPLE PHASE L1, L2 : 6nh to 10nh effective R1a, R1b : 25Ω to 35Ω C1a, C1b : 2.2pF to 2.6pF CP1, CP2 : 2.5pF to 3.5pF CP3, CP4, : 1.2pF to 1.8pF CACROSS : 0.8pF to 1.2pF R3 : 80Ω to 120Ω Switches: W1a, W1b : On Resistance: 25Ω to 35Ω W2 : On Resistance: 7.5Ω to 15Ω W3a, W3b : On Resistance: 40Ω to 60Ω W1a, W1b, W2, W3a, W3b : Off Resistance: 1e10 All switches are on in sample phase. Approximately half of every clock period is a sample phase. SAMPLE W 3a PHASE SWITCH CP4 VINCM 1V Figure 4. Analog Input Stage 12 ADS5521 www.ti.com SBAS309 − MAY 2004 This differential input topology produces a high level of AC performance for high sampling rates. It also results in a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5521 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575V and CM – 0.575V. This means that each input is driven with a signal of up to CM ± 0.575V, so that each input has a maximum differential signal of 1.15VPP for a total differential input signal swing of 2.3VPP. The maximum swing is determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM, pin 30). The ADS5521 obtains optimum performance when the analog inputs are driven differentially. The circuit shown in Figure 5 shows one possible configuration using an RF transformer. 4mA f s 125MSPS Where: fS > 60MSPS. (1) This equation helps to design the output capability and impedance of the driving circuit accordingly. When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a transformer, to drive the input of the ADS5521. TI offers a wide selection of single-ended operational amplifiers (including the THS3201, THS3202, OPA847, and OPA695) that can be selected depending on the application. An RF gain block amplifier, such as TI’s THS9001, can also be used with an RF transformer for very high input frequency applications. The THS4503 is a recommended differential input/output amplifier. Table 4 lists the recommended amplifiers. When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA847, or OPA695) to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5521. These three amplifier circuits minimize even-order harmonics. For very high frequency inputs, an RF gain block amplifier can be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of the ADS5521 directly, as shown in Figure 5, or with the addition of the filter circuit shown in Figure 6. Figure 6 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these components be included in the ADS5521 circuit layout when any of the amplifier circuits discussed previously are used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines of the ADS5521 input produces a degradation in performance at high input frequencies, mainly characterized by an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical symmetry as possible between both inputs. Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that can simplify the driver circuit for applications requiring DC coupling of the input. Flexible in their configurations (see Figure 7), such amplifiers can be used for singleended-to-differential conversion, signal amplification. 13 R0 50Ω Z0 50Ω 1:1 INP R 50Ω ADT1− 1WT 10Ω 1nF 0.1µF AC Signal Source ADS5521 INM CM Figure 5. Transformer Input to Convert Single-Ended Signal to Differential Signal The single-ended signal is fed to the primary winding of an RF transformer. Since the input signal must be biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM) from the ADS5521 is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM reference, best performance is obtained when the CM (pin 17) output is filtered to ground with 0.1µF and 0.01µF low-inductance capacitors. Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware that the input structure of the ADC sinks a common-mode current in the order of 4mA (2mA per input). Equation (1) describes the dependency of the common-mode current and the sampling frequency: PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 Table 4. Recommended Amplifiers to Drive the Input of the ADS5521 INPUT SIGNAL FREQUENCY DC to 20MHz DC to 50MHz RECOMMENDED AMPLIFIER THS4503 OPA847 OPA695 10MHz to 120MHz THS3201 THS3202 Over 100MHz THS9001 TYPE OF AMPLIFIER Differential In/Out Amp Operational Amp Operational Amp Operational Amp Operational Amp RF Gain Block USE WITH TRANSFORMER? No Yes Yes Yes Yes Yes +5V − 5V RS 100Ω OPA695 1000pF R1 400Ω AV = 8V/V (18dB) VIN 0.1µF 1:1 RT 100Ω RIN INP RIN CIN INM CM ADS5521 PRODUCT PREVIEW R2 57.5Ω 10Ω 0.1µ F Figure 6. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer RS RG +5V RF RT 10µ F 0.1µF R IN INP +3.3V VOCM 1 µF THS4503 10µ F 0.1µF R IN INM ADS5521 12-Bit/105MSPS CM 10Ω RG − 5V RF 0.1µF Figure 7. Using the THS4503 with the ADS5521 14 ADS5521 www.ti.com SBAS309 − MAY 2004 POWER SUPPLY SEQUENCE The ADS5521 requires a power-up sequence where the DRVDD supply must be at least 0.4V by the time the AVDD supply reaches 3.0V. Powering up both supplies at the same time will work without any problem. If this sequence is not followed, the device may stay in power-down mode. CLOCK INPUT The ADS5521 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 9. POWER DOWN The device will enter power-down in one of two ways: either by reducing the clock speed to between DC and 1MHz, or by setting a bit through the serial programming interface. Using the reduced clock speed, the power-down may be initiated for clock frequencies below 10MHz. For clock frequencies between 1MHz and 10Mhz, this can vary from device to device, but will power-down for clock speeds below 1MHz. The device can be powered down by programming the internal register (see Serial Programming Interface section). The outputs become tri-stated and only the internal reference is powered up to shorten the power-up time. The Power-Down mode reduces power dissipation to a minimum of 180mW. CM CM 5kΩ 5kΩ CLKP CLKM 6pF 3pF 3pF REFERENCE CIRCUIT The ADS5521 has built-in internal reference generation, requiring no external circuitry on the printed circuit board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1µF decoupling capacitor in series with a 1Ω resistor, as shown in Figure 8. In addition, an external 56.2kΩ resistor should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in Figure 8. No capacitor should be connected between pin 31 and ground; only the 56.2kΩ resistor should be used. Figure 9. Clock Inputs When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01µF capacitor, while CLKP is AC-coupled with a 0.01µF capacitor to the clock source, as shown in Figure 10. Square Wave or Sine Wave (3VPP) 0.01µF CLKP ADS5521 CLKM 1Ω 29 1µ F 1Ω 30 1µ F 31 56kΩ IREF REFM REFP 0.01µ F Figure 10. AC-Coupled, Single-Ended Clock Input The ADS5521 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.01µF capacitors, as shown in Figure 11. Figure 8. REFP, REFM, and IREF Connections for Optimum Performance 15 PRODUCT PREVIEW ADS5521 www.ti.com SBAS309 − MAY 2004 0.01µ F CLKP Differential Square Wave or Sine Wave (3VPP) ADS5521 0.01µ F CLKM amplitudes without exceeding the supply rails and absolute maximum ratings of the ADC clock input. Figure 13 shows the performance variation of the device versus input clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, refer to the ADS5521EVM User’s Guide, available for download from www.ti.com. Figure 11. AC-Coupled, Differential Clock Input For high input frequency sampling, it is recommended to use a clock source with very low jitter. Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty cycle should be provided. Figure 12 shows the performance variation of the ADC versus clock duty cycle. TBD Figure 13. AC Performance vs Clock Amplitude PRODUCT PREVIEW TBD Figure 12. AC Performance vs Clock Duty Cycle Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter will further improve as the amplitude is increased. In that sense, using a differential clock allows for the use of larger INTERNAL DLL In order to obtain the fastest sampling rates achievable with the ADS5521, the device uses an internal digital phase lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance at clock frequencies below 60MSPS. In order to operate the device below 60MSPS, the internal DLL must be shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical Performance Curves show the performance obtained in both modes of operation: DLL ON (default), and DLL OFF. In either of the two modes, the device will enter power down mode if no clock or slow clock is provided. The limit of the clock frequency where the device will function properly is ensured to be over 10MHz. 16 ADS5521 www.ti.com SBAS309 − MAY 2004 OUTPUT INFORMATION The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal (CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the full-scale limits. Two different output formats (straight offset binary or two’s complement) and two different output clock polarities (latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active high) is provided to tri-state the outputs. The output circuitry of the ADS5521 has being designed to minimize the noise produced by the transients of the data switching, and in particular its coupling to the ADC analog circuitry. Output D2 (pin 51) senses the load capacitance and adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in the timing diagram of Figure 1, as long as all outputs (including CLKOUT) have a similar load as the one at D2 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply voltage or temperature. External series resistors with the output are not necessary. SERIAL PROGRAMMING INTERFACE The ADS5521 has internal registers for the programming of some of the modes described in the previous sections. The registers should be reset after power-up by applying a 2µs (minimum) high pulse on RESET (pin 35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200kΩ internal pull-up resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. Table 2 shows the different modes and the bit values to be written on the register to enable them. Note that some of these modes may modify the standard operation of the device and possibly vary the performance with respect to the typical data shown in this data sheet. 17 PRODUCT PREVIEW PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device ADS5521IPAP ADS5521IPAPR (1) Status (1) PREVIEW PREVIEW Package Type HTQFP HTQFP Package Drawing PAP PAP Pins Package Eco Plan (2) Qty 64 64 160 1000 None None Lead/Ball Finish Call TI Call TI MSL Peak Temp (3) Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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