ADS5500IPAP

ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 14-Bit, 125Msps ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • • • • • • • • • • • The ADS5500 is a high-performance, 14-bit, 125 Msps analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5500 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic. 14-Bit Resolution 125 Msps Sample Rate High SNR: 71.2 dBFS at 100-MHz fIN High SFDR: 82 dBc at 100-MHz fIN 2.3-VPP Differential Input Voltage Internal Voltage Reference 3.3-V Single-Supply Voltage Analog Power Dissipation: 578 mW Serial Programming Interface TQFP-64 PowerPAD™ Package Recommended Amplifiers: OPA695, OPA847, THS3201, THS3202, THS4503, THS4509, THS9001 The ADS5500 is available in a 64-pin TQFP PowerPAD™ package and in both a commercial and industrial temperature grade device. APPLICATIONS • • • • • • Wireless Communication – Communication Receivers – Base Station Infrastructure Test and Measurement Instrumentation Single and Multichannel Digital Receivers Communication Instrumentation – Radar, Infrared Video and Imaging Medical Equipment ADS5500 PRODUCT FAMILY 80 Msps 105 Msps 125 Msps 12 Bit ADS5522 ADS5521 ADS5520 14 Bit ADS5542 ADS5541 ADS5500 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2007, Texas Instruments Incorporated ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE LEAD HTQFP-64 (2) ADS5500 (1) (2) PACKAGE DESIGNATOR PowerPAD SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to 85°C ADS5500I 0°C to 70°C ADS5500C PAP TRANSPORT MEDIA, QUANTITY ORDERING NUMBER ADS5500IPAP Tray, 160 ADS5500IPAPR Tape and Reel, 1000R ADS5500CPAP Tray, 160 ADS5500CPAPR Tape and Reel, 100 For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet. Thermal pad size: 3,5 mm × 3,5 mm (min), 4 mm × 4 mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in × 3 in PCB. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) ADS5500 Supply voltage UNIT AVDD to AGND, DRVDD to DRGND V AGND to DRGND V Analog input to AGND (2) (2) –0.3 to Min (AVDD + 0.3 V, 3.6 V) V Logic input to DRGND – 0.3 to DRVDD V Digital data output to DRGND –0.3 to DRVDD V 0 to 70 Operating temperature range Junction temperature Storage temperature range (1) (2) °C –40 to 85 105 °C –65 to 150 °C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ω should be added in series with each of the analog input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle of the overshoot should be limited to less than 5% for inputs up to 3.9 V. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage 3 3.3 3.6 V DRVDD Output driver supply voltage 3 3.3 3.6 V 1.45 1.55 ANALOG INPUT Differential input range VCM 2.3 Input common-mode voltage (1) VPP 1.65 V DIGITAL OUTPUT Maximum output load 10 pF CLOCK INPUT ADCLK input sample rate (sine DLL ON wave) 1/tC DLL OFF Clock amplitude, sine wave, differential (see Figure 50 for more information) (1) 2 Input common-mode should be connected to CM. Submit Documentation Feedback 60 125 2 80 1 3 Msps VPP ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS (continued) MIN Clock duty cycle (see Figure 49 for more information) NOM MAX UNIT 50% Open free-air temperature range 0 70 –40 85 °C ELECTRICAL CHARACTERISTICS Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 Msps, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 14 Bits 2.3 VPP ANALOG INPUTS Differential input range Differential input impedance See Figure 41 6.6 Ω Differential input capacitance See Figure 41 4 pF 300 µA Analog input common-mode current (per input) Analog input bandwidth Source impedance = 50Ω 750 Voltage overload recovery time MHz Clock Cycles 4 INTERNAL REFERENCE VOLTAGES VREFM Reference bottom voltage VREFP Reference top voltage 0.97 2.11 Reference error VCM V – 4% ±0.9% V 4% 1.55 ±0.05 Common-mode voltage output V DYNAMIC DC CHARACTERISTICS AND ACCURACY No missing codes Tested DNL Differential linearity error fIN = 10 MHz –0.9 ±0.75 1.1 LSB INL Integral linearity error fIN = 10 MHz –5 ±2.5 5 LSB –11 ±1.5 11 Offset error Offset temperature coefficient 0.02 DC power supply rejection ratio, DC PSRR Gain error mV mV/°C ∆offset error/∆AVDD from AVDD = 3 V to AVDD = 3.6 V (1) 0.25 –2 Gain temperature coefficient ±0.45 0.01 mV/V 2 %FS ∆%/°C DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 25°C to TMAX 71.5 73.2 Full temp range 70.5 72.8 fIN = 30 MHz 72.7 fIN = 55 MHz SNR Signal-to-noise ratio RMS output noise (1) fIN = 70 MHz 71.9 25°C to TMAX 70.8 72.3 Full temp range 69.8 72 fIN = 100 MHz 71.2 fIN = 150 MHz 70.1 fIN = 225 MHz 69.1 Input tied to common-mode 1.1 dBFS LSB Gain error is specified by design and characterization; it is not tested in production. Submit Documentation Feedback 3 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 Msps, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS fIN = 10 MHz MIN TYP 25°C 82 84 Full temp range 78 84 fIN = 30 MHz Spurious-free dynamic range fIN = 70 MHz 79 25°C 80 83 Full temp range 77 82 fIN = 100 MHz 82 fIN = 150 MHz 78 fIN = 225 MHz fIN = 10 MHz HD2 Second-harmonic 82 91 Full temp range 78 86 86 fIN = 55 MHz 84 25°C 80 87 Full temp range 77 83 fIN = 100 MHz 84 fIN = 150 MHz 78 fIN = 225 MHz fIN = 10 MHz 82 89 Full temp range 78 88 90 fIN = 55 MHz Third-harmonic fIN = 70 MHz 79 25°C 80 85 Full temp range 77 82 fIN = 100 MHz 82 fIN = 150 MHz 80 fIN = 225 MHz Worst-harmonic/spur (other than HD2 and HD3) SINAD 4 Signal-to-noise + distortion 25°C 88 fIN = 70 MHz 25°C 86 25°C to TMAX Full temp range 71 72.8 69.5 72.2 fIN = 30 MHz 72.3 fIN = 55 MHz 70.7 fIN = 70 MHz dBc 76 fIN = 10 MHz fIN = 10 MHz dBc 74 25°C fIN = 30 MHz HD3 dBc 74 25°C fIN = 30 MHz fIN = 70 MHz UNIT 84 fIN = 55 MHz SFDR MAX 25°C to TMAX Full temp range 70.3 71.6 69 71.3 fIN = 100 MHz 70.5 fIN = 150 MHz 69.1 fIN = 225 MHz 67.4 Submit Documentation Feedback dBc dBFS ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 Msps, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS fIN = 10 MHz MIN TYP 25°C 80 85 Full temp range 78 83 fIN = 30 MHz Total harmonic distortion fIN = 70 MHz 77 25°C Full temp range 77.5 81 76 79.5 fIN = 100 MHz ENOB IMD Effective number of bits Two-tone intermodulation distortion ACPSRR AC power supply rejection ratio UNIT 82 fIN = 55 MHz THD MAX dBc 79 fIN = 150 MHz 75 fIN = 225 MHz 71.8 fIN = 70 MHz 11.3 f = 10.1 MHz, 15.1 MHz (–7 dBFS each tone) 95 f = 30.1 MHz, 35.1 MHz (–7 dBFS each tone) 94 f = 50.1 MHz, 55.1 MHz (–7 dBFS each tone) 94 Supply noise frequency ≤ 100 MHz 35 Bits dBFS dB POWER SUPPLY ICC Total supply current fIN = 70 MHz 236 265 mA IAVDD Analog supply current fIN = 70 MHz 175 190 mA IDRVDD Output buffer supply current fIN = 70 MHz, 10-pF load from digital outputs to ground 61 75 mA Analog only 578 627 mW Power dissipation Output buffer power with 10-pF load on digital output to ground 202 248 mW Standby power With clocks running 181 250 mW DIGITAL CHARACTERISTICS Valid over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 10 µA Low-level input current –10 µA Input current for RESET Input capacitance –20 µA 4 pF 0.3 V DIGITAL OUTPUTS Low-level output voltage CLOAD = 10 pF High-level output voltage CLOAD = 10 pF Output capacitance Submit Documentation Feedback 2.8 3 V 3 pF 5 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TIMING CHARACTERISTICS NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. Figure 1. Timing Diagram TIMING CHARACTERISTICS (1) (2) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, sampling rate = 125 Msps, 50% clock duty cycle, AVDD = DRVDD = 3.3 V, 3-VPP differential clock, and CLOAD = 10 pF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SWITCHING SPECIFICATION tA Input CLK falling edge to data sampling point Aperture jitter (uncertainty) Uncertainty in sampling instant valid (3) 1 ns 300 fs ns tsu Data setup time Data to 50% of CLKOUT rising edge 2.1 2.5 th Data hold time 50% of CLKOUT rising edge to data becoming invalid(3) 1.7 2.1 tSTART Input clock to output data valid start (4) (5) Input clock rising edge to Data valid start delay tEND Input clock to output data valid end(4)(5) Input clock rising edge to Data valid end delay tJIT Output clock jitter Uncertainty in CLKOUT rising edge, peak-to-peak 150 210 ps tr Output clock rise time Rise time of CLKOUT measured from 20% to 80% of DRVDD 1.7 1.9 ns tf Output clock fall time Fall time of CLKOUT measured from 80% to 20% of DRVDD 1.5 1.7 ns tPDI Input clock to output clock delay Input clock rising edge, zero crossing, to output clock rising edge 50% 4.8 5.5 ns tr Data rise time Data rise time measured from 20% to 80% of DRVDD 3.6 4.6 ns tf Data fall time Data fall time measured from 80% to 20% of DRVDD 2.8 3.7 ns Output enable (OE) to data output delay Time required for outputs to have stable timings w.r.t input clock( after OE is activated (1) (2) (3) (4) (5) 6 Aperture delay 2.2 5.8 4.2 ns 2.9 6.9 ns ns 1000 Clock Cycles Timing parameters are ensured by design and characterization and not tested in production. See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies. Data valid refers to 2 V for LOGIC high and 0.8 V for LOGIC low. See the Output Information section for details on using the input clock for data capture. These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add ½ clock period for the valid number for a falling edge CLKOUT polarity. Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TIMING CHARACTERISTICS (continued) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, sampling rate = 125 Msps, 50% clock duty cycle, AVDD = DRVDD = 3.3 V, 3-VPP differential clock, and CLOAD = 10 pF, (unless otherwise noted) PARAMETER TEST CONDITIONS Wake-up time MIN TYP MAX Time to valid data after coming out of software power down 1000 Time to valid data after stopping and restarting the clock 1000 Latency Time for a sample to propagate to the ADC outputs 17.5 Clock Cycles 17.5 UNIT Clock Cycles Clock Cycles RESET TIMING CHARACTERISTICS Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, 3-VPP differential clock(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SWITCHING SPECIFICATION t1 Power-on delay Delay from power on of AVDD and DRVDD to RESET pulse 10 ms t2 Reset pulse width t3 Register write delay Pulse width of active RESET signal 2 µs Delay from RESET disable to SEN active 2 Power-up time Delay from power-up of AVDD and DRVDD to output stable µs 40 ms Figure 2. Reset Timing Diagram SERIAL PROGRAMMING INTERFACE CHARACTERISTICS The device has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of serial clock SCLK when SEN is active. • Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at falling edge. • Minimum width of data stream for a valid loading is 16 clocks. • Data is loaded at every 16th SCLK falling edge while SEN is low. • In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. • Data can be loaded in multiple of 16-bit words within a single active SEN pulse. • The first 4-bit nibble is the address of the register while the last 12 bits are the register contents. Submit Documentation Feedback 7 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Figure 3. DATA Communication is 2-Byte, MSB First Figure 4. Serial Programming Interface Timing Diagram Table 1. Serial Programming Interface Timing Characteristics MIN (1) PARAMETER TYP (1) MAX (1) 50% 75% tSCLK SCLK period tWSCLK SCLK duty cycle tSLOADS SEN to SCLK setup time 8 ns tSLOADH SCLK to SEN hold time 6 ns tDS Data setup time 8 ns tDH Data hold time 6 ns (1) 50 UNIT 25% ns Min, typ, and max values are characterized, but not production tested. Table 2. Serial Register Table (1) A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DLL CTR L Clock DLL 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Internal DLL is on, recommended for 60–125 Msps clock speed 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Internal DLL is off, recommended for 2-80 Msps clock speed 1 1 1 0 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation 1 1 1 0 0 0 1 0 0 0 0 0 0 0 X 0 All outputs forced to 0. (2) 1 1 1 0 0 1 0 0 0 0 0 0 0 0 X 0 All outputs forced to 1. (2) 1 1 1 0 0 1 1 0 0 0 0 0 0 0 X 0 Each output bit toggles between 0 and 1. (2) (3) 1 1 1 1 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation 1 1 1 1 1 0 0 0 0 0 0 0 0 0 X 0 Device is put in power down (low current) mode TP TP Test Mode PDN (1) (2) (3) 8 DESCRIPTION Power Down The register contents default to the appropriate setting for normal operation upon RESET. The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode outputs will be the two's complement equivalent of these patterns as described in the Output Information section. While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. For example, when D0 is a 1, D1 in not assured to be a 0, and vice versa. Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Table 3. Data Format Select (DFS Table) DFS-PIN VOLTAGE (VDFS) 2 V DFS t 12 AV DD DATA FORMAT CLOCK OUTPUT POLARITY Straight Binary Data valid on rising edge 4 12 5 AV DD t V DFS t 12 AV DD Two's Complement Data valid on rising edge 7 12 AV DD t V DFS t 8 12 AV DD Straight Binary Data valid on falling edge Two's Complement Data valid on falling edge V DFS u 10 12 AV DD PIN CONFIGURATION PIN ASSIGNMENTS TERMINAL NO. OF PINS I/O 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 12 I Analog power supply 6, 8, 12-14, 16, 18, 21, 23, 25, 27, 32, 36, 38 14 I Analog ground 49, 58 2 I Output driver power supply NAME NO. AVDD AGND DRVDD DESCRIPTION Submit Documentation Feedback 9 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 PIN CONFIGURATION (continued) PIN ASSIGNMENTS (continued) TERMINAL NAME NO. NO. OF PINS I/O DRGND 1, 42, 48, 50, 57, 59 6 I Output driver ground INP 19 1 I Differential analog input (positive) INM 20 1 I Differential analog input (negative) REFP 29 1 O Reference voltage (positive); 1-µF capacitor to GND REFM 30 1 O Reference voltage (negative); 1-µF capacitor to GND IREF 31 1 I Current set; 56.2-kΩ resistor to GND; do not connect capacitors CM 17 1 O Common-mode output voltage RESET 35 1 I Reset (active high), internal 200-kΩ resistor to AVDD OE 41 1 I Output enable (active high) DFS 40 1 I Data format and clock out polarity select CLKP 10 1 I Data converter differential input clock (positive) CLKM 11 1 I Data converter differential input clock (negative) SEN 4 1 I Serial interface chip select (3) SDATA 3 1 I Serial interface data (3) SCLK 2 1 I Serial interface clock (3) D0 (LSB)–D13(MSB) DESCRIPTION 44-47, 51-56, 60-63 14 O Parallel data output OVR 64 1 O Over-range indicator bit CLKOUT 43 1 O CMOS clock out in sync with data (1) (2) (3) NOTE: PowerPAD must be connected to analog ground. (1) (2) (3) If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details. Table 3 defines the voltage levels for each mode selectable via the DFS pin. Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins must also run off the same supply voltage as DRVDD. DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the falling edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. 10 Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error does not account for variations in the internal reference voltages (see the Electrical Specifications section for limits on the variation of VREFP and VREFM). Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Offset Error The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Effective Number of Bits (ENOB) The ENOB is a measure of a converter's performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.02 (3) Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX-TMIN. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first eight harmonics (PD). P THD + 10Log 10 S PD (4) Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first eight harmonics. P SNR + 10Log 10 S PN (1) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10Log 10 PN ) PD (2) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. DC Power Supply Rejection Ratio (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. Reference Error The reference error is the variation of the actual reference voltage (VREFP– VREFM) from its ideal value. The reference error is typically given as a percentage. Voltage Overload Recovery Time The voltage overload recovery time is defined as the time required for the ADC to recover to within 1% of the full-scale range in response to an input voltage overload of 10% beyond the full-scale range. Submit Documentation Feedback 11 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted 12 SPECTRAL PERFORMANCE (FFT for 2-MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 15-MHz Input Signal) Figure 5. Figure 6. SPECTRAL PERFORMANCE (FFT for 60-MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 70-MHz Input Signal) Figure 7. Figure 8. SPECTRAL PERFORMANCE (FFT for 80-MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 100-MHz Input Signal) Figure 9. Figure 10. Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SPECTRAL PERFORMANCE (FFT for 150-MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 225-MHz Input Signal) Figure 11. Figure 12. SPECTRAL PERFORMANCE (FFT for 300-MHz Input Signal) TWO-TONE INTERMODULATION Figure 13. Figure 14. TWO-TONE INTERMODULATION TWO-TONE INTERMODULATION Figure 15. Figure 16. Submit Documentation Feedback 13 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted 14 DIFFERENTIAL NONLINEARITY (DNL) INTEGRAL NONLINEARITY (INL) Figure 17. Figure 18. SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY Figure 19. Figure 20. Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE Figure 21. Figure 22. AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE Figure 23. Figure 24. Submit Documentation Feedback 15 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted 16 TOTAL POWER DISSIPATION vs SAMPLING FREQUENCY SIGNAL-TO-NOISE RATIO AND SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE Figure 25. Figure 26. AC PERFORMANCE vs INPUT AMPLITUDE AC PERFORMANCE vs INPUT AMPLITUDE Figure 27. Figure 28. Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted AC PERFORMANCE vs INPUT AMPLITUDE OUTPUT NOISE HISTOGRAM Figure 29. Figure 30. AC PERFORMANCE vs CLOCK AMPLITUDE WCDMA CARRIER Figure 31. Figure 32. Submit Documentation Feedback 17 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SIGNAL-TO-NOISE RATIO (SNR) WITH DLL ON Figure 33. SIGNAL-TO-NOISE RATIO (SNR) WITH DLL OFF Figure 34. 18 Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL ON Figure 35. SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL OFF Figure 36. Submit Documentation Feedback 19 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SECOND HARMONIC (HD2) WITH DLL ON Figure 37. SECOND HARMONIC (HD2) WITH DLL OFF Figure 38. 20 Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted THIRD HARMONIC (HD3) WITH DLL ON Figure 39. THIRD HARMONIC (HD3) WITH DLL OFF Figure 40. Submit Documentation Feedback 21 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS5500 is a low-power, 14-bit, 125 Msps, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 17.5 clock cycles, after which the output data is available as a 14-bit parallel word, coded in either straight offset binary or binary two's complement format.e sample through the pipeline every half clock cycle. This process results INPUT CONFIGURATION The analog input for the ADS5500 consists of a differential sample-and-hold architecture implemented using a switched capacitor technique, shown in Figure 41. NOTE: All Switches are ON in sampling phase which is approximately one half of a clock period. Figure 41. Analog Input Stage This differential input topology produces a high level of AC performance for high sampling rates. It also results in a high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5500 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. This means that each input is driven with a signal of up to CM 0.575 V, so that each input has a maximum 22 differential signal of 1.15 VPP for a total differential input signal swing of 2.3 VPP. The maximum swing is determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM, pin 30). The ADS5500 obtains optimum performance when the analog inputs are driven differentially. The circuit shown in Figure 42 shows one possible configuration using an RF transformer. Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 can be selected depending on the application. An RF gain block amplifier, such as TI's THS9001, can also be used with an RF transformer for very high input frequency applications. The THS4503 is a recommended differential input/output amplifier. Table 4 lists the recommended amplifiers. Figure 42. Transformer Input to Convert Single-Ended Signal to Differential Signal The single-ended signal is fed to the primary winding of an RF transformer. Since the input signal must be biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM) from the ADS5500 is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM reference, best performance is obtained when the CM (pin 17) output is filtered to ground with 0.1 µF and 0.001-µF low-inductance capacitors. Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware that the input structure of the ADC sinks a common-mode current in the order of 600 µA (300 µA per input) at 125 Msps. Equation 5 describes the dependency of the common-mode current and the sampling frequency: 600 mA f s 125MSPS (5) Where: fS > 2 Msps. This equation helps to design the output capability and impedance of the driving circuit accordingly. When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a transformer, to drive the input of the ADS5500. TI offers a wide selection of single-ended operational amplifiers (including the THS3201, THS3202, OPA847, and OPA695) that When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA847, or OPA695) to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5500. These three amplifier circuits minimize even-order harmonics. For very high frequency inputs, an RF gain block amplifier can be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of the ADS5500 directly, as shown in Figure 42, or with the addition of the filter circuit shown in Figure 43. Figure 43 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these components be included in the ADS5500 circuit layout when any of the amplifier circuits discussed previously are used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines of the ADS5500 input produces a degradation in performance at high input frequencies, mainly characterized by an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical symmetry as possible between both inputs. Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that can simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations (see Figure 44), such amplifiers can be used for single-endedto-differential conversion, signal amplification. Submit Documentation Feedback 23 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Table 4. Recommended Amplifiers to Drive the Input of the ADS5500 INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER DC to 20 MHz THS4503 Differential In/Out Amp No DC to 50 MHz OPA847 Operational Amp Yes DC to 100 MHz THS4509 Differential In/Out Amp NO OPA695 Operational Amp Yes THS3201 Operational Amp Yes THS3202 Operational Amp Yes THS90016 RF Gain Block Yes 10 MHz to 120 MHz Over 100 MHz USE WITH TRANSFORMER? Figure 43. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer Figure 44. Using the THS4503 With the ADS5500 POWER SUPPLY SEQUENCING POWER DOWN The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of AVDD and DRVDD. In the case that DRVDD ramps up first in the system, care must be taken to ensure that AVDD ramps up within 10 ms. The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit through the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock frequencies below 2 Msps. The exact frequency at which the power down occurs varies from device to device. 24 Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and only the internal reference remains on to reduce the power-up time. The power-down mode reduces power dissipation to approximately 180 mW. REFERENCE CIRCUIT The ADS5500 has built-in internal reference generation, requiring no external circuitry on the printed circuit board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1-µF decoupling capacitor (the 1-Ω series resistor shown in Figure 45 is optional). In addition, an external 56.2-kΩ resistor should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in Figure 45. No capacitor should be connected between pin 31 and ground; only the 56.2-kΩ resistor should be used. Figure 45. REFP, REFM, and IREF Connections for Optimum Performance CLOCK INPUT The ADS5500 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5-kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 46. Figure 46. Clock Inputs When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01-µF capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in Figure 47. Figure 47. AC-Coupled, Single-Ended Clock Input The ADS5500 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.01-µF capacitors, as shown in Figure 48. Figure 48. AC-Coupled, Differential Clock Input For high input frequency sampling, it is recommended to use a clock source with very low jitter. Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty cycle should be provided. Figure 49 shows the performance variation of the ADC versus clock duty cycle. Submit Documentation Feedback 25 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 DLL OFF mode described in the Serial Interface Programming section. The Typical Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The limit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz. OUTPUT INFORMATION Figure 49. AC Performance vs Clock Duty Cycle Bandpass filtering of the clock source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute maximum ratings of the ADC clock input. Figure 50 shows the performance variation of the device versus input clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the ADS5500EVM user's guide (SLWU010), available for download from www.ti.com. Figure 50. AC Performance vs Clock Amplitudes INTERNAL DLL In order to obtain the fastest sampling rates achievable with the ADS5500, the device uses an internal digital delay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance at clock frequencies below 60 Msps. In order to operate the device below 60 Msps, the internal DLL must be shut off using the 26 The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal (CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals one when the output reaches the full-scale limits. Two different output formats (straight offset binary or two's complement) and two different output clock polarities (latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active high) is provided to put the outputs into a high-impedance state. In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0x3FFF in straight offset binary output format, and 0x1FFF in 2's complement output format. For a negative input overdrive, the output code is 0x0000 in straight offset binary output format and 0x2000 in two's complement output format. These outputs to an overdrive signal are ensured through design and characterization. The output circuitry of the ADS5500, by design, minimizes the noise produced by the data switching transients and, in particular, its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance and adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have nearly the same load as D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply voltage or temperature. Placing external resistors in series with the outputs is not recommended. The timing characteristics of the digital outputs change for sampling rates below the 125 Msps maximum sampling frequency. Table 5 through Table 7 show the values of various timing parameters for lower sampling frequencies, both with DLL on and off. Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (td) that results in the desired setup or hold time. Use either of the following equations to calculate the value of td. Desired setup time = td– tSTART Desired hold time = tEND– td Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON) FS (Msps) tsu (ns) MIN TYP 105 2.2 80 65 th (ns) MAX MIN TYP 2.8 2.2 2.8 3.7 3.8 4.6 tSTART (ns) MAX MIN tEND (ns) TYP MAX MIN TYP 2.5 1.9 2.8 5.8 2.8 3.3 0.5 1.7 3.6 4.1 –0.5 0.8 tr MAX MIN (ns) tf (ns) TYP MAX MIN TYP MAX 7.3 4.4 5.1 3.3 3.8 5.3 7.9 5.8 6.6 4.4 5.3 5.3 8.5 6.7 7.2 5.5 6.4 Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF) FS (Msps) tsu (ns) MIN TYP 80 3.2 65 th (ns) MAX MIN TYP 4.2 1.8 4.3 5.7 40 8.5 20 tSTART (ns) MAX MIN tEND (ns) TYP MAX MIN TYP 3 3.8 5 8.4 2 3 2.8 4.5 11 2.6 3.5 –1 17 25.7 2.5 4.7 10 27 51 4 2 284 370 8 tr MAX MIN (ns) tf (ns) TYP MAX MIN TYP MAX 11 5.8 6.6 4.4 5.3 8.3 11.8 6.6 7.2 5.5 6.4 1.5 8.9 14.5 7.5 8 7.3 7.8 –9.8 2 9.5 21.6 7.5 8 7.6 8 6.5 –30 –3 11.5 31 19 185 320 515 576 50 82 75 150 Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON) FS (Msps) CLKOUT, Rise Time tr (ns) MIN CLKOUT, Fall Time tf (ns) MIN CLKOUT Jitter, Peak-to-Peak tJIT (ps) MIN Input-to-Output Clock Delay tPDI (ns) TYP MAX TYP MAX TYP MAX MIN TYP MAX 105 2 2.2 1.7 1.8 175 250 4 4.7 5.5 80 2.5 2.8 2.1 2.3 210 315 3.7 4.3 5.1 65 3.1 3.5 2.6 2.9 260 380 3.5 4.1 4.8 Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL OFF) FS (Msps) CLKOUT, Rise Time tr (ns) MIN CLKOUT, Fall Time tf (ns) TYP MAX 80 2.5 65 MIN CLKOUT Jitter, Peak-to-Peak tJIT (ps) TYP MAX 2.8 2.1 3.1 3.5 40 4.8 20 8.3 MIN MAX MIN TYP MAX 2.3 210 315 7.1 8 8.9 2.6 2.9 260 380 7.8 8.5 9.4 5.3 4 4.4 445 650 9.5 10.4 11.4 9.5 7.6 8.2 800 1200 13 15.5 18 16 20.7 25.5 537 551 567 10 2 31 Input-to-Output Clock Delay tPDI (ns) TYP 52 36 65 SERIAL PROGRAMMING INTERFACE The ADS5500 has internal registers for the programming of some of the modes described in the previous sections. The registers should be reset after power-up by applying a 2 µs (minimum) high pulse on RESET (pin 35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-kΩ internal pullup resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. Table 2 shows the different modes and the bit values to be written on the register to enable them. 2610 4400 Note that some of these modes may modify the standard operation of the device and possibly vary the performance with respect to the typical data shown in this data sheet. Applying a RESET signal is required to set the internal registers to their default states for normal operation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground and it is necessary to write the default values to the internal registers through the serial programming interface. The registers must be written in the following order. Write 9000h (Address 9, Data 000) Write A000h (Address A, Data 000) Write B000h (Address B, Data 000) Write C000h (Address C, Data 000) Submit Documentation Feedback 27 ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Write Write Write Write Write D000h (Address D, Data 000) E000h (Address E, Data 804) 0000h (Address 0, Data 000) 1000h (Address 1, Data 000) F000h (Address F, Data 000). 2. NOTE: This procedure is only required if a RESET pulse is not provided to the device. 3. PowerPAD PACKAGE The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use of bulky heat sinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques and can be removed and replaced using standard repair procedures. AVDD. The programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom of the IC. This provides a low thermal resistance path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a heatsink. Programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. 4. 5. 6. 7. 8. Data section. The recommended thermal pad dimension is 8 mm x 8 mm. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The small size prevents wicking of the solder through the holes. It is recommended to place a small number of 25 mil diameter holes under the package, but outside the thermal pad area to provide an additional heat path. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a ground plane). Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground plane. The spoke pattern increases the thermal resistance to the ground plane. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking. Apply solder paste to the exposed thermal pad area and all of the package terminals. For more detailed information regarding the PowerPAD package and its thermal properties, see either the SLMA004B application brief PowerPAD Made Easy or SLMA002 technical brief PowerPAD Thermally Enhanced Package. Assembly Process 1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in the Mechanical 28 Submit Documentation Feedback ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 REVISION HISTORY REVISION DATE DESCRIPTION 0.0 12/03 Preliminary data sheet released 1.0 03/04 Data sheet updated to reflect RTM silicon 2.0 09/05 Added information regarding thermal pad size and thermal characteristics of the package. Removed input current from Absolute Maximum Ratings table. Updated specifications to AGND and DRGND. Added notes regarding the input voltage overstress requirements. Changed minimum recommended sampling rate to 2 Msps. Clarified the Electrical Characteristics measurement conditions. Changed analog input common-mode current specification. Removed maximum sampling rate from specification table. Added Voltage Overload Recovery Time specification. Changed offset temperature coefficient to units of mV/°C. Changed power dissipation reporting to separate analog and digital power dissipation. Changed two-tone intermodulation distortion units to dBFS and updated the specification values to reflect this change. Clarified the Digital Characteristics measurement conditions. Added min VOH and max VOL specifications. Added data valid with respect to the input clock, output clock jitter, wakeup time, and output clock rise and fall time parameters. Clarified the Timing Characteristics measurement conditions. Updated the timing diagram in Figure 1 to include tSTART and tEND timing parameters. Added minimum and maximum specifications for various timing parameters. Added section on Reset Timing. Clarified serial interface data word format. Clarified output capture test modes. Simplified the information given in Table 3. Updated the definitions section. Clarified measurement conditions for the specifications plots. Corrected text annotations on the WCDMA signal plot. Added axis label to HD3 with DLL ON contour plot. Updated Figure 4 to correct parameter values and improve readability. Added 25-Ω series resistors to ADC inputs in Figure 5. Corrected text in Input Configuration section to accurately reflect the CM voltage decoupling depicted in Figure 5. Updated Equation 5 to match the new definition of common-mode input current and minimum sample rate. Added 25-Ω series resistors to ADC inputs in Figure 6. Changed Power Supply Sequence section to reduce constraints on the power-up sequence. Updated the Power Down section to reflect the newly specified 2 Msps minimum sampling rate. Updated Output Information text to include information on the output data in over-range conditions, describe data capture using the input clock, and add tables to specify timing parameters at various sampling rates. 3.0 10/05 Improved SNR performance parameters. Updated Reference Circuit section to reflect that the 1-Ω series resistors to REFP and REFM are now optional. Updated timing parameters in Table 5 through Table 8 to reflect revised silicon timing. REV G 02/07 Added min/max specs for offset and gain errors Submit Documentation Feedback 29 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 TRAY Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ ADS5500IPAP PAP HTQFP 64 160 Unit array Max L (mm) W matrix temperature (mm) (°C) 8 x 20 150 Pack Materials-Page 1 315 135.9 K0 (µm) P1 (mm) CL (mm) CW (mm) 7620 15.2 13.1 13 GENERIC PACKAGE VIEW PAP 64 HTQFP - 1.2 mm max height QUAD FLATPACK 10 x 10, 0.5 mm pitch This image is a representation of the package family, actual package may vary. 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