ADS58B18IRGZR

ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer Check for Samples: ADS58B18, ADS58B19 FEATURES DESCRIPTION • • • The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. 1 23 • • • • • • • • • ADS58B18: 11-Bit, 200MSPS ADS58B19: 9-Bit, 250MSPS Integrated High-Impedance Analog Input Buffer Ultralow Power: – Analog Power: 258mW at 200MSPS – I/O Power: 69mW (DDR LVDS, low LVDS swing) High Dynamic Performance: – ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz – ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only) – –77.7dBFS SNR in 20MHz Bandwidth Dynamic Power Scaling with Sample Rate Output Interface: – Double Data Rate (DDR) LVDS with Programmable Swing and Strength – Standard Swing: 350mV – Low Swing: 200mV – Default Strength: 100Ω Termination – 2x Strength: 50Ω Termination – 1.8V Parallel CMOS Interface Also Supported Programmable Gain for SNR/SFDR Trade-Off DC Offset Correction Supports Low Input Clock Amplitude Package: QFN-48 (7mm × 7mm) The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2). Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C). 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2009–2011, Texas Instruments Incorporated ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ADS58B18 QFN-48 RGZ ADS58B19 (1) (2) QFN-48 RGZ ECO PLAN (2) LEAD/BALL FINISH PACKAGE MARKING –40°C to +85°C GREEN (RoHS, no Sb/Br) Cu/NiPdAu AZ58B18 –40°C to +85°C GREEN (RoHS, no Sb/Br) Cu/NiPdAu AZ58B19 ORDERING NUMBER TRANSPORT MEDIA ADS58B18IRGZR Tape and reel ADS58B18IRGZT Tape and reel ADS58B19IRGZR Tape and reel ADS58B19IRGZT Tape and reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. ABSOLUTE MAXIMUM RATINGS (1) ADS58B18, ADS58B19 MIN MAX UNIT Supply voltage range, AVDD –0.3 2.1 V Supply voltage range, AVDD_BUF –0.3 3.9 V Supply voltage range, DRVDD –0.3 2.1 V Voltage between AGND and DRGND –0.3 0.3 V Voltage between AVDD to DRVDD (when AVDD leads DRVDD) –2.4 2.4 V Voltage between DRVDD to AVDD (when DRVDD leads AVDD) –2.4 2.4 V Voltage between AVDD_BUF to DRVDD/AVDD –4.2 4.2 V –0.3 minimum (1.9, AVDD + 0.3) V –0.3 AVDD + 0.3 V INP, INM Voltage applied to input pins (2) CLKP, CLKM , RESET, SCLK, SDATA, SEN, DFS, SNRBoost_En –40 Operating free-air temperature range, TA Operating junction temperature range, TJ –65 Storage temperature range, Tstg ESD, human body model (HBM) (1) (2) +85 °C +125 °C +150 °C 2 kV Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|. Doing so prevents the ESD protection diodes at the clock input pins from turning on. THERMAL INFORMATION ADS58B18 THERMAL METRIC (1) RGZ UNITS 48 PINS θJA Junction-to-ambient thermal resistance 29 θJCtop Junction-to-case (top) thermal resistance n/a θJB Junction-to-board thermal resistance 10 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 9 θJCbot Junction-to-case (bottom) thermal resistance 1.13 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS ADS58B18, ADS58B19 MIN TYP MAX UNIT 1.7 1.8 1.9 V 3 3.3 3.6 V 1.7 1.8 1.9 V SUPPLIES AVDD Analog supply voltage AVDD_BUF Analog buffer supply voltage DRVDD Digital supply voltage ANALOG INPUTS Differential input voltage range 1.5 VPP 1.7 ± 0.05 V Maximum analog input frequency with 1.5VPP input amplitude (1) 400 MHz Maximum analog input frequency with 1VPP input amplitude (1) 600 MHz Input common-mode voltage CLOCK INPUT Input clock sample rate: ADS58B18 Enable low speed mode (2) Low speed mode disabled (default mode after reset) 30 80 MSPS > 80 200 MSPS 30 80 MSPS > 80 250 MSPS Input clock sample rate: ADS58B19 Enable low speed mode (2) Low speed mode disabled (default mode after reset) Input clock amplitude differential (VCLKP – VCLKM) Sine wave, ac-coupled 0.2 1.5 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 1.8 Input clock duty cycle 35 50 V 65 % DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND 5 pF RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω TA Operating free-air temperature (1) (2) –40 +85 °C See the Theory of Operation section in the Application Information. See the Serial Interface section for details on the low-speed mode. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 3 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS58B18/ADS58B19 Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. ADS58B18 PARAMETER TEST CONDITIONS MIN TYP ADS58B19 MAX Resolution SINAD (signal-to-noise and distortion ratio), LVDS HD2 fIN = 70MHz 66.2 55.8 dBFS fIN = 100MHz 66.1 55.8 dBFS 55.8 dBFS fIN = 300MHz 65.3 55.8 dBFS fIN = 10MHz 66.2 55.8 dBFS fIN = 70MHz 66.1 55.8 dBFS fIN = 100MHz 66 55.8 dBFS 55.8 HD3 dBFS IMD Input overload recovery dBFS 76.5 dBc fIN = 70MHz 87 76.2 dBc fIN = 100MHz 87 76.1 dBc 76 dBc 71 81 68.5 fIN = 300MHz 75 75.7 dBc fIN = 10MHz 86.5 85 dBc fIN = 70MHz 85 80 dBc fIN = 100MHz 84 79 dBc 80.5 dBc 70 81 67.5 fIN = 300MHz 74.5 71.5 dBc fIN = 10MHz 90 88 dBc fIN = 70MHz 91 89 dBc fIN = 100MHz 92 85 dBc 85 dBc fIN = 300MHz 79 75 dBc fIN = 10MHz 87.5 89 dBc fIN = 70MHz 87 90 dBc fIN = 100MHz 87 82 dBc 85 71 dBc 76 87 68.5 81 68.5 fIN = 300MHz 75 75 dBc fIN = 10MHz 91 76.5 dBc fIN = 70MHz 91 76.2 dBc fIN = 100MHz 90 76.1 dBc 76 dBc 76 89 68.5 fIN = 300MHz 88 76 dBc f1 = 185MHz, f2 = 190MHz, each tone at –7dBFS –86 –86 dBFS Recovery to within 1% (of final value) for 6dB overload with sine-wave input 1 1 Clock cycles > 30 > 30 dB For 100mVPP signal on AVDD supply, up to 10MHz Effective number of bits ENOB fIN = 170MHz DNL fIN = 170MHz INL fIN = 170MHz 4 54.2 87.5 PSRR Integral nonlinearity 65.8 fIN = 10MHz AC power-supply rejection ratio Differential nonlinearity 54.7 55.7 fIN = 170MHz Two-tone intermodulation distortion 64 66 64.8 fIN = 170MHz Worst spur (other than second and third harmonics) 64.5 fIN = 300MHz fIN = 170MHz Third-harmonic distortion Bits dBFS fIN = 170MHz Second-harmonic distortion UNIT 55.8 fIN = 170MHz THD 9 66.3 fIN = 170MHz SFDR MAX fIN = 10MHz fIN = 170MHz Total harmonic distortion TYP 11 SNR (signal-to-noise ratio), LVDS Spurious-free dynamic range MIN 10.6 –0.7 9 ±0.25 2 ±0.5 ±2.5 Submit Documentation Feedback –0.6 LSBs ±0.15 0.85 LSBs ±0.25 ±1.2 LSBs © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. ADS58B18 PARAMETER MIN TYP ADS58B19 MAX MIN TYP MAX UNIT ANALOG INPUTS Differential input voltage range 1.5 1.5 VPP 4 4 kΩ Differential input capacitance; see Figure 60 2.1 2.1 pF Analog input bandwidth 550 550 MHz DC TYP MAX UNIT 20 MHz fSCLK SCLK frequency (equal to 1/tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDATA setup time 25 ns tDH SDATA hold time 25 ns Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 21 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Serial Register Readout The device includes a mode where the contents of the internal registers can be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially. OVR_SDOUT is a CMOS logic output buffer that runs off the DRVDD supply. 1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT to 0. Only the contents of the register at address 0 cannot be read in the register readout mode. 2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content must be read. 3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin. 4. The external controller can latch the contents at the falling edge of SCLK. 5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin. Register Address A[7:0] = 0x00 SDATA 0 0 0 0 0 0 Register Data D[7:0] = 0x01 0 0 0 0 0 0 0 0 0 1 SCLK SEN OVR_SDOUT The OVR_SDOUT pin functions as OVR (READOUT = 0). a) Enable serial readout (READOUT = 1) Register Address A[7:0] = 0x43 SDATA A7 A6 A5 A4 A3 A2 Register Data D[7:0] = XX (don’t care) A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 SCLK SEN OVR_SDOUT The OVR_SDOUT pin functions as a serial readout (READOUT = 1). b) Read contents of register 0x43. This register has been initialized with 0x40 (device is put in global power-down mode). (1) The OVR_SDOUT pin finctions as OVR (READOUT = 0). (2) The OVR_SDOUT pin finctions as a serial readout (READOUT = 1). Figure 13. Serial Readout Timing Diagram 22 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com SERIAL REGISTER MAP Table 8 summarizes the functions supported by the serial interface. Table 8. Serial Interface Register Map (1) (1) REGISTER ADDRESS DEFAULT VALUE AFTER RESET A[7:0] (Hex) D[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00 00 0 0 0 0 0 0 RESET READOUT 01 00 0 0 25 00 26 00 0 3D 00 DATA FORMAT 3E 00 3F 00 40 00 REGISTER DATA LVDS SWING GAIN 0 0 0 0 ENABLE OFFSET CORR SNRBoost Enable TEST PATTERNS 0 0 LVDS LVDS DATA CLKOUT STRENGTH STRENGTH SNRBoost Coeff1 SNRBoost Coeff2 0 0 0 0 0 0 CUSTOM PATTERN HIGH D[10:3] CUSTOM PATTERN D[2:0] 0 0 CMOS CLKOUT STRENGTH ENABLE CLKOUT RISE CLKOUT FALL POSN 0 0 DIS LOW LATENCY STBY PDN GLOBAL 0 PDN OBUF 0 0 0 0 0 41 00 LVDS CMOS 42 00 43 00 BF 00 0 OFFSET PEDESTAL CF 00 FREEZE OFFSET CORR EA 00 OVERRIDE SNRBoost_ EN PIN 0 DF 00 0 0 0 CLKOUT RISE POSN OFFSET CORR TIME CONSTANT 0 0 LOW SPEED 0 0 ENABLE CLKOUT FALL BYTE-WISE En EN LVDS SWING 0 0 0 0 0 0 0 0 0 0 0 0 Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 23 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DESCRIPTION OF SERIAL REGISTERS Register Address 00h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RESET READOUT Bits[7:2] Always write '0' Bit 1 RESET: Software reset applied This bit resets all internal registers to the default values and self-clears to 0 (default = 1). Bit 0 READOUT: Serial readout This bit sets the serial readout of the registers. 0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage indicator. 1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout. See the Serial Register Readout section. Register Address 01h (Default = 00h) 7 6 5 4 3 2 LVDS SWING Bits[7:2] 1 0 0 0 LVDS SWING: LVDS swing programmability (1) 000000 = Default LVDS swing; ±350mV with external 100Ω termination 011011 = LVDS swing increases to ±410mV 110010 = LVDS swing increases to ±465mV 010100 = LVDS swing increases to ±570mV 111110 = LVDS swing decreases to ±200mV 001111 = LVDS swing decreases to ±125mV Bits[1:0] (1) 24 Always write '0' The EN LVDS SWING register bits must be set to enable LVDS swing control. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 25h (Default = 00h) 7 6 5 4 GAIN Bits[7:4] 3 2 1 0 0 TEST PATTERNS GAIN: Gain programmability These bits set the gain programmability in 0.5dB steps. 0000 0110 0111 1000 1001 1010 1011 1100 = = = = = = = = 0dB gain (default after reset) 0.5dB gain 1dB gain 1.5dB gain 2dB gain 2.5dB gain 3dB gain 3.5dB gain Bit 3 Always write '0' Bits[2:0] TEST PATTERNS: Data capture These bits can be used to verify data capture. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern In the ADS58B18, output data D[10:0] are an alternating sequence of 01010101010 and 10101010101. In the ADS58B19, output data D[8:0] are an alternating sequence of 010101010 and 101010101. 100 = Outputs digital ramp Output data increments by one LSB (11-bit) every eighth clock cycle from code 0 to code 2047 101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern) 110 = Unused 111 = Unused Register Address 26h (Default = 00h) 7 0 6 0 5 0 4 0 3 0 2 1 0 0 LVDS CLKOUT STRENGTH LVDS DATA STRENGTH Bits[7:2] Always write '0' Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength This bit determines the external termination to be used with the LVDS output clock buffer. 0 = 100Ω external termination (default strength) 1 = 50Ω external termination (2x strength) Bit 0 LVDS DATA STRENGTH: LVDS data buffer strength This bit determines the external termination to be used with all of the LVDS data buffers. 0 = 100Ω external termination (default strength) 1 = 50Ω external termination (2x strength) Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 25 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 3Dh (Default = 00h) 7 6 DATA FORMAT Bits[7:6] 5 4 ENABLE OFFSET CORR SNRBoost Enable 3 2 1 0 SNRBoost Coeff1 DATA FORMAT: Data format selection These bits select the data format. 00 = The DFS pin controls data format selection 10 = Twos complement 11 = Offset binary Bit 5 ENABLE OFFSET CORR: Offset correction setting This bit sets the offset correction. 0 = Offset correction disabled 1 = Offset correction enabled Bit 4 SNRBoost Enable: SNRBoost setting This bit enables the SNRBoost. 0 = SNRBoost disabled 1 = SNRBoost enabled Bits[3:0] SNRBoost Coeff1: SNRBoost coefficient 1 See the SNR Enhancement Using SNRBoost section. Register Address 3Eh (Default = 00h) 7 6 5 4 SNRBoost Coeff2 Bits[7:4] 3 2 1 0 0 0 0 0 SNRBoost Coeff2: SNRBoost coefficient 2 See the SNR Enhancement Using SNRBoost section. Bits[3:0] Always write '0' Register Address 3Fh (Default = 00h) 7 6 5 4 3 2 1 0 CUSTOM PATTERN D10 CUSTOM PATTERN D9 CUSTOM PATTERN D8 CUSTOM PATTERN D7 CUSTOM PATTERN D6 CUSTOM PATTERN D5 CUSTOM PATTERN D4 CUSTOM PATTERN D3 Bits[7:0] CUSTOM PATTERN These bits set the custom pattern. Register Address 40h (Default = 00h) 7 6 5 4 3 2 1 0 CUSTOM PATTERN D2 CUSTOM PATTERN D1 CUSTOM PATTERN D0 0 0 0 0 0 Bits[7:5] CUSTOM PATTERN These bits set the custom pattern. Bits[4:0] 26 Always write '0' Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 41h (Default = 00h) 7 6 LVDS CMOS Bits[7:6] 5 4 CMOS CLKOUT STRENGTH 3 ENABLE CLKOUT RISE 2 1 CLKOUT RISE POSN 0 ENABLE CLKOUT FALL LVDS CMOS: Interface selection These bits select the interface. 00 = The DFS pin controls the selection of either LVDS or CMOS interface 01 = DDR LVDS interface 11 = Parallel CMOS interface Bits[5:4] CMOS CLKOUT STRENGTH Controls strength of CMOS output clock only. 00 = Maximum strength (recommended and used for specified timings) 01 = Medium strength 10 = Low strength 11 = Very low strength Bit 3 ENABLE CLKOUT RISE 0 = Disables control of output clock rising edge 1 = Enables control of output clock rising edge Bits[2:1] CLKOUT RISE POSN: CLKOUT rise control Controls position of output clock rising edge LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 500ps, hold increases by 500ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200ps, hold increases by 200ps CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 100ps, hold increases by 100ps 10 = Setup reduces by 200ps, hold increases by 200ps 11 = Setup reduces by 1.5ns, hold increases by 1.5ns Bit 0 ENABLE CLKOUT FALL 0 = Disables control of output clock fall edge 1 = Enables control of output clock fall edge Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 27 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 42h (Default = 00h) 7 6 CLKOUT FALL POSN Bits[7:6] 5 0 4 3 2 1 0 0 DIS LOW LATENCY STBY 0 BYTE-WISE En CLKOUT FALL POSN These bits control the position of the output clock falling edge. LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 400ps, hold increases by 400ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200ps, hold increases by 200ps CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Falling edge is advanced by 100ps 10 = Falling edge is advanced by 200ps 11 = Falling edge is advanced by 1.5ns Bits[5:4] Always write '0' Bit 3 DIS LOW LATENCY: Disable low latency This bit controls the low-latency mode. 0 = Recommended not to use this mode. 1 = After reset, the low-latency mode is disabled and 0dB gain is enabled. Bit 2 STBY: Standby mode This bit sets the standby mode. 0 = Normal operation 1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time from standby is fast Bit 1 Always write '0' Bit 0 BYTE-WISE En: Output data enable 0 = The output data bit sequence is bit-wise (see Figure 22). 1 = The output data bit sequence is byte-wise (see Figure 23 and Figure 24). 28 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 43h (Default = 00h) 7 6 5 4 3 2 1 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING Bit 7 Always write '0' Bit 6 PDN GLOBAL: Power-down 0 This bit sets the state of operation. 0 = Normal operation 1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time. Bit 5 Always write '0' Bit 4 PDN OBUF: Power-down output buffer This bit set the output buffer. 0 = Output buffer enabled 1 = Output buffer powered down Bits[3:2] Always write '0' Bits[1:0] EN LVDS SWING: LVDS swing control 00 01 10 11 = = = = LVDS swing control using LVDS SWING register bits is disabled Do not use Do not use LVDS swing control using LVDS SWING register bits is enabled Register Address BFh (Default = 00h) 7 6 OFFSET PEDESTAL Bits[7:5] 5 4 3 2 1 0 0 0 0 0 0 OFFSET PEDESTAL These bits set the offset pedestal. When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. 011 = +3 LSB 010 = +2 LSB 001 = +1 LSB 000 = 0 LSB 111 = –1 LSB 110 = –2 LSB 101 = –3 LSB 100 = –4 LSB Bits[4:0] Always write '0' Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 29 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address CFh (Default = 00h) 7 6 FREEZE OFFSET CORR 0 Bit 7 5 4 3 2 OFFSET CORR TIME CONSTANT 1 0 0 0 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit ENABLE OFFSET CORR must be set). 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the last estimated value is used for offset correction every clock cycle; see Offset Correction section. Bit 6 Always write '0' Bit[5:2] OFFSET CORR TIME CONSTANT These bits set the offset correction time constant for the correction loop time constant in number of clock cycles. Bits[1:0] VALUE TIME CONSTANT (Number of Clock Cycles) 0000 1M 0001 2M 0010 3M 0011 4M 0100 16M 0101 32M 0110 64M 0111 128M 1000 256M 1001 512M 1010 1G 1011 2G Always write '0' Register Address EAh (Default = 00h) 7 6 5 4 3 2 1 0 OVERRIDE SNBoost_EN PIN 0 0 0 0 0 0 0 Bit 7 OVERRIDE SNBoost_EN PIN: SNBoost_EN pin override After reset, the SNRBoost_En pin controls the turning on and off of the SNRBoost function, independent of the state of register bit SNRBoost Enable. By setting the OVER-RIDE bit to '1', the register bit can control the SNRBoost function. 0 = SNRBoost_En pin controls SNRBoost function, independent of register bit. 1 = Register bit SNRBoost Enable controls the SNRBoost function, independent of SNRBoost_En pin. Bits[6:0] 30 Always write '0' Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address DFh (Default = 00h) 7 6 0 0 5 4 LOW SPEED Bits[7:6] Always write '0' Bits[5:4] LOW SPEED: Low-speed mode 3 2 1 0 0 0 0 0 00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for sampling rates greater than 80MSPS. 11 = Low-speed mode enabled; this setting is recommended for sampling rates lower than or equal to 80MSPS. Bits[3:0] Always write '0' Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 31 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 92.8dBc SNR = 66.1dBFS SINAD = 66.1dBFS THD = 89.5dBc −10 −20 −30 −30 −40 −40 Amplitude (dB) Amplitude (dB) −20 −50 −60 −70 −50 −60 −70 −80 −80 −90 −90 −100 −100 −110 −110 −120 0 20 40 60 80 SFDR = 81.8dBc SNR = 65.8dBFS SINAD = 65.7dBFS THD = 80.6dBc −10 −120 100 0 Frequency (MHz) Figure 15. 80 100 FFT FOR TWO-TONE INPUT SIGNAL 0 Each Tone at −7dBFS Amplitude SFDR = 99.83dBFS fIN1 = 185MHz fIN2 = 190MHz Two-Tone IMD = 86.81dBFS −10 −20 −30 Each Tone at −36dBFS Amplitude SFDR = 98.38dBFS fIN1 = 185MHz fIN2 = 190MHz Two-Tone IMD = 96.95dBFS −10 −20 −30 −40 Amplitude (dB) −40 Amplitude (dB) 60 Figure 14. FFT FOR TWO-TONE INPUT SIGNAL 32 40 Frequency (MHz) 0 −50 −60 −70 −50 −60 −70 −80 −80 −90 −90 −100 −100 −110 −110 −120 20 0 20 40 60 80 100 −120 0 20 40 60 Frequency (MHz) Frequency (MHz) Figure 16. Figure 17. Submit Documentation Feedback 80 100 © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 150MHz INPUT SIGNAL (SNRBoost Enabled, 5MHz Bandwidth) FFT FOR 150MHz INPUT SIGNAL (SNRBoost Enabled, 5MHz Bandwidth) 0 0 AIN = −1dBFS SFDR = 88.5dBc SNR = 78.2dBFS SINAD = 77.6dBFS THD = 85.3dBc Coeff1 = 0x0 Coeff2 = 0x0 BW = 47.5MHz to 52.5MHz −10 −20 −30 −20 −30 −40 Amplitude (dB) Amplitude (dB) −40 −50 −60 −70 −60 −70 −80 −90 −90 −100 −100 −110 −110 0 20 40 60 80 −120 100 20 40 60 80 Frequency (MHz) Figure 18. Figure 19. FFT FOR 150MHz INPUT SIGNAL (SNRBoost Enabled, 20MHz Bandwidth) FFT FOR 150MHz INPUT SIGNAL (SNRBoost Enabled, 20MHz Bandwidth) 100 0 AIN = −1dBFS SFDR = 86.2dBc SNR = 73.7dBFS SINAD = 73.5dBFS THD = 85.1dBc Coeff1 = 0xf Coeff2 = 0x1 BW = 40MHz to 60MHz −10 −20 −30 −20 −30 −40 −50 −60 −70 −50 −60 −70 −80 −80 −90 −90 −100 −100 −110 −110 0 20 40 AIN = −40dBFS SFDR = 55dBc SNR = 77.7dBFS SINAD = 77.5dBFS THD = 52.3dBc Coeff1 = 0xf Coeff2 = 0x1 BW = 40MHz to 60MHz −10 Amplitude (dB) −40 −120 0 Frequency (MHz) 0 Amplitude (dB) −50 −80 −120 AIN = −40dBFS SFDR = 56.9dBc SNR = 83.8dBFS SINAD = 83.5dBFS THD = 55.4dBc Coeff1 = 0x0 Coeff2 = 0x0 BW = 47.5MHz to 52.5MHz −10 60 80 100 −120 0 20 40 60 Frequency (MHz) Frequency (MHz) Figure 20. Figure 21. 80 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 100 33 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 150MHz INPUT SIGNAL (SNRBoost Enabled, 30MHz Bandwidth) FFT FOR 150MHz INPUT SIGNAL (SNRBoost Enabled, 30MHz Bandwidth) 0 0 AIN = −1dBFS SFDR = 89.5dBc SNR = 72.2dBFS SINAD = 72dBFS THD = 85.9dBc Coeff1 = 0xd Coeff2 = 0x3 BW = 35MHz to 65MHz −10 −20 −30 −20 −30 −40 Amplitude (dB) Amplitude (dB) −40 −50 −60 −70 −50 −60 −70 −80 −80 −90 −90 −100 −100 −110 −110 −120 0 20 AIN = −40dBFS SFDR = 57.3dBc SNR = 75.6dBFS SINAD = 75.6dBFS THD = 55.2dBc Coeff1 = 0xd Coeff2 = 0x3 BW = 35MHz to 65MHz −10 40 60 80 −120 100 0 20 40 60 Frequency (MHz) Frequency (MHz) Figure 22. Figure 23. SFDR ACROSS INPUT FREQUENCY 80 100 SNR ACROSS INPUT FREQUENCY 67 95 90 66 85 SNR (dBFS) SFDR (dBc) 80 75 65 70 65 64 60 55 0 50 100 150 200 250 300 350 400 450 500 63 0 50 100 Input Frequency (MHz) Figure 24. 34 150 200 250 300 350 400 450 500 Input Frequency (MHz) Figure 25. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS GAIN SINAD ACROSS GAIN 68 96 150MHz 170MHz 220MHz 300MHz 400MHz 500MHz 92 88 66 64 SINAD (dBFS) SFDR (dBc) 84 80 76 72 68 62 60 58 150MHz 170MHz 220MHz 300MHz 400MHz 500MHz 64 56 60 56 0 0.5 1 1.5 2 2.5 3 54 3.5 0 0.5 1 1.5 Gain (dB) 2 2.5 3 3.5 Gain (dB) Figure 26. Figure 27. SFDR ACROSS AVDD SUPPLY vs TEMPERATURE SNR ACROSS AVDD SUPPLY vs TEMPERATURE 88 66.8 − 40°C − 25°C 25°C 55°C 85°C 86 84 66.4 − 40°C − 25°C 25°C 55°C 85°C 66 SNR (dBFS) SFDR (dBc) 82 80 65.6 65.2 78 64.8 76 64.4 74 Input Frequency = 170MHz 72 1.65 1.70 1.75 1.80 Input Frequency = 170MHz 1.85 1.90 1.95 64 1.65 1.70 1.75 1.80 1.85 AVDD Supply (V) AVDD Supply (V) Figure 28. Figure 29. 1.90 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 1.95 35 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT AMPLITUDE 66 84 SFDR SNR 65.4 78 SFDR (dBc, dBFS) 65.2 76 68 110 67 100 66 90 65 80 64 70 63 60 62 50 61 60 40 SFDR (dBc) SFDR (dBFS) SNR 30 Input Frequency = 170MHz 74 1.65 1.70 1.75 1.80 1.85 1.90 Input Frequency = 170.1MHz 65 1.95 20 −45 −40 −35 −30 DRVDD Supply (V) −20 −10 −5 0 58 Figure 31. PERFORMANCE ACROSS INPUT COMMON-MODE VOLTAGE PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 70 99 SFDR SNR 68 90 SFDR SNR 86 66 90 68.5 84 65 87 68 82 64 84 67.5 80 63 81 67 78 62 78 66.5 76 61 75 66 74 60 72 65.5 72 59 69 65 70 58 64.5 68 66 SFDR (dBc) 88 69 SNR (dBFS) 69.5 93 96 67 57 Input Frequency = 170MHz 63 1.55 1.60 1.65 1.70 1.75 1.80 Input Common-Mode Voltage (V) 64 1.85 Input Frequency = 170MHz 66 0 0.5 1 1.5 2 2.5 3 56 Differential Clock Amplitude (VPP) Figure 32. 36 −15 Amplitude (dBFS) Figure 30. SFDR (dBc) −25 59 SNR (dBFS) SFDR (dBc) 65.6 80 SNR (dBFS) 65.8 82 120 SNR (dBFS) PERFORMANCE ACROSS DRVDD SUPPLY Figure 33. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE ANALOG POWER vs SAMPLING FREQUENCY 67 95 260 THD SNR Includes AVDD and AVDD_BUF Power 250 240 230 66.5 90 66 85 Analog Power (mW) SNR (dBFS) THD (dBc) 220 210 200 190 180 170 65.5 80 160 150 140 Input Frequency = 10MHz 75 35 40 45 50 55 60 65 65 130 120 Input Clock Duty Cycle (%) 0 20 40 60 80 100 120 140 160 180 200 Sampling Speed (MSPS) Figure 34. Figure 35. DRVDD POWER vs SAMPLING FREQUENCY 110 100 DRVDD Power (mW) 90 80 70 60 50 Default With SNRBoost Enable 40 0 20 40 60 80 100 120 140 160 180 200 Sampling Speed (MSPS) Figure 36. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 37 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 75.8dBc SNR = 55.7dBFS SINAD = 55.7dBFS THD = 84.5dBc −10 −20 −20 −30 Amplitude (dB) Amplitude (dB) −30 −40 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 SFDR = 76.2dBc SNR = 55.7dBFS SINAD = 55.7dBFS THD = 78.6dBc −10 0 25 50 75 100 −100 125 0 Frequency (MHz) Figure 38. 100 125 FFT FOR TWO-TONE INPUT SIGNAL 0 Each Tone at −7dBFS Amplitude SFDR = 88.68dBc fIN1 = 185MHz fIN2 = 190MHz Two-Tone IMD = 86.8dBc −10 −20 Each Tone at −36dBFS Amplitude SFDR = 96.75dBFS fIN1 = 185MHz fIN2 = 190MHz Two-Tone IMD = 89.4dBFS −10 −20 −30 Amplitude (dB) −30 Amplitude (dB) 75 Figure 37. FFT FOR TWO-TONE INPUT SIGNAL 38 50 Frequency (MHz) 0 −40 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 25 0 25 50 75 100 125 −100 0 25 50 75 Frequency (MHz) Frequency (MHz) Figure 39. Figure 40. Submit Documentation Feedback 100 125 © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SNR ACROSS INPUT FREQUENCY 80 57 75 56.5 70 56 SNR (dBFS) SFDR (dBc) SFDR ACROSS INPUT FREQUENCY 65 55.5 60 55 55 54.5 50 0 50 100 150 200 250 300 350 400 450 54 500 0 50 100 150 Input Frequency (MHz) 250 300 350 Figure 41. Figure 42. SFDR ACROSS GAIN SINAD ACROSS GAIN 84 400 450 500 58 40MHz 150MHz 170MHz 220MHz 300MHz 400MHz 500MHz 80 57 76 SINAD (dBFS) 72 SFDR (dBc) 200 Input Frequency (MHz) 68 64 56 55 60 150MHz 170MHz 220MHz 300MHz 400MHz 500MHz 56 52 48 0 0.5 1 1.5 2 2.5 3 3.5 54 53 0 0.5 Gain (dB) 1 1.5 2 2.5 3 3.5 Gain (dB) Figure 43. Figure 44. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 39 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS AVDD SUPPLY vs TEMPERATURE 85 58 − 40°C − 25°C 25°C 55°C 85°C 83 81 − 40°C − 25°C 25°C 55°C 85°C 57.5 57 79 56.5 77 56 SNR (dBFS) 75 73 55.5 55 71 54.5 69 54 67 53.5 Input Frequency = 170MHz 65 1.65 1.70 1.75 1.80 1.85 1.90 Input Frequency = 170MHz 53 1.65 1.95 1.75 1.90 1.95 Figure 46. PERFORMANCE ACROSS DRVDD SUPPLY PERFORMANCE ACROSS INPUT AMPLITUDE 58 100 57 90 SFDR (dBc) SFDR (dBFS) SNR 57 56 74 55.5 SFDR (dBc, dBFS) 76 SNR (dBFS) 56.5 78 80 56 70 55 60 54 50 53 40 52 55 72 Input Frequency = 170MHz 1.70 1.75 1.80 1.85 1.90 54.5 1.95 Input Frequency = 170.1MHz 30 −30 −25 DRVDD Supply (V) −20 −15 −10 −5 0 51 Amplitude (dBFS) Figure 47. 40 1.85 Figure 45. SFDR SNR 70 1.65 1.80 AVDD Supply (V) 80 SFDR (dBc) 1.70 AVDD Supply (V) SNR (dBFS) SFDR (dBc) SNR ACROSS AVDD SUPPLY vs TEMPERATURE Figure 48. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT COMMON-MODE VOLTAGE 58 SFDR SNR 57 74 56.5 72 56 70 55.5 68 55 66 54.5 64 54 62 53.5 SFDR (dBc) 76 SNR (dBFS) 57.5 78 57 76 56 74 55 72 54 70 53 Input Frequency = 170MHz 60 1.55 1.60 1.65 1.70 1.75 1.80 Input Frequency = 170MHz 53 1.85 68 0 0.5 Input Common-Mode Voltage (V) 1 1.5 2 2.5 52 3.5 3 Differential Clock Amplitude (VPP) Figure 49. Figure 50. PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE ANALOG POWER vs SAMPLING FREQUENCY 57 90 280 THD SNR Includes AVDD and AVDD_BUF Power 260 240 55.5 75 Analog Power (mW) 56 80 SNR (dBFS) 56.5 85 THD (dBc) SNR (dBFS) SFDR SNR 78 SFDR (dBc) PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 80 58 80 220 200 180 160 140 Input Frequency = 10MHz 70 35 40 45 50 55 Input Clock Duty Cycle (%) 60 65 120 55 100 0 20 40 60 80 100 120 140 160 180 200 Sampling Speed (MSPS) Figure 51. Figure 52. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 41 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. DRVDD POWER vs SAMPLING FREQUENCY 120 110 DRVDD Power (mW) 100 90 80 70 60 50 40 0 20 40 60 80 100 120 140 160 180 200 Sampling Speed (MSPS) Figure 53. 42 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: GENERAL At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PSRR ACROSS FREQUENCY ZOOMED VIEW OF SPECTRUM WITH PSRR SIGNAL 0 0 PSRR on AVDD Supply 50mVPP PSRR on AVDD 3V Supply 100mVPP fIN = 10MHz fPSRR = 1MHz, 50mVPP Amplitude (fIN) = -1dBFS Amplitude (fPSRR) = -64.5 Amplitude (fIN + fP) = -67.4 Amplitude (fIN - fP) = -68.5 fIN −10 -20 −20 -40 Amplitude (dB) PSRR (dB) −30 −40 −50 -60 fPSRR fIN - fPSRR fIN + fPSRR -80 −60 -100 −70 −80 0 10 20 30 40 50 60 70 80 90 -120 100 0 10 5 15 Frequency of Signal on Supply (MHz) 20 25 Figure 54. 35 40 45 50 Figure 55. CMRR ACROSS FREQUENCY SPECTRUM WITH CMRR SIGNAL 0 0 Input Frequency = 170MHz 50mVPP Signal Superimposed on Input Common-Mode Voltage (1.7V) fIN = 170MHz fCM = 10MHz, 50mVPP SFDR = 79.36 Amplitude (fIN) = -1dBFS Amplitude (fCM) = -99.7 Amplitude (fIN + fCM) = -78.1 Amplitude (fIN - fCM) = -80.8 -10 −10 -20 -30 Amplitude (dB) −20 CMRR (dB) 30 Frequency (MHz) −30 -40 -50 fIN (10MHz) -60 fIN + fCM (180MHz) -70 −40 fIN - fCM (160MHz) -80 −50 fCM (10MHz) -90 -100 −60 0 50 100 150 200 250 300 -110 0 10 20 Frequency of Input Common-Mode Signal (MHz) Figure 56. 30 40 50 60 70 80 90 100 Frequency (MHz) Figure 57. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 43 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS58B18 and ADS58B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family with integrated analog buffers and SNRBoost technology. The analog-to-digital conversion process is initiated by a rising edge of the external input clock when the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 10 clock cycles. The output is available as 11-bit data (ADS58B18) or 9-bit data (ADS58B19), in DDR LVDS or CMOS, and coded in either offset binary or binary twos complement format. ANALOG INPUT The analog inputs include an analog buffer (powered by the AVDD_BUF supply) that internally drives the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (10kΩ dc resistance and 2pF input capacitance). The buffer helps to isolate the external driving source from the switching currents of the sampling circuit. With a constant input impedance, the ADC is easier to drive and to reproduce data sheet measurements. For wideband applications (such as power amplifier linearization) the signal gain across frequency is more consistent. Spectral performance variation across the sampling frequency is also reduced. The input common-mode is set internally using a 5kΩ resistor from each input pin to 1.7V, so the input signal can be ac-coupled to the pins. For a full-scale differential input, each input pin (INP, INM) must swing symmetrically between VCM + 0.375V and VCM – 0.375V, resulting in a 1.5VPP differential input swing. The input sampling circuit has a high 3dB bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage). Figure 58 shows an equivalent circuit for the analog input. LPKG 1nH INP Buffer 5W CBOND 1pF CEQ Buffer 5kW RESR 100W REQ Buffer Sampling Circuit 1.7V REQ Buffer LPKG 1nH INM 5W CBOND 1pF 5kW CEQ Buffer Buffer RESR 100W Figure 58. Analog Input Equivalent Circuit 44 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Drive Circuit Requirements The primary advantage of the buffered analog inputs is the isolation of the external drive source from the switching currents of the sampling circuit. The filtering of the glitches with an external R-C-R filter, as suggested for the ADS4149 family, is not required. Using a simple drive circuit, it is possible to obtain uniform performance over a wide frequency range. For optimum performance, the analog inputs must be driven differentially. This configuration improves the common-mode noise immunity and even-order harmonic rejection. A small resistor (5Ω to 10Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics. Figure 59 and Figure 60 show the differential impedance (ZIN = RIN || CIN) seen by looking into the ADC input pins. The presence of the analog input buffer results in an almost constant input capacitance up to 1GHz. Differential Input Resistance (kW) 100 10 1 0.1 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Input Frequency (GHz) Figure 59. ADC Analog Input Resistance (RIN) Across Frequency 2.5 Differential Input Capacitance (pF) 2.25 2 1.75 1.5 1.25 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Input Frequency (GHz) Figure 60. ADC Analog Input Capacitance (CIN) Across Frequency Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 45 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Driving Circuit Two example driving circuit configurations are shown in Figure 61 and Figure 62—one optimized for low input frequencies and the other optimized for high input frequencies. Notice in both cases that the board circuitry is simplified compared to the non-buffered ADS4149. In Figure 61, a single transformer is used and is suited for low input frequencies. To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended (see Figure 62). Note that both drive circuits have been terminated by 50Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. 5W T1 INP 0.1mF 25W 0.1mF 25W INM 1:1 5W Figure 61. Drive Circuit for Low Input Frequencies 5W T2 T1 INP 0.1mF 50W 0.1mF 50W 50W 50W INM 1:1 1:1 5W Figure 62. Drive Circuit for High Input Frequencies The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 61 and Figure 62. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω (for a 50Ω source impedance). 46 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com CLOCK INPUT The ADS58B18/19 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources. Figure 63 shows a circuit for the internal clock buffer. Clock Buffer LPKG 1nH 20W CLKP CBOND 1pF RESR 100W LPKG 1nH 5kW 2pF 20W CEQ CEQ 0.95V 5kW CLKM CBOND 1pF RESR 100W NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer. Figure 63. Internal Clock Buffer A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1μF capacitor, as shown in Figure 64. For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input (see Figure 34). Figure 65 shows a differential circuit. CMOS Clock Input 0.1mF 0.1mF CLKP CLKP Differential Sine-Wave, PECL, or LVDS Clock Input VCM 0.1mF 0.1mF CLKM CLKM Figure 64. Single-Ended Clock Driving Circuit Figure 65. Differential Clock Driving Circuit Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 47 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com SNR ENHANCEMENT USING SNRBoost (ADS58B18 ONLY) SNRBoost technology makes it possible to overcome SNR limitations resulting from quantization noise. Using SNRBoost, enhanced SNR can be obtained for any bandwidth (less than Nyquist or fS/2; see Table 4). SNR improvement is achieved without affecting the default harmonic performance. SNRBoost can be enabled using the SNRBoost_EN pin or via register bits. When SNRBoost is enabled, the noise floor in the spectrum acquires a typical bathtub shape; see Figure 66. The bathtub is centered around a specific frequency (called center frequency). The center frequency is located midway between two corner frequencies that are specified by the SNRBoost coefficients (register bits SNRBoost Coeff1 and SNRBoost Coeff2). 0 AIN = −1dBFS SFDR = 88.5dBc SNR = 78.2dBFS SINAD = 77.6dBFS THD = 85.3dBc Coeff1 = 0x0 Coeff2 = 0x0 BW = 47.5MHz to 52.5MHz −10 −20 −30 Amplitude (dB) −40 −50 −60 −70 −80 −90 −100 −110 −120 0 20 40 60 80 100 Frequency (MHz) Figure 66. Spectrum with SNRBoost Enabled 48 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Table 9 shows the relation between each coefficient and its corner frequency. By choosing appropriate coefficients, the bathtub can be positioned over the frequency range of 0 to fS/2 (Table 10 shows some examples). By positioning the bathtub within the desired signal band, SNR improvement can be achieved (see Table 4). Note that as the bandwidth is increased, the amount of SNR improvement reduces. After a reset, the device is in low-latency disabled mode. To use the SNRBoost: • For the required bathtub position, write the appropriate coefficients in the SNRBoost Coeff1 and SNRBoost Coeff2 registers • SNRBoost can be enabled or disabled using the SNRBoost_EN digital input pin. This pin has higher priority over the SNRBoost Enable1 and SNRBoost Enable2 register bits • To use the enable register bits, set the override bit (OVER_RIDE SNRBoost pin). Table 9. Setting the Corner Frequency SNRBoost COEFFICIENT VALUE NORMALIZED CORNER FREQUENCY (f/fS) SNRBoost COEFFICIENT VALUE NORMALIZED CORNER FREQUENCY (f/fS) 7 0.42 F 0.23 6 0.385 E 0.21 5 0.357 D 0.189 4 0.333 C 0.167 3 0.311 B 0.143 2 0.29 A 0.115 1 0.27 9 0.08 0 0.25 8 0 Table 10. Positioning the Corner Frequency SNRBoost COEFFICIENT1 (SNRBoost Coeff1) NORMALIZED CORNER FREQUENCY1 (f/fS) SNRBoost COEFFICIENT1 (SNRBoost Coeff2) NORMALIZED CORNER FREQUENCY2 (f/fS) CENTER FREQUENCY 0 0.25 0 0.25 fS × 0.25 F 0.23 1 0.27 fS × 0.25 6 0.385 2 0.29 fS × 0.3375 D 0.189 B 0.143 fS × 0.166 9 0.08 7 0.42 fS × 0.25 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 49 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com GAIN FOR SFDR/SNR TRADE-OFF The ADS58B18/19 include gain settings that can be used to get improved SFDR performance. The gain is programmable from 0dB to 3.5dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 11. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR. After a reset, the device is in low-latency disabled mode and gain is enabled with 0dB gain. For other gain settings, program the GAIN bits. Table 11. Full-Scale Range Across Gains GAIN (dB) TYPE FULL-SCALE (VPP) 0 Default after reset 1.5 0.5 1.41 1 1.33 1.5 2 50 1.26 Programmable gain 1.19 2.5 1.12 3 1.06 3.5 1 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com OFFSET CORRECTION The ADS58B18/19 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 12. Table 12. Time Constant of Offset Correction Loop (1) OFFSET CORR TIME CONSTANT TIME CONSTANT, TCCLK (Number of Clock Cycles) TIME CONSTANT, TCCLK × 1/fS (sec) (1) 0000 1M 5ms 0001 2M 10.5ms 0010 4M 21ms 0011 8M 42ms 0100 16M 84ms 0101 32M 168ms 0110 64M 336ms 0111 128M 671ms 1000 256M 1.34s 1001 512M 2.68s 1010 1G 5.37s 1011 2G 10.7s 1100 Reserved — 1101 Reserved — 1110 Reserved — 1111 Reserved — Sampling frequency, fS = 250MSPS. After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by default after reset. After a reset, the device is in low-latency disabled mode. To use offset correction, set ENABLE OFFSET CORR to '1' and program the required time constant. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 51 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com POWER DOWN The ADS58B18/19 has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down, resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To enter the global power-down mode, set the PDN GLOBAL register bit. Standby In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5µs. The total power dissipation in standby mode is approximately 185mW. To enter the standby mode, set the STANDBY register bit. Output Buffer Disable The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast, approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin. Input Clock Stop In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The power dissipation is approximately 80mW. POWER-SUPPLY SEQUENCE During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. Externally, they can be driven from separate supplies or from a single supply. DIGITAL OUTPUT INFORMATION The ADS58B18/19 provide either 11-bit or 9-bit data and an output clock synchronized with the data. Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. The output can be selected using the LVDS CMOS serial interface register bit or using the DFS pin. The DFS pin has higher priority for deciding the type of interface, unless the LVDS CMOS override bit is set. 52 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DDR LVDS Outputs In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 67 and Figure 68. Two bit order options are available: bit-wise sequence (default) and byte-wise sequence. Byte-wise sequence can be programmed with the BYTE-WISE En Register bit. Figure 67. ADS58B18 LVDS Outputs Pins CLKOUTP Pins Output Clock CLKOUTM CLKOUTP Output Clock CLKOUTM D0_P Data Bits D0 D0_P Data Bits D0 D1_D2_P LVDS Buffers LVDS Buffers D0_M Data Bits D1, D2 D1_D2_M D3_D4_P 11-Bit ADC Data Data Bits D3, D4 D3_D4_M D0_M D1_D2_P Data Bits D1, D2 D1_D2_M D3_D4_P D5_D6_P Data Bits D5, D6 9-Bit ADC Data Data Bits D3, D4 D3_D4_M D5_D6_M D5_D6_P Data Bits D5, D6 D7_D8_P D5_D6_M Data Bits D7, D8 D7_D8_M D7_D8_P Data Bits D7, D8 D9_D10_P D7_D8_M Data Bits D9, D10 D9_D10_M ADS58B19 ADS58B18 Figure 68. ADS58B19 LVDS Outputs Bit-Wise Sequence Even data bits (D0, D2, D4, etc) are output at the rising edge of CLKOUTP and the odd data bits (D1, D3, D5, etc) are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all the data bits; see Figure 69. Byte-Wise Sequence In the ADS58B18, data bits D[0:4] are output at the falling edge of CLKOUTP and data bits D[5:10] are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all the data bits; see Figure 70. In the ADS58B19, data bits D[0:3] are output at the falling edge of CLKOUTP and data bits D[4:8] are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all the data bits; see Figure 71. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 53 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com CLKOUTP CLKOUTM D0_P, D0_M 0 D0 0 D0 D1_D2_P, D1_D2_M D1 D2 D1 D2 D3_D4_P, D3_D4_M D3 D4 D3 D4 D5_D6_P, D5_D6_M D5 D6 D5 D6 D7_D8_P, D7_D8_M D7 D8 D7 D8 D9_D10_P, D9_D10_M D9 D10 D9 D10 Sample N Sample N + 1 (1) Bits D9 and D10 are only available in the ADS58B18. Figure 69. Bit-Wise Sequence (Only with DDR LVDS Interface) CLKOUTP CLKOUTM D0_P, D0_M 0 D5 0 D5 D1_D2_P, D1_D2_M D0 D6 D0 D6 D3_D4_P, D3_D4_M D1 D7 D1 D7 D5_D6_P, D5_D6_M D2 D8 D2 D8 D7_D8_P, D7_D8_M D3 D9 D3 D9 D9_D10_P, D9_D10_M D4 D10 D4 D10 Sample N Sample N + 1 Figure 70. ADS58B18 Byte-Wise Sequence (Only with DDR LVDS Interface) 54 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com CLKOUTP CLKOUTM D0_P, D0_M 0 D4 0 D4 D1_D2_P, D1_D2_M D0 D5 D0 D5 D3_D4_P, D3_D4_M D1 D6 D1 D6 D5_D6_P, D5_D6_M D2 D7 D2 D7 D7_D8_P, D7_D8_M D3 D8 D3 D8 Sample N Sample N + 1 Figure 71. ADS58B19 Byte-Wise Sequence (Only with DDR LVDS Interface) LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 72. After reset, the buffer presents an output impedance of 100Ω to match with the external 100Ω termination. Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively. The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. VDIFF High Low OUTP External 100W Load OUTM 1.1V ROUT VDIFF Low High Figure 72. LVDS Buffer Equivalent Circuit Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 55 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Parallel CMOS Interface In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 73 depicts the CMOS output interface. Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window (even at 250MSPS) is provided so the data outputs have minimal load capacitance. It is recommended to use short traces (1 to 2 inches, or 2,54cm to 5,08cm) terminated with less than 5pF load capacitance, as shown in Figure 74. For sampling frequencies greater than 200MSPS, it is recommended to use an external clock to capture data. The delay from input clock to output data and the data valid times are specified for higher sampling frequencies. These timings can be used to delay the input clock appropriately and use it to capture data. Pins OVR_SDOUT CLKOUT CMOS Output Buffers D0 D1 D2 D3 ¼ ¼ 11-Bit ADC Data D8 D9 D10 ADS58B18 Figure 73. CMOS Output Interface 56 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Use External Clock Buffer (> 200MSPS) Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CMOS Output Buffers D0 D1 D2 CLKIN D0_In D1_In D2_In 9-/11-Bit ADC Data ADS58B1x Use short traces between ADC output and receiver pins (1 to 2 inches). Figure 74. CMOS Capture Example CMOS Interface Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG) where: CL = load capacitance, N × FAVG = average number of output bits switching. (1) Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 57 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Input Over-Voltage Indication (OVR_SDOUT Pin) The device has an OVR_SDOUT pin that provides information about analog input overload (as long as the READOUT register bit is '0'). When the READOUT bit is '1', it functions as a serial readout pin. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS). For a positive overload, the D[10:0] output data bits are 7FFh in offset binary output format and 3FFh in twos complement output format. For a negative input overload, the output code is 000h in offset binary output format and 400h in twos complement output format. Output Data Format Two output data formats are supported: twos complement and offset binary. They can be selected using the DATA FORMAT serial interface register bit or using the DFS pin. BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout and grounding. Supply Decoupling Because the ADS58B18/19 already include internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. Exposed Pad In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com). 58 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3dB with respect to the low-frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate – The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and EGCHAN. To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal. Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN. Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. SNR = 10Log10 PS PN (2) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. SINAD = 10Log10 PS PN + PD (3) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 59 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (4) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (5) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V. AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (6) Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted. Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is the resulting change of the ADC output code (referred to the input), then: DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (7) Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. 60 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2010) to Revision D Page • Changed documet status to production data ........................................................................................................................ 1 • Updated status of ADS58B19 to production data throughout document .............................................................................. 1 • Updated document format to current standards ................................................................................................................... 1 • Changed Clock Input, Input clock sample rate parameters for both ADS58B18 and ADS58B19 in Recommended Operating Conditions table ................................................................................................................................................... 3 • Added footnote 3 to Recommended Operating Conditions table ......................................................................................... 3 • Changed conditions of ADC latency parameter in Timing Requirements table ................................................................. 15 • Deleted footnote 7 from Timing Requirements table .......................................................................................................... 15 • Deleted footnote 10 in Timing Requirements tableα .......................................................................................................... 16 • Deleted table 2 (CMOS Timing Across Sampling Frequencies, withe respect to output clock) and table 4 (CMOS Timing Across Sampling Frequencies, withe respect to input clock) ................................................................................. 17 • Changed titles of Table 2 and Table 3 ............................................................................................................................... 17 • Updated Figure 8 ................................................................................................................................................................ 18 • Changed description of logic high in Table 6 ..................................................................................................................... 20 • Updated bit D3 of registers 25 and 42 and added register DF to Table 8 ......................................................................... 23 • Changed bit 3 and description of bits 2 to 0 in Register Address 25h ............................................................................... 25 • Changed description of bit 4 in Register Address 3Dh ....................................................................................................... 26 • Changed bit 3 of register address 42h ............................................................................................................................... 28 • Added Register Address DFh to Description of Serial Registers section ........................................................................... 31 • Updated conditions of Typical Characteristics: ADS58B18 ................................................................................................ 32 • Updated Figure 36 .............................................................................................................................................................. 37 • Updated conditions of Typical Characteristics: ADS58B19 ................................................................................................ 38 • Updated Figure 53 .............................................................................................................................................................. 42 • Updated conditions of Typical Characteristics: General ..................................................................................................... 43 • Deleted Digital Functions and Low-Latency Mode section ................................................................................................. 48 • Changed SNRBoost enable description in SNR Enhancement Using SNRBoost section ................................................. 49 • Changed reset description in Gain for SFDR/SNR Trade-Off section ................................................................................ 50 • Changed reset description in Offset Correction section ..................................................................................................... 51 Changes from Revision B (July 2010) to Revision C Page • Changed Analog Inputs, Input common-mode voltage typical specification in Recommended Operating Conditions table ...................................................................................................................................................................................... 3 • Added Clock Input, Input clock duty cycle minimum and maximum specifiations to Recommended Operating Conditions table .................................................................................................................................................................... 3 • Updated format of Typical Characteristics graphs .............................................................................................................. 32 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): ADS58B18 ADS58B19 61 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS58B18IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 AZ58B18 ADS58B18IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 AZ58B18 ADS58B19IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 AZ58B19 ADS58B19IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 AZ58B19 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of