ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Quad-Channel, 250-MSPS Receiver and Feedback ADC
Check for Samples: ADS58H43
FEATURES
DESCRIPTION
•
•
The ADS58H43 is a high-linearity, quad-channel, 14bit, 250-MSPS analog-to-digital converter (ADC). The
four ADC channels are separated into two blocks with
two ADCs each. Each block can be individually
configured into three different operating modes. One
operating mode includes the implementation of the
SNRBoost3G+ signal processing technology to provide
high signal-to-noise ratio (SNR) in a band up to
90 MHz wide with only 11-bit resolution. Designed for
low power consumption and high spurious-free
dynamic range (SFDR), the ADC has low-noise
performance and outstanding SFDR over a large
input frequency range.
1
2
•
•
•
•
•
•
Quad Channel
Three Different Operating Modes:
– 11-Bit: 250 MSPS
– 11-Bit SNRBoost3G+: 250 MSPS
– 14-Bit: 250 MSPS (Burst Mode)
Maximum Sampling Data Rate: 250 MSPS
Power Dissipation:
– 11-Bit Mode: 365 mW per Channel
SNRBoost3G+ Bandwidth: 2x 45 MHz or 90 MHz
Spectral Performance at 170 MHz IF (typ):
– SNR: 70.5 dBFS in 90-MHz Band with
SNRBoost3G+
– SFDR: 85 dBc
DDR LVDS Digital Output Interface
144-Pad BGA (10-mm × 10-mm)
APPLICATIONS
•
•
•
•
Multi-Carrier GSM Cellular Infrastructure Base
Stations
Multi-Carrier Multi-Mode Cellular Infrastructure
Base Stations
Active Antenna Arrays for Wireless
Infrastructures
Communications Test Equipment
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
ECO PLAN (2)
LEAD AND
BALL
FINISH
PACKAGE
MARKING
ADS58H43
BGA-144
ZCR
–40°C to +85°C
GREEN (RoHS,
no SB or BR)
CuNiPdAu
ADS58H43I
(1)
(2)
ORDERING
NUMBER
TRANSPORT
MEDIA
ADS58H43IZCR
Tray
ADS58H43IZCRR
Tape and Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content
can be accessed at www.ti.com/leadfree.
GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight.
N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree.
Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total
product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage range
Voltage between
Voltage applied to input pins
Temperature
VALUE
UNIT
AVDD33
–0.3 to +3.6
V
AVDD
–0.3 to +2.1
V
DRVDD
–0.3 to +2.1
V
AVSS and DRVSS
–0.3 to +0.3
V
AVDD and DRVDD
–2.4 to +2.4
V
AVDD33 and DRVDD
–2.4 to +3.9
V
AVDD33 and AVDD
–2.4 to +3.9
V
XINP, XINM
–0.3 to minimum (1.9, AVDD + 0.3)
V
CLKP, CLKM (2)
–0.3 to minimum (1.9, AVDD + 0.3)
V
RESET, SCLK, SDATA, SEN, SNRB, TRIG_EN, PDN
–0.3 to +3.9
V
Operating free-air, TA
–40 to +85
°C
Operating junction, TJ
Storage, Tstg
Electrostatic discharge (ESD)
ratings
(1)
(2)
2
Human body model (HBM)
+150
°C
–65 to +150
°C
2
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKM is less than
| 0.3 V |). This recommendation prevents the ESD protection diodes at the clock input pins from turning on.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
THERMAL INFORMATION
ADS58H43
THERMAL METRIC (1)
ZCR (BGA)
UNITS
144 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
5.1
θJB
Junction-to-board thermal resistance
12.6
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
12.4
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
35.9
°C/W
SPACER
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
1.8
1.9
2.0
V
1.7
1.8
2.0
V
SUPPLIES
AVDD33
AVDD
Supply voltage
DRVDD
ANALOG INPUTS
Differential input voltage range
2
Input common-mode voltage
VCM ± 0.025
Analog input common-mode current (per input pin of each channel)
V
1.5
VCM current capability
Maximum analog input frequency
VPP
µA/MSPS
5
mA
2-VPP input amplitude (1)
400
MHz
1.4-VPP input amplitude
500
MHz
CLOCK INPUTS
184 (2)
Input clock sample rate
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
0.2
250
MSPS
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
1.8
40%
50%
VPP
60%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRVSS
(default strength)
3.3
pF
RLOAD
Differential load resistance between the LVDS output pairs (LVDS mode)
100
Ω
TEMPERATURE RANGE
TA
TJ
(1)
(2)
(3)
Operating free-air temperature
Operating junction temperature
+85
°C
Recommended
–40
+105
°C
Maximum rated (3)
+125
°C
See the Theory of Operation section.
The minimum functional clock speed can be 10 MSPS after writing the following special modes: address 4Ah, value 01h; address 62h,
value 01h; address 92h, value 01h; and address 7Ah, value 01h. See the SPECIAL MODE[17:14] bits in Table 4 of the Serial Interface
Registers section.
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
3
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Table 1. High-Performance Modes Summary (1) (2)
fS = 245.76 MSPS
ADDRESS
(Hex)
DATA (Hex)
D4
80
D5
80
D6
80
√
√
√
√
√
√
(1)
(2)
D7
0C
DB
30
F0
38
F1
20
F5
42
RS = 50
ZONE = 2
RS = 100
ZONE = 2
RS = 50
ZONE = 3
fS = 184.32 MSPS
RS = 100
ZONE = 3
RS = 50
ZONE = 2
RS = 100
ZONE = 2
√
√
√
√
√
√
√
√
√
√
√
√
√
RS refers to the source impedance. Zone refers to the Nyquist zone in which the signal band lies. Zone = 2 corresponds to the signal
band that lies between fS / 2 and fS. Zone = 3 corresponds to the signal band that lies between fS and 3 × fS / 2.
Best performance can be achieved by writing these modes depending upon source impedance, band of operation, and sampling speed.
ELECTRICAL CHARACTERISTICS
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC clock frequency = 250 MHz,
50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
Default resolution
11
Bits
2
VPP
ANALOG INPUTS
Differential input full-scale
VCM
Common mode input voltage
1.15
RIN
Input resistance, differential
V
At 170-MHz input frequency
700
Ω
CIN
Input capacitance, differential
At 170-MHz input frequency
3.3
pF
Analog input bandwidth, 3 dB
With a 50-Ω source driving the ADC
analog inputs
500
MHz
DYNAMIC ACCURACY
EO
Offset error
Gain error (1)
EG
Specified across devices and channels
–15
15
mV
As a result of internal
reference inaccuracy
alone
Specified across devices and channels
–5
5
%FS
Of channel alone
Specified across channels within a device
Channel gain error temperature coefficient (1)
±0.2
%FS
0.001
Δ%/°C
POWER SUPPLY (2)
IAVDD33
3.3-V analog supply
51
mA
IAVDD
1.9-V analog supply
350
mA
340
mA
400
mA
11-bit operation
Supply current
IDRVDD
1.8-V digital supply
PTOTAL
Total
Power dissipation
PDISS(standby)
Standby
PDISS(global)
Global power-down
(1)
(2)
4
3G+
SNRBoost
enabled (90 MHz)
14-bit burst mode
355
11-bit operation
1.45
1.6
W
SNRBoost3G+ enabled
1.55
1.8
W
14-bit burst mode
1.47
W
400
mW
6
mA
52
mW
There are two sources of gain error: internal reference inaccuracy and channel gain error.
A 185-MHz, full-scale, sine-wave input signal is applied to all four channels.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC clock frequency = 250 MHz,
50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise
noted.
PARAMETER
DYNAMIC AC CHARACTERISTICS
TEST CONDITIONS
11-bit SNRBoost3G+,
90-MHz BW
SNR
Signal-to-noise ratio
11-bit SNRBoost3G+,
60-MHz BW
SINAD
MIN
TYP
Signal-to-noise and
distortion ratio
11-bit SNRBoost3G+,
90-MHz BW
3G+
11-bit SNRBoost
60-MHz BW
71
dBFS
67
70.5
dBFS
fIN = 220 MHz, AIN = –1 dBFS
70
dBFS
fIN = 307 MHz, AIN = –3 dBFS
71.7
dBFS
fIN = 350 MHz, AIN = –3 dBFS
71.5
dBFS
fIN = 140 MHz, AIN = –1 dBFS
70.6
dBFS
70.1
dBFS
fIN = 220 MHz, AIN = –1 dBFS
69.5
dBFS
fIN = 307 MHz, AIN = –3 dBFS
69.7
,
dBFS
fIN = 350 MHz, AIN = –3 dBFS
69.2
dBFS
fIN = 140 MHz, AIN = –1 dBFS
85
dBc
85
dBc
fIN = 220 MHz, AIN = –1 dBFS
82
dBc
fIN = 307 MHz, AIN = –3 dBFS
78
dBc
fIN = 350 MHz, AIN = –3 dBFS
77
dBc
fIN = 140 MHz, AIN = –1 dBFS
82
dBc
82
dBc
fIN = 220 MHz, AIN = –1 dBFS
80
dBc
fIN = 307 MHz, AIN = –3 dBFS
77
dBc
fIN = 350 MHz, AIN = –3 dBFS
76
dBc
fIN = 140 MHz, AIN = –1 dBFS
86
dBc
85
dBc
fIN = 220 MHz, AIN = –1 dBFS
82
dBc
fIN = 307 MHz, AIN = –3 dBFS
78
dBc
fIN = 350 MHz, AIN = –3 dBFS
77
dBc
fIN = 140 MHz, AIN = –1 dBFS
85
dBc
85
dBc
fIN = 220 MHz, AIN = –1 dBFS
85
dBc
fIN = 307 MHz, AIN = –3 dBFS
85
dBc
fIN = 350 MHz, AIN = –3 dBFS
83
dBc
fIN = 140 MHz, AIN = –1 dBFS
95
dBc
95
dBc
fIN = 220 MHz, AIN = –1 dBFS
95
dBc
fIN = 307 MHz, AIN = –3 dBFS
95
dBc
fIN = 350 MHz, AIN = –3 dBFS
95
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
66
fIN = 170 MHz, AIN = –1 dBFS
SFDR
Spurious-free dynamic range
76
fIN = 170 MHz, AIN = –1 dBFS
THD
Total harmonic distortion
73
fIN = 170 MHz, AIN = –1 dBFS
Second-order harmonic distortion (5)
HD2
76
fIN = 170 MHz, AIN = –1 dBFS
HD3
Third-order harmonic distortion
76
fIN = 170 MHz, AIN = –1 dBFS
Worst spur
(non HD2, HD3)
DNL
Differential nonlinearity
INL
Integral nonlinearity
PSRR
(3)
(4)
(5)
MAX
UNITS
(3) (4)
87
–0.95
dBc
±0.5
1.6
±1.5
±5.25
LSBs
LSBs
Input overload recovery
Recovery to within 1% (of final value) for
6-dB output overload with sine-wave input
1
Clock
cycle
Crosstalk
With a full-scale, 220-MHz signal on
aggressor channel and no signal on victim
channel
90
dB
AC power-supply rejection ratio
For 50-mVPP signal on AVDD supply
< 30
dB
Phase and amplitude imbalances onboard must be minimized to obtain good performance.
Dynamic ac characteristics are taken with respect to the 14-bit burst mode, unless otherwise noted.
The minimum value across temperature is ensured by bench characterization.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
5
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level '0' or '1'. AVDD33 = 3.3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (1) (RESET, SCLK, SDATA, SEN, PDN, SNRB, TRIG_EN)
VIH
High-level input voltage
All digital inputs support 1.8-V logic
levels. SPI supports 3.3-V logic levels.
VIL
Low-level input voltage
All digital inputs support 1.8-V logic
levels. SPI supports 3.3-V logic levels.
IIH
High-level input
current
Low-level input
current
IIL
RESET, SCLK, PDN,
SNRB, TRIG_EN pins
SEN
(2)
pin
1.25
V
0.45
V
VHIGH = 1.8 V
10
µA
VHIGH = 1.8 V
0
µA
RESET, SCLK, PDN,
SNRB, TRIG_EN pins
VLOW = 0 V
0
µA
SEN pin
VLOW = 0 V
10
µA
DRVDD
V
DIGITAL OUTPUTS (SDOUT, HIRES, TRIG_RDY)
VOH
High-level output voltage
VOL
Low-level output voltage
DRVDD –
0.1
0
0.1
V
DIGITAL OUTPUTS, LVDS INTERFACE
(DAB[13:0]P, DAB[13:0]M, DCD[13:0]P, DCD[13:0]M, CLKOUTABP, CLKOUTABM, CLKOUTCDP, CLKOUTCDM)
VODH
High (3)
Standard-swing LVDS
270
350
465
mV
Low
Standard-swing LVDS
–465
–350
–270
mV
VODL
Output differential
voltage
VOCM
Output common-mode voltage
(1)
(2)
(3)
6
1.05
V
RESET, SDATA, SCLK, TRIG_EN, and SNRB have an internal 150-kΩ pull-down resistor.
SEN has an internal 150-kΩ pull-up resistor to DRVDD.
With an external 100-Ω termination.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
TIMING REQUIREMENTS (1)
Typical values are at +25°C, AVDD33 = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, sine-wave input clock, CLOAD = 3.3 pF (2), and
RLOAD = 100 Ω (3), unless otherwise noted.
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C.
PARAMETER
tA
TEST CONDITIONS
MIN
Aperture delay
tJ
0.7
Aperture delay matching
Between any two channels of the same device
Variation of aperture delay
Between two devices at the same temperature and
DRVDD supply
1.2
1.6
UNIT
ns
ps
±150
ps
140
fs rms
100
µs
Time to valid data after coming out of channel power
down
10
µs
Default latency in 11-bit mode
10
Output clock
cycles
Digital gain enabled
13
Output clock
cycles
Digital gain and offset correction enabled
14
Output clock
cycles
SNRBoost3G+ (90-MHz BW) enabled alone
13
Output clock
cycles
SNRBoost3G+ (90-MHz BW), digital gain, and offset
correction enabled
17
Output clock
cycles
SNRBoost3G+ (45-MHz BW) enabled alone
15
Output clock
cycles
SNRBoost3G+ (45-MHz BW), digital gain, and offset
correction enabled
19
Output clock
cycles
Time to valid data after coming out of global power
down
ADC latency (4) (5)
MAX
±70
Aperture jitter
Wake up time
TYP
OUTPUT TIMING (6)
tSU
Data setup time (7) (8) (9)
Data valid to CLKOUTxxP zero-crossing
0.6
0.85
ns
tH
Data hold time (7) (8) (9)
CLKOUTxxP zero-crossing to data becoming invalid
0.6
0.84
ns
LVDS bit clock duty cycle
Differential clock duty cycle (CLKOUTxxP –
CLKOUTxxM)
tPDI
Clock propagation delay (5)
Input clock falling edge cross-over to output clock
falling edge cross-over, 184 MSPS ≤ sampling
frequency ≤ 250 MSPS
tdelay
Delay time
Input clock falling edge cross-over to output clock
falling edge cross-over, 184 MSPS ≤ sampling
frequency ≤ 250 MSPS
tRISE,
tFALL
Data rise and fall time
Rise time measured from –100 mV to +100 mV
0.1
ns
tCLKRISE,
tCLKFALL
Output clock rise and fall
time
Rise time measured from –100 mV to +100 mV
0.1
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
50%
0.25 × tS + tdelay
6.9
8.65
ns
10.5
ns
Timing parameters are ensured by design and characterization and are not tested in production.
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
RLOAD is the differential load resistance between the LVDS output pair.
ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles.
Overall latency = ADC latency + tPDI.
Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address
ACh, value 60h. Refer to the Serial Interface Registers section. By default after reset, minimum setup time and minimum hold times are
520 ps each.
The setup and hold times of a channel are measured with respect to the same channel output clock.
Table 2. LVDS Timings Across Lower Sampling Frequencies
SETUP TIME (ns)
HOLD TIME (ns)
SAMPLING FREQUENCY
(MSPS)
MIN
TYP
MIN
TYP
210
0.89
1.03
0.82
1.01
185
1.06
1.21
0.95
1.15
MAX
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
MAX
7
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
PARAMETRIC MEASUREMENT INFORMATION
LVDS OUTPUT TIMING
Figure 1 shows a timing diagram of the LVDS output voltage levels. Figure 2 shows the latency described in the
Timing Requirements table.
DxnP
Logic 0
VODL
Logic 1
VODH
DxnM
VOCM
GND
Figure 1. LVDS Output Voltage Levels
N+1
Sample
N
Input
Signal
N+2
N+3
N+4
N+11
N+12
N+10
tA
CLKINM
Input
Clock
CLKINP
CLKOUTABM
(CLKOUTCDM)
CLKOUTABP
(CLKOUTCDP)
DDR
LVDS
tPDI
Output Data
DABP, DABM
(DCDP, DCDM)
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
(Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
(Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)
Figure 2. Latency Timing
8
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
PARAMETRIC MEASUREMENT INFORMATION (continued)
All 14 data bits of one channel (11 data bits in default SNRBoost3G+ mode) are included in the digital output
interface at the same time, as shown in Figure 3. Channel A and C data are output on the rising edge of the
output clock while channels B and D are output on the falling edge of the output clock.
CLKOUTABM
CLKOUTABP
DAB[13:0]P,
DAB[13:0]M
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
Sample N
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
DA[13:0]P,
DA[13:0]M
Sample N + 1
DB[13:0]P,
DB[13:0]M
Sample N + 2
CLKOUTCDM
CLKOUTCDP
DCD[13:0]P,
DCD[13:0]M
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
Sample N
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
DC[13:0]P,
DC[13:0]M
Sample N + 1
DD[13:0]P,
DD[13:0]M
Sample N + 2
Figure 3. LVDS Output Interface Timing
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
9
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
PIN CONFIGURATION
ZCR PACKAGE
BGA-144
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
A
AVDD
AVDD
CINM
CINP
AVDD
VCM
VCM
AVDD
BINM
BINP
AVDD
AVDD
B
DINP
AVSS
AVDD
AVDD
AVSS
AVDD33
AVDD33
AVSS
AVDD
AVDD
AVSS
AINM
C
DINM
AVSS
AVSS
AVSS
AVSS
CLKINM
CLKINP
AVSS
AVSS
AVSS
AVSS
AINP
D
AVDD
AVDD
VCM
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
VCM
AVDD
AVDD
E
AVDD33
AVDD33
SNRB
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
PDN
AVDD33
AVDD33
F
DCD13M
DCD13P
DRVDD
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
DRVDD
DAB13P
DAB13M
G
DCD12M
DCD12P
HIRES
RESET
SCLK
SDATA
SEN
SDOUT
DAB12P
DAB12M
H
DCD11M
DCD11P
DCD6P
DCD6M
DRVDD
DRVDD
DRVDD
DRVDD
DAB6M
DAB6P
DAB11P
DAB11M
J
DCD10M
DCD10P
DCD5P
DCD5M
DCD2P
DRVDD
DRVDD
DAB2M
DAB5M
DAB5P
DAB10P
DAB10M
K
DCD9M
DCD9P
DCD4P
DCD4M
DCD2M
DRVDD
DRVDD
DAB2P
DAB4M
DAB4P
DAB9P
DAB9M
L
DCD8M
DCD8P
DCD3P
DCD3M
DCD1P
DCD1M
DAB1M
DAB1P
DAB3M
DAB3P
DAB8P
DAB8M
M
DCD7M
DCD7P
CLKOUT
CDP
CLKOUT
CDM
DCD0P/
OVRCDP
DCD0M/
OVRCDM
DAB0M/
OVRABM
DAB0P/
OVRABP
CLKOUT
ABM
CLKOUT
ABP
DAB7P
DAB7M
10
TRIG_EN TRIG_RDY
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
PIN FUNCTIONS
PIN
NAME
NUMBER
I/O
DESCRIPTION
AINM
B12
I
Negative differential analog input for channel A
AINP
C12
I
Positive differential analog input for channel A
AVDD33
B6, B7, E1, E2, E11, E12
I
Analog 3.3-V power supply
AVDD
A1, A2, A5, A8, A11, A12,
B3, B4, B9, B10, D1, D2,
D11, D12
I
Analog 1.9-V power supply
AVSS
B2, B5, B8, B11, C2-C5,
C8-C11, D4-D9
I
Analog ground
BINM
A9
I
Negative differential analog input for channel B
BINP
A10
I
Positive differential analog input for channel B
CINM
A3
I
Negative differential analog input for channel C
CINP
A4
I
Positive differential analog input for channel C
CLKINM
C6
I
Negative differential clock input
CLKINP
C7
I
Positive differential clock input
CLKOUTABM
M9
O
Negative differential LVDS clock output for channel A and B
CLKOUTABP
M10
O
Positive differential LVDS clock output for channel A and B
CLKOUTCDM
M4
O
Negative differential LVDS clock output for channels C and D
CLKOUTCDP
M3
O
Positive differential LVDS clock output for channels C and D
DAB[13:1]P,
DAB0P/OVRABP,
DAB[13:1]M,
DAB0M/OVRABM
F11, F12, G11, G12,
H9-H12, J8-J12, K8-K12,
L7-L12, M7, M8, M11, M12
O
DDR LVDS outputs for channels A and B.
In 11-bit mode, DAB13 is the MSB, DAB3 is the LSB, and DAB0 is the over-range (OVR) bit.
In 14-bit burst mode, DAB13 is the MSB and DAB0 is the LSB. LSB can be programmed as
OVR bit in this mode.
DCD[13:1]P,
DCD0P/OVRCDP,
DCD[13:1]M,
DCD0M/OVRCDM
F1, F2, G1, G2, H1-H4,
J1-J5, K1-K5, L1-L6, M1,
M2, M5, M6
O
DDR LVDS outputs for channels C and D.
In 11-bit mode, DCD13 is the MSB, DCD3 is the LSB, and DCD0 is the OVR bit.
In 14-bit burst mode, DCD13 is the MSB and DCD0 is the LSB. LSB can be programmed as
OVR bit in this mode.
DINM
C1
I
Negative differential analog input for channel D
DINP
B1
I
Positive differential analog input for channel D
DRVDD
F3, F10, H5-H8, J6, J7, K6,
K7
I
Digital 1.8-V power supply
DRVSS
E4-E9, F4-F9
I
Digital ground
HIRES
G5
O
Indication in burst mode if output data is high or low resolution
PDN
E10
I
Power-down control; active high. Logic high is power down.
RESET
G6
I
Hardware reset; active high
SCLK
G7
I
Serial interface clock input
SDATA
G8
I
Serial interface data input
SDOUT
G10
O
Serial interface data output
SEN
G9
I
Serial interface enable
SNRB
E3
I
SNRB enable; active high
TRIG_EN
G3
I
Trigger burst mode; active high
TRIG_RDY
G4
O
Indication if ADC is ready for another high-resolution burst mode
VCM
A6, A7, D3, D10
O
Common-mode voltage for analog inputs. All VCM pins are internally connected together.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
11
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
Digital Processing Block
AINP,
AINM
14-Bit
ADC
Digital
Block
BINP,
BINM
DAB0P, DAB0M or
OVRABP, OVRABM
11-Bit
SNR Boost
13
Burst Mode
14-Bit
ADC
11-Bit
14-Bit
DAB[13:1]P,
DAB[13:1]M
CLKOUTABP,
CLKOUTABM
TRIG_RDY
Output
Formatter
CLKINP,
CLKINM
Digital Processing Block
CINP,
CINM
TRIG_EN
11-Bit
14-Bit
ADC
Digital
Block
DINP,
DINM
HRES
DDR
LVDS
SNR Boost
Burst Mode
14-Bit
ADC
11-Bit
DCD0P, DCD0M or
OVRCDP, OVRCDM
14-Bit
13
VCM
DCD[13:1]P,
DCD[13:1]M
CLKOUTCDP,
CLKOUTCDM
Common
Mode
12
SNRB
PDN
SDATA
SDOUT
SEN
SCLK
RESET
Configuration Registers
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
TYPICAL CHARACTERISTICS
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
0
0
SFDR = 88.1 dBc
SNR = 70.1 dBFS
SINAD = 70 dBFS
THD = 85 dBc
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
SFDR = 90.1 dBc
SNR = 69.6 dBFS
SINAD = 69.6 dBFS
THD = 86.3 dBc
0
25
50
75
Frequency (MHz)
100
−120
125
0
25
50
75
Frequency (MHz)
100
125
G001
G002
Figure 4. FFT IN 14-BIT MODE INPUT FREQUENCY
(140 MHz)
Figure 5. FFT IN 14-BIT MODE INPUT FREQUENCY
(170 MHz)
0
0
SFDR = 87.6 dBc
SNR = 69.5 dBFS
SINAD = 69.4 dBFS
THD = 85.5 dBc
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
SFDR = 85.8 dBc
SNR = 69.1 dBFS
SINAD = 69 dBFS
THD = 83.9 dBc
0
25
50
75
Frequency (MHz)
100
125
−120
0
25
50
75
Frequency (MHz)
100
125
G003
Figure 6. FFT IN 14-BIT MODE INPUT FREQUENCY
(185 MHz)
G005
Figure 7. FFT IN 14-BIT MODE INPUT FREQUENCY
(190 MHz)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
13
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
0
0
SFDR = 81.9 dBc
SNR = 68.9 dBFS
SINAD = 68.6 dBFS
THD = 79.4 dBc
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
BW = 90 MHz
(17.5 MHz to 107.5 MHz)
AIN = −1 dBFS
SFDR = 86.7 dBc
SNR = 70.4 dBFS
SINAD = 70.3 dBFS
0
25
50
75
Frequency (MHz)
100
−120
125
0
25
50
75
Frequency (MHz)
100
125
G005
G006
Figure 8. FFT IN 14-BIT MODE INPUT FREQUENCY
(230 MHz)
Figure 9. FFT IN 11-BIT MODE WITH SNRBoost
INPUT FREQUENCY (150 MHz, 90-MHz Bandwidth)
0
0
3G+
BW = 90 MHz
(17.5 MHz to 107.5 MHz)
AIN = −1 dBFS
SFDR = 86.5 dBc
SNR = 70.3 dBFS
SINAD = 70.2 dBFS
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
BW = 90 MHz
(17.5 MHz to 107.5 MHz)
AIN = −1 dBFS
SFDR = 84.7 dBc
SNR = 70.1 dBFS
SINAD = 70 dBFS
0
25
50
75
Frequency (MHz)
100
125
−120
0
25
50
75
Frequency (MHz)
100
125
G007
3G+
Figure 10. FFT IN 11-BIT MODE WITH SNRBoost
INPUT FREQUENCY (185 MHz, 90-MHz Bandwidth)
14
G008
3G+
Figure 11. FFT IN 11-BIT MODE WITH SNRBoost
INPUT FREQUENCY (230 MHz, 90-MHz Bandwidth)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
2−Tone IMD = 97 dBFS
SFDR = 102.2 dBFS
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
2−Tone IMD = 101 dBFS
SFDR = 100.9 dBFS
0
25
50
75
Frequency (MHz)
100
−120
125
0
25
50
75
Frequency (MHz)
100
G009
125
G010
Figure 12. FFT FOR –7-dBFS, TWO-TONE INPUT SIGNAL
IN 14-BIT MODE
Figure 13. FFT FOR –36-dBFS, TWO-TONE INPUT SIGNAL
IN 14-BIT MODE
71
100
70.5
95
90
SNR (dBFS)
SFDR (dBc)
70
85
69.5
69
80
75
140
68.5
155
170
185
200
215
230
Input Frequency (MHz)
68
140
G011
Figure 14. SPURIOUS-FREE DYNAMIC RANGE vs
INPUT FREQUENCY
155
170
185
200
215
Input Frequency (MHz)
Product Folder Links: ADS58H43
G012
Figure 15. SIGNAL-TO-NOISE RATIO vs
INPUT FREQUENCY
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
230
15
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
71
86
84
70.5
82
70
SNR (dBFS)
SFDR (dBc)
80
78
69.5
76
69
74
68.5
72
70
270
290
310
330
68
270
350
Input Frequency (MHz)
290
310
330
350
Input Frequency (MHz)
G013
Figure 16. SPURIOUS-FREE DYNAMIC RANGE vs
HIGH INPUT FREQUENCY (–3 dBFS)
G014
Figure 17. SIGNAL-TO-NOISE RATIO vs
HIGH INPUT FREQUENCY (–3 dBFS)
72
96
71
94
70
92
SINAD (dBFS)
SFDR (dBc)
69
90
88
68
67
66
86
84
82
65
140 MHz
170 MHz
185 MHz
190 MHz
230 MHz
0
0.5
1
1.5
2
2.5 3 3.5 4
Digital Gain (dB)
4.5
5
5.5
140 MHz
170 MHz
185 MHz
190 MHz
230 MHz
64
6
63
0
G015
Figure 18. SPURIOUS-FREE DYNAMIC RANGE vs
GAIN ACROSS INPUT FREQUENCY
16
0.5
1
1.5
2
2.5 3 3.5 4
Digital Gain (dB)
4.5
5
5.5
6
G016
Figure 19. SIGNAL-TO-NOISE RATIO AND DISTORTION vs
GAIN ACROSS INPUT FREQUENCY
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
70
110
73.5
100
73
SFDR (dBc,dBFS)
69
68
67
66
90
72.5
80
72
70
71.5
60
71
50
70.5
SNR (dBFS)
Input Frequency = 185 MHz
140 MHz
170 MHz
185 MHz
190 MHz
230 MHz
71
SNR (dBFS)
74
120
72
65
70
40
64
SFDR (dBc)
SFDR (dBFS)
SNR
30
63
62
20
−50
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
−40
−30
−20
Amplitude (dBFS)
6
−10
69.5
0
69
G018
Digital Gain (dB)
G017
Figure 20. SIGNAL-TO-NOISE RATIO vs
GAIN ACROSS INPUT FREQUENCY
Figure 21. PERFORMANCE vs INPUT AMPLITUDE
72
94
90
Input Frequency = 185 MHz
92
71.5
89
90
71
88
88
70.5
86
70
84
69.5
82
69
87
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
Input Frequency = 185 MHz
86
85
84
68.5
80
SFDR
SNR
78
0.7
0.8
83
68
1.3
0.9
1
1.1
1.2
Input Common−Mode Voltage (V)
82
−40
G019
AVDD = 1.8 V
AVDD = 1.9 V
AVDD = 2 V
−15
10
35
Temperature (°C)
60
85
G020
Figure 22. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE
Figure 23. SPURIOUS-FREE DYNAMIC RANGE vs
TEMPERATURE (AVDD Supply)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
17
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
71
90
Input Frequency = 185 MHz
Input Frequency = 185 MHz
89
70.5
88
SFDR (dBc)
SNR (dBFS)
70
69.5
87
86
69
85
68.5
68
−40
84
AVDD = 1.8 V
AVDD = 1.9 V
AVDD = 2 V
−15
10
35
Temperature (°C)
60
83
−40
85
DRVDD = 1.7 V
DRVDD = 1.8 V
DRVDD = 1.9 V
DRVDD = 2 V
−15
10
35
Temperature (°C)
60
85
G021
G022
Figure 24. SIGNAL-TO-NOISE RATIO vs
TEMPERATURE (AVDD Supply)
Figure 25. SPURIOUS-FREE DYNAMIC RANGE vs
TEMPERATURE (DRVDD Supply)
71
90
Input Frequency = 185 MHz
Input Frequency = 185 MHz
89
70.5
88
70
SFDR (dBc)
SNR (dBFS)
87
69.5
86
85
69
84
68.5
68
−40
DRVDD = 1.7 V
DRVDD = 1.8 V
DRVDD = 1.9 V
DRVDD = 2 V
−15
10
35
Temperature (°C)
83
60
85
82
−40
AVDD3V = 3.15 V
AVDD3V = 3.3 V
AVDD3V = 3.45 V
−15
10
35
Temperature (°C)
60
85
G023
Figure 26. SIGNAL-TO-NOISE RATIO vs
TEMPERATURE (DRVDD Supply)
18
G024
Figure 27. SPURIOUS-FREE DYNAMIC RANGE vs
TEMPERATURE (AVDD3V Supply)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
71
100
71
70.5
SFDR (dBc)
SNR (dBFS)
70
69.5
98
70.5
96
70
94
69.5
92
69
90
68.5
88
68
86
67.5
84
67
82
66.5
80
66
SNR (dBFS)
Input Frequency = 185 MHz
Input Frequency = 185 MHz
69
68.5
AVDD3V = 3.15 V
AVDD3V = 3.3 V
AVDD3V = 3.45 V
68
−40
−15
SFDR
SNR
78
76
0.2
10
35
Temperature (°C)
60
0.5
85
0.8
1.1
1.4
1.7
2
2.3
Differential Clock Amplitudes (Vpp)
2.6
65.5
65
2.9
G026
G025
Figure 28. SIGNAL-TO-NOISE RATIO vs
TEMPERATURE (AVDD3V Supply)
Figure 29. PERFORMANCE vs
DIFFERENTIAL CLOCK AMPLITUDE
72
92
2048
FS = 250 MSPS
FIN = 185 MHz
Input Frequency = 185 MHz
91
71.5
90
71
89
70.5
88
70
87
69.5
86
69
85
68.5
84
68
1792
83
82
SNR
THD
25
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
70
75
Output Code (LSB)
SNR (dBFS)
THD (dBc)
1536
1280
1024
768
512
67.5
256
67
0
0
G027
4096
8192 12288 16384 20480 24576 28672 32768
Sample Number
G028
Figure 30. PERFORMANCE vs
INPUT CLOCK DUTY CYCLE
Figure 31. TIME DOMAIN DATA WITH
SNRBoost3G+ ENABLED
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
19
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
0
2048
FS = 250 MSPS
FIN = 185 MHz
Input Frequency = 185 MHz
50−mVPP Signal Superimposed on VCM
−5
1792
−10
−15
−20
1280
CMRR (dB)
Output Code (LSB)
1536
1024
−25
−30
−35
768
−40
−45
512
−50
256
−55
0
0
4096
−60
8192 12288 16384 20480 24576 28672 32768
Sample Number
0
50
100
150
200
250
Frequency of Input Common−Mode Signal (MHz)
300
G029
G030
Figure 32. TIME DOMAIN DATA WITH
SNRBoost3G+ DISABLED (Default is 11-Bit Mode)
fIN = 185 MHz
fCM = 10 MHz, 50 mVPP
SFDR = 76.2 dBc
Amplitude:
fIN = -1 dBFS
fCM = -95.1 dBFS
fIN + fCM = -77.2 dBFS
fIN - fCM = 80.9 dBFS
−20
Amplitude (dB)
−40
−20
−25
−30
−35
−60
fIN + fCM = 195 MHz
PSRR on AVDD Supply
PSRR on AVDD3V Supply
fIN = 185 MHz
PSRR (dB)
0
Figure 33. COMMON-MODE REJECTION RATIO vs
FREQUENCY
fIN - fCM = 175 MHz
−40
−45
−50
−80
−55
fCM = 10 MHz
−60
−100
−65
−120
0
25
50
75
Frequency (MHz)
100
125
−70
Input Frequency = 10 MHz
50−mVPP Signal Superimposed on Supply
0
50
100
150
200
250
Frequency of Signal on Supply (MHz)
300
G031
Figure 34. COMMON-MODE REJECTION RATIO SPECTRUM
20
G032
Figure 35. POWER-SUPPLY REJECTION RATIO vs
FREQUENCY
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, 14-bit burst mode, sine
wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted.
0
−40
Default 11−bit
14−bit Burst Mode
11−bit with SNRBoost
1.4
1.2
Total Power (W)
−20
Amplitude (dB)
1.6
fIN = 10 MHz
fPSRR = 2 MHz, 50 mVPP
Amplitude (fIN) = -1 dBFS
Amplitude (fPSRR) = -87.4 dBFS
Amplitude (fIN + fPSRR) = -60.6 dBFS
Amplitude (fIN - fPSRR) = -60 dBFS
fIN
fIN - fPSRR
−60
fIN + fPSRR
fPSRR
1.0
0.8
−80
0.6
−100
0.4
Input Frequency = 185 MHz
−120
0
5
10
15
20
25
30
Frequency (MHz)
35
40
45
0.2
50
0
25
50
75 100 125 150 175
Sampling Speed (MSPS)
200
225
250
G033
G034
Figure 36. ZOOMED VIEW OF POWER-SUPPLY REJECTION
RATIO SPECTRUM
Figure 37. TOTAL POWER vs SAMPLING RATE
700
800
600
700
500
600
DRVDD Power (mW)
Analog Power (mW)
AVDD Power
AVDD3V Power
400
300
Default 11−bit
14−bit Burst Mode
11−bit with SNRBoost
500
400
200
300
100
200
Input Frequency = 185 MHz
0
0
25
50
75 100 125 150 175
Sampling Speed (MSPS)
200
225
Input Frequency = 185 MHz
250
100
0
25
50
75 100 125 150 175
Sampling Speed (MSPS)
200
225
250
G035
Figure 38. ANALOG POWER vs SAMPLING RATE
G036
Figure 39. DRVDD POWER vs SAMPLING RATE IN
VARIOUS DIGITAL MODES
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
21
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
DEVICE CONFIGURATION
The ADS58H43 can be configured with a serial programming interface (SPI), as described in the Serial Interface
section. In addition, the device has control pins that control power-down and SNRBoost3G+ operation.
SERIAL INTERFACE
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface input data), and SDOUT (serial interface
read back data) pins. The serial shift of bits into the device is enabled when SEN is low. Serial data (SDATA) are
latched at every SCLK falling edge when SEN is active (low). The serial data are loaded into the register at every
16th SCLK falling edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits
are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits
form the register address and the remaining eight bits are the register data. The interface can function with SCLK
frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through a hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns),
as shown in Figure 40; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D1 in register 00h) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin is kept low.
Register Address
SDATA
A6
A7
A5
A4
A3
Register Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 40. Serial Interface Timing
Table 3. Timing Characteristics for Figure 40
PARAMETER
MIN
MAX
UNIT
20
MHz
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDI setup time
25
ns
tDH
SDI hold time
25
ns
22
> dc
TYP
fSCLK
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back, as shown in
Figure 41. This read-back mode can be useful as a diagnostic check to verify the serial interface communication
between the external controller and ADC.
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers except register
address 00h.
2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.
3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin G10).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
Note that the contents of register 00h cannot be read back because the register contains RESET and READOUT
bits. When the READOUT bit is disabled, the SDOUT pin is in a high-impedance state. If serial readout is not
used, the SDOUT pin must not be connected (must float).
Register Address A[7:0] = 00h
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = 01h
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
The SDOUT pin is in a high-impedance state (READOUT = 0).
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
SCLK
SEN
SDOUT
The SDOUT pin functions as a serial readout (READOUT = 1).
b) Read contents of Register 45h. This register is initialized with 04h.
Figure 41. Serial Readout Timing Diagram
SDOUT comes out at the SCLK rising edge with an approximate delay (tSD_DELAY) of 8 ns, as shown in Figure 42.
SCLK
tSD_DELAY
SDOUT
Figure 42. SDOUT Delay Timing
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
23
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
SERIAL INTERFACE REGISTERS
Table 4 summarizes the ADS58H43 registers.
Table 4. Register Map
REGISTER
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
REGISTER DATA
D3
D2
D1
D0
00
0
0
0
0
0
0
RESET
READOUT
0
0
01
LVDS SWING
25
DIGITAL GAIN CH B
DIGITAL GAIN
BYPASS CH B
TEST PATTERN CH B
2B
DIGITAL GAIN CH A
DIGITAL GAIN
BYPASS CH A
TEST PATTERN CH A
31
DIGITAL GAIN CH D
DIGITAL GAIN
BYPASS CH D
TEST PATTERN CH D
DIGITAL GAIN CH C
DIGITAL GAIN
BYPASS CH C
TEST PATTERN CH C
37
3D
0
0
3F
0
0
SEL OFFSET
CORR
0
0
0
CUSTOM PATTERN[7:0]
0
0
0
AUTO BURST
ENABLE
HIGH RESOLUTION SAMPLES, NH
42
0
0
0
0
DIGITAL ENABLE
SNRB 45/95MHz
44
BMODE EN
CH CD
BMODE EN CH
AB
0
0
0
BMODE OVR
ENABLE
0
DIS SNRB
45
0
0
0
0
SEL OVR
GLOBAL POWER
DOWN
0
CONFIG PDN PIN
4A
0
0
0
0
0
0
0
SPECIAL
MODE 14
62
0
0
0
0
0
0
0
SPECIAL
MODE 15
7A
0
0
0
0
0
0
0
SPECIAL
MODE 17
92
0
0
0
0
0
0
0
SPECIAL
MODE 16
A9
0
0
0
0
AC
0
LOW RESOLUTION SAMPLES, NL
CLOCKOUT DELAY PROG CH AB
CLOCKOUT DELAY PROG CH CD
C3
0
0
0
FAST OVR THRESH PROG
C4
EN FAST OVR
THRESH
0
0
0
0
0
0
0
CF
0
0
0
0
SPECIAL
MODE 0
0
0
0
D4
SPECIAL
MODE 1
0
0
0
0
0
0
0
D5
SPECIAL
MODE 2
0
0
0
0
0
0
0
D6
SPECIAL
MODE 3
0
0
0
0
0
0
0
D7
0
0
0
0
SPECIAL
MODE 5
SPECIAL
MODE 4
0
0
SPECIAL
MODE 7
SPECIAL
MODE 6
0
0
0
0
DB
0
0
EA
SNRB PIN OVRD
0
0
0
0
0
0
0
0
SPECIAL
MODE 10
SPECIAL
MODE 9
SPECIAL
MODE 8
0
0
0
0
0
F0
24
0
CUSTOM PATTERN[13:8]
40
41
0
0
F1
0
0
SPECIAL
MODE 11
F5
0
SPECIAL
MODE 13
0
0
0
0
SPECIAL
MODE 12
0
FE
0
0
0
0
PDN CH D
PDN CH C
PDN CH A
PDN CH B
Submit Documentation Feedback
ENABLE LVDS SWING PROG
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
DESCRIPTION OF SERIAL REGISTERS
Register Address 00h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
RESET
READOUT
Bits D[7:2]
Always write '0'
Bit D1
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to '0'.
Bit D0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance
state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with
CMOS logic levels running from the DRVDD supply.
Register Address 01h (Default = 00h)
D7
D6
D5
D4
D3
LVDS SWING
Bits D[7:2]
D2
D1
D0
0
0
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing only after the ENABLE LVDS SWING PROG bits
are set to '11'.
000000 = Default LVDS swing; ±350 mV with an external 100-Ω termination
011011 = ±420-mV LVDS swing with an external 100-Ω termination
110010 = ±470-mV LVDS swing with an external 100-Ω termination
010100 = ±560-mV LVDS swing with an external 100-Ω termination
001111 = ±160-mV LVDS swing with an external 100-Ω termination
Bits D[1:0]
Always write '0'
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
25
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Register Address 25h (Default = 00h)
D7
D6
D5
D4
DIGITAL GAIN CH B
Bits D[7:4]
D3
DIGITAL GAIN BYPASS CH B
D2
D1
D0
TEST PATTERN CH B
DIGITAL GAIN CH B: Channel B digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel B. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH B: Channel B digital gain bypass
0 = Normal operation
1 = Digital gain feature for channel B is bypassed
Bits D[2:0]
TEST PATTERN CH B: Channel B test pattern programmability
These bits program the test pattern for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In 11-bit mode, output data (D[10:0]) are an alternating sequence of 10101010101 and
01010101010.
In 14-bit burst mode, output data ([D:0]) are an alternating sequence of
01010101010101 and 10101010101010.
100 = Outputs digital ramp
In 11-bit mode, output data increments by one 11-bit LSB every 8th clock cycle from
code 0 to code 2047.
In 14-bit burst mode, output data increments by one 14-bit LSB every clock cycle from
code 0 to code 16383
101 = Outputs custom pattern
To program a pattern in 11-bit mode, use the CUSTOM PATTERN D[13:3] bits of
registers 3Fh and 40h.
To program a pattern in 14-bit mode, use the CUSTOM PATTERN D[13:0] bits of
registers 3Fh and 40h.
110 = Unused
111 = Unused
26
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Register Address 2Bh (Default = 00h)
D7
D6
D5
D4
DIGITAL GAIN CH A
Bits D[7:4]
D3
DIGITAL GAIN BYPASS CH A
D2
D1
D0
TEST PATTERN CH A
DIGITAL GAIN CH A: Channel A digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel A. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH A: Channel A digital gain bypass
0 = Normal operation
1 = Digital gain feature for channel A is bypassed
Bits D[2:0]
TEST PATTERN CH A: Channel A test pattern programmability
These bits program the test pattern for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In 11-bit mode, output data (D[10:0]) are an alternating sequence of 10101010101 and
01010101010.
In 14-bit burst mode, output data ([D:0]) are an alternating sequence of
01010101010101 and 10101010101010.
100 = Outputs digital ramp
In 11-bit mode, output data increments by one 11-bit LSB every 8th clock cycle from
code 0 to code 2047.
In 14-bit burst mode, output data increments by one 14-bit LSB every clock cycle from
code 0 to code 16383
101 = Outputs custom pattern
To program a pattern in 11-bit mode, use the CUSTOM PATTERN D[13:3] bits of
registers 3Fh and 40h.
To program a pattern in 14-bit mode, use the CUSTOM PATTERN D[13:0] bits of
registers 3Fh and 40h.
110 = Unused
111 = Unused
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
27
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Register Address 31h (Default = 00h)
D7
D6
D5
D4
DIGITAL GAIN CH D
Bits D[7:4]
D3
DIGITAL GAIN BYPASS CH D
D2
D1
D0
TEST PATTERN CH D
DIGITAL GAIN CH D: Channel D digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel D. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH D: Channel D digital gain bypass
0 = Normal operation
1 = Digital gain feature for channel A is bypassed
Bits D[2:0]
TEST PATTERN CH D: Channel D test pattern programmability
These bits program the test pattern for channel D.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In 11-bit mode, output data (D[10:0]) are an alternating sequence of 10101010101 and
01010101010.
In 14-bit burst mode, output data ([D:0]) are an alternating sequence of
01010101010101 and 10101010101010.
100 = Outputs digital ramp
In 11-bit mode, output data increments by one 11-bit LSB every 8th clock cycle from
code 0 to code 2047.
In 14-bit burst mode, output data increments by one 14-bit LSB every clock cycle from
code 0 to code 16383
101 = Outputs custom pattern
To program a pattern in 11-bit mode, use the CUSTOM PATTERN D[13:3] bits of
registers 3Fh and 40h.
To program a pattern in 14-bit mode, use the CUSTOM PATTERN D[13:0] bits of
registers 3Fh and 40h.
110 = Unused
111 = Unused
28
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Register Address 37h (Default = 00h)
D7
D6
D5
D4
DIGITAL GAIN CH C
Bits D[7:4]
D3
DIGITAL GAIN BYPASS CH C
D2
D1
D0
TEST PATTERN CH C
DIGITAL GAIN CH C: Channel C digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel C. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH C: Channel C digital gain bypass
0 = Normal operation
1 = Digital gain feature for channel A is bypassed
Bits D[2:0]
TEST PATTERN CH C: Channel C test pattern programmability
These bits program the test pattern for channel C.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In 11-bit mode, output data (D[10:0]) are an alternating sequence of 10101010101 and
01010101010.
In 14-bit burst mode, output data ([D:0]) are an alternating sequence of
01010101010101 and 10101010101010.
100 = Outputs digital ramp
In 11-bit mode, output data increments by one 11-bit LSB every 8th clock cycle from
code 0 to code 2047.
In 14-bit burst mode, output data increments by one 14-bit LSB every clock cycle from
code 0 to code 16383
101 = Outputs custom pattern
To program a pattern in 11-bit mode, use the CUSTOM PATTERN D[13:3] bits of
registers 3Fh and 40h.
To program a pattern in 14-bit mode, use the CUSTOM PATTERN D[13:0] bits of
registers 3Fh and 40h.
110 = Unused
111 = Unused
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
29
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Register Address 3Dh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
SEL OFFSET CORR
0
0
0
0
0
Bits D[7:6]
Always write '0'
Bit D5
SEL OFFSET CORR: Offset correction setting
This bit enables the offset correction feature for all four channels after the DIGITAL
ENABLE bit is set to ‘1,’ correcting mid-code to 1023. In addition, write the SPECIAL
MODE 0 bit (register CFh, value 08h) for proper operation of the offset correction feature.
Note that the offset correction feature should only be used in the default 11-bit mode.
0 = Offset correction disabled
1 = Offset correction enabled
Bits D[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
CUSTOM
PATTERN D13
CUSTOM
PATTERN D12
CUSTOM
PATTERN D11
CUSTOM
PATTERN D10
CUSTOM
PATTERN D9
CUSTOM
PATTERN D8
Bits D[7:6]
Always write '0'
Bits D[5:0]
CUSTOM PATTERN D[13:8]
Set the custom pattern using these bits for all four channels.
Register Address 40h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
CUSTOM
PATTERN D7
CUSTOM
PATTERN D6
CUSTOM
PATTERN D5
CUSTOM
PATTERN D4
CUSTOM
PATTERN D3
CUSTOM
PATTERN D2
CUSTOM
PATTERN D1
CUSTOM
PATTERN D0
Bits D[7:0]
CUSTOM PATTERN D[7:0]
Set the custom pattern using these bits for all four channels.
30
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Register Address 41h (Default = 00h)
D7
D6
D5
0
0
0
D4
D3
D2
HIGH RESOLUTION SAMPLES, NH
Bits D[7:5]
Always write '0'
Bits D[4:1]
HIGH RESOLUTION SAMPLES, NH
D1
D0
AUTO BURST ENABLE
These bits control the number of high-resolution samples in 14-bit burst mode with
Equation 1:
210 + NH
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
Bit D0
NH
NH
NH
NH
NH
NH
NH
NH
NH
NH
NH
NH
NH
NH
NH
NH
(1)
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AUTO BURST ENABLE
0 = 14-bit burst mode disabled
1 = 14-bit burst mode auto-enabled
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
31
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Register Address 42h (Default = 00h)
D7
D6
D5
D4
D3
D2
0
0
0
0
DIGITAL ENABLE
SNRB 45/90MHz
Bits D[7:4]
Always write '0'
Bit D3
DIGITAL ENABLE
D1
D0
LOW RESOLUTION SAMPLES, NL
1 = Digital gain and offset correction features disabled
1 = Digital gain and offset correction features enabled
SNRB 45/90MHz: SNRBoost3G+ enable
Bit D2
0 = SNRBoost3G+ enabled with 90-MHz bandwidth (default after reset)
1 = SNRBoost3G+ enabled with 45-MHz bandwidth
Bits D[1:0]
LOW RESOLUTION SAMPLES, NL
These bits control the number of low-resolution samples in 14-bit burst mode with
Equation 2:
213 + NH + NL
00:
01:
10:
11:
NL
NL
NL
NL
=
=
=
=
(2)
0
1
2
3
Register Address 44h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
BMODE EN CH CD
BMODE EN CH AB
0
0
0
BMODE OVR ENABLE
0
DIS SNRB
Bit D7
BMODE EN CH CD
0 = 14-bit burst mode disabled for channels C and D
1 = 14-bit burst mode enabled for channels C and D
Bit D6
BMODE EN CH AB
0 = 14-bit burst mode disabled for channels A and B
1 = 14-bit burst mode enabled for channels A and B
Bits D[5:3]
Always write '0'
Bit D2
BMODE OVR ENABLE
This bit can only be used in 14-bit burst mode.
0 = 14-bit data comes out without an OVR
1 = The ADC data out bit (Dxx[0]) becomes OVRxx. See the Overrange Indication
(OVRxx) section for details.
Bit D1
Always write '0'
Bit D0
DIS SNRB: Disable SNRBoost
This bit only functions when SNRB PIN OVRD is set.
0 = Default
1 = SNRBoost3G+ is disabled for all four channels.
32
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Register Address 45h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
SEL OVR
GLOBAL POWER DOWN
0
CONFIG PDN PIN
Bits D[7:4]
Always write '0'
Bit D3
SEL OVR: OVR selection
0 = Fast OVR selected
1 = Normal OVR selected. See the Overrange Indication (OVRxx) section for details.
Bit D2
GLOBAL POWER DOWN
0 = Normal operation
1 = Global power down. All ADC channels, internal references, and output buffers are
powered down. Wakeup time from this mode is slow (100 µs).
Bit D1
Always write '0'
Bit D0
CONFIG PDN PIN
Use this bit to configure PDN pin.
0 = The PDN pin functions as a standby pin. All channels are put in standby. Wake-up
time from standby mode is fast (10 µs).
1 = The PDN pin functions as a global power-down pin. All ADC channels, internal
references, and output buffers are powered down. Wake-up time from global power
mode is slow (100 µs).
Register Address 4Ah (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
SPECIAL MODE 14
Bits D[7:1]
Always write '0'
Bit D0
SPECIAL MODE 14
Set the SPECIAL MODE[17:14] bits high to reduce the minimum functional clock speed
to 10 MSPS. Usage of these bits should be limited to functional checks only because
performance degrades when these bits are set high.
Register Address 62h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
SPECIAL MODE 15
Bits D[7:1]
Always write '0'
Bit D0
SPECIAL MODE 15
Set the SPECIAL MODE[17:14] bits high to reduce the minimum functional clock speed
to 10 MSPS. Usage of these bits should be limited to functional checks only because
performance degrades when these bits are set high.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
33
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Register Address 7Ah (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
SPECIAL MODE 17
Bits D[7:1]
Always write '0'
Bit D0
SPECIAL MODE 17
Set the SPECIAL MODE[17:14] bits high to reduce the minimum functional clock speed
to 10 MSPS. Usage of these bits should be limited to functional checks only because
performance degrades when these bits are set high.
Register Address 92h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
SPECIAL MODE 16
Bits D[7:1]
Always write '0'
Bit D0
SPECIAL MODE 16
Set the SPECIAL MODE[17:14] bits high to reduce the minimum functional clock speed
to 10 MSPS. Usage of these bits should be limited to functional checks only because
performance degrades when these bits are set high.
Register Address A9h (Default = 00h)
D7
D6
D5
D4
0
0
0
0
Bits D[7:4]
Always write '0'
Bits D[6:3]
CLOCKOUT DELAY PROG CH AB
D3
D2
D1
D0
CLOCKOUT DELAY PROG CH AB
These bits program the clock out delay for channels A and B, see Table 5.
34
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Register Address ACh (Default = 00h)
D7
D6
0
D5
D4
D3
CLOCKOUT DELAY PROG CH CD
Bit D7
Always write '0'
Bits D[7:4]
CLOCKOUT DELAY PROG CH CD
D2
D1
D0
0
0
0
These bits program the clock out delay for channels C and D, as shown in Table 5.
Bits D[2:0]
Always write '0'
Table 5. Clock Out Delay Programmability for All Channels
CLOCKOUT DELAY PROG CHxx
DELAY (ps)
0000
0
0001
–30
0010
70
0011
30
0100
–150
0101
–180
0110
–70
0111
–110
1000
270
1001
230
1010
340
1011
300
1100
140
1101
110
1110
200
1111
170
Register Address C3h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
FAST OVR THRESH PROG
Bits D[7:0]
FAST OVR THRESH PROG
The ADS58H43 has a fast OVR mode that indicates an overload condition at the ADC
input. The input voltage level at which the overload is detected is referred to as the
threshold and is programmable using the FAST OVR THRESH PROG bits.
FAST OVR is triggered seven output clock cycles after the overload condition occurs. To
enable the FAST OVR programmability, enable the EN FAST OVR THRESH register bit.
The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the
FAST OVR THRESH PROG bits] / 255).
After reset, when EN FAST OVR THRESH PROG is set, the default value of the FAST
OVR THRESH PROG bits is 230 (decimal).
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
35
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Register Address C4h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
EN FAST OVR THRESH
0
0
0
0
0
0
0
Bit D7
EN FAST OVR THRESH
This bit enables the ADS58H43 to be programmed to select the fast OVR threshold.
Bits D[6:0]
Always write '0'
Register Address CFh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
SPECIAL MODE 0
0
0
0
Bits D[7:4]
Always write '0'
Bit D3
SPECIAL MODE 0
This bit must be set to ‘1’ when the SEL OFFSET CORR bit is selected.
Bits D[2:0]
Always write '0'
Register Address D4h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
SPECIAL MODE 1
0
0
0
0
0
0
0
Bit D7
SPECIAL MODE 1
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[6:0]
Always write '0'
Register Address D5h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
SPECIAL MODE 2
0
0
0
0
0
0
0
Bit D7
SPECIAL MODE 2
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[6:0]
Always write '0'
Register Address D6h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
SPECIAL MODE 3
0
0
0
0
0
0
0
Bit D7
SPECIAL MODE 3
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[6:0]
36
Always write '0'
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Register Address D7h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
SPECIAL MODE 5
SPECIAL MODE 4
0
0
Bits D[7:4]
Always write '0'
Bit D3
SPECIAL MODE 5
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bit D2
SPECIAL MODE 4
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[1:0]
Always write '0'
Register Address DBh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
SPECIAL MODE 7
SPECIAL MODE 6
0
0
0
0
Bits D[7:6]
Always write '0'
Bit D5
SPECIAL MODE 7
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bit D4
SPECIAL MODE 6
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[3:0]
Always write '0'
Register Address EAh (Default = 00h)
Bit D7
D7
D6
D5
D4
D3
D2
D1
D0
SNRB PIN OVRD
0
0
0
0
0
0
0
SNRB PIN OVRD
0 = SNRBoost3G+ is controlled by the SNRB pin.
1 = SNRBoost3G+ is controlled by the DIS SNRB register bit.
Bits D[6:0]
Always write '0'
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
37
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Register Address F0h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
SPECIAL MODE 10
SPECIAL MODE 9
SPECIAL MODE 8
0
0
0
Bits D[7:6]
Always write '0'
Bit D5
SPECIAL MODE 10
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bit D4
SPECIAL MODE 9
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bit D3
SPECIAL MODE 8
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[2:0]
Always write '0'
Register Address F1h (Default = 00h)
D7
D6
D5
D4
D3
0
0
SPECIAL MODE 11
0
0
Bits D[7:6]
Always write '0'
Bit D7
SPECIAL MODE 11
D2
D1
D0
ENABLE LVDS SWING PROG
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[4:3]
Always write '0'
Bits D[2:0]
ENABLE LVDS SWING PROG
This bit enables the LVDS swing control with the LVDS SWING bits.
00 = LVDS swing control disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control enabled
38
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Register Address F5h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
SPECIAL MODE 13
0
0
0
0
SPECIAL MODE 12
0
Bit D7
Always write '0'
Bit D6
SPECIAL MODE 13
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bits D[5:2]
Always write '0'
Bit D1
SPECIAL MODE 12
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Bit D0
Always write '0'
Register Address FEh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
PDN CH D
PDN CH C
PDN CH A
PDN CH B
Bits D[7:4]
Always write '0'
Bit D3
PDN CH D: Power-down channel D
Channel D is powered down.
Bit D2
PDN CH C: Power-down channel C
Channel C is powered down.
Bit D1
PDN CH B: Power-down channel A
Channel B is powered down.
Bit D0
PDN CH A: Power-down channel B
Channel A is powered down.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
39
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS58H43 is a quad-channel, 11-bit, analog-to-digital converter (ADC) with sampling rates up to
250 MSPS. At every falling edge of the input clock, the analog input signal for each channel is sampled
simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each
stage, the sampled-and-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference
(residue) between the stage input and its quantized equivalent is gained and propagates to the next stage. At
every clock, each subsequent stage resolves the sampled input with greater accuracy. The digital outputs from
all stages are combined in a digital correction logic block and digitally processed to create the final code, after a
data latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential
signaling (LVDS) interface and is coded in binary twos complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor-based differential sample-and-hold architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 1.15 V, available on the
VCM pin. For a full-scale differential input, each input pin (INP, INM) must swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing.
The input sampling circuit has a high 3-dB bandwidth that extends up to 500 MHz when a 50-Ω source drives the
ADC analog inputs.
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This configuration improves the
common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each
input pin is recommended to damp out ringing caused by package parasitics.
Spurious-free dynamic range (SFDR) performance can be limited because of several reasons (such as the effect
of sampling glitches, sampling circuit nonlinearity, and quantizer nonlinearity that follows the sampling circuit).
Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant
part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling
circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance.
Glitches are caused by opening and closing the sampling switches. The driving circuit should present a low
source impedance to absorb these glitches, otherwise these glitches may limit performance. A low impedance
path between the analog input pins and VCM is required from the common-mode switching currents perspective
as well. This impedance can be achieved by using two resistors from each input terminated to the common-mode
voltage (VCM).
The ADS58H43 includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb
the sampling glitches inside the device itself. The R-C component values are also optimized to support high input
bandwidth (up to 500 MHz). However, using an R-LC-R filter (refer to Figure 46, Figure 47, Figure 48, Figure 49,
and Figure 50) improves glitch filtering, thus further resulting in better performance.
40
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched source impedance. In doing so, the ADC input impedance must be considered. Figure 43,
Figure 44, and Figure 45 show the impedance (ZIN = RIN || CIN) at the ADC input pins.
XINP(1)
RIN
ZIN(2)
CIN
XINM(1)
(1) X = A, B, C, or D.
(2) ZIN = RIN || (1 / jωCIN).
Figure 43. ADC Equivalent Input Impedance
1
6
Differential Input Capacitance, Cin (pF)
Differential Input Resistance, Rin (kΩ)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
5
4
3
2
1
0.2
0.1
100
200
300
Frequency (MHz)
400
500
0
100
200
300
Frequency (MHz)
400
G037
Figure 44. ADC Analog Input Resistance (RIN) vs
Frequency
500
G038
Figure 45. ADC Analog Input Capacitance (CIN) vs
Frequency
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
41
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Driving Circuit
Two example driving circuits with a 50-Ω source impedance are shown in Figure 46 and Figure 47. The driving
circuit in Figure 46 is optimized for input frequencies in the second Nyquist zone (centered at 185 MHz), whereas
the circuit in Figure 47 is optimized for input frequencies in third Nyquist zone (centered at 310 MHz).
Note that both drive circuits are terminated by 50 Ω near the ADC side. This termination is accomplished with a
25-Ω resistor from each input to the 1.15-V common-mode (VCM) from the device. This architecture allows the
analog inputs to be biased around the required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals.
50 :
T1
T2
0.1 PF
10 :
INP
25 :
Band-Pass Filter
Centered at
f0 = 185 MHz
BW = 125 MHz
25 :
82 nH
RIN
10 pF
CIN
0.1 PF
25 :
25 :
INM
1:1
1:1
10 :
0.1 PF
VCM
Device
Figure 46. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies
in the Second Nyquist Zone
50 :
T1
T2
0.1 PF
10 :
INP
25 :
Band-Pass Filter
Centered at
f0 = 310 MHz
BW = 125 MHz
25 :
27 nH
RIN
10 pF
CIN
0.1 PF
25 :
25 :
INM
1:1
1:1
0.1 PF
10 :
VCM
Device
Figure 47. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies
in the Third Nyquist Zone
42
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Appropriate high-performance modes must be written to ensure best performance in a given Nyquist zone and
source impedance. Table 6 summarizes all available high-performance modes.
Table 6. High-Performance Modes Summary (1) (2)
fS = 245.76 MSPS
(1)
(2)
RS = 50
ZONE = 2
RS = 100
ZONE = 2
fS = 184.32 MSPS
ADDRESS
(Hex)
DATA (Hex)
RS = 50
ZONE = 3
D4
80
D5
80
D6
80
√
√
√
D7
0C
√
√
√
DB
30
F0
38
F1
20
F5
42
RS = 100
ZONE = 3
RS = 50
ZONE = 2
RS = 100
ZONE = 2
√
√
√
√
√
√
√
√
√
√
√
√
√
RS refers to the source impedance. Zone refers to the Nyquist zone in which the signal band lies. Zone = 2 corresponds to the signal
band that lies between fS / 2 and fS. Zone = 3 corresponds to the signal band that lies between fS and 3 × fS / 2.
Best performance can be achieved by writing these modes depending upon source impedance, band of operation, and sampling speed.
Two example driving circuits with 100-Ω differential termination are shown in Figure 48 and Figure 49. In these
example circuits, the 1:2 transformer (T1) is used to transform the 50-Ω source impedance into a differential 100
Ω at the input of the band-pass filter. In Figure 48, the parallel combination of two 68-Ω resistors and one 120-nH
inductor and two 100-Ω resistors is used (100-Ω is the effective impedance in pass-band) for better performance.
The required high-performance modes for these applications are given in Table 6.
50 :
T1
0.1 PF
T2
10 :
INP
68 :
Band-Pass Filter
Centered at
f0 = 185 MHz
BW = 125 MHz
25 :
100 :
120 nH
82 nH
RIN
10 pF
CIN
0.1 PF
100 :
68 :
25 :
10 :
1:2
INM
0.1 PF
1:1
VCM
Device
Figure 48. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies
in the Second Nyquist Zone
50 :
T1
T2
0.1 PF
10 :
INP
25 :
50 :
Band-Pass Filter
Centered at
f0 = 310 MHz
BW = 125 MHz
27 nH
RIN
10 pF
CIN
0.1 PF
50 :
25 :
10 :
1:2
1:1
0.1 PF
INM
VCM
Device
Figure 49. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies
in the Third Nyquist Zone
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
43
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Input Common Mode
To ensure a low-noise, common-mode reference, the VCM pin should be filtered with a 0.1-µF low-inductance
capacitor connected to ground. The VCM pin is designed to directly bias the ADC inputs (refer to Figure 46 to
Figure 49).
Each ADC input pin sinks a common-mode current of approximately 1.5 µA per MSPS of clock frequency. When
a differential amplifier is used to drive the ADC (with dc-coupling), ensure that the output common-mode of the
amplifier is within the acceptable input common-mode range of the ADC inputs (VCM ± 25 mV).
Clock Input
The ADS58H43 clock inputs can be driven differentially with a sine, LVPECL, or LVDS source with little or no
difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using
internal 5-kΩ resistors, as shown in Figure 50. This setting allows the use of transformer-coupled drive circuits for
sine-wave clock or ac-coupling for LVPECL, LVDS, and LVCMOS clock sources (see Figure 51, Figure 52, and
Figure 53).
For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to commonmode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 VPP to obtain
best performance. A clock source with very low jitter is recommended for high input frequency sampling. Bandpass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a
non-50% duty cycle clock input.
Clock Buffer
LPKG
~ 2 nH
20 Ω
CLKP
CBOND
~ 1 pF
CEQ
RESR
~ 100 Ω
CEQ
5 kΩ
0.95V
LPKG
~ 2 nH
5 kΩ
20 Ω
CLKM
CBOND
~ 1 pF
RESR
~ 100 Ω
CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 50. Internal Clock Buffer
(1) RT is the termination resistor (optional).
44
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
0.1 mF
ZO
0.1 mF
CLKP
CLKP
150 W
Differential
Sine-Wave
Clock Input
Typical LVPECL
Clock Input
RT
0.1 mF
100 W
ZO
0.1 mF
CLKM
CLKM
150 W
Figure 51. Differential Sine-Wave Clock Driving
Circuit
ZO
Figure 52. LVPECL Clock Driving Circuit
0.1 mF
0.1 mF
CLKP
Typical LVDS
Clock Input
CLKP
CMOS
Clock Input
100 W
ZO
0.1 mF
VCM
0.1 mF
CLKM
CLKM
Figure 53. LVDS Clock Driving Circuit
Figure 54. Typical LVCMOS Clock Driving Circuit
OVERVIEW OF OPERATING MODES
There are three available operating modes: 11-bit, 250-MSPS mode; 11-bit SNRBoost3G+, 250-MSPS mode; and
14-bit, 250-MSPS mode (burst mode). Table 7 shows a summary of the operating modes.
Table 7. Operating Mode Summary
RESULTING MODE OF OPERATION
PIN SETTING
Default
(after power up)
REGISTER SETTING
CHANNELS A AND B
CHANNELS C AND D
—
11 bit, 250 MSPS
11 bit, 250 MSPS
—
SNRBoost3G+, 90 MHz
SNRBoost3G+, 90 MHz
Set SNRB 45/95MHz bit
(register 42h, value 4h)
SNRBoost3G+, 45 MHz
SNRBoost3G+, 45 MHz
Set SNRB pin high
Set BMODE EN CH AB bit
(register 44h, value 40h)
Burst mode:
Low resolution = 11 bits at 250 MSPS
High resolution = 14 bits at 250 MSPS
SNRBoost3G+, 90 MHz
Set SNRB pin high
Set BMODE EN CH CD bit
(register 44h, value 80h)
SNRBoost3G+, 90 MHz
Burst mode:
Low resolution = 11 bits at 250 MSPS
High resolution = 14 bits at 250 MSPS
Set SNRB pin low
(default)
Set both BMODE EN CH AB
and BMODE EN CH CD bits
(register 44h, value C0h)
Burst mode:
Low resolution = 11 bits at 250 MSPS
High resolution = 14 bits at 250 MSPS
Burst mode:
Low resolution = 11 bits at 250 MSPS
High resolution = 14 bits at 250 MSPS
Set SNRB pin high
11-Bit, 250-MSPS Mode: Output of the 11 MSBs on the digital DDR LVDS interface.
11-Bit SNRBoost3G+, 250-MSPS Mode: 11-bit output using SNRBoost3G+ signal processing.
• 90-MHz wide (centered on fS / 4)
• 45-MHz wide (centered on fS / 8 and 3 fS / 8)
14-Bit, 250-MSPS (Burst) Mode: In burst mode, the 14-bit, 250-MSPS digital output data stream alternates
between high resolution (14-bit) and low resolution (11-bit). The high-resolution sample can be transmitted using
the burst trigger input (TRIG_EN). The HIRES output flag indicates high-resolution data. The amount of highresolution samples is programmable.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
45
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
There are two different options available in burst mode: auto-trigger and manual-trigger.
• Auto-Trigger Mode: After transmission of the final low-resolution sample, the ADS58H43 immediately begins
sending the high-resolution samples. However, auto-trigger mode requires an initial trigger at the TRIG_EN
pin to start the high-resolution process. Thereafter, all subsequent triggers are automated.
• Manual-Trigger Mode: After transmission of the final low-resolution sample, the ADS58H43 is ready for the
manual trigger of a high-resolution data burst indicated by the TRIG_RDY flag. The high-resolution samples
are triggered every time by the rising edge of the pulse on the TRIG_EN pin.
The default mode of operation is 11-bit resolution. A set of two channels (channels A and B and channels C and
D) can be in either SNRBoost3G+ mode or in burst mode, separately.
SNRBoost3G+ can be enabled by the SNRB pin or by the SPI bit (SNRB PIN OVRD). However, burst mode can
only be enabled by using an SPI register bit. In burst mode, the automatic trigger can be enabled by setting the
SPI register bit AUTO BURST ENABLE (register 41h, bit 0) and the manual trigger can be enabled through the
TRIG_EN pin. Table 7 summarizes the process for enabling SNRBoost3G+ from pin settings and enabling burst
mode from the SPI registers on different channels.
Burst Mode
After enabling burst mode, the device is limited to 11-bit (low-resolution) samples until a trigger is asserted
through the TRIG_EN pin. A TRIG_EN rising edge causes the device to output a set of 14-bit (high-resolution)
samples, followed by another set of 11-bit (low-resolution) samples.
In auto-trigger mode (set using the SPI register), this cycle repeats as long as the device is in burst mode. In
manual-trigger mode, this cycle is followed by a delay until the next rising edge on the TRIG_EN pin occurs.
During this cycle (high-resolution samples followed by low-resolution samples), any edge on TRIG_EN is
ignored.
The HIRES output flag is set high when the device outputs high-resolution, 14-bit data; otherwise, HIRES is '0'.
The TRIG_RDY output flag is set high while the device waits for a rising edge on the TRIG_EN pin; otherwise,
this flag is cleared.
The ratio of high-resolution, 14-bit samples to low-resolution, 11-bit samples is programmable between 1:8 and
1:64. The number of high-resolution, 14-bit samples is also programmable.
The number of 14-bit, high-resolution samples is shown in Equation 3:
210 + NH
where:
0 ≤ NH ≤ 15
(3)
The number of 11-bit, low-resolution samples is shown in Equation 4:
213 + NH + NL
where:
0 ≤ NL ≤ 3
(4)
Both NH and NL parameters can be programmed through the SPI at any time, but are internally updated at the
end of the high-resolution data transmission.
46
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
Manual-Trigger Mode
Figure 55 shows a timing diagram for this mode.
Enable
Burst Mode
Manual Trigger
TRIG_EN
Trigger on TRIG_EN Rising Edge
tTRIG_DELAY
TRIG_RDY
DAB[13:0],
DCD[13:0]
High-Resolution
(14-Bit)
210 Samples
Low Resolution (11-Bit)
213 Samples
Ready for
New Trigger
High-Resolution
(14-Bit)
210+NH Samples
Low Resolution (11-Bit)
2(13+NH+NL) Samples
Ready for
New Trigger
Update NH and
NL Values
Update NH and
NL Values
HIRES
Figure 55. Timing For Manual-Trigger Mode
Auto-Trigger Mode
In this mode, the output data cycles automatically between 11-bit and 14-bit resolution, as shown in Figure 56.
After the first rising edge of the pulse on TRIG_EN that turns the 14-bit burst mode on, the device continues to
provide high-resolution samples interlaced with low-resolution samples and any subsequent edge on TRIG_EN is
ignored. The TRIG_RDY output flag is invalid in this mode.
Enable Burst Mode
Auto Trigger
DAB[13:0],
DCD[13:0]
Low Resolution
(11-Bit)
213 Samples
High-Resolution
(14-Bit)
210 Samples
Low Resolution (11-Bit)
2(13+NH+NL) Samples
Update NH and
NL Values
High-Resolution
(14-Bit)
210+NH Samples
Update NH and
NL Values
HIRES
Figure 56. Timing for Auto-Trigger Mode
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
47
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
Overrange Indication (OVRxx)
The ADS58H43 outputs overrange information on the Dxx0P and Dxx0M pins (where xx = channels A and B or
channels C and D) of the digital output interface. When transmitting high-resolution (14-bit) output data in burst
mode, Dxx0P and Dxx0M transmit the output data LSB instead. An OVR timing diagram is shown in Figure 57.
CLKOUTP,
CLKOUTM
DAB13P, DAB13M
(MSB)
A
B
A
B
DAB12P,
DAB12M
A
B
A
B
...
...
SNRBoost3G+
11-Bit Output
DAB4P,
DAB4M
A
B
A
B
DAB3P, DAB3M
(LSB)
A
B
A
B
B
A
B
DAB2P,
DAB2M
Not Valid Output Data
DAB1P,
DAB1M
Not Valid Output Data
OVRABP, OVRABM
(DAB0P, DAB0M)
A
Sample N
Overrange
Indicator
Sample N+1
Figure 57. Overrange Indicator (OVR) Timing
Normal overrange indication (OVR) shows the event of the ADS58H43 digital output being saturated when the
input signal exceeds the ADC full-scale range. Normal OVR has the same latency as digital output data.
However, an overrange event can be indicated earlier (than normal latency) by using the fast OVR mode. The
fast OVR mode (enabled by default) is triggered seven clock cycles after the overrange condition that occurred at
the ADC input. The fast OVR thresholds are programmable with the FAST OVR THRESH PROG bits (refer to
Table 4, register address C3h). At any time, either normal or fast OVR mode can be programmed on the Dxx0P
and Dxx0M pins. A block diagram indicating required register writes to enable OVR is shown in Figure 58.
Dxx[13:1]
0
Dxx[0]
Fast OVR
Dxx[0]/OVR
0
0
1
1
Normal OVR
1
HIRES Bit
BMODE OVR ENABLE Bit
SEL OVR Bit
Figure 58. OVR Block Diagram
48
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
SNRBoost3G+ Implementation
There are two possible filter configurations in SNRBoost3G+ mode. The SNRBoost3G+ bandwidth can be set to
90 MHz (Figure 59) or 45 MHz (Figure 60). In the 45-MHz mode, there are two 45-MHz filter bands available
simultaneously. One band is centered on fS / 8 (low side) and the other band is centered on 3 fS / 8 (high side).
The filter configurations are detailed in Table 8.
Table 8. SNRBoost3G+ Filter Configurations
START
STOP
CENTER FREQUENCY
fS / 4
90
0.06 × fS
0.44 × fS
45 (low side)
0.03 × fS
0.216 × fS
fS / 8
45 (high side)
0.286 × fS
0.466 × fS
3 × fS / 8
0
0
−20
−20
−40
−40
Amplitude (dB)
Amplitude (dB)
CORNER FREQUENCIES
BANDWIDTH (MHz)
−60
−60
−80
−80
−100
−100
−120
0
25
50
75
Frequency (MHz)
100
125
−120
0
25
50
75
Frequency (MHz)
100
G093
3G+
Figure 59. 90-MHz SNRBoost
Filter Bandwidth
Centered on fS / 4
125
G092
3G+
Figure 60. 45-MHz SNRBoost
Filter Bandwidth
Centered on fS / 8 and 3 fS / 8
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
49
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
GAIN FOR SFDR AND SNR TRADE-OFF
The ADS58H43 includes gain settings that can be used to obtain improved SFDR performance. The gain is
programmable from 0 dB to 6 dB (in 0.5-dB steps) using the DIGITAL GAIN CH X register bits. For each gain
setting, the analog input full-scale range scales proportionally, as shown in Table 9.
Table 9. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
Default after reset
2
1
Fine, programmable
1.78
2
Fine, programmable
1.59
3
Fine, programmable
1.42
4
Fine, programmable
1.26
5
Fine, programmable
1.12
6
Fine, programmable
1
SFDR improvement is achieved at the expense of SNR; for each gain setting, SNR degrades by approximately
0.5 dB to 1 dB. SNR degradation is diminished at high input frequencies. As a result, the fine gain is very useful
at high input frequencies because SFDR improvement is significant with marginal degradation in SNR. Therefore,
fine gain can be used to trade-off between SFDR and SNR.
After a reset, the gain function is disabled. To use fine gain:
• First, program the DIGITAL ENABLE bits to enable digital functions.
• This setting enables the gain for all four channels and places the device in a 0-dB gain mode.
• For other gain settings, program the DIGITAL GAIN CH X register bits.
DIGITAL OUTPUT INFORMATION
The ADS58H43 provides 11-bit (or 14-bit in burst mode) digital data for each channel and two output clocks in
LVDS mode. Output pins are shared by a pair of channels that are accompanied by one dedicated output clock.
DDR LVDS Outputs
In the LVDS interface mode, the data bits and clock are output using LVDS levels. The data bits of two channels
are multiplexed and output on each LVDS differential pair of pins; see Figure 61 and Figure 62.
50
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
CLKOUTxxP,
CLKOUTxxM
Dxx0P,
Dxx0M
Dxx1P,
Dxx1M
Dxx2P,
Dxx2M
14-Bit Output in Burst Mode
(11-Bit in Default and SNRBoost3G+
Mode on the Dxx[13:3] Output Pins)
Dxx12P,
Dxx12M
Dxx13P,
Dxx13M
Device
NOTE: xx = channels A and B or C and D.
Figure 61. DDR LVDS Interface
CLKOUTABM
CLKOUTABP
DAB[13:0]P,
DAB[13:0]M
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
Sample N
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
DA[13:0]P,
DA[13:0]M
Sample N + 1
DB[13:0]P,
DB[13:0]M
Sample N + 2
CLKOUTCDM
CLKOUTCDP
DCD[13:0]P,
DCD[13:0]M
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
Sample N
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
DC[13:0]P,
DC[13:0]M
Sample N + 1
DD[13:0]P,
DD[13:0]M
Sample N + 2
Figure 62. DDR LVDS Interface Timing Diagram
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
51
ADS58H43
SBAS598 – NOVEMBER 2012
www.ti.com
LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 63. After reset, the buffer presents an
output impedance of 100 Ω to match with the external 100-Ω termination.
The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits (refer to Table 4, register address 01h).
The buffer output impedance behaves similar to a source-side series termination. By absorbing reflections from
the receiver end, the source-side termination helps to improve signal integrity.
VDIFF(high)
High
Low
OUTP
External
100-W Load
OUTM
1.1 V
ROUT
VDIFF(low)
Low
High
Figure 63. LVDS Buffer Equivalent Circuit
Output Data Format
The ADS58H43 transmits data in binary twos complement format. In the event of an input voltage overdrive, the
digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 3FFh. For a
negative input overdrive, the output code is 400h.
BOARD DESIGN CONSIDERATIONS
For evaluation module (EVM) board information, refer to the ADS58H40 EVM User's Guide (SLAU455).
Grounding
A single ground plane is sufficient to provide good performance, as long as the analog, digital, and clock sections
of the board are cleanly partitioned. See the ADS58H40 EVM User's Guide (SLAU455) for details on layout and
grounding.
52
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
ADS58H43
www.ti.com
SBAS598 – NOVEMBER 2012
DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – INL is the deviation of the ADC transfer function from a best-fit line determined by
a least-squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from the ideal value. Gain error
is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of
reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and
EGCHAN.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) × fS ideal to (1 + 0.5 / 100) × fS ideal.
Offset Error – Offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. The coefficient is calculated by dividing the
maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(5)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
SINAD = 10Log10
PS
PN + PD
(6)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ADS58H43
53
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS58H43IZCR
ACTIVE
NFBGA
ZCR
144
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS58H43I
ADS58H43IZCRR
ACTIVE
NFBGA
ZCR
144
1000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS58H43I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of