ADS62P45IRGC25

ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Check for Samples: ADS62P45, ADS62P44, ADS62P43, ADS62P42 FEATURES 1 • • • • • • • • • • • Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes 95 dB Crosstalk Parallel CMOS and DDR LVDS Output Options 3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off Digital Processing Block with: – Offset Correction – Fine Gain Correction, in Steps of 0.05 dB – Decimation by 2/4/8 – Built-in and Custom Programmable 24-Tap Low-/High-/Band-Pass Filters Supports Sine, LVPECL, LVDS and LVCMOS Clocks and Amplitude Down to 400 mVPP Clock Duty Cycle Stabilizer Internal Reference; Supports External Reference also 64-QFN Package (9mm × 9mm) Pin Compatible 12-Bit Family (ADS62P2X) APPLICATIONS • • • • Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e • • • Medical Imaging Radar Systems Test and Measurement Instrumentation DESCRIPTION ADS62P4X is a dual channel 14-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. ADS62P4X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled. Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P4X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). Table 1. ADS62P4X Performance Summary Fin = 10 MHz (0 dB gain) SFDR, dBc Fin = 190 MHz (3.5 dB gain) SINAD, dBFS ADS62P45 ADS62P44 ADS62P43 ADS62P42 88 92 93 94 84 86 87 85 Fin = 10 MHz (0 dB gain) 73.7 74.2 74.6 74.7 Fin = 190 MHz (3.5 dB gain) 70.8 71 71.3 70.9 799 710 594 515 Analog Power, mW 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2012, Texas Instruments Incorporated ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. DRGND DRVDD AGND AVDD ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Digital Processing Block DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 Channel A INA_P INA_M SHA CLKP CLKM 14-Bit ADC Output Buffers 14 Bit 14 Bit SHA 14-Bit ADC Channel A Output Clock Buffer CLOCKGEN INB_P INB_M Digital Encoder Digital Encoder 14 Bit 14 Bit CLKOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 Output Buffers Channel B Digital Processing Block Channel B VCM Reference Control Interface CTRL1 CTRL2 CTRL3 RESET SCLK SEN SDAATA CMOS Interface B0286-01 ADS62PXX Family 2 125 MSPS 105 MSPS 80 MSPS 65 MSPS ADS62P4X 14 Bits ADS62P45 ADS62P44 ADS62P43 ADS62P42 ADS62P2X 12 Bits ADS62P25 ADS62P24 ADS62P23 ADS62P22 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS62P45 QFN-64 (2) RGC –40°C to 85°C AZ62P45 ADS62P44 QFN-64 (2) RGC –40°C to 85°C AZ62P44 ADS62P43 QFN-64 (2) RGC –40°C to 85°C AZ62P43 ADS62P42 (1) (2) QFN-64 (2) RGC –40°C to 85°C AZ62P42 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS62P45IRGCT Tape and Reel, 250 ADS62P45IRGCR Tape and Reel, 2500 ADS62P44IRGCT Tape and Reel, 250 ADS62P44IRGCR Tape and Reel, 2500 ADS62P43IRGCT Tape and Reel, 250 ADS62P43IRGCR Tape and Reel, 2500 ADS62P42IRGCT Tape and Reel, 250 ADS62P42IRGCR Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in × 3 in (7.62 cm × 7.62 cm) PCB. ABSOLUTE MAXIMUM RATINGS (1) VI VALUE UNIT Supply voltage range, AVDD –0.3 to 3.9 V Supply voltage range, DRVDD –0.3 to 3.9 V Voltage between AGND and DRGND –0.3 to 0.3 V Voltage between AVDD to DRVDD –0.3 to 3.3 V –0.3 to 2 V –0.3 to minimum ( 3.6, AVDD + 0.3) V Voltage applied to VCM pin (in external reference mode) Voltage applied to analog input pins, INP and INM Voltage applied to analog input pins, CLKP and CLKM TA Operating free-air temperature range TJ Operating junction temperature range Tstg Storage temperature range (1) –0.3 to (AVDD + 0.3) V –40 to 85 °C 125 °C –65 to 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 3 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage (1) DRVDD Output buffer supply voltage CMOS interface 3 3.3 3.6 V 1.65 1.8 to 3.3 3.6 V 3 3.3 3.6 V LVDS interface ANALOG INPUTS Differential input voltage range VIC 2 Vpp 1.5 ± 0.1 Input common-mode voltage Voltage applied on VCM in external reference mode 1.45 1.5 V 1.55 V CLOCK INPUT Input clock sample rate, FS ADS62P45 1 125 ADS62P44 1 105 ADS62P43 1 80 ADS62P42 1 Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) 0.4 65 1.5 ± 0.8 LVPECL, ac-coupled Vpp ± 0.35 LVDS, ac-coupled LVCMOS, ac-coupled MSPS 3.3 Input clock duty cycle 35% 50% 65% DIGITAL OUTPUTS Output buffer drive strength (2) for CLOAD ≤ 5 pF and DRVDD ≥ 2.2 V DEFAULT strength for CLOAD > 5 pF and DRVDD ≥ 2.2 V MAXIMUM strength for DRVDD < 2.2 V MAXIMUM strength CMOS interface, maximum buffer strength CLOAD Maximum external load capacitance from each output pin to DRGND 10 LVDS interface, without internal termination 5 LVDS interface, with internal termination RLOAD Differential load resistance (external) between the LVDS output pairs TA Operating free-air temperature (1) (2) 4 pF 10 Ω 100 -40 85 °C For easy migration to the next generation, higher sampling speed devices (> 125 MSPS), use 1.8V DRVDD supply. See Output Buffer Strength Programmability in application section. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 v to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted. ADS62P45 FS = 125 MSPS PARAMETER MIN RESOLUTION TYP ADS62P44 FS = 105 MSPS MAX MIN TYP ADS62P43 FS = 80 MSPS MAX MIN TYP ADS62P42 FS = 65 MSPS MAX MIN TYP UNIT MAX 14 14 14 14 Bits 2 2 2 2 VPP >1 >1 >1 >1 MΩ 7 7 7 7 pF 450 450 450 450 MHz μA/MSP S ANALOG INPUT Differential input voltage range Differential input resistance (dc) see Figure 84 Differential input capacitance see Figure 85 Analog input bandwidth Analog input common mode current (per input pin of each ADC) 1.3 1.3 1.3 1.3 1 1 1 1 V V REFERENCE VOLTAGES VREFB Internal reference bottom voltage VREFT Internal reference top voltage VCM Common mode output voltage VCM output current capability 2 2 2 2 1.5 1.5 1.5 1.5 4 4 4 4 V mA DC ACCURACY No missing codes EO Specified Offset error -10 Offset error temperature coefficient ±2 Specified 10 -10 0.05 ±2 Specified 10 -10 0.05 ±2 Specified 10 -10 0.05 ±2 10 0.05 mV mV/°C There are two sources of gain error – internal reference inaccuracy and channel gain error EGREF EGCHAN Gain error due to internal reference inaccuracy alone -2 0.25 2 -2 0.25 2 -2 0.25 2 -2 0.25 2 % FS -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 % FS (1) Gain error of channel alone across devices & across channels within a device. Channel gain error temperature coefficient DNL Differential nonlinearity INL Integral nonlinearity 0.005 0.00 5 0.005 -0.95 ± 0.6 -5 ± 2.5 5 240 275 -0.95 ± 0.6 -5 ± 2.5 5 215 240 0.95 ± 0.5 -5 ±2 5 180 200 0.005 Δ%/°C 0.95 ± 0.5 LSB -5 ±2 5 LSB 156 175 mA POWER SUPPLY IAVDD IDRVDD Analog supply current Digital supply current, CMOS interface DRVDD = 1.8 V Fin = 2 MHz (2) No external load capacitance 17 14 12 10 mA 10-pF external load capacitance 30 26 22 19 mA 73 73 73 73 mA IDRVDD Digital supply current, LVDS interface with 100-Ω external termination PAVDD Analog power dissipation PDRVDD Digital power dissipation, CMOS interface DRVDD = 1.8 V (3) 799 (3) 710 792 594 660 515 578 mW 31 25 22 18 mW 10-pF external load capacitance 54 47 40 34 mW Global powerdown (1) (2) 908 No external load capacitance 50 75 50 75 50 75 50 75 mW This is specified by design and characterization; it is not tested in production. In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the supply voltage (see Figure 81 and CMOS power dissipation in application section). The maximum DRVDD current depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 5 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS ADS62P45 FS = 125 MSPS MIN TYP MAX ADS62P44 FS = 105 MSPS MIN TYP MAX ADS62P43 FS = 80 MSPS MIN TYP MAX ADS62P42 FS = 65 MSPS MIN TYP UNIT MAX DYNAMIC AC CHARACTERISTICS Fin = 10 MHz Fin = 50 MHz SNR Signal to noise ratio RMS Output Noise 70 Fin = 70 MHz Fin = 190 MHz 0 dB gain 3.5 dB coarse gain Inputs tied to common-mode ENOB Effective Number of Bits Fin = 50 MHz 69 Fin = 70 MHz Fin = 190 MHz 72.2 71 71.2 71.6 70.8 1.0 1.0 1.0 1.0 73.7 74.2 74.6 74.7 73.3 73.5 74.2 74.3 71.5 3.5 dB coarse gain 70.8 71 71.3 70.9 11.2 69 11.9 11.3 11.2 76 92 80 83 86 78 11.3 93 78 73.9 89 89 83 83 81 3.5 dB coarse gain 84 86 87 85 88 90 92 93 79 82 Fin = 70 MHz 84.5 75 86 84 88 88 79 80 80 79 3.5 dB coarse gain 81 82 82 82 94 93 95 98 92 93 76 Fin = 70 MHz 92 78 78 94 93 94 96 86 86 85 86 3.5 dB coarse gain 88 88 88 89 88 92 93 94 76 Fin = 70 MHz 80 86 83 78 78 87 85 89 89 81 83 83 81 3.5 dB coarse gain 84 86 87 85 Fin = 10 MHz 95 96 97 99 Fin = 50 MHz 94 95 96 98 Fin = 70 MHz 94 95 96 97 Fin = 190 MHz 90 93 95 92 Submit Documentation Feedback dBc dBc 87 79 0 dB gain Fin = 190 MHz dBc 97 79 0 dB gain Fin = 50 MHz Bits 86 76 0 dB gain Fin = 50 MHz dBFS 87 79 81 76 LSB 94 87 85 12 0 dB gain 73 dBFS 12 11.95 88 70 74.1 72 Fin = 10 MHz 6 72.5 73.8 Fin = 10 MHz Worst Spur (Other than HD2, HD3) 72.3 71.8 Fin = 50 MHz HD3 Third Harmonic Distortion 72.3 70 71 73.5 Fin = 10 MHz Fin = 190 MHz 74.5 73.9 Fin = 70 MHz Fin = 190 MHz 74.8 74.4 71.4 Fin = 50 MHz SFDR Fin = 70 MHz Spurious Free Dynamic Range Fin = 190 MHz 70 74.8 71 74 73.2 Fin = 50 MHz HD2 Second Harmonic Distortion 74.2 0 dB gain Fin = 10 MHz THD Total Harmonic Distortion 74.5 73.9 73.6 Fin = 10 MHz SINAD Signal to noise and distortion ratio 74.2 dBc dBc Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS ADS62P45 FS = 125 MSPS MIN TYP ADS62P44 FS = 105 MSPS MAX MIN TYP MAX ADS62P43 FS = 80 MSPS MIN TYP MAX ADS62P42 FS = 65 MSPS MIN TYP UNIT MAX IMD 2-Tone Intermodulation Distortion F1 = 185 MHz, F2 = 190 MHz each tone at -7 dBFS 88 87 92 92 dBFS Crosstalk Up to 100 MHz 95 95 95 95 dB Input Overload Recovery Recovery to within 1% (of final value) for 6-dB overload with sine wave input 1 1 1 1 clock cycles PSRR AC Power Supply Rejection Ratio for 100 mVpp signal on AVDD supply 35 35 35 35 dBc DIGITAL CHARACTERISTICS (1) The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1, AVDD = 3.0 V to 3.6 V. PARAMETER TEST CONDITIONS ADS62P45/ADS62P44 ADS62P43/ADS62P42 MIN DIGITAL INPUTS RESET, CTRL1, CTRL2, CTRL3, SCLK, SDATA & SEN TYP MAX UNIT (2) High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 μA Low-level input current –33 μA 4 pF High-level output voltage DRVDD V Low-level output voltage 0 V 2 pF High-level output voltage 1375 mV Low-level output voltage 1025 mV 350 mV 1200 mV 2 pF Input capacitance DIGITAL OUTPUTS CMOS INTERFACE, DRVDD = 1.65 V to 3.6 V Output capacitance inside the device, from each output to ground Output capacitance DIGITAL OUTPUTS LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V, IO = 3.5 mA, RL = 100 Ω (3) Output differential voltage, |VOD| 225 VOS Output offset voltage, single-ended Common-mode voltage of OUTP, OUTM Output capacitance Output capacitance inside the device, from either output to ground (1) (2) (3) All LVDS and CMOS specifications are characterized, but not tested at production. SCLK & SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins, analog voltage needs to be applied as per Table 4 & Table 5 IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 7 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. PARAMETER TEST CONDITIONS ADS62P45 FS = 125 MSPS MIN TYP Aperture delay ta Aperture delay matching 0.7 | ta1 - ta2 | , Channel-to-channel within the same device Wake-up time (to valid data) Latency 0.7 1.5 ADS62P43 FS = 80 MSPS ADS62P42 FS = 65 MSPS UNIT MAX MIN TYP MAX MIN TYP MAX 2.5 0.7 1.5 2.5 0.7 1.5 2.5 50 50 ns 50 ps | ta1 - ta2 | , Channel-to-channel across two devices at same temperature from global power down 450 450 450 450 150 150 150 150 15 50 15 50 15 50 15 fs rms 50 μs 15 50 15 50 15 50 15 50 μs CMOS 100 200 100 200 100 200 100 200 ns LVDS 200 500 200 500 200 500 200 500 ns from standby from output buffer disable 2.5 MIN TYP 50 Aperture jitter tj 1.5 MAX ADS62P44 FS = 105 MSPS default, after reset 14 14 14 14 clock cycles with low latency mode enabled 10 10 10 10 clock cycles with decimation filter enabled 15 15 15 15 clock cycles (4) DDR LVDS MODE , DRVDD = 3.0 V to 3.6 V tsu Data setup time (5) Data valid (6) to zero-cross of CLKOUTP 0.6 1.5 1.0 2.3 2.4 3.8 3.8 5.2 ns th Data hold time (5) Zero-cross of CLKOUTP to data becoming invalid (6) 1.0 2.3 1.0 2.3 1.0 2.3 1.0 2.3 ns tPDI Clock propagation delay Input clock rising edge zero-cross to output clock rising edge zero-cross 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 3.5 5.5 7.5 LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTPCLKOUTM) 10 ≤ Fs ≤ 125 MSPS 46% 50% 53% 46% 50% 53% 46% 50% 53% 46% 50% 53% tr tf Data rise time Data fall time Rise time measured from –50 mV to 50 mV Fall time measured from 50 mV to –50 mV 1 ≤ Fs ≤ 125 MSPS 70 100 170 70 100 170 70 100 170 70 100 170 ps tCLKRISE tCLKFALL Rise time measured from –50 mV to 50 Output clock mV rise time Fall time measured Output clock from 50 mV to –50 fall time mV 1 ≤ Fs ≤ 125 MSPS 70 100 170 70 100 170 70 100 170 70 100 170 ps (1) (2) (3) (4) (5) (6) 8 7.5 ns Timing parameters are specified by design and characterization and not tested in production. CL is the effective external single-ended load capacitance between each output pin and ground. IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to logic high of +100 mV and logic low of –100 mV. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1) (continued) Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF(2), IO = 3.5 mA, RL = 100 Ω(3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. PARAMETER TEST CONDITIONS ADS62P45 FS = 125 MSPS MIN TYP MAX ADS62P44 FS = 105 MSPS MIN TYP ADS62P43 FS = 80 MSPS MAX PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength MIN TYP ADS62P42 FS = 65 MSPS MAX MIN TYP UNIT MAX (7) tsu Data setup time (5) Data valid (8) to 50% of CLKOUT rising edge 2.0 3.5 2.8 4.3 4.3 5.8 5.7 7.2 ns th Data hold time (5) 50% of CLKOUT rising edge to data becoming invalid (8) 2.0 3.5 2.7 4.2 4.2 5.7 5.6 7.1 ns tPDI Clock propagation delay Input clock rising edge zero-cross to 50% of CLKOUT rising edge 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 5.8 7.3 8.8 45% 53% 60% 45% 53% 60% 45% 53% 60% 45% 53% 60% Duty cycle of output Output clock clock (CLKOUT) duty cycle 10 ≤ Fs ≤ 125 MSPS 8.8 ns tr tf Data rise time Data fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1 ≤ Fs ≤ 125 MSPS 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns tCLKRISE tCLKFALL Rise time measured from 20% to 80% of Output clock DRVDD rise time Fall time measured Output clock from 80% to 20% of fall time DRVDD 1 ≤ Fs ≤ 125 MSPS 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns 3.6 ns PARALLEL CMOS INTERFACE, DRVDD = 1.8V, maximum buffer drive strength (9) tSTART Start time Input clock rising edge to data getting valid 8.5 7.5 5.5 (10) (11) Width of valid data window tDV 3.3 6.0 5.0 7.5 8.0 10.5 10.5 13.5 ns PARALLEL CMOS INTERFACE, DRVDD = 1.8V, MULTIPLEXED MODE, maximum buffer drive strength FS = 65 MSPS MIN tSTART_CHA Start time, channel A Input clock falling edge to channel A data getting valid (10) FS = 40 MSPS TYP MAX 0.8 2.3 MIN TYP MAX –4.5 –3 UNIT ns (11) tDV_CHA Data valid, channel A Width of valid data window tSTART_CHB Start time, channel B Input clock rising edge to channel B data getting valid (10) (11) tDV_CHB Data valid, channel B Width of valid data window 5.4 6.4 1.1 5 10.3 –4.1 2.4 6 11.3 9.7 ns –2.5 10.7 ns ns For DRVDD < 2.2 V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See Parallel CMOS interface in application section. (8) Data valid refers to logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V). (9) For DRVDD < 2.2 V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the desired setup & hold times at the receiving chip (10) Data valid refers to LOGIC HIGH of 1.26 V and LOGIC LOW of 0.54 V for DRVDD = 1.8 V (11) Measured from zero-crossing of input clock having 50% duty cycle (7) Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 9 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 2. Timing Characteristics at Lower Sampling Frequencies Sampling frequency, MSPS tsu DATA SETUP TIME, ns MIN TYP MAX tPDI CLOCK PROPAGATION DELAY, ns th DATA HOLD TIME, ns MIN TYP MAX MIN TYP MAX 5.8 7.3 8.8 3.5 5.5 7.5 CMOS INTERFACE, DRVDD = 2.5 V TO 3.6 V 40 10.5 12 10.3 11.8 20 23 24.5 23 24.5 LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V 10 40 8.5 10 1 2.3 20 21 22.5 1 2.3 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com N+4 N+3 N+2 N+16 N+15 N+1 Sample N N+14 Input Signal ta CLKM Input Clock CLKP CLKOUTM CLKOUTP tsu 14 Clock Cycles DDR LVDS Output Data DXP, DXM O E E O O E E O (1) E O E – Even Bits D0,D2,D4,D6,D8,D10,D12 O – Odd Bits D1,D3,D5,D7,D9,D11,D13 tPDI th O N–10 E E O N–9 E O O N N–1 E O N+1 E N+2 tPDI CLKOUT tsu Parallel CMOS 14 Clock Cycles Output Data D0–D13 (1) (1) th N–10 N–9 N N–1 N+1 N+2 Latency is 10 clock cycles in low-latency mode. Figure 1. Latency Input Clock CLKM CLKP tPDI Output Clock CLKOUTM CLKOUTP th tsu tsu Output Data Pair (1) (2) Dn Dn_Dn+1_P, Dn_Dn+1_M th Dn (1) Dn+1 (2) – Bits D0, D2, D4, D6, D8, D10, D12 Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13 T0106-04 Figure 2. LVDS Mode Timing Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 11 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com CLKM Input Clock clock CLKP t PDI PDI Output Clock clock CLKOUTCLKOUT t su su Output Data data DAn, DBn t hh Dn * Dn CLKM Input Clock clock CLKP t START PDI t DV su Output Data data DAn, DBn Dn * Dn *Dn - Bits D0, D1, D2, . . . of Channels A & B Figure 3. CMOS Mode Timing CLKM CLKP Input Clock clock CLKM CLKP t START_CHA PDI t START_CHB PDI t DV_CHB su t DV_CHA su Output Data data Pin DBn Dn * * *Dn - Bits D0, D1, D2, . . . Figure 4. Multiplexed Mode Timing (CMOS only) 12 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DEVICE CONFIGURATION ADS62P4X can be configured independently using either parallel interface control or serial interface programming. USING PARALLEL INTERFACE CONTROL ONLY To control the device using the parallel interface, keep RESET tied to high (AVDD). Pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC. After power-up, the device will automatically get configured as per the parallel pin voltage settings (Table 4 to Table 6). In this mode, SEN and SCLK function as parallel analog control pins, which can be configured using a simple resistor divider (Figure 5, using resistors DC TYP MAX UNIT 20 MHz fSCLK SCLK frequency tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDS SDATA setup time 25 ns tDH SDATA hold time 25 ns 16 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Register Address SDATA A7 A6 A5 A4 A3 A2 Register Data A1 A0 D7 D6 t(SCLK) D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-01 Figure 6. Serial Interface Timing Serial Register Readout (only when CMOS interface is used) The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. 1. First, set register bit = 1. This also disables any further writes into the registers. 2. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. 3. The device outputs the contents (D7-D0) of the selected register on the SDOUT pin. 4. The external controller can latch the contents at the falling edge of SCLK. 5. To enable register writes, reset register bit = 0. The serial register readout works only with CMOS interface; with LVDS interface, pin 56 functions as CLKOUTM. When is disabled, SDOUT pin is forced low or high by the device (and not put in high-impedance). If serial readout is not used, SDOUT pin must be floated. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 17 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com A) Enable serial read back ( = 1) (Serial register writes are disabled) R EGIST ER A DDR ESS (A7:A0) = 0x00 SDA TA 0 0 0 0 0 0 0 REGISTER DAT A (D7:D 0) = 0x01 0 0 0 0 0 0 0 0 1 SC LK SEN SDOUT Pin SD OU T is NOT in hig h-im ped ance state; it is forced low o r h ig h b y th e de vice ( = 0) B) Read contents of register 0x14. This register has been initialized with 0xB0 (over-ride bit set, LVDS interface, 3.5dB coarse gain, internal reference, normal operation) REGISTER ADD RESS (A 7:A 0) = 0x14 SDA TA A7 A6 A5 A4 A3 A2 A1 R EGIST ER D ATA (D 7:D 0) = XX (do n’ t care) A0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 0 0 0 0 SC LK SEN SDOUT Pin SDOUT fu nc tio ns as serial reado u t ( = 1) Figure 7. Serial Readout RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise noted. PARAMETER CONDITIONS MIN t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse width t3 Register write delay tPO Power-up time Delay from power-up of AVDD and DRVDD to output stable 18 TYP MAX UNIT 5 ms Pulse width of active RESET signal 10 ns Delay from RESET disable to SEN active 25 ns Submit Documentation Feedback 7 ms Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Power Supply AVDD, DRVDD t1 RESET t2 t3 SEN T0108-01 NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 8. Reset Timing Diagram Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 19 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com SERIAL REGISTER MAP Table 7. Summary of Functions Supported by Serial Interface REGISTER ADDRESS REGISTER FUNCTIONS A7–A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 Software Reset 0 0 0 0 0 0 10 LVDS buffer current double 0 0 12 0 0 13 0 0 0 0 14 Over-ride bit 0 LVDS or CMOS interface 3.5 dB gain Internal/External reference and MUX mode 16 0 0 0 2s complement or straight binary Bit/Byte wise (LVDS only) 17 0 0 0 0 19 0 0 1A 1B Offset correction enable 0 In-built or custom coefficients Enable digital filtering 1D 0 0 0 0 0 Internal termination programmability 0 0 0 0 to 6 dB gain in 0.5 dB steps Lower 8 bits Upper 6 bits Offset correction time constant 0 to 0.5 dB, steps of 0.05 dB Decimate by 2, 4, 8 0 12 coefficients, each 12 bit signed 1E to 2F 20 LVDS buffer current programmability 11 18 (1) (1) Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DESCRIPTION OF SERIAL REGISTERS Table 8. A7–A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 Software Reset D1 0 Software reset applied – resets all internal registers and self-clears to 0. D0 0 1 Serial readout disabled. SDOUT pin is forced low or high by the device ( and not put in high-impedance state) Serial readout enabled, SDOUT functions as serial data readout pin. Table 9. A7–A0 (hex) 10 D7–D6 01 00 11 10 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D1 D0 Output clock buffer drive strength control WEAKER than default drive DEFAULT drive strength STRONGER than default drive strength (recommended for load capacitances > 5 pF) MAXIMUM drive strength (recommended for load capacitances > 5 pF) Table 10. A7–A0 (hex) D7 D6 11 0 0 D5 D4 LVDS buffer current double D3 D2 LVDS CURRENT> LVDS buffer current programmability D1–D0 01 00 11 10 Output data buffer drive strength control WEAKER than default drive DEFAULT drive strength STRONGER than default drive strength (recommended for load capacitances > 5 pF) MAXIMUM drive strength (recommended for load capacitances > 5 pF) D3–D2 00 01 10 11 LVDS Current programmability 3.5 mA 2.5 mA 4.5 mA 1.75 mA D5–D4 00 01 10 11 CURRENT DOUBLE> LVDS Current double control Default current, set by LVDS clock buffer current is doubled, 2x LVDS data and clock buffers current are doubled, 2x Unused Copyright © 2007–2012, Texas Instruments Incorporated DATAOUT STRENGTH> Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 21 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 11. A7–A0 (hex) D7 D6 12 0 0 D5 D4 D3 D2 D1 D0 Internal termination programmability D5–D3 000 001 010 011 100 101 110 111 Internal termination control for data outputs No internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω D2–D0 000 001 010 011 100 101 110 111 Internal termination control for clock output No internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω Table 12. A7–A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0 13 0 0 0 0 0 0 0 D4 0 1 22 Offset correction becomes inactive and the last estimated offset value is used to cancel the offset Offset correction active Offset correction inactive Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 13. A7–A0 (hex) D7 D6 D5 D4 D3 14 Over-ride bit 0 LVDS or CMOS interface 3.5 dB gain Internal / External reference D2 D1 D0 D2-D0 000 001 010 011 100 101 110 111 Normal operation Channel A output buffer disabled Channel B output buffer disabled Channel A and B output buffers disabled Global power down Channel A standby Channel B standby Multiplexed mode, MUX – (only with CMOS interface) Channel A and B data is multiplexed and output on DB13 to DB0 pins. D3 0 1 Reference mode Internal reference enabled External reference enabled D4 0 1 Coarse gain control 0 dB coarse gain 3.5 dB coarse gain D5 0 1 Output interface selection Parallel CMOS data outputs DDR LVDS data outputs D7 Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins. By setting = 1, register bits LVDS and will over-ride the settings of the parallel pins. Disable over-ride Enable over-ride 0 1 Table 14. A7–A0 (hex) D7 D6 D5 D4 D3 16 0 0 0 DATA FORMAT> 2s complement or straight binary Bit / Byte wise (LVDS only) Copyright © 2007–2012, Texas Instruments Incorporated D2 D1 Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 D0 23 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com D2–D0 000 001 010 011 100 101 110 111 Test Patterns to verify capture Normal ADC operation Outputs all zeros Outputs all ones Outputs toggle pattern Outputs digital ramp Outputs custom pattern Unused Unused D3 0 1 Bit-wise/Byte-wise selection (DDR LVDS mode ONLY) Bit wise – even bits(D0,D2..D12) on CLOCKOUT rising edge, odd bits(D1,D3..D13) on CLOCKOUT falling edge Byte wise – lower 7 bits (D0,D1..D6) on CLOCKOUT rising edge, upper 7 bits(D7,D8..D13) on CLOCKOUT falling edge. D4 0 1 Data format selection 2s complement Straight binary 24 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 15. A7–A0 (hex) D7 D6 D5 D4 17 0 0 0 0 D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Others D3 D2 D1 D0 0 to 6 dB gain in 0.5 dB steps Gain programmability in 0.5 dB steps 0 dB gain, default after reset 0.5 dB gain 1.0 dB gain 1.5 dB gain 2.0 dB gain 2.5 dB gain 3.0 dB gain 3.5 dB gain 4.0 dB gain 4.5 dB gain 5.0 dB gain 5.5 dB gain 6.0 dB gain Unused Table 16. A7–A0 (hex) D7 D6 0 0 D4 D3 D2 D1 D0 Lower 8 bits 18 19 D5 Upper 6 bits D7-D0 8 lower bits of custom pattern available at the output instead of ADC data. D5-D0 6 upper bits of custom pattern available at the output instead of ADC data. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 25 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 17. A7–A0 (hex) D7 1A D6 D5 D4 D3 D2 Offset correction time constant D1 D0 0 to 0.5 dB, steps of 0.05 dB D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels) 0 dB gain, default after reset +0.5 dB gain +0.10 dB gain +0.15 dB gain +0.20 dB gain +0.25 dB gain +0.30 dB gain +0.35 dB gain +0.40 dB gain +0.45 dB gain +0.5 dB gain D6-D4 000 001 010 011 100 101 110 111 Time constant of offset correction in number of clock cycles (seconds, for sampling frequency = 125 MSPS) 227 (1.1 s) 226 (0.55 s) 225 (0.27 s) 224 (0.13 s) 228 (2.15 s) 229 (4.3 s) 227 (1.1 s) 227 (1.1 s) D7 0 1 Default latency, 14 clock cycles Low latency enabled, 10 clock cycles – Digital Processing Block is bypassed. Table 18. A7–A0 (hex) D7 1B Offset correction enable 26 D6 D5 D4 D3 0 In-built or custom coefficients Enable digital filtering Submit Documentation Feedback D2 D1 D0 Decimate by 2,4,8 Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com D2-D0 000 001 011 100 Decimation filters Decimate by 2 (pre-defined or user coefficients can be used) Decimate by 4 (pre-defined or user coefficients can be used) NO decimation (Pre-defined coefficients are disabled, only custom coefficients are available) Decimate by 8 (Only custom coefficients are available) D3 0 1 Even taps enabled (24 coefficients) 0 Odd taps enabled (23 coefficients) D4 0 1 Digital filter bypassed Digital filter enabled D5 0 1 Pre-defined coefficients are loaded in the filter User-defined coefficients are loaded in the filter (coefficients have to be loaded in registers – to - ) D7 0 1 Offset correction disabled Offset correction enabled Table 19. A7–A0 (hex) D7 D6 D5 D4 D3 D2 1D 0 0 0 0 0 0 00 01 10, 11 Decimation filters With decimate by 2, = 000: Low pass filter (–6 dB frequency at Fs/4) High pass filter (–6 dB frequency at Fs/4) Unused 00 01 10 11 With decimate by 4, = 001: Low pass filter (-3 dB frequency at Fs/8) Band pass filter (center frequency at 3Fs/16) Band pass filter (center frequency at 5Fs/16) High pass filter (-3 dB frequency at 3Fs/8) D1-D0 Copyright © 2007–2012, Texas Instruments Incorporated D1 D0 Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 27 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com PIN DESCRIPTION (CMOS INTERFACE) DRVDD DRGND DA8 DA9 DA10 DA11 DA12 DA13 SDOUT CLKOUT DRVDD DRGND DB0 DB1 DB2 DB3 DRGND RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 DRVDD 2 47 DA7 DB5 3 46 DA6 DB6 4 45 DA5 DB7 5 44 DA4 DB8 6 43 DA3 DB9 7 42 DA2 DB10 8 41 DA1 DB11 9 40 DA0 DB12 10 39 DRGND DB13 11 38 DRVDD RESET 12 37 CTRL3 SCLK 13 36 CTRL2 SDATA 14 35 CTRL1 SEN 15 34 AVDD 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AGND INP_A INM_A AGND AGND CLKM CLKP AGND VCM AGND AGND INP_B INM_B AGND AGND AVDD PAD (Connected to DRGND) AGND DB4 P0056-09 28 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (CMOS INTERFACE) PIN NAME DESCRIPTION AVDD Analog power supply AGND Analog ground CLKP, CLKM INM_A, INP_A PIN NUMBER NUMBER OF PINS 16, 33, 34 3 17, 18, 21, 22, 24, 27, 28, 31, 32 9 Differential input clock 25, 26 2 Differential input signal-Channel A. When not used, the analog input pins (INM_A, INP_A) MUST be tied to VCM and CANNOT be floated. 29, 30 2 INM_B, INP_B Differential input signal-Channel B. When not used, the analog input pins (INM_B, INP_B) MUST be tied to VCM and CANNOT be floated. 19, 20 2 VCM Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the ADC internal references. 23 1 RESET Serial interface RESET input. In serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset (refer to Serial Interface section). In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100-kΩ pull-down resistor. 12 1 SCLK This pin functions as serial interface clock input when RESET is low. It functions as analog control pin when RESET is tied high and controls coarse gain and internal/external reference selection. See Table 4 for details. The pin has an internal pull-down resistor to ground. 13 1 SDATA This pin functions as serial interface data input when RESET is low. The pin has an internal pull-down resistor to ground. 14 1 SEN This pin functions as serial interface enable input when RESET is low. It functions as analog control pin when RESET is tied high and controls the output interface (LVDS/CMOS) and data format selection. See Table 5 for details. The pin has an internal pull-up resistor to AVDD. 15 1 CTRL1 These are digital logic input pins. Together they control various power down and multiplexed mode. see Table 6 for details 35 1 36 1 CTRL2 CTRL3 37 1 DA0 to DA13 Channel A 14-bit data outputs, CMOS 40-47, 50-55 14 DB0 to DB13 Channel B 14-bit data outputs, CMOS 60-63, 2-11 14 CLKOUT CMOS Output clock 57 1 DRVDD Digital supply 1, 38, 48, 58 4 DRGND Digital ground 39, 49, 59, 64 and PAD 4 PAD Digital ground. Solder the bottom pad to the digital ground on the board using multiple vias for good electrical and thermal performance. – 1 SDOUT It functions as serial data readout pin ONLY when = 1. When = 0, SDOUT pin is forced low or high by the device (and not put in high-impedance state). If serial readout is not used, SDOUT pin has to be floated and should not be connected on the board. 56 1 Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 29 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com PIN DESCRIPTION (LVDS INTERFACE) DRGND DA8M DA8P DA10M DA10P DA12M DA12P CLKOUTM CLKOUTP DRVDD DRGND DB0M DB0P DB2M DB2P DRGND RGC PACKAGE (TOP VIEW) DRVDD DB4M 2 47 DA6P DB4P 3 46 DA6M DB6M 4 45 DA4P DB6P 5 44 DA4M DB8M 6 43 DA2P DB8P 7 42 DA2M DB10M 8 41 DA0P DB10P 9 40 DA0M DB12M 10 39 DRGND DB12P 11 38 DRVDD RESET 12 37 CTRL3 SCLK 13 36 CTRL2 SDATA 14 35 CTRL1 SEN 15 34 AVDD 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AGND INP_A INM_A AGND AGND CLKM CLKP AGND VCM AGND AGND INP_B INM_B AGND AGND AVDD PAD (Connected to DRGND) AGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 DRVDD P0056-10 Pin Assignments (LVDS INTERFACE) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS AVDD Analog power supply 16, 33, 34 3 AGND Analog ground 17, 18, 21, 22, 24, 27, 28, 31,32 9 CLKP, CLKM Differential input clock 25, 26 2 INM_A, INP_A Differential input signal-Channel A. When not used, the analog input pins (INM_A, INP_A) MUST be tied to VCM and CANNOT be floated. 29, 30 2 INM_B, INP_B Differential input signal-Channel B. When not used, the analog input pins (INM_B, INP_B) MUST be tied to VCM and CANNOT be floated. 19, 20 2 VCM Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the ADC internal references. 23 1 30 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (LVDS INTERFACE) (continued) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS RESET Serial interface RESET input. In serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset (refer to Serial Interface section). In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100-kΩ pull-down resistor. 12 1 SCLK This pin functions as serial interface clock input when RESET is low. It functions as analog control pin when RESET is tied high and controls coarse gain and internal/external reference selection. See Table 4 for details. The pin has an internal pull-down resistor to ground. 13 1 SDATA This pin functions as serial interface data input when RESET is low. The pin has an internal pull-down resistor to ground. 14 1 SEN This pin functions as serial interface enable input when RESET is low. It functions as analog control pin when RESET is tied high and controls the output interface (LVDS/CMOS) and data format selection. See Table 5 for details. The pin has an internal pull-up resistor to AVDD. 15 1 CTRL1 These are digital logic input pins. Together they control various power down and multiplexed mode. See Table 6 for details. 35 1 36 1 37 1 CTRL2 CTRL3 DA0P Channel A Differential output data D0 and D1 multiplexed, true 41 1 DA0M Channel A Differential output data D0 and D1 multiplexed, complement 40 1 DA2P Channel A Differential output data D2 and D3 multiplexed, true 43 1 DA2M Channel A Differential output data D2 and D3 multiplexed, complement 42 1 DA4P Channel A Differential output data D4 and D5 multiplexed, true 45 1 DA4M Channel A Differential output data D4 and D5 multiplexed, complement 44 1 DA6P Channel A Differential output data D6 and D7 multiplexed, true 47 1 DA6M Channel A Differential output data D6 and D7 multiplexed, complement 46 1 DA8P Channel A Differential output data D8 and D9 multiplexed, true 51 1 DA8M Channel A Differential output data D8 and D9 multiplexed, complement 50 1 DA10P Channel A Differential output data D10 and D11 multiplexed, true 53 1 DA10M Channel A Differential output data D10 and D11 multiplexed, complement 52 1 DA12P Channel A Differential output data D12 and D13 multiplexed, true 55 1 DA12M Channel A Differential output data D12 and D13 multiplexed, complement 54 1 CLKOUTP Differential output clock, true 57 1 CLKOUTM Differential output clock, complement 56 1 DB0P Channel B Differential output data D0 and D1 multiplexed, true 61 1 DB0M Channel B Differential output data D0 and D1 multiplexed, complement 60 1 DB2P Channel B Differential output data D2 and D3 multiplexed, true 63 1 DB2M Channel B Differential output data D2 and D3 multiplexed, complement 62 1 DB4P Channel B Differential output data D4 and D5 multiplexed, true 3 1 DB4M Channel B Differential output data D4 and D5 multiplexed, complement 2 1 DB6P Channel B Differential output data D6 and D7 multiplexed, true 5 1 DB6M Channel B Differential output data D6 and D7 multiplexed, complement 4 1 DB8P Channel B Differential output data D8 and D9 multiplexed, true 7 1 DB8M Channel B Differential output data D8 and D9 multiplexed, complement 6 1 DB10P Channel B Differential output data D10 and D11 multiplexed, true 9 1 DB10M Channel B Differential output data D10 and D11 multiplexed, complement 8 1 DB12P Channel B Differential output data D12 and D13 multiplexed, true 11 1 DB12M Channel B Differential output data D12 and D13 multiplexed, complement 10 1 Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 31 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (LVDS INTERFACE) (continued) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS DRVDD Digital supply 1, 38, 48, 58 4 DRGND Digital ground 39, 49, 59, 64 and PAD 4 PAD Digital ground. Solder the bottom pad to the digital ground on the board using multiple vias for good electrical and thermal performance. – 1 32 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.2 dBc SINAD = 73.7 dBFS SNR = 73.8 dBFS THD = 88.2 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 60 f − Frequency − MHz 0 10 20 30 40 50 60 f − Frequency − MHz G001 G002 Figure 9. Figure 10. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 0 SFDR = 78.9 dBc SINAD = 71.2 dBFS SNR = 72.1 dBFS THD = 77.3 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –89 dBFS SFDR = –96 dBFS −20 −40 Amplitude − dB −40 Amplitude − dB SFDR = 86.6 dBc SINAD = 73.4 dBFS SNR = 73.7 dBFS THD = 85.4 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 60 f − Frequency − MHz 0 10 20 30 40 50 60 f − Frequency − MHz G003 Figure 11. G004 Figure 12. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 76 94 92 Gain = 3.5 dB 75 88 SNR − dBFS SFDR − dBc 90 86 84 Gain = 0 dB 74 73 72 82 80 Gain = 3.5 dB Gain = 0 dB 71 78 76 70 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 13. Copyright © 2007–2012, Texas Instruments Incorporated 175 200 G005 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz G006 Figure 14. Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 33 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAINS 94 96 92 94 Gain = 3.5 dB 90 92 86 84 4 dB 86 84 82 Gain = 0 dB 78 80 76 1 dB 6 dB 0 dB 78 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz 0 25 50 G007 Figure 15. 100 SINAD vs INPUT FREQUENCY ACROSS GAINS 0 dB 175 200 G009 PERFORMANCE vs AVDD 1 dB 89 2 dB 73 3 dB 80 fIN = 70.1 MHz DRVDD = 3.31 V 79 SFDR 88 SFDR − dBc 72 71 70 69 77 86 76 85 75 SNR 84 67 4 dB 5 dB 66 6 dB 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 82 3.0 200 73 3.1 3.2 PERFORMANCE vs DRVDD fIN = 70.1 MHz AVDD = 3.31 V G011 88 79 78 87 77 SFDR SFDR 87 77 86 76 85 75 SFDR − dBc 78 SNR − dBFS 88 86 76 85 75 84 74 SNR 74 SNR 83 83 73 3.3 72 3.6 3.5 PERFORMANCE vs TEMPERATURE 80 3.2 3.4 Figure 18. 90 84 3.3 AVDD − Supply Voltage − V G010 Figure 17. 3.1 74 83 Input adjusted to get −1dBFS input 65 78 87 68 SFDR − dBc 150 90 74 3.4 DRVDD − Supply Voltage − V Figure 19. 34 125 Figure 16. 75 SINAD − dBFS 75 fIN − Input Frequency − MHz SNR − dBFS 0 SNR − dBFS 80 82 3.0 5 dB 88 82 89 3 dB 2 dB 90 SFDR − dBc 88 SFDR − dBc Input adjusted to get −1dBFS input Submit Documentation Feedback 3.5 73 fIN = 70.1 MHz 72 3.6 82 −40 G012 72 −20 0 20 40 T − Temperature − °C 60 80 G013 Figure 20. Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE 110 SFDR (dBFS) 100 90 94 85 92 80 fIN = 20.1 MHz 79 75 SNR (dBFS) 70 70 60 65 78 88 77 86 76 84 75 SNR 50 SFDR (dBc) 40 fIN = 20.1 MHz −50 −40 −30 −20 −10 60 82 74 55 80 73 50 78 0.5 0 Input Amplitude − dBFS 2.0 2.5 PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM (INPUTS TIED TO COMMON-MODE) 90 SFDR 88 79 40 78 35 77 30 76 86 75 84 74 SNR 15 80 72 10 78 71 5 70 0 40 45 50 55 60 65 70 Input Clock Duty Cycle − % RMS = 1.033 LSB 20 73 35 G015 25 82 76 72 3.0 Input Clock Amplitude − VPP Figure 22. fIN = 20.1 MHz 30 1.5 Figure 21. 94 92 1.0 G014 Occurence − % 30 −60 SFDR − dBc 90 SNR − dBFS 80 SFDR − dBc 80 SNR − dBFS 90 SNR − dBFS SFDR − dBc, dBFS SFDR 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 Output Code G016 Figure 23. G017 Figure 24. PERFORMANCE IN EXTERNAL REFERENCE MODE 93 80 fIN = 20.1 MHz External Reference Mode 78 SFDR 89 76 87 74 SNR 85 83 1.30 SNR − dBFS SFDR − dBc 91 72 1.35 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V 1.60 1.65 70 1.70 G018 Figure 25. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 35 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.26 dBc SINAD = 73.81 dBFS SNR = 73.94 dBFS THD = 88 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 f − Frequency − MHz 0 10 20 40 50 G020 Figure 26. Figure 27. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 82.36 dBc SINAD = 71.57 dBFS SNR = 72.09 dBFS THD = 80.05 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –87 dBFS SFDR = –90 dBFS −20 −40 Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 f − Frequency − MHz 0 10 20 30 40 50 f − Frequency − MHz G021 Figure 28. G022 Figure 29. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 96 76 Gain = 3.5 dB 94 75 92 Gain = 0 dB 90 SNR − dBFS SFDR − dBc 30 f − Frequency − MHz G019 0 Amplitude − dB SFDR = 84.45 dBc SINAD = 73.45 dBFS SNR = 73.8 dBFS THD = 83.4 dBc −20 88 86 84 74 73 72 82 80 Gain = 0 dB Gain = 3.5 dB 71 78 76 70 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 30. 36 Submit Documentation Feedback 175 200 G023 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 G024 Figure 31. Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAINS 96 96 94 94 Gain = 3.5 dB 92 86 84 88 86 84 Gain = 0 dB 78 80 76 78 0 25 50 75 100 4 dB 82 80 125 150 175 200 fIN − Input Frequency − MHz 6 dB 1 dB 0 dB 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz G025 Figure 32. G027 Figure 33. SINAD vs INPUT FREQUENCY ACROSS GAINS PERFORMANCE vs AVDD 88 76 Input adjusted to get −1dBFS input 0 dB 75 87 1 dB 74 2 dB 79 SFDR 86 3 dB SFDR − dBc 73 80 fIN = 70.1 MHz DRVDD = 3.31 V 72 71 70 69 78 85 77 84 76 83 75 SNR 82 74 81 73 SNR − dBFS 82 SINAD − dBFS 3 dB 90 SFDR − dBc 88 2 dB 5 dB 92 90 SFDR − dBc Input adjusted to get −1dBFS input 68 5 dB 6 dB 66 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 80 3.0 200 3.1 3.2 PERFORMANCE vs DRVDD fIN = 70.1 MHz AVDD = 3.31 V 78 88 77 SFDR 87 77 SFDR 86 76 85 75 SNR 84 74 83 73 3.3 3.4 DRVDD − Supply Voltage − V Figure 36. Copyright © 2007–2012, Texas Instruments Incorporated 3.5 SFDR − dBc 78 SNR − dBFS SFDR − dBc 90 79 88 3.2 G029 PERFORMANCE vs TEMPERATURE 80 3.1 72 3.6 3.5 Figure 35. 90 82 3.0 3.4 AVDD − Supply Voltage − V G028 Figure 34. 89 3.3 86 76 84 75 SNR 82 74 80 SNR − dBFS 4 dB 67 73 fIN = 70.1 MHz 72 3.6 78 −40 G030 72 −20 0 20 40 60 80 T − Temperature − °C G031 Figure 37. Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 37 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE 110 90 94 85 92 80 SFDR (dBFS) 100 fIN = 20.1 MHz 79 75 SNR (dBFS) 70 70 60 65 50 SFDR (dBc) 40 fIN = 20.1 MHz 30 −60 −50 −40 −30 −20 −10 88 77 86 76 84 74 55 80 73 50 78 0.0 0.5 1.0 1.5 2.0 2.5 Figure 38. Figure 39. PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 79 40 78 35 90 77 88 76 86 75 SNR 84 74 20 15 73 80 72 10 78 71 5 70 0 30 35 40 45 50 55 60 65 70 75 Input Clock Duty Cycle − % RMS = 1.006 LSB 25 82 76 G033 30 Occurence − % SFDR 72 3.0 Input Clock Amplitude − VPP G032 fIN = 20.1 MHz 25 75 SNR 82 0 94 SFDR − dBc 78 60 Input Amplitude − dBFS 92 90 SNR − dBFS 80 SFDR − dBc 80 SNR − dBFS 90 SNR − dBFS SFDR − dBc, dBFS SFDR 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 Output Code G034 Figure 40. G035 Figure 41. 80 92 78 SFDR 88 76 SNR 84 74 80 SNR − dBFS SFDR − dBc PERFORMANCE IN EXTERNAL REFERENCE MODE 96 72 fIN = 20.1 MHz External Reference Mode 76 1.30 1.35 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V 1.60 1.65 70 1.70 G036 Figure 42. 38 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 89 dBc SINAD = 74.15 dBFS SNR = 74.55 dBFS THD = 83.74 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 f − Frequency − MHz 0 10 20 30 40 f − Frequency − MHz G037 G038 Figure 43. Figure 44. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 0 SFDR = 84.34 dBc SINAD = 72.39 dBFS SNR = 72.76 dBFS THD = 82.19 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = −93 dBFS SFDR = −98 dBFS −20 −40 Amplitude − dB −40 Amplitude − dB SFDR = 89.82 dBc SINAD = 74.02 dBFS SNR = 74.13 dBFS THD = 88.99 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 f − Frequency − MHz 0 10 20 30 40 f − Frequency − MHz G039 Figure 45. G040 Figure 46. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 76 98 96 75 Gain = 0 dB Gain = 3.5 dB 92 SNR − dBFS SFDR − dBc 94 90 88 74 73 Gain = 3.5 dB 72 86 Gain = 0 dB 84 71 82 80 70 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 47. Copyright © 2007–2012, Texas Instruments Incorporated 175 200 G041 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz G042 Figure 48. Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 39 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAINS 98 98 96 96 94 Input adjusted to get −1dBFS input 4 dB 94 5 dB 3 dB Gain = 3.5 dB 92 SFDR − dBc SFDR − dBc 92 90 88 90 88 86 86 Gain = 0 dB 84 6 dB 84 82 82 80 80 1 dB 2 dB 0 dB 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz G043 Figure 49. G045 Figure 50. SINAD vs INPUT FREQUENCY ACROSS GAINS PERFORMANCE vs AVDD 91 76 0 dB 75 1 dB 90 2 dB 74 3 dB 80 fIN = 70.1 MHz DRVDD = 3.3 V 79 89 78 72 71 70 SFDR 88 77 87 76 86 75 SNR 69 85 74 84 73 SNR − dBFS SFDR − dBc SINAD − dBFS 73 68 4 dB 67 5 dB 6 dB Input adjusted to get −1dBFS input 83 3.0 66 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 3.1 3.2 3.3 PERFORMANCE vs DRVDD PERFORMANCE vs TEMPERATURE 80 fIN = 70.1 MHz AVDD = 3.31 V 79 92 78 90 77 77 88 76 87 75 SNR 86 74 85 73 84 3.0 3.1 3.2 3.3 3.4 DRVDD − Supply Voltage − V Figure 53. Submit Documentation Feedback 3.5 SFDR 88 76 86 75 SNR 84 74 82 SNR − dBFS SFDR 89 SFDR − dBc 78 SNR − dBFS 90 SFDR − dBc G047 Figure 52. 92 40 72 3.6 3.5 AVDD − Supply Voltage − V G046 Figure 51. 91 3.4 73 fIN = 70.1 MHz 72 3.6 80 −40 G048 72 −20 0 20 40 T − Temperature − °C 60 80 G049 Figure 54. Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE 90 94 100 85 92 90 80 90 79 78 77 88 76 86 75 70 70 60 65 50 60 82 73 55 80 72 50 78 0.0 SFDR (dBc) 40 fIN = 20.1 MHz 30 −60 −50 −40 −30 −20 −10 0.5 1.0 1.5 2.0 2.5 Figure 56. PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE SFDR 79 40 78 35 77 88 76 86 75 SNR 84 74 20 15 73 80 72 10 78 71 5 70 0 30 35 40 45 50 55 60 65 70 75 Input Clock Duty Cycle − % RMS = 1.019 LSB 25 82 76 G051 30 Occurence − % 90 71 3.0 Input Clock Amplitude − VPP G050 fIN = 20.1 MHz 25 74 SNR Figure 55. 94 92 84 0 Input Amplitude − dBFS SFDR − dBc fIN = 20.1 MHz SFDR SFDR − dBc 75 SNR (dBFS) SNR − dBFS 80 SNR − dBFS SFDR − dBc, dBFS SFDR (dBFS) SNR − dBFS 110 8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 Output Code G052 Figure 57. G053 Figure 58. PERFORMANCE IN EXTERNAL REFERENCE MODE 92 80 fIN = 20.1 MHz External Reference Mode 78 SFDR 88 76 86 74 SNR − dBFS SFDR − dBc 90 SNR 84 82 1.35 72 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V 1.60 70 1.65 G054 Figure 59. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 41 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.5 dBc SINAD = 74.35 dBFS SNR = 74.56 dBFS THD = 86.5 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 f − Frequency − MHz 0 10 20 G056 Figure 60. Figure 61. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 89.9 dBc SINAD = 71.51 dBFS SNR = 71.88 dBFS THD = 81.32 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = 92 dBFS SFDR = 95 dBFS −20 −40 Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 f − Frequency − MHz 0 10 20 30 f − Frequency − MHz G057 Figure 62. G058 Figure 63. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 96 76 Gain = 3.5 dB 94 75 92 90 SNR − dBFS SFDR − dBc 30 f − Frequency − MHz G055 0 Amplitude − dB SFDR = 88.18 dBc SINAD = 74.13 dBFS SNR = 74.28 dBFS THD = 87.89 dBc −20 88 86 84 Gain = 0 dB 74 73 Gain = 3.5 dB 72 82 80 Gain = 0 dB 71 78 76 70 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 64. 42 Submit Documentation Feedback 175 200 G059 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 G060 Figure 65. Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAINS 96 98 94 96 Gain = 3.5 dB 94 88 86 84 3 dB 90 88 86 82 80 78 82 76 80 25 50 75 100 6 dB 84 Gain = 0 dB 0 125 150 175 200 fIN − Input Frequency − MHz 0 dB 2 dB 1 dB 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz G061 Figure 66. G063 Figure 67. SINAD vs INPUT FREQUENCY ACROSS GAINS PERFORMANCE vs AVDD 91 76 0 dB 75 90 1 dB 74 2 dB 3 dB 80 fIN = 70.1 MHz DRVDD = 3.3 V 79 89 SFDR − dBc 72 71 70 69 78 SFDR 73 SINAD − dBFS 4 dB 5 dB 92 SFDR − dBc SFDR − dBc 90 88 77 87 76 86 75 SNR 85 74 84 73 SNR − dBFS 92 Input adjusted to get −1dBFS input 68 6 dB Input adjusted to get −1dBFS input 5 dB 83 3.0 66 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 3.1 3.2 PERFORMANCE vs DRVDD fIN = 70.1 MHz AVDD = 3.31 V 90 89 76 88 75 SNR 87 74 86 73 3.3 77 SFDR 3.4 DRVDD − Supply Voltage − V Figure 70. Copyright © 2007–2012, Texas Instruments Incorporated 3.5 SFDR − dBc 77 3.2 78 78 SNR − dBFS SFDR − dBc 92 79 SFDR 3.1 G065 PERFORMANCE vs TEMPERATURE 80 90 85 3.0 72 3.6 3.5 Figure 69. 93 91 3.4 AVDD − Supply Voltage − V G064 Figure 68. 92 3.3 88 76 86 75 SNR 84 74 82 SNR − dBFS 4 dB 67 73 fIN = 70.1 MHz 72 3.6 80 −40 G066 72 −20 0 20 40 60 80 T − Temperature − °C G067 Figure 71. Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 43 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE 110 100 90 94 85 92 77 76 SFDR 75 SNR (dBFS) 70 70 60 65 50 SFDR (dBc) 40 −50 −40 −30 −20 73 72 60 82 71 55 80 70 78 0.0 0 0.5 1.0 1.5 2.0 2.5 Figure 72. Figure 73. PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 79 40 78 35 77 SFDR 94 76 92 75 SNR 90 74 20 15 73 86 72 10 84 71 5 70 0 30 35 40 45 50 55 60 65 70 75 Input Clock Duty Cycle − % RMS = 1.025 LSB 25 88 82 G069 30 Occurence − % 96 69 3.0 Input Clock Amplitude − VPP G068 fIN = 20.1 MHz 25 74 SNR 84 50 −10 100 SFDR − dBc 88 86 Input Amplitude − dBFS 98 75 fIN = 20.1 MHz fIN = 20.1 MHz 30 −60 SFDR − dBc 80 90 SNR − dBFS 80 SNR − dBFS 90 SNR − dBFS SFDR − dBc, dBFS SFDR (dBFS) 8175 8176 8177 8178 8179 8180 8181 8182 8183 Output Code G070 Figure 74. G071 Figure 75. PERFORMANCE IN EXTERNAL REFERENCE MODE 95 80 fIN = 20.1 MHz External Reference Mode 93 78 91 76 89 74 SNR − dBFS SFDR − dBc SFDR SNR 87 85 1.30 72 1.35 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V 1.60 1.65 70 1.70 G072 Figure 76. 44 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS – LOW SAMPLING FREQUENCIES All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FS = 25 MSPS SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 100 80 78 95 76 90 SNR − dBFS SFDR − dBc Gain = 3.5 dB 85 Gain = 0 dB 80 Gain = 0 dB 74 72 Gain = 3.5 dB 70 75 68 70 66 0 25 50 75 100 125 150 175 fIN − Input Frequency − MHz 200 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz G075 G076 Figure 77. Figure 78. COMMON-MODE REJECTION RATIO vs FREQUENCY POWER DISSIPATION vs SAMPLING FREQUENCY (DDR LVDS and CMOS) COMMON PLOTS 1.0 −10 0.9 PD − Power Dissipation − W 0 −20 CMRR − dBc −30 −40 −50 −60 −70 −80 fIN = 2.5 MHz CL = 5 pF 0.8 LVDS 0.7 0.6 0.5 CMOS 0.4 0.3 0.2 0.1 −90 0.0 −100 0 25 50 75 100 125 150 f − Frequency − MHz Figure 79. Copyright © 2007–2012, Texas Instruments Incorporated 175 200 G077 0 25 50 75 100 125 fS − Sampling Frequency − MSPS G078 Figure 80. Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 45 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS – LOW SAMPLING FREQUENCIES (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) DRVDD current (CMOS) vs SAMPLING FREQUENCY across load capacitance at 2 MHz input frequency 60 3.3 V, No Load 1.8 V, 5 pF DRVDD Current − mA 50 1.8 V, 10 pF 40 3.3 V, 5 pF 30 3.3 V, 10 pF 20 10 1.8 V, No Load 0 0 25 50 75 100 fS − Sampling Frequency − MSPS 125 G079 Figure 81. 46 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ADS62P4X is a low power 14-bit dual channel pipeline ADC family fabricated in a CMOS process using switched capacitor techniques. The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline resulting in a data latency of 14 clock cycles. The output is available as 14-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary 2s complement format. ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology results in very good AC performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2 VPP differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal). Sampling Switch Lpkg » 2 nH Sampling Capacitor RCR Filter INP Cbond » 1 pF 25 W Resr 100 W Cpar2 1 pF 50 W 3.2 pF Ron 15 W Cpar1 0.8 pF Csamp 4 pF Ron 10 W 50 W Lpkg » 2 nH Ron 15 W 25 W Csamp 4 pF INM Cbond » 1 pF Resr 100 W Sampling Capacitor Cpar2 1 pF Sampling Switch S0322-01 Figure 82. Analog Input Equivalent Circuit The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins to the sampled voltage). Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 47 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com 1 0 Magnitude − dB −1 −2 −3 −4 −5 −6 −7 0 100 200 300 400 500 fI − Input Frequency − MHz 600 G080 Figure 83. ADC Analog Bandwidth Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. It is also necessary to present low impedance (50 Ω) for the common mode switching currents. This can be achieved by using two resistors from each input terminated to the common mode voltage (VCM). In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure 84 and Figure 85 show the impedance (Zin = Rin || Cin) looking into the ADC input pins. R − Resistance − kΩ 100 10 1 0.1 0.01 0 100 200 300 400 f − Frequency − MHz 500 600 G081 Figure 84. ADC Analog Input Resistance (Rin) Across Frequency 48 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com 9 C − Capacitance − pF 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 f − Frequency − MHz 600 G082 Figure 85. ADC Analog Input Capacitance (Cin) Across Frequency Using RF-Transformer Based Drive Circuits Figure 86 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can be used for low input frequencies (about 100 MHz). The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5-V common mode (VCM). The value of the termination resistors (connected to common mode) has to be low (