ADS7128IRTET

Order Now Product Folder Support & Community Tools & Software Technical Documents ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 ADS7128 Small, 8-Channel, 12-Bit ADC With I2C Interface, GPIOs, and CRC 1 Features 2 Applications • • • • • 1 • • • • • • • • • Small package size: – 3-mm × 3-mm WQFN 8 channels configurable as any combination of: – Up to 8 analog inputs, digital inputs, or digital outputs GPIOs for I/O expansion: – Open-drain, push-pull digital outputs Analog watchdog: – Programmable thresholds per channel – Event counter for transient rejection Wide operating ranges: – AVDD: 2.35 V to 5.5 V – DVDD: 1.65 V to 5.5 V – –40°C to +85°C temperature range CRC for read/write operations: – CRC on data read/write – CRC on power-up configuration I2C interface: – Up to 3.4 MHz (high-speed mode) – 8 configurable I2C addresses Programmable averaging filters Root-mean-square module: – 16-bit true RMS output – Programmable RMS time window Zero-crossing-detect module: – ZCD output corresponding to any analog input – Built-in transient rejection and hysteresis – Digitally adjustable detection threshold Mobile robot CPU boards Refrigerators and freezers Digital multimeters (DMM) Rack servers 3 Description The ADS7128 is an easy-to-use, 8-channel, multiplexed, 12-bit, successive approximation register analog-to-digital converter (SAR ADC). The eight channels can be independently configured as either analog inputs, digital inputs, or digital outputs. The device has an internal oscillator for ADC conversion processes. The ADS7128 communicates via an I2C-compatible interface and operates in either autonomous or single-shot conversion mode. The ADS7128 implements analog watchdog function by eventtriggered interrupts per channel using a digital window comparator with programmable high and low thresholds, hysteresis, and an event counter. The ADS7128 has a built-in cyclic redundancy check (CRC) for data read/write operations and the powerup configuration. The ADS7128 features a root-meansquare (RMS) module that computes a 16-bit true RMS result for any analog input channel. The integrated zero-crossing-detect (ZCD) module allows for transient rejection and hysteresis near the configurable threshold crossings. Device Information(1) PART NAME ADS7128 PACKAGE BODY SIZE (NOM) WQFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. ADS7128 Block Diagram and Applications Example System Architecture Device Block Diagram DECAP AVDD VCC DVDD AIN0 / GPIO0 AIN1 / GPIO1 ADC Digital Window Comparator AIN3 / GPIO3 AIN4 / GPIO4 AIN5 / GPIO5 AIN6 / GPIO6 AIN7 / GPIO7 MUX ADDR Sequencer I2C Interface GPO Write RMS Module GPI Read ZCD Module ADC GPIO MUX Pin CFG OVP ALERT Programmable Averaging Filter AIN2 / GPIO2 LOAD AVDD High/Low Threshold ± Hysteresis OCP SDA SCL CRC GND OVP: Over voltage protection OCP: Over current protection 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 5 5 5 5 6 7 7 7 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... I2C Timing Requirements.......................................... Timing Requirements ................................................ I2C Switching Characteristics.................................... Switching Characteristics .......................................... Typical Characteristics ............................................ Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming........................................................... ADS7128 Registers................................................. 14 24 27 30 Application and Implementation ........................ 74 9.1 Application Information............................................ 74 9.2 Typical Applications ................................................ 74 10 Power Supply Recommendations ..................... 77 10.1 AVDD and DVDD Supply Recommendations....... 77 11 Layout................................................................... 78 11.1 Layout Guidelines ................................................. 78 11.2 Layout Example .................................................... 78 12 Device and Documentation Support ................. 79 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 79 79 79 79 79 13 Mechanical, Packaging, and Orderable Information ........................................................... 79 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2019) to Revision A • 2 Page Changed document status from advance information to production data ............................................................................. 1 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 5 Device Comparison Table PART NUMBER DESCRIPTION ADS7128 ADS7138 8-channel, 12-bit ADC with I2C interface and GPIOs ADS7138-Q1 CRC MODULE ZERO-CROSSING-DETECT (ZCD) MODULE ROOT-MEAN-SQUARE (RMS) MODULE Yes Yes Yes Yes No No Yes No No Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 3 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 6 Pin Configuration and Functions AIN2/GPIO2 1 AIN3/GPIO3 2 AIN1/GPIO1 AIN0/GPIO0 SDA SCL 16 15 14 13 RTE Package 16-Pin WQFN Top View 12 ALERT 11 ADDR 10 DVDD Thermal 7 8 AVDD DECAP 9 6 4 AIN7/GPIO7 AIN5/GPIO5 Pad 5 3 AIN6/GPIO6 AIN4/GPIO4 GND Not to scale Pin Functions PIN NAME NO. FUNCTION (1) DESCRIPTION AIN0/GPIO0 15 AI, DI, DO Channel 0; configurable as either an analog input (default) or a general-purpose input/output (GPIO) AIN1/GPIO1 16 AI, DI, DO Channel 1; configurable as either an analog input (default) or a GPIO AIN2/GPIO2 1 AI, DI, DO Channel 2; configurable as either an analog input (default) or a GPIO AIN3/GPIO3 2 AI, DI, DO Channel 3; configurable as either an analog input (default) or a GPIO AIN4/GPIO4 3 AI, DI, DO Channel 4; configurable as either an analog input (default) or a GPIO AIN5/GPIO5 4 AI, DI, DO Channel 5; configurable as either an analog input (default) or a GPIO AIN6/GPIO6 5 AI, DI, DO Channel 6; configurable as either an analog input (default) or a GPIO AIN7/GPIO7 6 AI, DI, DO Channel 7; configurable as either an analog input (default) or a GPIO ADDR 11 AI ALERT 12 Digital output AVDD 7 Supply Analog supply input, also used as the reference voltage to the ADC; connect a 1-µF decoupling capacitor to GND DECAP 8 Supply Connect a1-µF decoupling capacitor between the DECAP and GND pins for the internal power supply DVDD 10 Supply Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND GND 9 Supply Ground for the power supply; all analog and digital signals are referred to this pin voltage SDA 14 DI, DO Serial data input or output for the I2C interface SCL 13 DI Thermal pad — Supply (1) 4 Input for selecting the device I2C address. Connect a resistor to this pin from DECAP pin or GND to select one of the eight addresses. Open-drain (default) or push-pull output for the digital comparator Serial clock for the I2C interface Exposed thermal pad; connect to GND. AI = analog input, DI = digital input, and DO = digital output. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 7 Specifications 7.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted) (1) DVDD to GND AVDD to GND MIN MAX –0.3 5.5 UNIT V –0.3 5.5 V AINx/GPOx (2) GND – 0.3 AVDD + 0.3 V ADDR GND – 0.3 2.1 V Digital inputs GND – 0.3 5.5 V Current through any pin except supply pins (3) –10 10 mA Junction temperature, TJ –40 125 °C Storage temperature, Tstg –60 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. AINx/GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16. Pin current must be limited to 10mA or less. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD Analog supply voltage 2.35 3.3 5.5 V DVDD Digital supply voltage 1.65 3.3 5.5 V 0 AVDD V –0.1 AVDD + 0.1 V 85 ℃ ANALOG INPUTS FSR Full-scale input range AINX (1) - GND VIN Absolute input voltage AINX - GND TEMPERATURE RANGE TA (1) Ambient temperature –40 25 AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7. 7.4 Thermal Information ADS7128 THERMAL METRIC (1) RTE (WQFN) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 49.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 53.4 °C/W RθJB Junction-to-board thermal resistance 24.7 °C/W ΨJT Junction-to-top characterization parameter 1.3 °C/W ΨJB Junction-to-board characterization parameter 24.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 9.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 5 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 7.5 Electrical Characteristics at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS CSH Sampling capacitance 12 pF DC PERFORMANCE Resolution No missing codes DNL Differential nonlinearity INL Integral nonlinearity V(OS) Input offset error Post offset calibration Input offset thermal drift Post offset calibration GE Gain error 12 bits –0.75 ±0.45 0.75 LSB –1.5 ±0.5 1.5 LSB –2 ±0.3 2 ±1 –0.065 Gain error thermal drift ±0.05 LSB ppm/°C 0.065 ±1 %FSR ppm/°C AC PERFORMANCE SINAD Signal-to-noise + distortion ratio SNR Signal-to-noise ratio Crosstalk AVDD = 5 V, fIN = 2 kHz 70 72.8 AVDD = 3 V, fIN = 2 kHz 69.8 72.4 AVDD = 5 V, fIN = 2 kHz 71.2 73 AVDD = 3 V, fIN = 2 kHz 70.5 72.5 100-kHz signal applied on any OFF channel and measured on the ON channel dB dB –100 dB DECAP Pin CDECAP Decoupling capacitor on DECAP pin Voltage output on DECAP pin 0.1 CDECAP = 1 µF 1 4.7 1.8 µF V DIGITAL INPUT/OUTPUT (SCL, SDA) VIH Input high logic level All I2C modes 0.7 x DVDD 5.5 V VIL Input low logic level All I2C modes –0.3 0.3 x DVDD V VOL Output low logic level IOL Low-level output current (sink) Sink current = 2 mA, DVDD > 2 V 0 0.4 Sink current = 2 mA, DVDD ≤ 2 V 0 0.2 x DVDD VOL = 0.4 V, standard and fast mode 3 VOL = 0.6 V, fast mode 6 VOL = 0.4 V, fast mode plus V mA 20 GPIOs VIH Input high logic level VIL Input low logic level 0.7 x AVDD AVDD + 0.3 –0.3 0.3 x AVDD V 100 nA 0.8 x AVDD AVDD V 0 0.2 x AVDD 10 V Input leakge current GPIO configured as input VOH Output high logic level GPO_DRIVE_CFG = push-pull, ISOURCE = 2 mA VOL Output low logic level ISINK = 2 mA IOH Output high source current VOH > 0.7 x AVDD 5 mA IOL Output low sink current VOL < 0.3 x AVDD 5 mA V DIGITAL OUTPUT (ALERT) VOH Output high logic level GPO_DRIVE_CFG = push-pull, ISOURCE = 2 mA VOL Output low logic level ISINK = 2 mA IOH Output high sink current VOH > 0.7 x DVDD 5 mA IOL Output low sink current VOL < 0.3 x DVDD 5 mA 0.8 x DVDD DVDD 0 0.2 x DVDD V V POWER SUPPLY CURRENTS 6 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Electrical Characteristics (continued) at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX 155 195 I2C fast mode plus, AVDD = 5 V 45 75 I2C fast mode, AVDD = 5 V 29 37 I2C standard mode, AVDD = 5 V 13 18 7 15 I2C high-speed mode, AVDD = 5 V IAVDD Analog supply current No conversion, AVDD = 5 V UNIT µA 7.6 I2C Timing Requirements MODE (1) STANDARD, FAST, AND FAST MODE PLUS MIN MAX HIGH-SPEED MODE MIN UNIT MAX fSCL SCL clock frequency (2) tSUSTA START condition setup time for repeated start 260 160 ns tHDSTA Start condition hold time 260 160 ns tLOW Clock low period 500 160 ns tHIGH Clock high period 260 60 ns tSUDAT Data in setup time 50 10 ns tHDDAT Data in hold time 0 tR SCL rise time 120 80 ns tF SCL fall time 120 80 ns tSUSTO STOP condition hold time 260 60 ns tBUF Bus free time before new transmission 500 300 ns (1) (2) 1 3.4 MHz 0 ns The device supports standard, full-speed, and fast modes by default on power-up. For selecting high-speed mode refer to the section on Configuring the Device for High-Speed I2C Mode. Bus load (CB) consideration; CB ≤ 400 pF for fSCL ≤ 1 MHz; CB < 100 pF for fSCL = 3.4 MHz. 7.7 Timing Requirements at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C. MIN tACQ Acquisition time MAX UNIT 300 ns 7.8 I2C Switching Characteristics MODE STANDARD, FAST, AND FAST MODE PLUS MIN MAX HIGH-SPEED MODE MIN UNIT MAX tVDDATA SCL low to SDA data out valid 450 200 ns tVDACK SCL low to SDA acknowledge time 450 200 ns tSTRETCH Clock stretch time in one-shot conversion mode 1400 1000 ns tSP Noise supression time constant on SDA and SCL 50 10 ns Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 7 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 7.9 Switching Characteristics at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C. PARAMETER TEST CONDITIONS MIN MAX UNIT CONVERSION CYCLE tCONV Manual and auto sequence modes ADC conversion time Autonomous mode tSTRETCH ns 600 ns 5 ms 5 ms RESET AND ALERT AVDD ≥ 2.35 V tPU Power-up time for device tRST Delay time; RST bit = 1b to device reset complete (1) tALERT_HI ALERT high period ALERT_LOGIC[1:0] = 1x 50 150 ns tALERT_LO ALERT low period ALERT_LOGIC[1:0] = 1x 50 150 ns (1) RST bit is automatically reset to 0b after tRST. 9th clock tLOW tHIGH SCL tR tSUDAT tF tSUSTO tSTRETCH tHDSTA tHDDAT tSUSTA tSP SDA tBUF P tVDDAT tVDACK Sr S P NOTE: S = start, Sr = repeated start, and P = stop. Figure 1. I2C Timing Diagram 8 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 7.10 Typical Characteristics at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and maximum throughput (unless otherwise noted) 0.8 Frequency 45000 Differential Nonlinearity (LSB) 60000 39581 30000 25955 15000 0.4 0 -0.4 -0.8 0 2048 2049 0 Output Code 1024 2048 Output Code C001 Standard deviation = 0.49 LSB 3072 4095 C002 Typical DNL = ±0.2 LSB Figure 2. DC Input Histogram Figure 3. Typical DNL 0.8 0.5 0.3 0.4 Differential Nonlinearity Integral Nonlinearity (LSB) Minimum Maximum 0 -0.4 0.1 -0.1 -0.3 -0.8 0 1024 2048 Output Code 3072 -0.5 -40 4095 -15 C004 10 35 Temperature (°C) 60 85 C003 Typical INL = ±0.5 LSB Figure 4. Typical INL Figure 5. DNL vs Temperature 0.75 Differential Nonlinearity (LSB) Integral Nonlinearity (LSB) 0.6 0.3 Minimum Maximum 0 -0.3 -0.6 -40 0.5 0.25 0 -0.25 -0.5 -0.75 2.5 -15 10 35 Temperature (°C) 60 Maximum Minimum 85 3 3.5 4 AVDD (V) 4.5 5 5.5 C018 C005 Figure 7. DNL vs AVDD Figure 6. INL vs Temperature Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 9 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and maximum throughput (unless otherwise noted) 0.5 0.5 Maximum Minimum 0.3 Offset Error (LSB) Integral Nonlinearity (LSB) 0.75 0.25 0 -0.25 -0.5 -0.75 2.5 0.1 -0.1 -0.3 3 3.5 4 AVDD (V) 4.5 5 -0.5 -40 5.5 C019 -15 10 35 Temperature (°C) 60 85 C006 Figure 8. INL vs AVDD 0.5 0.45 0.3 Offset error (LSB) Gain Error (%FSR) Figure 9. Offset Error vs Temperature 0.75 0.15 -0.15 -0.1 -0.3 -0.45 -0.75 -40 0.1 -15 10 35 Temperature (°C) 60 -0.5 2.5 85 3 4.5 5 5.5 C016 Figure 11. Offset Error vs AVDD 1 0 0.6 -30 Amplitude (dBFS) Gain error (%FSR) 4 AVDD (V) C007 Figure 10. Gain Error vs Temperature 0.2 -0.2 -0.6 -1 2.5 3.5 -60 -90 -120 -150 3 3.5 4 AVDD (V) 4.5 5 5.5 0 16.7 C017 33.4 50.1 Frequency (kHz) 66.8 83.5 C008 fIN = 2 kHz, SNR = 73.2 dB, THD = 92.3 dB Figure 12. Gain Error vs AVDD 10 Figure 13. Typical FFT Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and maximum throughput (unless otherwise noted) 73.5 73.2 11.8 73 11.775 72.8 -40 -15 10 35 Temperature (°C) SNR, SINAD (dBFS) 11.825 ENOB (Bits) SNR, SINAD (dBFS) 73.2 73.4 11.75 85 60 12 SINAD SNR ENOB 72.9 11.8 72.6 11.7 72.3 11.6 72 2.5 3 Figure 14. Noise Performance vs Temperature 96 -90 94.5 -91 93 91.5 85 THD (dBFS) -89 SFDR (dBFS) THD (dBFS) 97.5 C010 94 -84 92 -86 90 -88 88 -90 2.5 3 3.5 4 AVDD (V) C011 Figure 16. Distortion Performance vs Temperature 132 136 129 132 126 128 124 4.5 86 5.5 5 C012 Figure 17. Distortion Performance vs AVDD 140 IAVDD (PA) IAVDD (PA) 11.5 5.5 5 THD SFDR -88 60 4.5 Figure 15. Noise Performance vs AVDD THD SFDR 10 35 Temperature (°C) 4 AVDD (V) -82 99 -15 3.5 C009 -87 -92 -40 11.9 ENOB (Bits) 11.85 SINAD SNR ENOB SFDR (dBFS) 73.6 123 120 120 -40 -15 10 35 Temperature (°C) 60 85 117 2.5 3 C013 Figure 18. Analog Supply Current vs Temperature 3.5 4 AVDD (V) 4.5 5 5.5 C014 Figure 19. Analog Supply Current vs AVDD Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 11 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and maximum throughput (unless otherwise noted) 150 IAVDD (µA) 120 90 60 30 0 0 30 60 90 120 Throughput (kSPS) 150 180 C015 Figure 20. Analog Supply Current vs Throughput 12 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8 Detailed Description 8.1 Overview The ADS7128 is a small, eight-channel, multiplexed, 12-bit, analog-to-digital converter (ADC) with an I2Ccompatible serial interface. The eight channels of the ADS7128 can be individually configured as either analog inputs, digital inputs, or digital outputs. The device includes a digital comparator with a dedicated alert pin that can be used to interrupt the host when a programmed high or low threshold is crossed on any input channel. The device uses an internal oscillator for conversion. The ADC can be used in the manual mode for reading ADC data over the I2C interface or in autonomous mode for monitoring the analog inputs without an active I2C interface. The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution. The root-mean-square (RMS) module computes a 16-bit true RMS result of any analog input channel over a configurable time window. The zero-crossing-detect (ZCD) module can be used to generate a digital output corresponding to the programmable threshold crossings of any analog input channel. The I2C serial interface supports standard-mode, fast-mode, fast-mode plus, and high-speed mode. The device also features an 8-bit cyclic redundancy check (CRC) for the serial communication interface. 8.2 Functional Block Diagram DECAP AVDD High/Low Threshold ± Hysteresis DVDD AIN0 / GPIO0 AIN1 / GPIO1 ADC ALERT Programmable Averaging Filter AIN2 / GPIO2 Digital Window Comparator AIN3 / GPIO3 AIN4 / GPIO4 MUX AIN5 / GPIO5 AIN6 / GPIO6 AIN7 / GPIO7 ADDR Sequencer 2 Pin CFG I C Interface GPO Write RMS Module GPI Read ZCD Module SDA SCL CRC GND Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 13 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.3 Feature Description 8.3.1 Multiplexer and ADC The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose inputs/outputs (GPIOs). Figure 21 shows that each input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. On power-up or after device reset, all eight multiplexer channels are configured as analog inputs. Figure 21 shows an equivalent circuit for pins configured as analog inputs. The ADC sampling switch is represented by an ideal switch (SW) in series with the resistor, RSW (typically 150 Ω), and the sampling capacitor, CSH (typically 12 pF). GPO_VALUE[0] GPIO_CFG[0] AVDD GPI_VALUE[0] PIN_CFG[0] AIN0 / GPIO0 RSW SW MUX Multiplexer AVDD CSH ADC AIN7 / GPIO7 PIN_CFG[7] GPI_VALUE[7] GPIO_CFG[7] GPO_VALUE[7] Figure 21. Analog Inputs, GPIOs, and ADC Connections During acquisition, the SW switch is closed to allow the signal on the selected analog input channel to charge the internal sampling capacitor. During conversion, the SW switch is opened to disconnect the analog input channel from the sampling capacitor. The multiplexer channels can be configured as GPIOs in the PIN_CFG register. The direction of a GPIO (either as an input or an output) can be set in the GPIO_CFG register. The logic level on the channels configured as digital I/O can be read from the GPI_VALUE register. The digital outputs can be accessed by writing to the GPO_VALUE register. The digital outputs can be configured as either open-drain or push-pull in the GPO_DRIVE_CFG register. 8.3.2 Reference The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process. TI recommends connecting a 1-µF, low-equivalent series resistance (ESR) ceramic decoupling capacitor between the AVDD and GND pins. 8.3.3 ADC Transfer Function The ADC output is in straight binary format. Equation 1 computes the ADC resolution: 1 LSB = VREF / 2N where: • • VREF = AVDD N = 12 (1) Figure 22 and Table 1 detail the transfer characteristics for the device. 14 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Feature Description (continued) ADC Code (Hex) PFSC MC + 1 MC NFSC+1 NFSC VIN 1 LSB AVDD/2 (AVDD/2 + 1 LSB) (AVDD ± 1 LSB) Figure 22. Ideal Transfer Characteristics Table 1. Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSBs NFSC + 1 — 001 (AVDD / 2) to (AVDD / 2) + 1 LSB MC Mid code 800 (AVDD / 2) + 1 LSB to (AVDD / 2) + 2 LSB MC + 1 — 801 ≥ AVDD – 1 LSB PFSC Positive full-scale code FFF 8.3.4 ADC Offset Calibration The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit to check the ADC offset calibration completion status. 8.3.5 I2C Address Selector The I2C address for the device is determined by connecting external resistors on the ADDR pin. The device address is determined at power-up based on the resistor values. The device retains this address until the next power-up event, until the next device reset, or until the device receives a command to program its own address. Figure 23 shows a connection diagram for the ADDR pin and Table 2 lists the resistor values for selecting different addresses of the device. DECAP Pin R1 ADDR R2 Figure 23. External Resistor Connection Diagram for the ADDR Pin Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 15 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 2. I2C Address Selection RESISTORS R2 (1) 0Ω DNP (2) 001 0111b (17h) 11 kΩ DNP (2) 001 0110b (16h) 33 kΩ DNP (2) 001 0101b (15h) 100 kΩ DNP (2) 001 0100b (14h) (2) (2) 001 0000b (10h) DNP DNP DNP (2) 11 kΩ 001 0001b (11h) DNP (2) 33 kΩ 001 0010b (12h) 100 kΩ 001 0011b (13h) DNP (1) (2) ADDRESS R1 (1) (2) Tolerance for R1, R2 ≤ ±5%. DNP = Do not populate. 8.3.6 Programmable Averaging Filter The ADS7128 features a built-in oversampling (OSR) function that can be used to average several samples. The averaging filter can be enabled by programming the OSR[2:0] bits in the OSR_CFG register. The averaging filter configuration is common to all analog input channels. Figure 24 shows that the averaging filter module output is 16 bits long. In the manual conversion mode and auto-sequence mode, only the first conversion for the selected analog input channel must be initiated by the host; see the Manual Mode and Auto-Sequence Mode sections. As shown in Figure 24, any remaining conversions for the selected averaging factor are generated internally. The time required to complete the averaging operation is determined by the sampling speed and number of samples to be averaged. As shown in Figure 24, the 16-bit result can be read out after the averaging operation completes. Sample AINX S 7-bit ADDR R Sample AINX A Sample AINX Sample AINX OSR_DONE = 1 Bus idle or Poll OSR_DONE bit DATA[15:8] A DATA[7:0] A OSR_DONE = 0 OSR_CFG[2:0] = 2 Time = tCONV x OSR_CFG[2:0] Data from host to device Data from device to host Figure 24. Averaging Example In Figure 24, SCL is stretched by the device after the start of conversions until the averaging operation is complete. If SCL stretching is not required during averaging, enable the statistics registers by setting STATS_EN to 1b and initiate conversions by writing 1b to the CNVST bit. The OSR_DONE bit in the SYSTEM_STATUS register can be polled to check the averaging completion status. When using the CNVST bit to initiate conversion, the result can be read in the RECENT_CHx_LSB and RECENT_CHx_MSB registers. In the autonomous mode of operation, samples from the analog input channels that are enabled in the AUTO_SEQ_CH_SEL register are averaged sequentially; see the Autonomous Mode section. The digital window comparator compares the top 12 bits of the 16-bit average result with the thresholds. Equation 2 provides the LSB value of the 16-bit average result. AVDD 1 LSB 216 16 Submit Documentation Feedback (2) Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.3.7 CRC on Data Interface The ADS7128 features a cyclic redundancy check (CRC) module for checking the integrity of the data bits exchanged over the I2C interface. The CRC module is bidirectional and appends an 8-bit CRC to every byte read from the device while also evaluating the CRC of every incoming byte over the I2C interface. The CRC module uses the CRC-8-CCITT polynomial (x8 + x2 + x + 1) for CRC computation. To enable the CRC module, set the CRC_EN bit in the GENERAL_CFG register. Table 3 shows how a CRC error can be detected when configuring the ADS7128. Table 3. Configuration Notifications When a CRC Error is Detected CRC ERROR NOTIFICATION CONFIGURATION DESCRIPTION ALERT pin ALERT_CRCIN = 1b ALERT pin is asserted if a CRC error is detected by the device. Status flags APPEND_STATUS = 10b 4-bit status flags are appended to the ADC data; see the Output Data Format section for details. Register read — Read the CRC_ERR_IN bit to check if a CRC error is detected. When the ADS7128 detects a CRC error, the erroneous data are ignored and the CRC_ERR_IN bit is set. Table 3 describes the additional notifications that can be enabled. Further register writes are disabled until the CRC_ERR_IN bit is cleared by writing 1b to it. When using autonomous mode, further conversions can be disabled on the CRC error by setting CONV_ON_ERR to 1b; see the Autonomous Mode section. 8.3.8 General-Purpose I/Os (GPIOs) The eight channels of the ADS7128 can be independently configured as analog inputs, digital inputs, or digital outputs. Table 4 describes how the PIN_CFG and GPIO_CFG registers can be used to configure the channels. Table 4. Configuring Channels as Analog Inputs or GPIOs PIN_CFG[7:0] GPIO_CFG[7:0] GPO_DRIVE_CFG[7:0] CHANNEL CONFIGURATION 0 x x Analog input (default) 1 0 x Digital input 1 1 0 Digital output; open-drain driver 1 1 1 Digital output; push-pull driver The digital outputs can be configured to logic 1 or 0 by writing to the GPO_VALUE register. Reading the GPI_VALUE register returns the logic level for all channels configured as digital inputs. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 17 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.3.9 Oscillator and Timing Control The device uses an internal oscillator for conversions. When using the averaging module or the RMS module, the host initiates the first conversion and all subsequent conversions are generated internally by the device. However, in the autonomous mode of operation, the start of the conversion signal is generated by the device. Table 5 shows that when the device generates the start of the conversion, the sampling rate is controlled by the OSC_SEL and CLK_DIV[3:0] register fields. Table 5. Configuring Sampling Rate for Internal Conversion Start Control OSC_SEL = 0 OSC_SEL = 1 CLK_DIV[3:0] SAMPLING FREQUENCY, fCYCLE (kSPS) CYCLE TIME, tCYCLE (µs) SAMPLING FREQUENCY, fCYCLE (kSPS) CYCLE TIME, tCYCLE (µs) 0000b 1000 1 31.25 32 0001b 666.7 1.5 20.83 48 0010b 500 2 15.63 64 0011b 333.3 3 10.42 96 0100b 250 4 7.81 128 0101b 166.7 6 5.21 192 0110b 125 8 3.91 256 0111b 83 12 2.60 384 1000b 62.5 16 1.95 512 1001b 41.7 24 1.3 768 1010b 31.3 32 0.98 1024 1011b 20.8 48 0.65 1536 1100b 15.6 64 0.49 2048 1101b 10.4 96 0.33 3072 1110b 7.8 128 0.24 4096 1111b 5.2 192 0.16 6144 The conversion time of the device (see tCONV in the Switching Characteristics table) is independent of the OSC_SEL and CLK_DIV[3:0] configuration. 8.3.10 Output Data Format Figure 25 illustrates various I2C frames for reading data. • Read the ADC conversion result: Two 8-bit I2C packets are required (frame A). • Read the averaged conversion result: Two 8-bit I2C packets are required (frame B). • Read data with the channel ID or status flags appended: The 4-bit channel ID or status flags can be appended to the 12-bit ADC result by configuring the APPEND_STATUS field in the GENERAL_CFG register. The status flags can be used to detect if a CRC error is detected and if an alert condition is detected by the digital window comparator. When the channel ID or status flags are appended to the 12-bit ADC data, two I2C packets are required (frame C). If the channel ID or status flags are appended to the 16-bit average result, three I2C frames are required (frame D). 18 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Sample A S 7-bit Slave Address R A Sample A + 1 D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 D1 D0 0 0 0 0 A D7 D6 D5 D4 D3 D2 D1 D0 A D1 D0 Frame A : Reading ADC data S 7-bit Slave Address R A D15 D14 D13 D12 D11 D10 D9 D8 A Frame B : Reading ADC data with averaging enabled S 7-bit Slave Address R A D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 4-bit Channel ID or Status Flags A Frame C : Reading ADC data with status flags or channel ID appended S 7-bit Slave Address R A D15 D14 D8 A D7 D6 D0 A 4-bit Channel ID or Status Flags 0 0 0 0 A Frame D : Reading ADC data with averaging enabled & status flags or channel ID appended Clock stretching for conversion time Data from host to device Data from device to host Figure 25. Data Frames for Reading Data When status flags are enabled, APPEND_STATUS is set to 10b and four bits are appended to the ADC output. The device outputs status flags in this order: {1b, 0b, CRCERR_IN, ALERT}. The level transitions on the digital interface, resulting from the fixed 1b and 0b in the status flags, can be used to detect if the digital outputs are shorted to a fixed voltage in the system. The CRCERR_IN flag reflects the corresponding bit in the GENERAL_CFG register. The ALERT flag is the output of the logical OR of the bits in the EVENT_FLAG register. 8.3.11 Digital Window Comparator The internal digital window comparator (DWC) is available in all functional modes of the device (see the Device Functional Modes section for details). The digital window comparator controls output of the ALERT pin buffer. The ALERT pin can be configured as open-drain (default) or push-pull output using the ALERT_DRIVE bit in the ALERT_PIN_CFG register. Figure 26 shows a block diagram for the digital window comparator. EVENT_RGN[7] EVENT_RGN[0] Digital input CH0 12-bit ADC data or [15:4] Average result ADC High threshold Hysteresis Programmable Averaging Filter Event Counter Low threshold + Hysteresis ALERT EVENT_HIGH_FLAG[0] MUX EVENT_LOW_FLAG[0] ALERT_CH_SEL[0] PIN_CFG[0] GPIO_CFG[0] All registers are specific for individual analog input channels Figure 26. Digital Window Comparator Block Diagram Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 19 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com The low-side threshold, high-side threshold, event counter, and hysteresis parameters are independently programmable for each input channel. Figure 27 shows the events that can be monitored for every analog input channel by the window comparator. High threshold Hysteresis 0xFFF High threshold Hysteresis Digital code xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Signal above limit xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Digital code 0xFFF Low threshold + Hysteresis 0x000 0x000 Low threshold + Hysteresis xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Signal below limit xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Samples 0x000 xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Signal out of band xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx High threshold Hysteresis DWC_CH_POL = 0 Low threshold + Hysteresis xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Signal out of band xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx 0xFFF High threshold Digital code Digital code 0xFFF Samples Hysteresis xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Signal in band xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx Low threshold + Hysteresis DWC_CH_POL = 1 0x000 Samples Samples Figure 27. Event Monitoring With the Window Comparator To enable the digital window comparator, set the DWC_EN bit in the GENERAL_CFG register. By default, hysteresis is 0, the high threshold is 0xFFF, and the low threshold is 0x000. A 12-bit straight binary code cannot be higher than 0xFFF or lower than 0x000, thus the thresholds have no effect unless set to different values. Figure 27 shows the various types of event that can be detected by adjusting the thresholds. For detecting when a signal is in-band, the EVENT_RGN register must be configured. In each of the cases shown in Figure 27, either or both EVENT_HIGH_FLAG and EVENT_LOW_FLAG can be set. The programmable event counter counts consecutive thresholds violations before alert flags can be set. The event count can be set to a higher value to avoid transients in the input signal setting the alert flags. In order to assert the ALERT pin when the alert flag is set for a particular analog input channel, set the corresponding bit in the ALERT_CH_SEL register. Alert flags are set regardless of the ALERT_CH_SEL configuration if DWC_EN is 1 and the high or low thresholds are exceeded. 20 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.3.11.1 Interrupts From Digital Inputs Logic 1 or logic 0 events can detected on channels configured as digital inputs, as shown in Table 6, by enabling the corresponding ALERT_CH_SEL bit. Table 6. Configuring Interrupts From Digital Inputs ALERT_CH_SEL[7: EVENT_RGN [7:0] 0] PIN_CFG[7:0] GPIO_CFG[7:0] EVENT DESCRIPTION 1 0 1 0 EVENT_HIGH_FLAG is set when digital input channel is at logic 1. 1 0 1 1 EVENT_LOW_FLAG is set when digital input channel is at logic 0. 8.3.11.2 Changing Digital Outputs on Alert and ZCD Figure 28 shows how digital outputs can be updated in response to alerts from individual channels or synchronized to the zero-crossing-detect signal. Digital output 7 Digital output 0 Select alerts on which channels should be enabled as triggers CH [7:0] trigger GPO_TRIGGER_UPDATE_EN [0] Enable the triggers GPO_OUTPUT_VALUE [0] GPO_ZCD_UPDATE_ EN [0] GPO0_VALUE_ON_ZCD_CFG_ CH0 [1:0] 0 00 Logic 0 01 ZCD 10 ZCD 11 Logic 1 1 0 1 GPO_VALUE_ON_TRIGGER [0] Figure 28. Block Diagram for the Digital Output Logic 8.3.11.2.1 Changing Digital Outputs on Alerts Any given digital output can be updated in response to an alert condition on one or more analog inputs and digital inputs. To update the digital output in response to alert conditions, the trigger must be configured and the value must be launched on the trigger. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 21 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.3.11.2.1.1 Trigger The following events can act as triggers for updating the value on the digital output: • An alert occurs on one or more analog input channels. The digital window comparator must be enabled for these channels. • An alert occurs on one or more digital input channels. The digital window comparator must be enabled for these channels. Configure the GPOx_TRIG_EVENT_SEL register to select which channels, analog inputs, or digital inputs can trigger an update on the digital output pin. After configuring the triggers for updating a digital output, the logic can be enabled by configuring the corresponding bit in the GPO_TRIGGER_UPDATE_EN register. 8.3.11.2.1.2 Output Value The digital outputs can be set to logic 1 or logic 0 in response to the triggers. The value to be updated on the digital output when a trigger event occurs can be configured in the GPO_VALUE_ON_TRIGGER register. 8.3.11.2.2 Changing Digital Outputs Synchronous to the Zero-Crossing Detect Individual digital outputs can be set to either logic 0, logic 1, ZCD, or ZCD synchronous to the zero-crossingdetect signal. This function can be enabled for individual digital outputs by configuring the GPO_VALUE_ON_ZCD_CFG_CHx field and setting the corresponding bit in the GPO_ZCD_UPDATE_EN [7:0] register. 8.3.12 Root-Mean-Square Module The ADS7128 features an RMS computation module. Any one analog input channel can be selected for computing the RMS result. The RMS result is computed over a block of samples from the selected channel and the result can be read from the RMS_RESULT_LSB and RMS_RESULT_MSB registers. Equation 3 shows how the RMS result is computed by calculating the 16-bit square root of the mean of the accumulated result of the squares of the ADC conversion data. 4/5 = ¨F &1 2 + &2 2 + &3 2 + ® + &0 2 &1 + &2 + &3 + ® + &0 2 p .5$ GF>×l 0 0 AC component DC component where • • D is the data corresponding to the analog input channel selected for RMS measurement N is the number of samples over which the RMS is computed (3) The DC offset must be subtracted from the AC component because the analog input signal to the ADC is unipolar. DC subtraction can be enabled or disabled, as given by b in Equation 3, by configuring the DC_SUB field. When DC subtraction is enabled, the DC input voltage must be within ±5% tolerance of the mid-scale voltage i.e. (0.5 × AVDD) ± 5%. The RMS result is 16 bits long and Equation 4 gives the size of the 1 LSB of RMS result. 1 LSB = AVDD / 216 (4) The procedure for using the RMS module is outlined in the steps below: 1. Select the channel for the RMS computation using the RMS_CHID field in the RMS_CFG register. 2. Define the time over which the RMS is to be computed by configuring the RMS_SAMPLES field. 3. Start the RMS computation by setting RMS_EN to 1 in the GENERAL_CFG register. 4. The device starts computing the RMS result when the sample size defined by RMS_SAMPLES is converted on the analog input selected for RMS computation. An additional 40 samples must be converted to complete the RMS computation. 5. To monitor for when the RMS computation completes, poll the RMS_DONE bit in the SYSTEM_STATUS register. The ALERT pin can also be used for requesting an interrupt by configuring the ALERT_RMS bit in the ALERT_MAP register. 22 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 6. For starting a new RMS measurement, write 1 to the RMS_EN bit in the GENERAL_CFG register. 8.3.13 Zero-Crossing-Detect Module Figure 29 shows the zero-crossing-detection (ZCD) module that generates a digital output corresponding to the threshold crossings of an analog input. In order to detect threshold crossings on a particular analog input, configure the 4-bit channel ID in the ZCD_CHID register field. The threshold crossing to be detected can be configured in the HIGH_TH register. The output of the ZCD module can be mapped to any digital output by configuring the GPO_ZCD_UPDATE_EN, GPO_VALUE_ZCD_CFG_CH0_CH3, and GPO_VALUE_ZCD_CFG_CH4_CH7 registers. Transient rejection Analog input High threshold AIN0 AIN1 High threshold AIN2 MUX ADC ZCD Module Programmable Averaging Filters AIN3 Sequencer Configurable GPO4 transient rejection time GPO5 GPO6 Transient Rejection Channel ID Digital Output Logic GPO7 Digital output Figure 29. ZCD Module Operation Block Diagram The ADC conversion result of the selected analog input channel is compared with the digital threshold and the digital output is set accordingly. Equation 5 shows how transients near zero crossings can be rejected by configuring the ZCD_BLANKING register. 1 transient rejection time = MULT_EN × ZCD_BLANKING>6: 0? × seconds sampling rate for ZCD channel (5) 8.3.14 Minimum, Maximum, and Latest Data Registers The ADS7128 can record the minimum, maximum, and latest code (statistics registers) for every analog input channel. To enable or re-enable recording statistics, set the STATS_EN bit in the GENERAL_CFG register. Writing 1 to the STATS_EN bit reinitializes the statistics module, after which results from new conversions are recorded in the statistics registers. Until a new conversion result is available, previous values can be read from the statistics registers. Before reading the statistics registers, set STATS_EN to 0 to prevent any updates to this register block. 8.3.15 I2C Protocol Features 8.3.15.1 General Call On receiving a general call (00h), the device provides an acknowledge (ACK). 8.3.15.2 General Call With Software Reset On receiving a general call (00h) followed by a software reset (06h), the device resets itself. 8.3.15.3 General Call With a Software Write to the Programmable Part of the Slave Address On receiving a general call (00h) followed by 04h, the device reevaluates its own I2C address configured by the ADDR pin. During this operation, the device does not respond to other I2C commands except the general-call command. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 23 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.3.15.4 Configuring the Device for High-Speed I2C Mode The device can be configured in high-speed I2C mode by providing an I2C frame with one of these codes: 0x09, 0x0B, 0x0D, or 0x0F. After receiving one of these codes, the device sets the I2C_HIGH_SPEED bit in the SYSTEM_STATUS register and remains in high-speed I2C mode until a STOP condition is received in an I2C frame. 8.4 Device Functional Modes Table 7 lists the functional modes supported by the ADS7128. Table 7. Functional Modes FUNCTIONAL MODE CONVERSION CONTROL MUX CONTROL CONV_MODE[1:0] SEQ_MODE[1:0] Manual 9th falling edge of SCL (ACK) Register write to MANUAL_CHID 00b 00b Auto-sequence 9th falling edge of SCL (ACK) Channel sequencer 00b 01b Autonomous Internal to the device Channel sequencer 01b 01b The device powers up in manual mode (see the Manual Mode section) and can be configured into any mode listed in Table 7 by writing the configuration registers for the desired mode. 8.4.1 Device Power-Up and Reset On power-up, the device calculates the address from the resistors connected on the ADDR pin and the BOR bit is set, thus indicating a power-cycle or reset event. The device can be reset by an I2C general call (00h) followed by a software reset (06h), by setting the RST bit, or by recycling the power on the AVDD pin. 8.4.2 Manual Mode Manual mode allows the external host processor to directly select the analog input channel. Figure 30 lists the steps for operating the device in manual mode. Idle SEQ_MODE = 0 CONV_MODE = 0 Configure channels as AIN/GPIO using PIN_CFG Select Manual mode (CONV_MODE = 00b, SEQ_MODE = 00b) Configure desired Channel ID in MANUAL_CHID field Host provides Conversion Start Frame on I2C Bus Host provides Conversion Read Frame on I2C Bus No Same Channel ID? Yes Manual mode with channel selection using register write Figure 30. Device Operation in Manual Mode 24 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Provide an I2C start or restart frame to initiate a conversion, as shown in the conversion start frame of Figure 31, after configuring the device registers. ADC data can be read in subsequent I2C frames. The number of I2C frames required to read conversion data depends on the output data frame size; see the Output Data Format section for more details. A new conversion is initiated on the ninth falling edge of SCL (ACK bit) when the last byte of output data is read. Sample A + 1 Sample A S 7-bit Slave Address R A 8 bit I2C frame A 8 bit I2C frame A 8 bit I2C frame A 8 bit I2C frame A Clock stretching for conversion time Clock stretching for conversion time Data from host to device Data from device to host Figure 31. Starting a Conversion and Reading Data in Manual Mode 8.4.3 Auto-Sequence Mode In auto-sequence mode, the internal channel sequencer switches the multiplexer to the next analog input channel after every conversion. The desired analog input channels can be configured for sequencing in the AUTO_SEQ_CHSEL register. To enable the channel sequencer, set SEQ_START to 1b. After every conversion, the channel sequencer switches the multiplexer to the next analog input in ascending order. To stop the channel sequencer from selecting channels, set SEQ_START to 0b. Figure 32 lists the conversion start and read frames for auto-sequence mode. Idle SEQ_MODE = 0 CONV_MODE = 0 Configure channels as AIN/GPIO using PIN_CFG Enable analog inputs for sequencing (AUTO_SEQ_CHSEL) Select Auto-sequence mode (SEQ_MODE = 01b) (optional) Configure alert conditions (optional) Append Channel ID to data using APPEND_STATUS Enable channel sequencing SEQ_START = 1 Host provides Conversion Start Frame on I2C Bus Host provides Conversion Read Frame on I2C Bus Device selects next channel according to AUTO_SEQ_CHSEL Continue? Yes No Disable channel sequencing SEQ_START = 0 Idle Figure 32. Device Operation in Auto-Sequence Mode Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 25 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.4.4 Autonomous Mode In autonomous mode, the device can be programmed to monitor the voltage applied on the analog input pins of the device and generate a signal on the ALERT pin when the programmable high or low threshold values are crossed. In this mode, the device generates the start of conversion using the internal oscillator. The first start of conversion must be provided by the host and the device then generates the subsequent start of conversions. Figure 33 shows the steps for configuring the operation mode to autonomous mode. Abort the ongoing sequence by setting SEQ_START to 0b before changing the functional mode or device configuration. Idle SEQ_MODE = 0 CONV_MODE = 0 Configure channels as AIN/GPIO using GPIO_CFG Enable analog inputs for sequencing (AUTO_SEQ_CHSEL) Select Auto-sequence mode (SEQ_MODE = 01b) Channel selection Configure alert condition using HIGH_THRESHOLD_CHx, LOW_THRESHOLD_CHx,EVENT_COUNT, HYSTERESIS_CHx, and EVENT_REGION_CHx fields Enable analog inputs to trigger ALERT pin using ALERT_CH_SEL Configuration Threshold & Alert configuration Configure ALERT pin behavior using ALERT_DRIVE and ALERT_LOGIC Configure sampling rate of analog inputs using OSC_SEL and CLK_DIV Set mode to autonomous monitoring (CONV_MODE = 01b) Sampling rate configuration (optional) Enable averaging and min/max recording (OSR[2:0] and STATS_EN) Enable threshold comparison (DWC_EN = 1) Enable autonomous monitoring (SEQ_START = 1) Active Operation (Host can sleep) No ALERT? (optional) read conversion results in MIN_VALUE_CHx, MAX_VALUE_CHx, and LAST_VALUE_CHx registers Yes Stop autonomous monitoring (SEQ_START = 0) Disable threshold comparison (DWC_EN = 0) ALERT Detected Read alert flags ± EVENT_FLAG, EVENT_HIGH_FLAG, EVENT_LOW_FLAG Clear alert flags ± EVENT_HIGH_FLAG, EVENT_LOW_FLAG Figure 33. Configuring the Device in Autonomous Mode 26 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.5 Programming Table 8 provides the acronyms for different conditions in an I2C frame. Table 9 lists the various command opcodes. Table 8. I2C Frame Acronyms SYMBOL DESCRIPTION S Start condition for the I2C frame Sr Restart condition for the I2C frame P Stop condition for the I2C frame A ACK (low) N NACK (high) R Read bit (high) W Write bit (low) Table 9. Opcodes for Commands OPCODE COMMAND DESCRIPTION 0001 0000b Single register read 0000 1000b Single register write 0001 1000b Set bit 0010 0000b Clear bit 0011 0000b Reading a continuous block of registers 0010 1000b Writing a continuous block of registers 8.5.1 Reading Registers The I2C master can either read a single register or a continuous block registers from the device, as described in the Single Register Read and Reading a Continuous Block of Registers sections. 8.5.1.1 Single Register Read To read a single register from the device, the I2C master must provide an I2C command with three frames to set the register address for reading data. Table 9 lists the opcodes for different commands. After this command is provided, the I2C master must provide another I2C frame (as shown in Figure 34) containing the device address and the read bit. After this frame, the device provides the register data. The device provides the same register data even if the host provides more clocks. To end the register read command, the master must provide a STOP or a RESTART condition in the I2C frame. S 7-bit Slave Address W A 0001 0000b Register Address A Data from host to device A P/Sr S 7-bit Slave Address R A Register Data A P/Sr Data from device to host NOTE: S = start, Sr = repeated start, and P = stop. Figure 34. Reading Register Data Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 27 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.5.1.2 Reading a Continuous Block of Registers To read a continuous block of registers, the I2C master must provide an I2C command to set the register address. The register address is the address of the first register in the block that must be read. After this command is provided, the I2C master must provide another I2C frame, as shown in Figure 35, containing the device address and the read bit. After this frame, the device provides the register data. The device provides data for the next register when more clocks are provided. When data are read from addresses that do not exist in the register map of the device, the device returns zeros. If the device does not have any further registers to provide data on, the device provide zeros. To end the register read command, the master must provide a STOP or a RESTART condition in the I2C frame. S 7-bit Slave Address W A 0011 0000b A 1st Reg Address in the Block A Data from host to device P/Sr S 7-bit Slave Address R A Register Data A P/Sr Data from device to host NOTE: S = start, Sr = repeated start, and P = stop. Figure 35. Reading a Continuous Block of Registers 8.5.2 Writing Registers The I2C master can either write a single register or a continuous block of registers to the device, set a few bits in a register, or clear a few bits in a register. 8.5.2.1 Single Register Write To write a single register from the device, as shown in Figure 36, the I2C master must provide an I2C command with four frames. The register address is the address of the register that must be written and the register data is the value that must be written. Table 9 lists the opcodes for different commands. To end the register write command, the master must provide a STOP or a RESTART condition in the I2C frame. S 7-bit Slave Address W A 0000 1000b Data from host to device A Register Address A Register Data A P/Sr Data from device to host NOTE: S = start, Sr = repeated start, and P = stop. Figure 36. Writing a Single Register 8.5.2.2 Set Bit The I2C master must provide an I2C command with four frames, as shown in Figure 36, to set bits in a register without changing the other bits. The register address is the address of the register that the bits must set and the register data is the value representing the bits that must be set. Bits with a value of 1 in the register data are set and bits with a value of 0 in the register data are not changed. Table 9 lists the opcodes for different commands. To end this command, the master must provide a STOP or RESTART condition in the I2C frame. 8.5.2.3 Clear Bit The I2C master must provide an I2C command with four frames, as shown in Figure 36, to clear bits in a register without changing the other bits. The register address is the address of the register that the bits must clear and the register data is the value representing the bits that must be cleared. Bits with a value of 1 in the register data are cleared and bits with a value of 0 in the register data are not changed. Table 9 lists the opcodes for different commands. To end this command, the master must provide a STOP or a RESTART condition in the I2C frame. 28 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.5.2.4 Writing a Continuous Block of Registers The I2C master must provide an I2C command, as shown in Figure 37, to write a continuous block of registers. The register address is the address of the first register in the block that must be written. The I2C master must provide data for registers in subsequent I2C frames in an ascending order of register addresses. Writing data to addresses that do not exist in the register map of the device have no effect. Table 9 lists the opcodes for different commands. If the data provided by the I2C master exceeds the address space of the device, the device ignores the data beyond the address space. To end the register write command, the master must provide a STOP or a RESTART condition in the I2C frame. S 7-bit Slave Address W A 0010 1000b A 1st Reg Address in the block Data from host to device A Register Data A P/Sr Data from device to host NOTE: S = start, Sr = repeated start, and P = stop. Figure 37. Writing a Continuous Block of Registers Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 29 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.6 ADS7128 Registers Table 10 lists the ADS7128 registers. All register offset addresses not listed in Table 10 should be considered as reserved locations and the register contents should not be modified. Table 10. ADS7128 Registers Address 30 Acronym 0x0 SYSTEM_STATUS 0x1 GENERAL_CFG 0x2 DATA_CFG 0x3 OSR_CFG 0x4 OPMODE_CFG 0x5 PIN_CFG 0x7 GPIO_CFG 0x9 GPO_DRIVE_CFG 0xB GPO_VALUE 0xD GPI_VALUE 0xF ZCD_BLANKING_CFG 0x10 SEQUENCE_CFG 0x11 CHANNEL_SEL 0x12 AUTO_SEQ_CH_SEL 0x14 ALERT_CH_SEL 0x16 ALERT_MAP 0x17 ALERT_PIN_CFG 0x18 EVENT_FLAG Register Name Section SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81] GENERAL_CFG Register (Address = 0x1) [reset = 0x0] DATA_CFG Register (Address = 0x2) [reset = 0x0] OSR_CFG Register (Address = 0x3) [reset = 0x0] OPMODE_CFG Register (Address = 0x4) [reset = 0x0] PIN_CFG Register (Address = 0x5) [reset = 0x0] GPIO_CFG Register (Address = 0x7) [reset = 0x0] GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0] GPO_VALUE Register (Address = 0xB) [reset = 0x0] GPI_VALUE Register (Address = 0xD) [reset = 0x0] ZCD_BLANKING_CFG Register (Address = 0xF) [reset = 0x0] SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0] CHANNEL_SEL Register (Address = 0x11) [reset = 0x0] AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0] ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0] ALERT_MAP Register (Address = 0x16) [reset = 0x0] ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0] EVENT_FLAG Register (Address = 0x18) [reset = 0x0] 0x1A EVENT_HIGH_FLAG EVENT_HIGH_FLAG Register (Address = 0x1A) [reset = 0x0] 0x1C EVENT_LOW_FLAG EVENT_LOW_FLAG Register (Address = 0x1C) [reset = 0x0] 0x1E EVENT_RGN 0x20 HYSTERESIS_CH0 0x21 HIGH_TH_CH0 0x22 EVENT_COUNT_CH0 0x23 LOW_TH_CH0 0x24 HYSTERESIS_CH1 0x25 HIGH_TH_CH1 0x26 EVENT_COUNT_CH1 0x27 LOW_TH_CH1 0x28 HYSTERESIS_CH2 0x29 HIGH_TH_CH2 0x2A EVENT_COUNT_CH2 0x2B LOW_TH_CH2 0x2C HYSTERESIS_CH3 0x2D HIGH_TH_CH3 0x2E EVENT_COUNT_CH3 0x2F LOW_TH_CH3 0x30 HYSTERESIS_CH4 0x31 HIGH_TH_CH4 0x32 EVENT_COUNT_CH4 0x33 LOW_TH_CH4 0x34 HYSTERESIS_CH5 0x35 HIGH_TH_CH5 EVENT_RGN Register (Address = 0x1E) [reset = 0x0] HYSTERESIS_CH0 Register (Address = 0x20) [reset = 0xF0] HIGH_TH_CH0 Register (Address = 0x21) [reset = 0xFF] EVENT_COUNT_CH0 Register (Address = 0x22) [reset = 0x0] LOW_TH_CH0 Register (Address = 0x23) [reset = 0x0] HYSTERESIS_CH1 Register (Address = 0x24) [reset = 0xF0] HIGH_TH_CH1 Register (Address = 0x25) [reset = 0xFF] EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0] LOW_TH_CH1 Register (Address = 0x27) [reset = 0x0] HYSTERESIS_CH2 Register (Address = 0x28) [reset = 0xF0] HIGH_TH_CH2 Register (Address = 0x29) [reset = 0xFF] EVENT_COUNT_CH2 Register (Address = 0x2A) [reset = 0x0] LOW_TH_CH2 Register (Address = 0x2B) [reset = 0x0] HYSTERESIS_CH3 Register (Address = 0x2C) [reset = 0xF0] HIGH_TH_CH3 Register (Address = 0x2D) [reset = 0xFF] EVENT_COUNT_CH3 Register (Address = 0x2E) [reset = 0x0] LOW_TH_CH3 Register (Address = 0x2F) [reset = 0x0] HYSTERESIS_CH4 Register (Address = 0x30) [reset = 0xF0] HIGH_TH_CH4 Register (Address = 0x31) [reset = 0xFF] EVENT_COUNT_CH4 Register (Address = 0x32) [reset = 0x0] LOW_TH_CH4 Register (Address = 0x33) [reset = 0x0] HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0] HIGH_TH_CH5 Register (Address = 0x35) [reset = 0xFF] Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 10. ADS7128 Registers (continued) Address Acronym 0x36 EVENT_COUNT_CH5 0x37 LOW_TH_CH5 0x38 HYSTERESIS_CH6 Register Name Section EVENT_COUNT_CH5 Register (Address = 0x36) [reset = 0x0] LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0] HYSTERESIS_CH6 Register (Address = 0x38) [reset = 0xF0] 0x39 HIGH_TH_CH6 0x3A EVENT_COUNT_CH6 HIGH_TH_CH6 Register (Address = 0x39) [reset = 0xFF] 0x3B LOW_TH_CH6 0x3C HYSTERESIS_CH7 0x3D HIGH_TH_CH7 0x3E EVENT_COUNT_CH7 0x3F LOW_TH_CH7 0x60 MAX_CH0_LSB MAX_CH0_LSB Register (Address = 0x60) [reset = 0x0] 0x61 MAX_CH0_MSB MAX_CH0_MSB Register (Address = 0x61) [reset = 0x0] 0x62 MAX_CH1_LSB MAX_CH1_LSB Register (Address = 0x62) [reset = 0x0] 0x63 MAX_CH1_MSB MAX_CH1_MSB Register (Address = 0x63) [reset = 0x0] 0x64 MAX_CH2_LSB MAX_CH2_LSB Register (Address = 0x64) [reset = 0x0] 0x65 MAX_CH2_MSB MAX_CH2_MSB Register (Address = 0x65) [reset = 0x0] 0x66 MAX_CH3_LSB MAX_CH3_LSB Register (Address = 0x66) [reset = 0x0] 0x67 MAX_CH3_MSB MAX_CH3_MSB Register (Address = 0x67) [reset = 0x0] 0x68 MAX_CH4_LSB MAX_CH4_LSB Register (Address = 0x68) [reset = 0x0] 0x69 MAX_CH4_MSB MAX_CH4_MSB Register (Address = 0x69) [reset = 0x0] 0x6A MAX_CH5_LSB MAX_CH5_LSB Register (Address = 0x6A) [reset = 0x0] 0x6B MAX_CH5_MSB MAX_CH5_MSB Register (Address = 0x6B) [reset = 0x0] 0x6C MAX_CH6_LSB MAX_CH6_LSB Register (Address = 0x6C) [reset = 0x0] 0x6D MAX_CH6_MSB MAX_CH6_MSB Register (Address = 0x6D) [reset = 0x0] 0x6E MAX_CH7_LSB MAX_CH7_LSB Register (Address = 0x6E) [reset = 0x0] 0x6F MAX_CH7_MSB MAX_CH7_MSB Register (Address = 0x6F) [reset = 0x0] 0x80 MIN_CH0_LSB MIN_CH0_LSB Register (Address = 0x80) [reset = 0xFF] 0x81 MIN_CH0_MSB MIN_CH0_MSB Register (Address = 0x81) [reset = 0xFF] 0x82 MIN_CH1_LSB MIN_CH1_LSB Register (Address = 0x82) [reset = 0xFF] 0x83 MIN_CH1_MSB MIN_CH1_MSB Register (Address = 0x83) [reset = 0xFF] 0x84 MIN_CH2_LSB MIN_CH2_LSB Register (Address = 0x84) [reset = 0xFF] 0x85 MIN_CH2_MSB MIN_CH2_MSB Register (Address = 0x85) [reset = 0xFF] 0x86 MIN_CH3_LSB MIN_CH3_LSB Register (Address = 0x86) [reset = 0xFF] 0x87 MIN_CH3_MSB MIN_CH3_MSB Register (Address = 0x87) [reset = 0xFF] 0x88 MIN_CH4_LSB MIN_CH4_LSB Register (Address = 0x88) [reset = 0xFF] 0x89 MIN_CH4_MSB MIN_CH4_MSB Register (Address = 0x89) [reset = 0xFF] 0x8A MIN_CH5_LSB MIN_CH5_LSB Register (Address = 0x8A) [reset = 0xFF] 0x8B MIN_CH5_MSB MIN_CH5_MSB Register (Address = 0x8B) [reset = 0xFF] 0x8C MIN_CH6_LSB MIN_CH6_LSB Register (Address = 0x8C) [reset = 0xFF] 0x8D MIN_CH6_MSB MIN_CH6_MSB Register (Address = 0x8D) [reset = 0xFF] 0x8E MIN_CH7_LSB MIN_CH7_LSB Register (Address = 0x8E) [reset = 0xFF] 0x8F MIN_CH7_MSB MIN_CH7_MSB Register (Address = 0x8F) [reset = 0xFF] 0xA0 RECENT_CH0_LSB RECENT_CH0_LSB Register (Address = 0xA0) [reset = 0x0] 0xA1 RECENT_CH0_MSB RECENT_CH0_MSB Register (Address = 0xA1) [reset = 0x0] 0xA2 RECENT_CH1_LSB RECENT_CH1_LSB Register (Address = 0xA2) [reset = 0x0] 0xA3 RECENT_CH1_MSB RECENT_CH1_MSB Register (Address = 0xA3) [reset = 0x0] 0xA4 RECENT_CH2_LSB RECENT_CH2_LSB Register (Address = 0xA4) [reset = 0x0] EVENT_COUNT_CH6 Register (Address = 0x3A) [reset = 0x0] LOW_TH_CH6 Register (Address = 0x3B) [reset = 0x0] HYSTERESIS_CH7 Register (Address = 0x3C) [reset = 0xF0] HIGH_TH_CH7 Register (Address = 0x3D) [reset = 0xFF] EVENT_COUNT_CH7 Register (Address = 0x3E) [reset = 0x0] LOW_TH_CH7 Register (Address = 0x3F) [reset = 0x0] Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 31 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 10. ADS7128 Registers (continued) Address Acronym Register Name Section 0xA5 RECENT_CH2_MSB 0xA6 RECENT_CH3_LSB RECENT_CH2_MSB Register (Address = 0xA5) [reset = 0x0] RECENT_CH3_LSB Register (Address = 0xA6) [reset = 0x0] 0xA7 RECENT_CH3_MSB RECENT_CH3_MSB Register (Address = 0xA7) [reset = 0x0] 0xA8 RECENT_CH4_LSB RECENT_CH4_LSB Register (Address = 0xA8) [reset = 0x0] 0xA9 RECENT_CH4_MSB RECENT_CH4_MSB Register (Address = 0xA9) [reset = 0x0] 0xAA RECENT_CH5_LSB RECENT_CH5_LSB Register (Address = 0xAA) [reset = 0x0] RECENT_CH5_MSB Register (Address = 0xAB) [reset = 0x0] 0xAB RECENT_CH5_MSB 0xAC RECENT_CH6_LSB RECENT_CH6_LSB Register (Address = 0xAC) [reset = 0x0] 0xAD RECENT_CH6_MSB RECENT_CH6_MSB Register (Address = 0xAD) [reset = 0x0] 0xAE RECENT_CH7_LSB RECENT_CH7_LSB Register (Address = 0xAE) [reset = 0x0] 0xAF RECENT_CH7_MSB RECENT_CH7_MSB Register (Address = 0xAF) [reset = 0x0] 0xC0 RMS_CFG RMS_CFG Register (Address = 0xC0) [reset = 0x0] 0xC1 RMS_LSB RMS_LSB Register (Address = 0xC1) [reset = 0x0] 0xC2 RMS_MSB 0xC3 GPO0_TRIG_EVENT_SEL GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2] 0xC5 GPO1_TRIG_EVENT_SEL GPO1_TRIG_EVENT_SEL Register (Address = 0xC5) [reset = 0x2] 0xC7 GPO2_TRIG_EVENT_SEL GPO2_TRIG_EVENT_SEL Register (Address = 0xC7) [reset = 0x2] 0xC9 GPO3_TRIG_EVENT_SEL GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x2] 0xCB GPO4_TRIG_EVENT_SEL GPO4_TRIG_EVENT_SEL Register (Address = 0xCB) [reset = 0x2] 0xCD GPO5_TRIG_EVENT_SEL GPO5_TRIG_EVENT_SEL Register (Address = 0xCD) [reset = 0x2] 0xCF GPO6_TRIG_EVENT_SEL GPO6_TRIG_EVENT_SEL Register (Address = 0xCF) [reset = 0x2] 0xD1 GPO7_TRIG_EVENT_SEL GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x2] 0xE3 GPO_VALUE_ZCD_CFG_CH0_CH3 GPO_VALUE_ZCD_CFG_CH0_CH3 Register (Address = 0xE3) [reset = 0x0] 0xE4 GPO_VALUE_ZCD_CFG_CH4_CH7 GPO_VALUE_ZCD_CFG_CH4_CH7 Register (Address = 0xE4) [reset = 0x0] 0xE7 GPO_ZCD_UPDATE_EN 0xE9 GPO_TRIGGER_CFG 0xEB GPO_VALUE_TRIG RMS_MSB Register (Address = 0xC2) [reset = 0x0] GPO_ZCD_UPDATE_EN Register (Address = 0xE7) [reset = 0x0] GPO_TRIGGER_CFG Register (Address = 0xE9) [reset = 0x0] GPO_VALUE_TRIG Register (Address = 0xEB) [reset = 0x0] Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for access types in this section. Table 11. ADS7128 Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W Reset or Default Value -n Value after reset or the default value Register Array Variables 32 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 11. ADS7128 Access Type Codes (continued) Access Type Code Description i,j,k,l,m,n When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When this variable is used in a register name, an offset, or an address it refers to the value of a register array. 8.6.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81] SYSTEM_STATUS is shown in Figure 38 and described in Table 12. Return to the Summary Table. Figure 38. SYSTEM_STATUS Register 7 RSVD 6 SEQ_STATUS 5 I2C_SPEED 4 RMS_DONE 3 OSR_DONE R-1b R-0b R-0b R/W-0b R/W-0b 2 CRC_ERR_FU SE R-0b 1 CRC_ERR_IN 0 BOR R/W-0b R/W-1b Table 12. SYSTEM_STATUS Register Field Descriptions Bit Field Type Reset Description 7 RSVD R 1b Reads return 1b. 6 SEQ_STATUS R 0b Status of the channel sequencer. 0b = Sequence stopped 1b = Sequence in progress 5 I2C_SPEED R 0b I2C high-speed status. 0b = I2C bus is not in high speed mode. 1b = I2C bus is in high speed mode. 4 RMS_DONE R/W 0b RMS computation status. Clear this bit by writing 1b to this bit. 0b = RMS operation in progress or not started; RMS result not ready. 1b = RMS computation complete; RMS result ready. 3 OSR_DONE R/W 0b Averaging status. Clear this bit by writing 1b to this bit. 0b = Averaging in progress or not started; average result is not ready. 1b = Averaging complete; average result is ready. 2 CRC_ERR_FUSE R 0b Device power-up configuration CRC check status. To re-evaluate this bit, software reset the device or power cycle AVDD. 0b = No problems detected in power-up configuration. 1b = Device configuration not loaded correctly. 1 CRC_ERR_IN R/W 0b Status of CRC check on incoming data. Write 1b to clear this error flag. 0b = No CRC error. 1b = CRC error detected. All register writes, except to addresses 0x00 and 0x01, are blocked. 0 BOR R/W 1b Brown out reset indicator. This bit is set if brown out condition occurs or device is power cycled. Write 1b to this bit to clear the flag. 0b = No brown out since last time this bit was cleared. 1b = Brown out condition detected or device power cycled. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 33 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.6.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0] GENERAL_CFG is shown in Figure 39 and described in Table 13. Return to the Summary Table. Figure 39. GENERAL_CFG Register 7 RMS_EN R/W-0b 6 CRC_EN R/W-0b 5 STATS_EN R/W-0b 4 DWC_EN R/W-0b 3 CNVST W-0b 2 CH_RST R/W-0b 1 CAL R/W-0b 0 RST W-0b Table 13. GENERAL_CFG Register Field Descriptions Bit 7 Field Type Reset Description RMS_EN R/W 0b Enableor disable the RMS module. 0b = RMS module disabled. 1b = RMS module enabled; writing 1b to this bit clears RMS_RESULT resgiters and initiates new RMS computation. 6 CRC_EN R/W 0b Enable or disable the CRC on device interface. 0b = CRC module disabled. 1b = CRC appended to data output. CRC check is enabled on incoming data. 5 STATS_EN R/W 0b Enable or disable the statistics module to update minimum, maximum, and latest output code registers. 0b = Statistics registers are not updated. 1b = Clear statistics registers and conitnue updating with new conversion results. 4 DWC_EN R/W 0b Enable or disable the digital window comparator. 0b = Reset or disable the digital window comparator. 1b = Enable the digital window comparator. 3 CNVST W 0b Control start conversion on selected analog input. Readback of this bit returns 0b. 0b = Normal operation; conversions start on the 9th falling edge of I2C frame. Device stretches SCL until end of conversion or completion of averaging. 1b = Initiate start of conversion. Device does not stretch SCL until end of conversion or completion of averaging. 2 CH_RST R/W 0b Force all channels to be analog inputs. 0b = Normal operation. 1b = All channels are configured as analog inputs irrespective of configuration in other registers. 1 CAL R/W 0b Calibrate ADC offset. 0b = Normal operation. 1b = ADC offset is calibrated. After calibration is complete, this bit is set to 0b. 0 RST W 0b Software reset all registers to default values. 0b = Normal operation. 1b = Device is reset. After reset is complete, this bit is set to 0b and BOR bit is set to 1b. 8.6.3 DATA_CFG Register (Address = 0x2) [reset = 0x0] DATA_CFG is shown in Figure 40 and described in Table 14. Return to the Summary Table. 34 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Figure 40. DATA_CFG Register 7 FIX_PAT R/W-0b 6 RESERVED R-0b 5 4 APPEND_STATUS[1:0] R/W-0b 3 2 1 0 RESERVED R-0b Table 14. DATA_CFG Register Field Descriptions Bit 7 Field Type Reset Description FIX_PAT R/W 0b Device will output fixed data bits which can be helpful for debugging communication with the device. 0b = Normal operation. 1b = Device will output fixed code 0xA5A repeatitively when reading ADC data. 6 5-4 RESERVED R 0b Reserved. Reads return 0. APPEND_STATUS[1:0] R/W 0b Append 4-bit channel ID or status flags to output data. 0b = Channel ID and status flags are not appended to ADC data. 1b = 4-bit channel ID is appended to ADC data. 10b = 4-bit status flags are appended to ADC data. 11b = Reserved. 3-0 RESERVED R 0b Reserved. Reads return 0. 8.6.4 OSR_CFG Register (Address = 0x3) [reset = 0x0] OSR_CFG is shown in Figure 41 and described in Table 15. Return to the Summary Table. Figure 41. OSR_CFG Register 7 6 5 RESERVED R-0b 4 3 2 1 OSR[2:0] R/W-0b 0 Table 15. OSR_CFG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0b Reserved. Reads return 0. 2-0 OSR[2:0] R/W 0b Selects the oversampling ratio for ADC conversion result. 0b = No averaging 1b = 2 samples 10b = 4 samples 11b = 8 samples 100b = 16 samples 101b = 32 samples 110b = 64 samples 111b = 128 samples 8.6.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x0] OPMODE_CFG is shown in Figure 42 and described in Table 16. Return to the Summary Table. Figure 42. OPMODE_CFG Register 7 CONV_ON_ER R R/W-0b 6 5 CONV_MODE[1:0] 4 OSC_SEL R/W-0b R/W-0b 3 2 1 0 CLK_DIV[3:0] R/W-0b Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 35 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 16. OPMODE_CFG Register Field Descriptions Bit 7 Field Type Reset Description CONV_ON_ERR R/W 0b Control continuation of autonomous modes if CRC error is detected on communication interface. 0b = If CRC error is detected, device continues channel sequencing and pin configuration is retained. See the CRC_ERR_IN bit for more details. 1b = If CRC error is detected, device changes all channels to analog inputs and channel sequencing is paused until CRC_ERR_IN bit is set to 0b. After clearing CRC_ERR_IN flag, device resumes channel sequencing and pin confguration is restored. 6-5 CONV_MODE[1:0] R/W 0b These bits set the mode of conversion of the ADC. 0b = Manual mode; conversions are initiated by the host. 1b = Autonomous mode; conversions are initiated by the internal state machine. 4 OSC_SEL R/W 0b Selects the oscillator for internal timing generation. 0b = High-speed oscillator. 1b = Low-power oscillator. 3-0 CLK_DIV[3:0] R/W 0b Sampling speed control in autonomous monitoring mode (CONV_MODE = 01b). See the section on oscillator and timing control for details. 8.6.6 PIN_CFG Register (Address = 0x5) [reset = 0x0] PIN_CFG is shown in Figure 43 and described in Table 17. Return to the Summary Table. Figure 43. PIN_CFG Register 7 6 5 4 3 2 1 0 PIN_CFG[7:0] R/W-0b Table 17. PIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 PIN_CFG[7:0] R/W 0b Configure device channels AIN/GPIO[7:0] as analog inputs or GPIOs. 0b = Channel is configured as analog input. 1b = Channel is configured as GPIO. 8.6.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0] GPIO_CFG is shown in Figure 44 and described in Table 18. Return to the Summary Table. Figure 44. GPIO_CFG Register 7 6 5 4 3 2 1 0 GPIO_CFG[7:0] R/W-0b Table 18. GPIO_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 GPIO_CFG[7:0] R/W 0b Configure GPIO[7:0] as either digital inputs or digital outputs. 0b = GPIO is configured as digital input. 1b = GPIO is configured as digital output. 36 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.6.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0] GPO_DRIVE_CFG is shown in Figure 45 and described in Table 19. Return to the Summary Table. Figure 45. GPO_DRIVE_CFG Register 7 6 5 4 3 GPO_DRIVE_CFG[7:0] R/W-0b 2 1 0 Table 19. GPO_DRIVE_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 GPO_DRIVE_CFG[7:0] R/W 0b Configure digital outputs GPO[7:0] as either open-drain or push-pull outputs. 0b = Digital output is open-drain; connect external pullup resistor. 1b = Pushpull driver is used for digital output. 8.6.9 GPO_VALUE Register (Address = 0xB) [reset = 0x0] GPO_VALUE is shown in Figure 46 and described in Table 20. Return to the Summary Table. Figure 46. GPO_VALUE Register 7 6 5 4 3 GPO_VALUE[7:0] R/W-0b 2 1 0 Table 20. GPO_VALUE Register Field Descriptions Bit Field Type Reset Description 7-0 GPO_VALUE[7:0] R/W 0b Logic level to be set on digital outputs GPO[7:0]. 0b = Digital output set to logic 0. 1b = Digital output set to logic 1. 8.6.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0] GPI_VALUE is shown in Figure 47 and described in Table 21. Return to the Summary Table. Figure 47. GPI_VALUE Register 7 6 5 4 3 GPI_VALUE[7:0] R-0b 2 1 0 Table 21. GPI_VALUE Register Field Descriptions Bit Field Type Reset Description 7-0 GPI_VALUE[7:0] R 0b Readback the logic level on GPIO[7:0]. 0b = GPIO is at logic 0. 1b = GPIO is at logic 1. 8.6.11 ZCD_BLANKING_CFG Register (Address = 0xF) [reset = 0x0] ZCD_BLANKING_CFG is shown in Figure 48 and described in Table 22. Return to the Summary Table. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 37 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Figure 48. ZCD_BLANKING_CFG Register 7 MULT_EN R/W-0b 6 5 4 3 ZCD_BLANKING[6:0] R/W-0b 2 1 0 Table 22. ZCD_BLANKING_CFG Register Field Descriptions Bit 7 Field Type Reset Description MULT_EN R/W 0b Multiplier enable bit for the ZCD_BLANKING field. 0b = Blanking count = ZCD_BLANKING 1b = Blanking count = ZCD_BLANKING x 8 6-0 ZCD_BLANKING[6:0] R/W 0b This field defines the number of analog conversions, of the ZCD channel, which must be ignored for generating next ZCD event. The counting starts from ZCD event detection. 8.6.12 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0] SEQUENCE_CFG is shown in Figure 49 and described in Table 23. Return to the Summary Table. Figure 49. SEQUENCE_CFG Register 7 6 RESERVED R-0b 5 4 SEQ_START R/W-0b 3 2 RESERVED R-0b 1 0 SEQ_MODE[1:0] R/W-0b Table 23. SEQUENCE_CFG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0b Reserved. Reads return 0. 4 SEQ_START R/W 0b Control for start of channel sequence when using auto sequence mode (SEQ_MODE = 01b). 0b = Stop channel sequencing. 1b = Start channel sequencing in ascending order for channels enabled in AUTO_SEQ_CH_SEL register. 3-2 RESERVED R 0b Reserved. Reads return 0. 1-0 SEQ_MODE[1:0] R/W 0b Selects the mode of scanning of analog input channels. 0b = Manual sequence mode; channel selected by MANUAL_CHID field. 1b = Auto sequence mode; channel selected by internal channel sequencer. 10b = Reserved. 11b = Reserved. 8.6.13 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0] CHANNEL_SEL is shown in Figure 50 and described in Table 24. Return to the Summary Table. Figure 50. CHANNEL_SEL Register 7 6 5 4 3 ZCD_CHID[3:0] R/W-0b 38 Submit Documentation Feedback 2 1 MANUAL_CHID[3:0] R/W-0b 0 Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 24. CHANNEL_SEL Register Field Descriptions Bit Field Type Reset Description 7-4 ZCD_CHID[3:0] R/W 0b Input channel to treat as ZCD input. If the selected channel is configured as an analog input, internally generated ZCD signal is used (setup thresholds accordingly). If the selected channel is a digital input, the digital signal on this channel is directly used as ZCD signal. 3-0 MANUAL_CHID[3:0] R/W 0b In manual mode (SEQ_MODE = 00b), this field contains the 4-bit channel ID of the analog input channel for next ADC conversion. For valid ADC data, the selected channel must not be configured as GPIO in PIN_CFG register. 0b = AIN0 1b = AIN1 10b = AIN2 11b = AIN3 100b = AIN4 101b = AIN5 110b = AIN6 111b = AIN7 1000b = Reserved. 8.6.14 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0] AUTO_SEQ_CH_SEL is shown in Figure 51 and described in Table 25. Return to the Summary Table. Figure 51. AUTO_SEQ_CH_SEL Register 7 6 5 4 3 AUTO_SEQ_CH_SEL[7:0] R/W-0b 2 1 0 Table 25. AUTO_SEQ_CH_SEL Register Field Descriptions Bit Field Type 7-0 AUTO_SEQ_CH_SEL[7:0] R/W Reset Description 0b Select analog input channels AIN[7:0] in for auto sequencing mode. 0b = Analog input channel is not enabled in scanning sequence. 1b = Analog input channel is enabled in scanning sequence. 8.6.15 ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0] ALERT_CH_SEL is shown in Figure 52 and described in Table 26. Return to the Summary Table. Figure 52. ALERT_CH_SEL Register 7 6 5 4 3 ALERT_CH_SEL[7:0] R/W-0b 2 1 0 Table 26. ALERT_CH_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 ALERT_CH_SEL[7:0] R/W 0b Select channels for which the alert flags can assert the ALERT pin. 0b = Alert flags for this channel do not assert the ALERT pin. 1b = Alert flags for this channel assert the ALERT pin. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 39 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.6.16 ALERT_MAP Register (Address = 0x16) [reset = 0x0] ALERT_MAP is shown in Figure 53 and described in Table 27. Return to the Summary Table. Figure 53. ALERT_MAP Register 7 6 5 4 3 2 RESERVED R-0b 1 ALERT_RMS R/W-0b 0 ALERT_CRCIN R/W-0b Table 27. ALERT_MAP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0b Reserved. Reads return 0. 1 ALERT_RMS R/W 0b Enable or disable the notification on the ALERT pin based on the status of RMS computation (RMS_DONE = 1b). 0b = ALERT pin is not asserted when RMS_DONE =1b. 1b = ALERT pin is asserted when RMS_DONE = 1b. Clear RMS_DONE flag to deassert the ALERT pin. 0 ALERT_CRCIN R/W 0b Enable or disable the notification on the ALERT pin for CRC error on input data (CRCERR_IN = 1b). 0b = ALERT pin is not asserted when CRCERR_IN = 1b. 1b = ALERT pin is asserted when CRCERR_IN = 1b. Clear CRCERR_IN for deasserting the ALERT pin. 8.6.17 ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0] ALERT_PIN_CFG is shown in Figure 54 and described in Table 28. Return to the Summary Table. Figure 54. ALERT_PIN_CFG Register 7 6 5 RESERVED R-0b 4 3 2 ALERT_DRIVE R/W-0b 1 0 ALERT_LOGIC[1:0] R/W-0b Table 28. ALERT_PIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0b Reserved. Reads return 0. ALERT_DRIVE R/W 0b Configure output drive of the ALERT pin. 2 0b = Open-drain output. Connect external pullup resistor. 1b = Push-pull output. 1-0 ALERT_LOGIC[1:0] R/W 0b Configure how the ALERT pin is asserted. 0b = Active low. 1b = Active high. 10b = Pulsed low (one logic low pulse one time per alert flag). 11b = Pulsed high (one logic high pulse one time per alert flag). 8.6.18 EVENT_FLAG Register (Address = 0x18) [reset = 0x0] EVENT_FLAG is shown in Figure 55 and described in Table 29. Return to the Summary Table. 40 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Figure 55. EVENT_FLAG Register 7 6 5 4 3 EVENT_FLAG[7:0] R-0b 2 1 0 Table 29. EVENT_FLAG Register Field Descriptions Bit Field Type Reset Description 7-0 EVENT_FLAG[7:0] R 0b Alert flags indicating digital window comparator status for CH[7:0]. Clear individual bits of EVENT_HIGH_FLAG and EVENT_LOW_FLAG registers to clear the corresponding alert flag. 0b = Event condition not detected. 1b = Event condition detected. 8.6.19 EVENT_HIGH_FLAG Register (Address = 0x1A) [reset = 0x0] EVENT_HIGH_FLAG is shown in Figure 56 and described in Table 30. Return to the Summary Table. Figure 56. EVENT_HIGH_FLAG Register 7 6 5 4 3 EVENT_HIGH_FLAG[7:0] R/W-0b 2 1 0 Table 30. EVENT_HIGH_FLAG Register Field Descriptions Bit Field Type Reset Description 7-0 EVENT_HIGH_FLAG[7:0] R/W 0b Alert flag corresponding to high threshold of analog input or logic 1 on digital input on CH[7:0]. Write 1b to clear this flag. 0b = No alert condition detected. 1b = Either high threshold was exceeded (analog input) or logic 1 was detected (digital input). 8.6.20 EVENT_LOW_FLAG Register (Address = 0x1C) [reset = 0x0] EVENT_LOW_FLAG is shown in Figure 57 and described in Table 31. Return to the Summary Table. Figure 57. EVENT_LOW_FLAG Register 7 6 5 4 3 EVENT_LOW_FLAG[7:0] R/W-0b 2 1 0 Table 31. EVENT_LOW_FLAG Register Field Descriptions Bit Field Type Reset Description 7-0 EVENT_LOW_FLAG[7:0] R/W 0b Alert flag corresponding to low threshold of analog input or logic 0 on digital input on CH[7:0]. Write 1b to clear this flag. 0b = No Event condition detected. 1b = Either low threshold was exceeded (analog input) or logic 0 was detected (digital input). 8.6.21 EVENT_RGN Register (Address = 0x1E) [reset = 0x0] EVENT_RGN is shown in Figure 58 and described in Table 32. Return to the Summary Table. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 41 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Figure 58. EVENT_RGN Register 7 6 5 4 3 EVENT_RGN[7:0] R/W-0b 2 1 0 Table 32. EVENT_RGN Register Field Descriptions Bit Field Type Reset Description 7-0 EVENT_RGN[7:0] R/W 0b Choice of region used in monitoring analog/digital inputs CH[7:0]. 0b = Alert flag is set if: (conversion result < low threshold) or (conversion result > high threshold). For digital inputs, logic 1 sets the alert flag. 1b = Alert flag is set if: (low threshold > conversion result < high threshold). For digital inputs, logic 0 sets the alert flag. 8.6.22 HYSTERESIS_CH0 Register (Address = 0x20) [reset = 0xF0] HYSTERESIS_CH0 is shown in Figure 59 and described in Table 33. Return to the Summary Table. Figure 59. HYSTERESIS_CH0 Register 7 6 5 HIGH_THRESHOLD_CH0_LSB[3:0] R/W-1111b 4 3 2 1 HYSTERESIS_CH0[3:0] R/W-0b 0 Table 33. HYSTERESIS_CH0 Register Field Descriptions Bit Field Reset Description 7-4 HIGH_THRESHOLD_CH0 R/W _LSB[3:0] Type 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 HYSTERESIS_CH0[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.23 HIGH_TH_CH0 Register (Address = 0x21) [reset = 0xFF] HIGH_TH_CH0 is shown in Figure 60 and described in Table 34. Return to the Summary Table. Figure 60. HIGH_TH_CH0 Register 7 6 5 4 3 HIGH_THRESHOLD_CH0_MSB[7:0] R/W-11111111b 2 1 0 Table 34. HIGH_TH_CH0 Register Field Descriptions Bit Field 7-0 HIGH_THRESHOLD_CH0 R/W _MSB[7:0] Type Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.24 EVENT_COUNT_CH0 Register (Address = 0x22) [reset = 0x0] EVENT_COUNT_CH0 is shown in Figure 61 and described in Table 35. Return to the Summary Table. 42 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Figure 61. EVENT_COUNT_CH0 Register 7 6 5 LOW_THRESHOLD_CH0_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH0[3:0] R/W-0b 0 Table 35. EVENT_COUNT_CH0 Register Field Descriptions Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH0 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 EVENT_COUNT_CH0[3:0 R/W ] 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.25 LOW_TH_CH0 Register (Address = 0x23) [reset = 0x0] LOW_TH_CH0 is shown in Figure 62 and described in Table 36. Return to the Summary Table. Figure 62. LOW_TH_CH0 Register 7 6 5 4 3 LOW_THRESHOLD_CH0_MSB[7:0] R/W-0b 2 1 0 Table 36. LOW_TH_CH0 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH0 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.26 HYSTERESIS_CH1 Register (Address = 0x24) [reset = 0xF0] HYSTERESIS_CH1 is shown in Figure 63 and described in Table 37. Return to the Summary Table. Figure 63. HYSTERESIS_CH1 Register 7 6 5 HIGH_THRESHOLD_CH1_LSB[3:0] R/W-1111b 4 3 2 1 HYSTERESIS_CH1[3:0] R/W-0b 0 Table 37. HYSTERESIS_CH1 Register Field Descriptions Bit Field Reset Description 7-4 HIGH_THRESHOLD_CH1 R/W _LSB[3:0] Type 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 HYSTERESIS_CH1[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.27 HIGH_TH_CH1 Register (Address = 0x25) [reset = 0xFF] HIGH_TH_CH1 is shown in Figure 64 and described in Table 38. Return to the Summary Table. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 43 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Figure 64. HIGH_TH_CH1 Register 7 6 5 4 3 HIGH_THRESHOLD_CH1_MSB[7:0] R/W-11111111b 2 1 0 Table 38. HIGH_TH_CH1 Register Field Descriptions Bit Field Type 7-0 HIGH_THRESHOLD_CH1 R/W _MSB[7:0] Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.28 EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0] EVENT_COUNT_CH1 is shown in Figure 65 and described in Table 39. Return to the Summary Table. Figure 65. EVENT_COUNT_CH1 Register 7 6 5 LOW_THRESHOLD_CH1_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH1[3:0] R/W-0b 0 Table 39. EVENT_COUNT_CH1 Register Field Descriptions Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH1 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 EVENT_COUNT_CH1[3:0 R/W ] 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.29 LOW_TH_CH1 Register (Address = 0x27) [reset = 0x0] LOW_TH_CH1 is shown in Figure 66 and described in Table 40. Return to the Summary Table. Figure 66. LOW_TH_CH1 Register 7 6 5 4 3 LOW_THRESHOLD_CH1_MSB[7:0] R/W-0b 2 1 0 Table 40. LOW_TH_CH1 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH1 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.30 HYSTERESIS_CH2 Register (Address = 0x28) [reset = 0xF0] HYSTERESIS_CH2 is shown in Figure 67 and described in Table 41. Return to the Summary Table. Figure 67. HYSTERESIS_CH2 Register 7 44 6 5 HIGH_THRESHOLD_CH2_LSB[3:0] R/W-1111b 4 3 Submit Documentation Feedback 2 1 HYSTERESIS_CH2[3:0] R/W-0b 0 Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 41. HYSTERESIS_CH2 Register Field Descriptions Bit Field Reset Description 7-4 HIGH_THRESHOLD_CH2 R/W _LSB[3:0] Type 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 HYSTERESIS_CH2[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.31 HIGH_TH_CH2 Register (Address = 0x29) [reset = 0xFF] HIGH_TH_CH2 is shown in Figure 68 and described in Table 42. Return to the Summary Table. Figure 68. HIGH_TH_CH2 Register 7 6 5 4 3 HIGH_THRESHOLD_CH2_MSB[7:0] R/W-11111111b 2 1 0 Table 42. HIGH_TH_CH2 Register Field Descriptions Bit Field 7-0 HIGH_THRESHOLD_CH2 R/W _MSB[7:0] Type Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.32 EVENT_COUNT_CH2 Register (Address = 0x2A) [reset = 0x0] EVENT_COUNT_CH2 is shown in Figure 69 and described in Table 43. Return to the Summary Table. Figure 69. EVENT_COUNT_CH2 Register 7 6 5 LOW_THRESHOLD_CH2_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH2[3:0] R/W-0b 0 Table 43. EVENT_COUNT_CH2 Register Field Descriptions Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH2 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 EVENT_COUNT_CH2[3:0 R/W ] 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.33 LOW_TH_CH2 Register (Address = 0x2B) [reset = 0x0] LOW_TH_CH2 is shown in Figure 70 and described in Table 44. Return to the Summary Table. Figure 70. LOW_TH_CH2 Register 7 6 5 4 3 LOW_THRESHOLD_CH2_MSB[7:0] R/W-0b 2 1 0 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 45 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 44. LOW_TH_CH2 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH2 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.34 HYSTERESIS_CH3 Register (Address = 0x2C) [reset = 0xF0] HYSTERESIS_CH3 is shown in Figure 71 and described in Table 45. Return to the Summary Table. Figure 71. HYSTERESIS_CH3 Register 7 6 5 HIGH_THRESHOLD_CH3_LSB[3:0] R/W-1111b 4 3 2 1 HYSTERESIS_CH3[3:0] R/W-0b 0 Table 45. HYSTERESIS_CH3 Register Field Descriptions Bit Field 7-4 3-0 Type Reset Description HIGH_THRESHOLD_CH3 R/W _LSB[3:0] 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. HYSTERESIS_CH3[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.35 HIGH_TH_CH3 Register (Address = 0x2D) [reset = 0xFF] HIGH_TH_CH3 is shown in Figure 72 and described in Table 46. Return to the Summary Table. Figure 72. HIGH_TH_CH3 Register 7 6 5 4 3 HIGH_THRESHOLD_CH3_MSB[7:0] R/W-11111111b 2 1 0 Table 46. HIGH_TH_CH3 Register Field Descriptions Bit Field 7-0 HIGH_THRESHOLD_CH3 R/W _MSB[7:0] Type Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.36 EVENT_COUNT_CH3 Register (Address = 0x2E) [reset = 0x0] EVENT_COUNT_CH3 is shown in Figure 73 and described in Table 47. Return to the Summary Table. Figure 73. EVENT_COUNT_CH3 Register 7 6 5 LOW_THRESHOLD_CH3_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH3[3:0] R/W-0b 0 Table 47. EVENT_COUNT_CH3 Register Field Descriptions 46 Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH3 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 47. EVENT_COUNT_CH3 Register Field Descriptions (continued) Bit Field 3-0 EVENT_COUNT_CH3[3:0 R/W ] Type Reset Description 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.37 LOW_TH_CH3 Register (Address = 0x2F) [reset = 0x0] LOW_TH_CH3 is shown in Figure 74 and described in Table 48. Return to the Summary Table. Figure 74. LOW_TH_CH3 Register 7 6 5 4 3 LOW_THRESHOLD_CH3_MSB[7:0] R/W-0b 2 1 0 Table 48. LOW_TH_CH3 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH3 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.38 HYSTERESIS_CH4 Register (Address = 0x30) [reset = 0xF0] HYSTERESIS_CH4 is shown in Figure 75 and described in Table 49. Return to the Summary Table. Figure 75. HYSTERESIS_CH4 Register 7 6 5 HIGH_THRESHOLD_CH4_LSB[3:0] R/W-1111b 4 3 2 1 HYSTERESIS_CH4[3:0] R/W-0b 0 Table 49. HYSTERESIS_CH4 Register Field Descriptions Bit Field 7-4 3-0 Type Reset Description HIGH_THRESHOLD_CH4 R/W _LSB[3:0] 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. HYSTERESIS_CH4[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.39 HIGH_TH_CH4 Register (Address = 0x31) [reset = 0xFF] HIGH_TH_CH4 is shown in Figure 76 and described in Table 50. Return to the Summary Table. Figure 76. HIGH_TH_CH4 Register 7 6 5 4 3 HIGH_THRESHOLD_CH4_MSB[7:0] R/W-11111111b 2 1 0 Table 50. HIGH_TH_CH4 Register Field Descriptions Bit Field 7-0 HIGH_THRESHOLD_CH4 R/W _MSB[7:0] Type Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 47 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.6.40 EVENT_COUNT_CH4 Register (Address = 0x32) [reset = 0x0] EVENT_COUNT_CH4 is shown in Figure 77 and described in Table 51. Return to the Summary Table. Figure 77. EVENT_COUNT_CH4 Register 7 6 5 LOW_THRESHOLD_CH4_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH4[3:0] R/W-0b 0 Table 51. EVENT_COUNT_CH4 Register Field Descriptions Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH4 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 EVENT_COUNT_CH4[3:0 R/W ] 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.41 LOW_TH_CH4 Register (Address = 0x33) [reset = 0x0] LOW_TH_CH4 is shown in Figure 78 and described in Table 52. Return to the Summary Table. Figure 78. LOW_TH_CH4 Register 7 6 5 4 3 LOW_THRESHOLD_CH4_MSB[7:0] R/W-0b 2 1 0 Table 52. LOW_TH_CH4 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH4 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.42 HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0] HYSTERESIS_CH5 is shown in Figure 79 and described in Table 53. Return to the Summary Table. Figure 79. HYSTERESIS_CH5 Register 7 6 5 HIGH_THRESHOLD_CH5_LSB[3:0] R/W-1111b 4 3 2 1 HYSTERESIS_CH5[3:0] R/W-0b 0 Table 53. HYSTERESIS_CH5 Register Field Descriptions Bit Field 7-4 3-0 Type Reset Description HIGH_THRESHOLD_CH5 R/W _LSB[3:0] 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. HYSTERESIS_CH5[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.43 HIGH_TH_CH5 Register (Address = 0x35) [reset = 0xFF] HIGH_TH_CH5 is shown in Figure 80 and described in Table 54. Return to the Summary Table. 48 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Figure 80. HIGH_TH_CH5 Register 7 6 5 4 3 HIGH_THRESHOLD_CH5_MSB[7:0] R/W-11111111b 2 1 0 Table 54. HIGH_TH_CH5 Register Field Descriptions Bit Field Type 7-0 HIGH_THRESHOLD_CH5 R/W _MSB[7:0] Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.44 EVENT_COUNT_CH5 Register (Address = 0x36) [reset = 0x0] EVENT_COUNT_CH5 is shown in Figure 81 and described in Table 55. Return to the Summary Table. Figure 81. EVENT_COUNT_CH5 Register 7 6 5 LOW_THRESHOLD_CH5_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH5[3:0] R/W-0b 0 Table 55. EVENT_COUNT_CH5 Register Field Descriptions Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH5 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 EVENT_COUNT_CH5[3:0 R/W ] 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.45 LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0] LOW_TH_CH5 is shown in Figure 82 and described in Table 56. Return to the Summary Table. Figure 82. LOW_TH_CH5 Register 7 6 5 4 3 LOW_THRESHOLD_CH5_MSB[7:0] R/W-0b 2 1 0 Table 56. LOW_TH_CH5 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH5 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.46 HYSTERESIS_CH6 Register (Address = 0x38) [reset = 0xF0] HYSTERESIS_CH6 is shown in Figure 83 and described in Table 57. Return to the Summary Table. Figure 83. HYSTERESIS_CH6 Register 7 6 5 HIGH_THRESHOLD_CH6_LSB[3:0] R/W-1111b 4 3 2 1 HYSTERESIS_CH6[3:0] R/W-0b 0 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 49 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 57. HYSTERESIS_CH6 Register Field Descriptions Bit Field Reset Description 7-4 HIGH_THRESHOLD_CH6 R/W _LSB[3:0] Type 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 HYSTERESIS_CH6[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.47 HIGH_TH_CH6 Register (Address = 0x39) [reset = 0xFF] HIGH_TH_CH6 is shown in Figure 84 and described in Table 58. Return to the Summary Table. Figure 84. HIGH_TH_CH6 Register 7 6 5 4 3 HIGH_THRESHOLD_CH6_MSB[7:0] R/W-11111111b 2 1 0 Table 58. HIGH_TH_CH6 Register Field Descriptions Bit Field 7-0 HIGH_THRESHOLD_CH6 R/W _MSB[7:0] Type Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.48 EVENT_COUNT_CH6 Register (Address = 0x3A) [reset = 0x0] EVENT_COUNT_CH6 is shown in Figure 85 and described in Table 59. Return to the Summary Table. Figure 85. EVENT_COUNT_CH6 Register 7 6 5 LOW_THRESHOLD_CH6_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH6[3:0] R/W-0b 0 Table 59. EVENT_COUNT_CH6 Register Field Descriptions Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH6 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. 3-0 EVENT_COUNT_CH6[3:0 R/W ] 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.49 LOW_TH_CH6 Register (Address = 0x3B) [reset = 0x0] LOW_TH_CH6 is shown in Figure 86 and described in Table 60. Return to the Summary Table. Figure 86. LOW_TH_CH6 Register 7 50 6 5 4 3 LOW_THRESHOLD_CH6_MSB[7:0] R/W-0b Submit Documentation Feedback 2 1 0 Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 60. LOW_TH_CH6 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH6 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.50 HYSTERESIS_CH7 Register (Address = 0x3C) [reset = 0xF0] HYSTERESIS_CH7 is shown in Figure 87 and described in Table 61. Return to the Summary Table. Figure 87. HYSTERESIS_CH7 Register 7 6 5 HIGH_THRESHOLD_CH7_LSB[3:0] R/W-1111b 4 3 2 1 HYSTERESIS_CH7[3:0] R/W-0b 0 Table 61. HYSTERESIS_CH7 Register Field Descriptions Bit Field 7-4 3-0 Type Reset Description HIGH_THRESHOLD_CH7 R/W _LSB[3:0] 1111b Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. HYSTERESIS_CH7[3:0] 0b 4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] R/W 8.6.51 HIGH_TH_CH7 Register (Address = 0x3D) [reset = 0xFF] HIGH_TH_CH7 is shown in Figure 88 and described in Table 62. Return to the Summary Table. Figure 88. HIGH_TH_CH7 Register 7 6 5 4 3 HIGH_THRESHOLD_CH7_MSB[7:0] R/W-11111111b 2 1 0 Table 62. HIGH_TH_CH7 Register Field Descriptions Bit Field 7-0 HIGH_THRESHOLD_CH7 R/W _MSB[7:0] Type Reset Description 11111111b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.52 EVENT_COUNT_CH7 Register (Address = 0x3E) [reset = 0x0] EVENT_COUNT_CH7 is shown in Figure 89 and described in Table 63. Return to the Summary Table. Figure 89. EVENT_COUNT_CH7 Register 7 6 5 LOW_THRESHOLD_CH7_LSB[3:0] R/W-0b 4 3 2 1 EVENT_COUNT_CH7[3:0] R/W-0b 0 Table 63. EVENT_COUNT_CH7 Register Field Descriptions Bit Field Type Reset Description 7-4 LOW_THRESHOLD_CH7 _LSB[3:0] R/W 0b Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 51 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 63. EVENT_COUNT_CH7 Register Field Descriptions (continued) Bit Field 3-0 EVENT_COUNT_CH7[3:0 R/W ] Type Reset Description 0b Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. 8.6.53 LOW_TH_CH7 Register (Address = 0x3F) [reset = 0x0] LOW_TH_CH7 is shown in Figure 90 and described in Table 64. Return to the Summary Table. Figure 90. LOW_TH_CH7 Register 7 6 5 4 3 LOW_THRESHOLD_CH7_MSB[7:0] R/W-0b 2 1 0 Table 64. LOW_TH_CH7 Register Field Descriptions Bit Field Type Reset Description 7-0 LOW_THRESHOLD_CH7 _MSB[7:0] R/W 0b MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. 8.6.54 MAX_CH0_LSB Register (Address = 0x60) [reset = 0x0] MAX_CH0_LSB is shown in Figure 91 and described in Table 65. Return to the Summary Table. Figure 91. MAX_CH0_LSB Register 7 6 5 4 3 MAX_VALUE_CH0_LSB[7:0] R-0b 2 1 0 Table 65. MAX_CH0_LSB Register Field Descriptions Bit Field Type 7-0 MAX_VALUE_CH0_LSB[7 R :0] Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.55 MAX_CH0_MSB Register (Address = 0x61) [reset = 0x0] MAX_CH0_MSB is shown in Figure 92 and described in Table 66. Return to the Summary Table. Figure 92. MAX_CH0_MSB Register 7 6 5 4 3 MAX_VALUE_CH0_MSB[7:0] R-0b 2 1 0 Table 66. MAX_CH0_MSB Register Field Descriptions 52 Bit Field Type Reset Description 7-0 MAX_VALUE_CH0_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.6.56 MAX_CH1_LSB Register (Address = 0x62) [reset = 0x0] MAX_CH1_LSB is shown in Figure 93 and described in Table 67. Return to the Summary Table. Figure 93. MAX_CH1_LSB Register 7 6 5 4 3 MAX_VALUE_CH1_LSB[7:0] R-0b 2 1 0 Table 67. MAX_CH1_LSB Register Field Descriptions Bit Field 7-0 MAX_VALUE_CH1_LSB[7 R :0] Type Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.57 MAX_CH1_MSB Register (Address = 0x63) [reset = 0x0] MAX_CH1_MSB is shown in Figure 94 and described in Table 68. Return to the Summary Table. Figure 94. MAX_CH1_MSB Register 7 6 5 4 3 MAX_VALUE_CH1_MSB[7:0] R-0b 2 1 0 Table 68. MAX_CH1_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 MAX_VALUE_CH1_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.58 MAX_CH2_LSB Register (Address = 0x64) [reset = 0x0] MAX_CH2_LSB is shown in Figure 95 and described in Table 69. Return to the Summary Table. Figure 95. MAX_CH2_LSB Register 7 6 5 4 3 MAX_VALUE_CH2_LSB[7:0] R-0b 2 1 0 Table 69. MAX_CH2_LSB Register Field Descriptions Bit Field Type 7-0 MAX_VALUE_CH2_LSB[7 R :0] Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.59 MAX_CH2_MSB Register (Address = 0x65) [reset = 0x0] MAX_CH2_MSB is shown in Figure 96 and described in Table 70. Return to the Summary Table. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 53 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Figure 96. MAX_CH2_MSB Register 7 6 5 4 3 MAX_VALUE_CH2_MSB[7:0] R-0b 2 1 0 Table 70. MAX_CH2_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 MAX_VALUE_CH2_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.60 MAX_CH3_LSB Register (Address = 0x66) [reset = 0x0] MAX_CH3_LSB is shown in Figure 97 and described in Table 71. Return to the Summary Table. Figure 97. MAX_CH3_LSB Register 7 6 5 4 3 MAX_VALUE_CH3_LSB[7:0] R-0b 2 1 0 Table 71. MAX_CH3_LSB Register Field Descriptions Bit Field Type 7-0 MAX_VALUE_CH3_LSB[7 R :0] Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.61 MAX_CH3_MSB Register (Address = 0x67) [reset = 0x0] MAX_CH3_MSB is shown in Figure 98 and described in Table 72. Return to the Summary Table. Figure 98. MAX_CH3_MSB Register 7 6 5 4 3 MAX_VALUE_CH3_MSB[7:0] R-0b 2 1 0 Table 72. MAX_CH3_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 MAX_VALUE_CH3_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.62 MAX_CH4_LSB Register (Address = 0x68) [reset = 0x0] MAX_CH4_LSB is shown in Figure 99 and described in Table 73. Return to the Summary Table. Figure 99. MAX_CH4_LSB Register 7 54 6 5 4 3 MAX_VALUE_CH4_LSB[7:0] R-0b Submit Documentation Feedback 2 1 0 Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 73. MAX_CH4_LSB Register Field Descriptions Bit Field 7-0 MAX_VALUE_CH4_LSB[7 R :0] Type Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.63 MAX_CH4_MSB Register (Address = 0x69) [reset = 0x0] MAX_CH4_MSB is shown in Figure 100 and described in Table 74. Return to the Summary Table. Figure 100. MAX_CH4_MSB Register 7 6 5 4 3 MAX_VALUE_CH4_MSB[7:0] R-0b 2 1 0 Table 74. MAX_CH4_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 MAX_VALUE_CH4_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.64 MAX_CH5_LSB Register (Address = 0x6A) [reset = 0x0] MAX_CH5_LSB is shown in Figure 101 and described in Table 75. Return to the Summary Table. Figure 101. MAX_CH5_LSB Register 7 6 5 4 3 MAX_VALUE_CH5_LSB[7:0] R-0b 2 1 0 Table 75. MAX_CH5_LSB Register Field Descriptions Bit Field Type 7-0 MAX_VALUE_CH5_LSB[7 R :0] Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.65 MAX_CH5_MSB Register (Address = 0x6B) [reset = 0x0] MAX_CH5_MSB is shown in Figure 102 and described in Table 76. Return to the Summary Table. Figure 102. MAX_CH5_MSB Register 7 6 5 4 3 MAX_VALUE_CH5_MSB[7:0] R-0b 2 1 0 Table 76. MAX_CH5_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 MAX_VALUE_CH5_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 55 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.6.66 MAX_CH6_LSB Register (Address = 0x6C) [reset = 0x0] MAX_CH6_LSB is shown in Figure 103 and described in Table 77. Return to the Summary Table. Figure 103. MAX_CH6_LSB Register 7 6 5 4 3 MAX_VALUE_CH6_LSB[7:0] R-0b 2 1 0 Table 77. MAX_CH6_LSB Register Field Descriptions Bit Field 7-0 MAX_VALUE_CH6_LSB[7 R :0] Type Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.67 MAX_CH6_MSB Register (Address = 0x6D) [reset = 0x0] MAX_CH6_MSB is shown in Figure 104 and described in Table 78. Return to the Summary Table. Figure 104. MAX_CH6_MSB Register 7 6 5 4 3 MAX_VALUE_CH6_MSB[7:0] R-0b 2 1 0 Table 78. MAX_CH6_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 MAX_VALUE_CH6_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.68 MAX_CH7_LSB Register (Address = 0x6E) [reset = 0x0] MAX_CH7_LSB is shown in Figure 105 and described in Table 79. Return to the Summary Table. Figure 105. MAX_CH7_LSB Register 7 6 5 4 3 MAX_VALUE_CH7_LSB[7:0] R-0b 2 1 0 Table 79. MAX_CH7_LSB Register Field Descriptions Bit Field Type 7-0 MAX_VALUE_CH7_LSB[7 R :0] Reset Description 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.69 MAX_CH7_MSB Register (Address = 0x6F) [reset = 0x0] MAX_CH7_MSB is shown in Figure 106 and described in Table 80. Return to the Summary Table. 56 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Figure 106. MAX_CH7_MSB Register 7 6 5 4 3 MAX_VALUE_CH7_MSB[7:0] R-0b 2 1 0 Table 80. MAX_CH7_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 MAX_VALUE_CH7_MSB[ 7:0] R 0b Maximum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0. 8.6.70 MIN_CH0_LSB Register (Address = 0x80) [reset = 0xFF] MIN_CH0_LSB is shown in Figure 107 and described in Table 81. Return to the Summary Table. Figure 107. MIN_CH0_LSB Register 7 6 5 4 3 MIN_VALUE_CH0_LSB[7:0] R-11111111b 2 1 0 Table 81. MIN_CH0_LSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH0_LSB[7: R 0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.71 MIN_CH0_MSB Register (Address = 0x81) [reset = 0xFF] MIN_CH0_MSB is shown in Figure 108 and described in Table 82. Return to the Summary Table. Figure 108. MIN_CH0_MSB Register 7 6 5 4 3 MIN_VALUE_CH0_MSB[7:0] R-11111111b 2 1 0 Table 82. MIN_CH0_MSB Register Field Descriptions Bit Field 7-0 MIN_VALUE_CH0_MSB[7 R :0] Type Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.72 MIN_CH1_LSB Register (Address = 0x82) [reset = 0xFF] MIN_CH1_LSB is shown in Figure 109 and described in Table 83. Return to the Summary Table. Figure 109. MIN_CH1_LSB Register 7 6 5 4 3 MIN_VALUE_CH1_LSB[7:0] R-11111111b 2 1 0 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 57 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 83. MIN_CH1_LSB Register Field Descriptions Bit Field 7-0 MIN_VALUE_CH1_LSB[7: R 0] Type Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.73 MIN_CH1_MSB Register (Address = 0x83) [reset = 0xFF] MIN_CH1_MSB is shown in Figure 110 and described in Table 84. Return to the Summary Table. Figure 110. MIN_CH1_MSB Register 7 6 5 4 3 MIN_VALUE_CH1_MSB[7:0] R-11111111b 2 1 0 Table 84. MIN_CH1_MSB Register Field Descriptions Bit Field 7-0 MIN_VALUE_CH1_MSB[7 R :0] Type Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.74 MIN_CH2_LSB Register (Address = 0x84) [reset = 0xFF] MIN_CH2_LSB is shown in Figure 111 and described in Table 85. Return to the Summary Table. Figure 111. MIN_CH2_LSB Register 7 6 5 4 3 MIN_VALUE_CH2_LSB[7:0] R-11111111b 2 1 0 Table 85. MIN_CH2_LSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH2_LSB[7: R 0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.75 MIN_CH2_MSB Register (Address = 0x85) [reset = 0xFF] MIN_CH2_MSB is shown in Figure 112 and described in Table 86. Return to the Summary Table. Figure 112. MIN_CH2_MSB Register 7 6 5 4 3 MIN_VALUE_CH2_MSB[7:0] R-11111111b 2 1 0 Table 86. MIN_CH2_MSB Register Field Descriptions 58 Bit Field Type 7-0 MIN_VALUE_CH2_MSB[7 R :0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.6.76 MIN_CH3_LSB Register (Address = 0x86) [reset = 0xFF] MIN_CH3_LSB is shown in Figure 113 and described in Table 87. Return to the Summary Table. Figure 113. MIN_CH3_LSB Register 7 6 5 4 3 MIN_VALUE_CH3_LSB[7:0] R-11111111b 2 1 0 Table 87. MIN_CH3_LSB Register Field Descriptions Bit Field 7-0 MIN_VALUE_CH3_LSB[7: R 0] Type Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.77 MIN_CH3_MSB Register (Address = 0x87) [reset = 0xFF] MIN_CH3_MSB is shown in Figure 114 and described in Table 88. Return to the Summary Table. Figure 114. MIN_CH3_MSB Register 7 6 5 4 3 MIN_VALUE_CH3_MSB[7:0] R-11111111b 2 1 0 Table 88. MIN_CH3_MSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH3_MSB[7 R :0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.78 MIN_CH4_LSB Register (Address = 0x88) [reset = 0xFF] MIN_CH4_LSB is shown in Figure 115 and described in Table 89. Return to the Summary Table. Figure 115. MIN_CH4_LSB Register 7 6 5 4 3 MIN_VALUE_CH4_LSB[7:0] R-11111111b 2 1 0 Table 89. MIN_CH4_LSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH4_LSB[7: R 0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.79 MIN_CH4_MSB Register (Address = 0x89) [reset = 0xFF] MIN_CH4_MSB is shown in Figure 116 and described in Table 90. Return to the Summary Table. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 59 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Figure 116. MIN_CH4_MSB Register 7 6 5 4 3 MIN_VALUE_CH4_MSB[7:0] R-11111111b 2 1 0 Table 90. MIN_CH4_MSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH4_MSB[7 R :0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.80 MIN_CH5_LSB Register (Address = 0x8A) [reset = 0xFF] MIN_CH5_LSB is shown in Figure 117 and described in Table 91. Return to the Summary Table. Figure 117. MIN_CH5_LSB Register 7 6 5 4 3 MIN_VALUE_CH5_LSB[7:0] R-11111111b 2 1 0 Table 91. MIN_CH5_LSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH5_LSB[7: R 0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.81 MIN_CH5_MSB Register (Address = 0x8B) [reset = 0xFF] MIN_CH5_MSB is shown in Figure 118 and described in Table 92. Return to the Summary Table. Figure 118. MIN_CH5_MSB Register 7 6 5 4 3 MIN_VALUE_CH5_MSB[7:0] R-11111111b 2 1 0 Table 92. MIN_CH5_MSB Register Field Descriptions Bit Field 7-0 MIN_VALUE_CH5_MSB[7 R :0] Type Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.82 MIN_CH6_LSB Register (Address = 0x8C) [reset = 0xFF] MIN_CH6_LSB is shown in Figure 119 and described in Table 93. Return to the Summary Table. Figure 119. MIN_CH6_LSB Register 7 60 6 5 4 3 MIN_VALUE_CH6_LSB[7:0] R-11111111b Submit Documentation Feedback 2 1 0 Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 93. MIN_CH6_LSB Register Field Descriptions Bit Field 7-0 MIN_VALUE_CH6_LSB[7: R 0] Type Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.83 MIN_CH6_MSB Register (Address = 0x8D) [reset = 0xFF] MIN_CH6_MSB is shown in Figure 120 and described in Table 94. Return to the Summary Table. Figure 120. MIN_CH6_MSB Register 7 6 5 4 3 MIN_VALUE_CH6_MSB[7:0] R-11111111b 2 1 0 Table 94. MIN_CH6_MSB Register Field Descriptions Bit Field 7-0 MIN_VALUE_CH6_MSB[7 R :0] Type Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.84 MIN_CH7_LSB Register (Address = 0x8E) [reset = 0xFF] MIN_CH7_LSB is shown in Figure 121 and described in Table 95. Return to the Summary Table. Figure 121. MIN_CH7_LSB Register 7 6 5 4 3 MIN_VALUE_CH7_LSB[7:0] R-11111111b 2 1 0 Table 95. MIN_CH7_LSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH7_LSB[7: R 0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. 8.6.85 MIN_CH7_MSB Register (Address = 0x8F) [reset = 0xFF] MIN_CH7_MSB is shown in Figure 122 and described in Table 96. Return to the Summary Table. Figure 122. MIN_CH7_MSB Register 7 6 5 4 3 MIN_VALUE_CH7_MSB[7:0] R-11111111b 2 1 0 Table 96. MIN_CH7_MSB Register Field Descriptions Bit Field Type 7-0 MIN_VALUE_CH7_MSB[7 R :0] Reset Description 11111111b Minimum code recorded on the analog input channel from the last time this register was read. Reading the register will reset the value to 0xFF. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 61 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.6.86 RECENT_CH0_LSB Register (Address = 0xA0) [reset = 0x0] RECENT_CH0_LSB is shown in Figure 123 and described in Table 97. Return to the Summary Table. Figure 123. RECENT_CH0_LSB Register 7 6 5 4 3 LAST_VALUE_CH0_LSB[7:0] R-0b 2 1 0 Table 97. RECENT_CH0_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH0_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.87 RECENT_CH0_MSB Register (Address = 0xA1) [reset = 0x0] RECENT_CH0_MSB is shown in Figure 124 and described in Table 98. Return to the Summary Table. Figure 124. RECENT_CH0_MSB Register 7 6 5 4 3 LAST_VALUE_CH0_MSB[7:0] R-0b 2 1 0 Table 98. RECENT_CH0_MSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH0_MSB R [7:0] Type Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. 8.6.88 RECENT_CH1_LSB Register (Address = 0xA2) [reset = 0x0] RECENT_CH1_LSB is shown in Figure 125 and described in Table 99. Return to the Summary Table. Figure 125. RECENT_CH1_LSB Register 7 6 5 4 3 LAST_VALUE_CH1_LSB[7:0] R-0b 2 1 0 Table 99. RECENT_CH1_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH1_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.89 RECENT_CH1_MSB Register (Address = 0xA3) [reset = 0x0] RECENT_CH1_MSB is shown in Figure 126 and described in Table 100. Return to the Summary Table. 62 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Figure 126. RECENT_CH1_MSB Register 7 6 5 4 3 LAST_VALUE_CH1_MSB[7:0] R-0b 2 1 0 Table 100. RECENT_CH1_MSB Register Field Descriptions Bit Field Type 7-0 LAST_VALUE_CH1_MSB R [7:0] Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. 8.6.90 RECENT_CH2_LSB Register (Address = 0xA4) [reset = 0x0] RECENT_CH2_LSB is shown in Figure 127 and described in Table 101. Return to the Summary Table. Figure 127. RECENT_CH2_LSB Register 7 6 5 4 3 LAST_VALUE_CH2_LSB[7:0] R-0b 2 1 0 Table 101. RECENT_CH2_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH2_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.91 RECENT_CH2_MSB Register (Address = 0xA5) [reset = 0x0] RECENT_CH2_MSB is shown in Figure 128 and described in Table 102. Return to the Summary Table. Figure 128. RECENT_CH2_MSB Register 7 6 5 4 3 LAST_VALUE_CH2_MSB[7:0] R-0b 2 1 0 Table 102. RECENT_CH2_MSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH2_MSB R [7:0] Type Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. 8.6.92 RECENT_CH3_LSB Register (Address = 0xA6) [reset = 0x0] RECENT_CH3_LSB is shown in Figure 129 and described in Table 103. Return to the Summary Table. Figure 129. RECENT_CH3_LSB Register 7 6 5 4 3 LAST_VALUE_CH3_LSB[7:0] R-0b 2 1 0 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 63 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 103. RECENT_CH3_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH3_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.93 RECENT_CH3_MSB Register (Address = 0xA7) [reset = 0x0] RECENT_CH3_MSB is shown in Figure 130 and described in Table 104. Return to the Summary Table. Figure 130. RECENT_CH3_MSB Register 7 6 5 4 3 LAST_VALUE_CH3_MSB[7:0] R-0b 2 1 0 Table 104. RECENT_CH3_MSB Register Field Descriptions Bit Field Type 7-0 LAST_VALUE_CH3_MSB R [7:0] Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. 8.6.94 RECENT_CH4_LSB Register (Address = 0xA8) [reset = 0x0] RECENT_CH4_LSB is shown in Figure 131 and described in Table 105. Return to the Summary Table. Figure 131. RECENT_CH4_LSB Register 7 6 5 4 3 LAST_VALUE_CH4_LSB[7:0] R-0b 2 1 0 Table 105. RECENT_CH4_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH4_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.95 RECENT_CH4_MSB Register (Address = 0xA9) [reset = 0x0] RECENT_CH4_MSB is shown in Figure 132 and described in Table 106. Return to the Summary Table. Figure 132. RECENT_CH4_MSB Register 7 6 5 4 3 LAST_VALUE_CH4_MSB[7:0] R-0b 2 1 0 Table 106. RECENT_CH4_MSB Register Field Descriptions 64 Bit Field 7-0 LAST_VALUE_CH4_MSB R [7:0] Type Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.6.96 RECENT_CH5_LSB Register (Address = 0xAA) [reset = 0x0] RECENT_CH5_LSB is shown in Figure 133 and described in Table 107. Return to the Summary Table. Figure 133. RECENT_CH5_LSB Register 7 6 5 4 3 LAST_VALUE_CH5_LSB[7:0] R-0b 2 1 0 Table 107. RECENT_CH5_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH5_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.97 RECENT_CH5_MSB Register (Address = 0xAB) [reset = 0x0] RECENT_CH5_MSB is shown in Figure 134 and described in Table 108. Return to the Summary Table. Figure 134. RECENT_CH5_MSB Register 7 6 5 4 3 LAST_VALUE_CH5_MSB[7:0] R-0b 2 1 0 Table 108. RECENT_CH5_MSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH5_MSB R [7:0] Type Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. 8.6.98 RECENT_CH6_LSB Register (Address = 0xAC) [reset = 0x0] RECENT_CH6_LSB is shown in Figure 135 and described in Table 109. Return to the Summary Table. Figure 135. RECENT_CH6_LSB Register 7 6 5 4 3 LAST_VALUE_CH6_LSB[7:0] R-0b 2 1 0 Table 109. RECENT_CH6_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH6_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.99 RECENT_CH6_MSB Register (Address = 0xAD) [reset = 0x0] RECENT_CH6_MSB is shown in Figure 136 and described in Table 110. Return to the Summary Table. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 65 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Figure 136. RECENT_CH6_MSB Register 7 6 5 4 3 LAST_VALUE_CH6_MSB[7:0] R-0b 2 1 0 Table 110. RECENT_CH6_MSB Register Field Descriptions Bit Field Type 7-0 LAST_VALUE_CH6_MSB R [7:0] Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. 8.6.100 RECENT_CH7_LSB Register (Address = 0xAE) [reset = 0x0] RECENT_CH7_LSB is shown in Figure 137 and described in Table 111. Return to the Summary Table. Figure 137. RECENT_CH7_LSB Register 7 6 5 4 3 LAST_VALUE_CH7_LSB[7:0] R-0b 2 1 0 Table 111. RECENT_CH7_LSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH7_LSB[ R 7:0] Type Reset Description 0b Lower 8 bits of the last conversion result for this analog input channel. 8.6.101 RECENT_CH7_MSB Register (Address = 0xAF) [reset = 0x0] RECENT_CH7_MSB is shown in Figure 138 and described in Table 112. Return to the Summary Table. Figure 138. RECENT_CH7_MSB Register 7 6 5 4 3 LAST_VALUE_CH7_MSB[7:0] R-0b 2 1 0 Table 112. RECENT_CH7_MSB Register Field Descriptions Bit Field 7-0 LAST_VALUE_CH7_MSB R [7:0] Type Reset Description 0b MSB aligned first 8 bits of the last conversion result for this analog input channel. 8.6.102 RMS_CFG Register (Address = 0xC0) [reset = 0x0] RMS_CFG is shown in Figure 139 and described in Table 113. Return to the Summary Table. Figure 139. RMS_CFG Register 7 6 5 RMS_CHID[3:0] R/W-0b 66 4 3 RESERVED R-0b Submit Documentation Feedback 2 RMS_DC_SUB R/W-0b 1 0 RMS_SAMPLES[1:0] R/W-0b Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 113. RMS_CFG Register Field Descriptions Bit Field Type Reset Description 7-4 RMS_CHID[3:0] R/W 0b Select analog input channel for RMS computation. 3 RESERVED R 0b Reserved. Reads return 0b. 2 RMS_DC_SUB R/W 0b Subtract DC component from the RMS result. 0b = Do not subtract DC component. 1b = Subtract DC component. 1-0 RMS_SAMPLES[1:0] R/W 0b Number of samples for computing RMS result. Additional 40 samples are required for completing RMS computation. 0b = 1024 1b = 4096 10b = 16384 11b = 65536 8.6.103 RMS_LSB Register (Address = 0xC1) [reset = 0x0] RMS_LSB is shown in Figure 140 and described in Table 114. Return to the Summary Table. Figure 140. RMS_LSB Register 7 6 5 4 3 RMS_RESULT_LSB[7:0] R-0b 2 1 0 1 0 1 0 Table 114. RMS_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 RMS_RESULT_LSB[7:0] R 0b Lower 8-bits of RMS computation result. 8.6.104 RMS_MSB Register (Address = 0xC2) [reset = 0x0] RMS_MSB is shown in Figure 141 and described in Table 115. Return to the Summary Table. Figure 141. RMS_MSB Register 7 6 5 4 3 RMS_RESULT_MSB[7:0] R-0b 2 Table 115. RMS_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 RMS_RESULT_MSB[7:0] R 0b Upper 8-bits of RMS result. 8.6.105 GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2] GPO0_TRIG_EVENT_SEL is shown in Figure 142 and described in Table 116. Return to the Summary Table. Figure 142. GPO0_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO0_TRIG_EVENT_SEL[7:0] R/W-10b 2 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 67 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 116. GPO0_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO0_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO0. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO0 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO0 output. 8.6.106 GPO1_TRIG_EVENT_SEL Register (Address = 0xC5) [reset = 0x2] GPO1_TRIG_EVENT_SEL is shown in Figure 143 and described in Table 117. Return to the Summary Table. Figure 143. GPO1_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO1_TRIG_EVENT_SEL[7:0] R/W-10b 2 1 0 Table 117. GPO1_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO1_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO1. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO1 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO1 output. 8.6.107 GPO2_TRIG_EVENT_SEL Register (Address = 0xC7) [reset = 0x2] GPO2_TRIG_EVENT_SEL is shown in Figure 144 and described in Table 118. Return to the Summary Table. Figure 144. GPO2_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO2_TRIG_EVENT_SEL[7:0] R/W-10b 2 1 0 Table 118. GPO2_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO2_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO2. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO2 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO2 output. 8.6.108 GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x2] GPO3_TRIG_EVENT_SEL is shown in Figure 145 and described in Table 119. Return to the Summary Table. 68 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Figure 145. GPO3_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO3_TRIG_EVENT_SEL[7:0] R/W-10b 2 1 0 Table 119. GPO3_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO3_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO3. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO3 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO3 output. 8.6.109 GPO4_TRIG_EVENT_SEL Register (Address = 0xCB) [reset = 0x2] GPO4_TRIG_EVENT_SEL is shown in Figure 146 and described in Table 120. Return to the Summary Table. Figure 146. GPO4_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO4_TRIG_EVENT_SEL[7:0] R/W-10b 2 1 0 Table 120. GPO4_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO4_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO4. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO4 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO4 output. 8.6.110 GPO5_TRIG_EVENT_SEL Register (Address = 0xCD) [reset = 0x2] GPO5_TRIG_EVENT_SEL is shown in Figure 147 and described in Table 121. Return to the Summary Table. Figure 147. GPO5_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO0_TRIG_EVENT_SEL[7:0] R/W-10b 2 1 0 Table 121. GPO5_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO0_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO5. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO5 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO5 output. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 69 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 8.6.111 GPO6_TRIG_EVENT_SEL Register (Address = 0xCF) [reset = 0x2] GPO6_TRIG_EVENT_SEL is shown in Figure 148 and described in Table 122. Return to the Summary Table. Figure 148. GPO6_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO6_TRIG_EVENT_SEL[7:0] R/W-10b 2 1 0 Table 122. GPO6_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO6_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO6. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO6 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO6 output. 8.6.112 GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x2] GPO7_TRIG_EVENT_SEL is shown in Figure 149 and described in Table 123. Return to the Summary Table. Figure 149. GPO7_TRIG_EVENT_SEL Register 7 6 5 4 3 GPO7_TRIG_EVENT_SEL[7:0] R/W-10b 2 1 0 Table 123. GPO7_TRIG_EVENT_SEL Register Field Descriptions Bit Field Type Reset Description 7-0 GPO7_TRIG_EVENT_SE L[7:0] R/W 10b Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger an event based update on GPO7. 0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO7 output. 1b = Alert flags for the AIN/GPIO corresponding to this bit do trigger GPO7 output. 8.6.113 GPO_VALUE_ZCD_CFG_CH0_CH3 Register (Address = 0xE3) [reset = 0x0] GPO_VALUE_ZCD_CFG_CH0_CH3 is shown in Figure 150 and described in Table 124. Return to the Summary Table. Figure 150. GPO_VALUE_ZCD_CFG_CH0_CH3 Register 7 6 GPO_VALUE_ZCD_CFG_CH3[1 :0] R/W-0b 70 5 4 GPO_VALUE_ZCD_CFG_CH2[1 :0] R/W-0b 3 2 GPO_VALUE_ZCD_CFG_CH1[1 :0] R/W-0b Submit Documentation Feedback 1 0 GPO_VALUE_ZCD_CFG_CH0[1 :0] R/W-0b Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Table 124. GPO_VALUE_ZCD_CFG_CH0_CH3 Register Field Descriptions Bit Field Type Reset Description 7-6 GPO_VALUE_ZCD_CFG _CH3[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges 5-4 GPO_VALUE_ZCD_CFG _CH2[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges 3-2 GPO_VALUE_ZCD_CFG _CH1[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges 1-0 GPO_VALUE_ZCD_CFG _CH0[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges 8.6.114 GPO_VALUE_ZCD_CFG_CH4_CH7 Register (Address = 0xE4) [reset = 0x0] GPO_VALUE_ZCD_CFG_CH4_CH7 is shown in Figure 151 and described in Table 125. Return to the Summary Table. Figure 151. GPO_VALUE_ZCD_CFG_CH4_CH7 Register 7 6 GPO_VALUE_ZCD_CFG_CH7[1 :0] R/W-0b 5 4 GPO_VALUE_ZCD_CFG_CH6[1 :0] R/W-0b 3 2 GPO_VALUE_ZCD_CFG_CH5[1 :0] R/W-0b 1 0 GPO_VALUE_ZCD_CFG_CH4[1 :0] R/W-0b Table 125. GPO_VALUE_ZCD_CFG_CH4_CH7 Register Field Descriptions Bit Field Type Reset Description 7-6 GPO_VALUE_ZCD_CFG _CH7[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges 5-4 GPO_VALUE_ZCD_CFG _CH6[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 71 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Table 125. GPO_VALUE_ZCD_CFG_CH4_CH7 Register Field Descriptions (continued) Bit Field Type Reset Description 3-2 GPO_VALUE_ZCD_CFG _CH5[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges 1-0 GPO_VALUE_ZCD_CFG _CH4[1:0] R/W 0b Define the GPO value to be launched on ZCD rising and falling edges. 0b = Rising (0) and falling (0) -> logic 0 on both edges 1b = Rising (0) and falling (1) -> ZCD 10b = Rising (1) and falling (0) -> ZCD 11b = Rising (1) and falling (1) -> logic 1 on both edges 8.6.115 GPO_ZCD_UPDATE_EN Register (Address = 0xE7) [reset = 0x0] GPO_ZCD_UPDATE_EN is shown in Figure 152 and described in Table 126. Return to the Summary Table. Figure 152. GPO_ZCD_UPDATE_EN Register 7 6 5 4 3 GPO_ZCD_UPDATE_EN[7:0] R/W-0b 2 1 0 Table 126. GPO_ZCD_UPDATE_EN Register Field Descriptions Bit Field 7-0 GPO_ZCD_UPDATE_EN[ R/W 7:0] Type Reset Description 0b Update digital outputs GPO[7:0] synchronous to ZCD. 0b = Digital output is not updated synchronous to the ZCD event. 1b = Digital output is updated synchronous to ZCD event. Configure the GPO_VALUE_ON_ZCD_CFG register. 8.6.116 GPO_TRIGGER_CFG Register (Address = 0xE9) [reset = 0x0] GPO_TRIGGER_CFG is shown in Figure 153 and described in Table 127. Return to the Summary Table. Figure 153. GPO_TRIGGER_CFG Register 7 6 5 4 3 GPO_TRIGGER_UPDATE_EN[7:0] R/W-0b 2 1 0 Table 127. GPO_TRIGGER_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 GPO_TRIGGER_UPDAT E_EN[7:0] R/W 0b Update digital outputs GPO[7:0] when the corresponding trigger is set. 0b = Digital output is not updated in response to the alert flags. 1b = Digital output is updated when the corresponding alert flags are set. Configure GPOx_TRIG_EVENT_SEL register to select which alert flags can trigger an update on the desired GPO. 72 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 8.6.117 GPO_VALUE_TRIG Register (Address = 0xEB) [reset = 0x0] GPO_VALUE_TRIG is shown in Figure 154 and described in Table 128. Return to the Summary Table. Figure 154. GPO_VALUE_TRIG Register 7 6 5 4 3 GPO_VALUE_ON_TRIGGER[7:0] R/W-0b 2 1 0 Table 128. GPO_VALUE_TRIG Register Field Descriptions Bit Field 7-0 GPO_VALUE_ON_TRIGG R/W ER[7:0] Type Reset Description 0b Value to be set on digital outputs GPO[7:0] when the corresponding trigger occurs. GPO update on alert flags must be enabled in the corresponding bit in the GPO_TRIGGER_CFG register. 0b = Digital output is set to logic 0. 1b = Digital output is set to logic 1. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 73 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The following sections give example circuits and suggestions for using the ADS7128 in various applications. 9.2 Typical Applications 9.2.1 Mixed-Channel Configuration AVDD (VREF) Digital Output (open-drain) Digital Output (push-pull) Analog Input Analog Input Analog Input Analog Input I2C Controller Device Digital Input Digital Input Figure 155. DAQ Circuit: Single-Supply DAQ 9.2.1.1 Design Requirements The goal of this application is to configure some channels of the ADS7128 as digital inputs, open-drain digital outputs, and push-pull digital outputs. 9.2.1.2 Detailed Design Procedure The ADS7128 can support GPIO functionality at each input pin. Any analog input pin can be independently configured as a digital input, a digital open-drain output, or a digital push-pull output though the PIN_CFG and GPIO_CFG registers; see Table 4. 9.2.1.2.1 Digital Input The digital input functionality can be used to monitor a signal within the system. Figure 156 illustrates that the state of the digital input can be read from the GPI_VALUE register. ADC From input device AVDD GPIx SW GPIx Figure 156. Digital Input 74 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 Typical Applications (continued) 9.2.1.2.2 Digital Open-Drain Output The channels of the ADS7128 can be configured as digital open-drain outputs supporting an output voltage up to 5.5 V. An open-drain output, as shown in Figure 157, consists of an internal FET (Q) connected to ground. The output is idle when not driven by the device, which means Q is off and the pull-up resistor, RPULL_UP, connects the GPOx node to the desired output voltage. The output voltage can range anywhere up to 5.5 V, depending on the external voltage that the GPIOx is pulled up to. When the device is driving the output, Q turns on, thus connecting the pull-up resistor to ground and bringing the node voltage at GPOx low. VPULL_UP Receiving Device ADC RPULL_UP GPOx ILOAD Q Figure 157. Digital Open-Drain Output The minimum value of the pullup resistor, as calculated in Equation 6, is given by the ratio of VPULL_UP and the maximum current supported by the device digital output (5 mA). RMIN = (VPULL_UP / 5 mA) (6) The maximum value of the pullup resistor, as calculated in Equation 7, depends on the minimum input current requirement, ILOAD, of the receiving device driven by this GPIO. RMAX = (VPULL_UP / ILOAD) (7) Select RPULL_UP such that RMIN < RPULL_UP < RMAX. 9.2.1.3 Application Curve 60000 Frequency 45000 39581 30000 25955 15000 0 2048 2049 Output Code C001 Standard deviation = 0.49 LSB Figure 158. DC Input Histogram Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 75 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com Typical Applications (continued) 9.2.2 Digital Push-Pull Output The channels of the ADS7128 can be configured as digital push-pull outputs supporting an output voltage up to AVDD. As shown in Figure 159, a push-pull output consists of two mirrored opposite bipolar transistors, Q1 and Q2. The device can both source and sink current because only one transistor is on at a time (either Q2 is on and pulls the output low, or Q1 is on and sets the output high). A push-pull configuration always drives the line opposed to an open-drain output where the line is left floating. ADC AVDD Q1 GPOx Digital output Q2 Figure 159. Digital Push-Pull Output 76 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 10 Power Supply Recommendations 10.1 AVDD and DVDD Supply Recommendations The ADS7128 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is used for the interface circuits. For supplies greater than 2.35 V, AVDD and DVDD can be shorted externally if single-supply operation is desired. The AVDD supply also defines the full-scale input range of the device. Decouple the AVDD and DVDD pins individually, as shown in Figure 160, with 1-µF ceramic decoupling capacitors. The minimum capacitor value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If both supplies are powered from the same source, a minimum capacitor value of 220 nF is required for decoupling. Connect a 1-µF decoupling capacitor between the DECAP and GND pins for the internal power supply. AVDD AVDD 1 PF DECAP 1 PF GND GND 1 PF DVDD DVDD Figure 160. Power-Supply Decoupling Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 77 ADS7128 SBAS868A – MAY 2019 – REVISED MAY 2020 www.ti.com 11 Layout 11.1 Layout Guidelines Figure 161 shows a board layout example for the ADS7128. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the AVDD supply away from noise sources. Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference voltage for the ADS7128. Place the decoupling capacitor for AVDD close to the device AVDD and GND pins and connect the decoupling capacitor to the device pins with thick copper tracks. DVDD GND ALERT ADDR 11.2 Layout Example SCL DECAP SDA AVDD AIN/GPIO Figure 161. Example Layout 78 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 ADS7128 www.ti.com SBAS868A – MAY 2019 – REVISED MAY 2020 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS7128 79 PACKAGE OUTLINE RTE0016C WQFN - 0.8 mm max height SCALE 3.600 PLASTIC QUAD FLATPACK - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 1.68 0.07 (DIM A) TYP 5 8 EXPOSED THERMAL PAD 12X 0.5 4 9 4X 1.5 SYMM 17 1 12 16X PIN 1 ID (OPTIONAL) 16 13 0.1 0.05 SYMM 16X 0.30 0.18 C A B 0.5 0.3 4219117/B 04/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RTE0016C WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.68) SYMM 13 16 16X (0.6) 1 12 16X (0.24) SYMM 17 (2.8) (0.58) TYP 12X (0.5) 9 4 ( 0.2) TYP VIA 5 (R0.05) ALL PAD CORNERS 8 (0.58) TYP (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL EXPOSED METAL SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4219117/B 04/2022 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RTE0016C WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.55) 16 13 16X (0.6) 1 12 16X (0.24) 17 SYMM (2.8) 12X (0.5) 9 4 METAL ALL AROUND 5 SYMM 8 (R0.05) TYP (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X 4219117/B 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS7128IRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 X71X8 ADS7128IRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 X71X8 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of