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ADS7142
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
ADS7142 纳瓦级功率、双通道、可编程传感器监控器
1 特性
2 应用
•
适用于成本敏感型设计的独立纳瓦级功率传感器监
控器
•
•
小封装尺寸：1.5mm × 2mm
高效的主机休眠和唤醒
– 自主监控功耗为 900nW
– 用于事件触发主机唤醒的窗口比较器
– 主机休眠期间数据缓冲
独立的传感器配置和校准
– 双通道、伪差动或接地检测输入配置
– 用于校准的可编程阈值
– 内部校准改善了偏移和漂移
错误触发防护
– 每个通道的可编程阈值
– 用于实现抗噪性能的可编程磁滞
– 用于瞬态抑制的事件计数器
深入的数据分析
– 用于故障诊断的数据缓冲
– 用于实现 16 位精度的高精度模式
– 用于快速数据捕获的一次性模式
I2C™ 接口
– 兼容 1.65V 至 3.6V 的电压范围
– 8 个可配置地址
– 高达 3.4MHz（高速）
宽工作频率范围：
– 模拟电源：1.65V 到 3.6V
– 温度范围：-40°C 至 125°C
1
•
•
•
•
•
•
•
•
•
•
•
•
•
物联网 (IoT) 的传感器节点
气体、热量、PIR 运动和烟雾探测器
用于电梯、自动扶梯、HVAC、工业设备等的预防
性维护
可穿戴电子产品
用于故障指示器的过零检测
监控功能
具有可编程基准电压的比较器
用于深入学习人工智能的传感器
3 说明
ADS7142 可在优化系统功耗、可靠性和性能的过程中
自主监测信号。它可使用带有可编程高低阈值、磁滞和
事件计数器的数字窗口比较器根据通道实施由事件引发
的中断。该器件在逐次逼近型寄存器模数转换器 (SAR
ADC) 前方包含一个双通道模拟多路复用器，后跟一个
用于转换和捕获传感器数据的内部数据缓冲器。
ADS7142 采用 10 引脚 QFN 封装，功耗仅为 900
nW。该器件体积小巧，功耗低，非常适合空间受限型
和/或电池供电类 应用。
器件信息(1)
部件名称
ADS7142
封装
封装尺寸（标称值）
X2QFN (10)
1.50mm x 2.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Example System Architecture
System Data Capture
Cloud
High
Threshold
Sensor
Node
Bio
Temperature
!
Low
Threshold
Wake-up
Alert
Sensor
ADS7142
Output
!
Sensor
Node
!
ADS7142 Samples
Sensor
Node
Gateway
System Energy Consumption
MCU
Optical
Motion
!
Sensor
Output
Sensor
Node
Sensor
Node
Energy
Consumed
Blood
Glucouse
Sensor
Node
MCU + Polling
with Internal
ADC
MCU + Event Trigger MCU + Event Trigger
with Comparator
with ADS7142
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS773
ADS7142
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics - All Modes........................ 5
Electrical Characteristics - Manual Mode.................. 6
Electrical Characteristics - Autonomous Modes ....... 7
Electrical Characteristics - High Precision Mode ...... 7
Timing Requirements ................................................ 8
Switching Characteristics ........................................ 9
Typical Characteristics for All Modes.................... 12
Typical Characteristics for Manual Mode.............. 12
Typical Characteristics for Autonomous Modes.... 17
Typical Characteristics for High Precision Mode .. 18
Detailed Description ............................................ 19
7.2
7.3
7.4
7.5
7.6
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Optimizing Power Consumed by the Device ..........
Register Map...........................................................
19
20
31
41
43
Application and Implementation ........................ 60
8.1 Application Information............................................ 60
8.2 Typical Applications ................................................ 60
9
Power-Supply Recommendations...................... 67
9.1 AVDD and DVDD Supply Recommendations......... 67
10 Layout................................................................... 68
10.1 Layout Guidelines ................................................. 68
10.2 Layout Example .................................................... 68
11 器件和文档支持 ..................................................... 70
11.1
11.2
11.3
11.4
11.5
11.6
文档支持................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
70
70
70
70
70
70
12 机械、封装和可订购信息 ....................................... 70
7.1 Overview ................................................................. 19
4 修订历史记录
Changes from Original (September 2017) to Revision A
Page
•
将器件状态从预告信息更改成了生产数据 ............................................................................................................................... 1
2
Copyright © 2017, Texas Instruments Incorporated
ADS7142
www.ti.com.cn
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
5 Pin Configuration and Functions
RUG PACKAGE
10-Pin X2QFN
TOP VIEW
GND
10
AVDD
1
9
AINP/AIN0
2
8 SCL
AINM/AIN1
3
7 SDA
ADDR
4
6 ALERT
DVDD
5
BUSY/RDY
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AVDD
1
Supply
Analog supply input, also used as the reference voltage for analog-to-digital conversion.
AINP/AIN0
2
Analog input
Single-Channel operation: Positive analog signal input
Two-Channel operation: Analog signal input, Channel 0
AINM/AIN1
3
Analog input
Single-Channel operation: Negative analog signal input
Two-Channel operation: Analog signal input, Channel 1
ADDR
4
Analog Input
Input for selecting I2C address of the device. The device address can be selected from one of
the eight values by connecting resistors on this pin.
Refer 表 2 for details
BUSY/RDY
5
Digital output
The device pulls this pin high when it is scanning through channels in a sequence and brings
this pin low when sequence is completed or aborted.
ALERT
6
Digital output
Active low, open drain output. Status of this pin is controlled by Digital window comparator
block. Connect a pull-up resistor from DVDD to this pin
SDA
7
SCL
8
Digital input
DVDD
9
Supply
Digital I/O supply voltage
GND
10
Supply
Ground for power supply, all analog and digital signals are referred to this pin
Digital input/output Serial data in/out for I2C interface. Connect a pull-up resistor from DVDD to this pin
Copyright © 2017, Texas Instruments Incorporated
Serial clock for I2C interface. Connect a pull-up resistor from DVDD to this pin
3
ADS7142
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
ADDR to GND
–0.3
AVDD + 0.3
V
AVDD to GND
–0.3
3.9
V
DVDD to GND
–0.3
3.9
V
AINP/AIN0 to GND
–0.3
AVDD + 0.3
V
AINM/AIN1 to GND
–0.3
AVDD + 0.3
V
Input current on any pin except supply pins
-10
10
mA
Digital Input to GND
–0.3
DVDD + 0.3
V
Storage Temperature, Tstg
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
Analog Supply Voltage Range
1.65
3.6
DVDD
Digital Voltage Supply Voltage Range
1.65
3.6
V
A
TA
Ambient temperature
–40
125
°C
TJ
Junction temperature
–60
150
°C
6.4 Thermal Information
ADS7142
THERMAL METRIC (1)
RUG
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
120.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.7
°C/W
RθJB
Junction-to-board thermal resistance
51.1
°C/W
ΨJT
Junction-to-top characterization parameter
0.8
°C/W
ΨJB
Junction-to-board characterization parameter
51.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
ADS7142
www.ti.com.cn
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
6.5 Electrical Characteristics - All Modes
At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT - Two-Channel Single-Ended Configuration
Full-scale input voltage
span (1)
AINP/AIN0 to GND or AINM/AIN1 to GND
0
AVDD
V
Absoulte Input voltage
range
AINP/AIN0 to GND or AINM/AIN1 to GND
–0.1
AVDD + 0.1
V
0
AVDD
V
AINP/AIN0 to GND
–0.1
AVDD + 0.1
V
AINM/AIN1 to GND
–0.1
0.1
V
–AVDD/2
AVDD/2
V
AINP/AIN0 to GND
–0.1
AVDD + 0.1
V
AINM/AIN1 to GND
AVDD/2–0.1
AVDD/2+0.1
V
ANALOG INPUT - Single-Channel Single-Ended Configuration (with Remote Ground Sense)
Full-scale input voltage
span (1)
Absoulte Input voltage
range
AINP/AIN0 to GND or AINM/AIN1 to GND
ANALOG INPUT - Single-Channel Pseudo-Differential Configuration
Full-scale input voltage
span (1)
Absoulte Input voltage
range
AINP/AIN0 to GND or AINM/AIN1 to GND
Internal Oscillator
tHSO
Time Period for High
Speed Oscillator
50
110
ns
tLPO
Time Period for Low
Power Oscillator
95.2
300
µs
Digital Input/Output (SCL, SDA)
VIH
High Level input Voltage
0.7 × DVDD
DVDD
V
VIL
Low Level input Voltage
0
0.3 × DVDD
V
With 3 mA Sink Current and DVDD > 2 V
0
0.4
V
With 3 mA Sink Current and 1.65 V < DVDD
50 kHz).
2. Set sampling speed by programming the nCLK register:
Oscillator frequency
nCLK
fS
•
•
•
fs = Sampling Speed
Oscillator Frequency = 1/tHSO or 1/tLPO depending on the OSC_SEL bit, refer the Specifications for 1/tHSO or
1/tLPO.
nCLK is number of clocks in one conversion cycle (nCLK register)
(2)
7.3.6 I2C Address Selector
The I2C address for the device is determined by connecting external resistors on ADDR pin. The device address
are selected on power-up based on the resistor values. The device retains this address until the next power up,
or until next device reset, or until the device receives a command to program its own address (General Call with
Write Software programmable part of slave address). 图 45 provides the connection diagram for the ADDR pin
and 表 2 provides the resistor values for selecting different addresses of the device.
22
版权 © 2017, Texas Instruments Incorporated
ADS7142
www.ti.com.cn
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
AVDD
R1
ADDR
R2
Copyright © 2017, Texas Instruments Incorporated
图 45. External Resistor Connection Diagram for ADDR Pin
表 2. I2C Address Selection
Resistors
R1
R2 (1)
0Ω
DNP (2)
0011111b (1Fh)
11 kΩ
DNP (2)
0011110b (1Eh)
33 kΩ
DNP (2)
0011101b (1Dh)
100 kΩ
DNP (2)
0011100b (1Ch)
DNP (2)
0Ω or DNP (2)
0011000b (18h)
(2)
11 kΩ
0011001b (19h)
DNP (2)
33 kΩ
0011010b (1Ah)
DNP (2)
100 kΩ
0011011b (1Bh)
DNP
(1)
(2)
Address
(1)
Tolerance for R1,R2 < ±5%
DNP = Do not populate
7.3.7 Data Buffer
When operating in Autonomous Monitoring Mode, the device can use the internal data buffer for data storage.
The internal data buffer is 16-bit wide and 16-word deep and follows the FIFO (first-in, first-out) approach.
7.3.7.1 Filling of the Data Buffer
The write operation to the data buffer starts and stops as per the settings in the DATA_BUFFER_OPMODE
register. The DATA_BUFFER_STATUS register provides the number of entries filled in the data buffer and this
register can be read during an active sequence to get the current status of the data buffer.
The time between two consecutive conversions is set by the nCLK register and 公式 3 provides the relationship
for time between two consecutive conversions of the same channel and nCLK parameter.
tcc = k x nCLK x OscillatorTimePeriod
where
•
•
•
•
tcc is time between two consecutive conversions of same channel, tcc = k × tcycle .
k is number of channels enabled in the device sequence.
nCLK is number of clocks used by device for one conversion cycle.
Oscillator Timer Period is tLPO or tHSO depending on OSC_SEL value . Refer to the Specifications for tLPO or
tHSO .
(3)
The format of the 16-bit contents of each entry in the data buffer are set by programming the DATA_OUT_CFG
register. The DATA_OUT_CFG register enables the Channel ID and DATA_VALID flag in data buffer. Channel
ID represents the channel number for the data entry in the data buffer. DATA_VALID is set to zero in either of
the following conditions:
版权 © 2017, Texas Instruments Incorporated
23
ADS7142
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
•
•
www.ti.com.cn
If the entry in the data buffer is not filled after the last start of sequence.
If the I2C master tries to read more than 16 entries from the data buffer, device provides zeros with
DATA_VALID set to zero.
At the end of the write operation, the data buffer always has results of 16 (or lesser) consecutive conversions.
The data buffer is filled in the order that the data is converted by the ADC. The channels converted by the ADC
are controlled by the AUTO_SEQ_CHEN register. The entries that are not filled during an active sequence are
filled with zeros.
7.3.7.2 Reading data from the Data Buffer
The device brings the BUSY/RDY pin low after completion of the sequence or after the SEQ_ABORT bit is set.
As illustrated in 图 46, the device provides the contents of the data buffer (in FIFO fashion) on receiving I2C read
frame, which consists of the device address and the read bit set to 1.
S
Device Address (7 Bits)
R
A
MSB for Data Buffer Entry 0
A
LSB for Data Buffer Entry 0
A
MSB for Data Buffer Entry 1
A
LSB for Data Buffer Entry 15
N
P/Sr
Data from Host to Device
Data from Device to Host
图 46. Reading Data Buffer (16 Bit Words × 16 Words)
The device returns zeroes with DATA VALID flag set to zero for all I2C read frames received after all the valid
data words from the data buffer are read or when a I2C read frame is issued during an active sequence
(indicated by high on the BUSY/RDY pin). The I2C master needs to provide a NACK followed by a STOP or
RESTART condition in an I2C frame to finish the reading process. The data buffer is reset by setting the
SEQ_START bit or after resetting the device.
7.3.8 Accumulator
When operating in High Precision Mode, the device offers a 16-bit internal accumulator per channel. The
Accumulator for a channel is enabled only if that channel is selected in the channel scanning sequence. The
accumulator adds sixteen 12-bit conversion results. The result of adding 16 twelve bit words is one 16 bit word
that has an effective resolution of an 16-bit ADC. The time between two consecutive conversions for
accumulation is controlled by the nCLK register and 公式 3 provides the relationship for time between two
consecutive conversions of same channel and nCLK parameter.
The accumulated data can be read from the ACCUMULATOR_DATA registers in the device.
ACCUMULATOR_STATUS register provides the number of accumulations done in the accumulator since last
conversion. This register can be read during an active sequence to get the current status of the accumulator.
The accumulator is reset on setting the SEQ_START bit and on resetting the device.
公式 4 provides the relationship between high precision data and ADC conversion results.
16
High Precision Data for CHx
¦ Conversion Result[k]
for CHx
(4)
k 1
公式 5 provides the value of LSB in high precision mode for the accumulated result.
AVDD
1 LSB
216
24
(5)
版权 © 2017, Texas Instruments Incorporated
ADS7142
www.ti.com.cn
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
7.3.9 Digital Window Comparator
The internal Digital Window Comparator is available in all modes. In Autonomous Modes with Thresholds
monitoring and Diagnostics, the digital window comparator controls the filling of the data and the output of the
alert pin and in other modes, it only controls the output of the alert pin. 图 47 provides the block diagram for
digital window comparator.
DWC_BLOCK_EN
ALERT_EN_CH1
Channel 1
ALERT_EN_CH0
Channel 0
(High Side Threshold, Hysteresis)
for CH0
ADC
Conversion Result for CH0
High Side Comparator
High Side
Counter
End of
Conversion
(Low Side Threshold, Hysteresis)
for CH0
S
Q
High Latched Flag for CH0
R
Write Bit to
Reset
Low Side
Counter
OR
OR
ALERT
R
Q
Low Latched Flag for CH0
S
Low Side Comaparator
图 47. Digital Comparator Block Diagram
The Low Side Threshold, High Side Threshold, and Hysteresis parameters are independently programmable for
each input channel. 图 48 shows the comparison thresholds and hysteresis for the two comparators. A Pre-Alert
event counter after each comparator counts the output of the comparator and sets the latched flags. The PreAlert Event Counter settings are common to the two channels.
版权 © 2017, Texas Instruments Incorporated
25
ADS7142
ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
www.ti.com.cn
NOTE: PRE_ALT_MAX_EVENT_COUNT = 70h
(waits for 8 counts to set alert)
2
High Threshold
1
3
1
5
High Threshold - Hysteresis
8
2
4
7
3
4 5
6
6
Counter Reset because the high-side-comparator reset
before 8.
Counter Reset because the high-side-comparator reset
before 8.
Low Threshold + Hysteresis
7
4
Low Threshold
5
6
3
1
2
High Side Comparator
(Internal Only Signal)
Low Side Comparator
(Internal Only Signal)
ALERT
图 48. Thresholds, Hysteresis and Event Counter for Digital Window Comparator
DWC_BLOCK_EN bit in ALERT_DWC_EN register enables/disables the complete Digital Window Comparator
block (disabled at power-up) and ALERT_EN_CHx bits in ALERT_CHEN register enables Digital Window
Comparator for individual channels. Once enabled, whenever a new conversion result is available:
1. The output of the high side comparator transitions to logic high when the conversion result is greater than the
High Threshold. This comparator resets when the conversion result is less than the High Threshold –
Hysteresis.
26
版权 © 2017, Texas Instruments Incorporated
ADS7142
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ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
2. The output of the low side comparator transitions to logic high when the conversion result is less than the
Low Threshold. This comparator resets when the conversion result is greater than the Low Threshold +
Hysteresis.
3. A different threshold and hysteresis can be used for each channel.
4. Once the output of either the high side or low side comparator transitions high the Pre-Alert Event Counter
begins to increment for each subsequent conversion. This counter continues to increment until it reaches the
value
stored
in
the
PRE_ALT_MAX_EVENT_COUNT
register.
Once
it
reaches
PRE_ALT_MAX_EVENT_COUNT, the Alert becomes active and sets the latched flags. If the comparator
output becomes zero before counter reaches PRE_ALT_MAX_EVENT_COUNT, then the event counter is
reset to zero, Alert does not be set and lateched flag is not set.
Therefore, the latched flags (high and low) for the channel are updated only if the respective comparator output
remains 1 for the specified number of consecutive conversions (set by the PRE_ALT_MAX_EVENT_COUNT).
The latched flags can be read from the ALERT_LOW_FLAGS and ALERT_HIGH_FLAGS registers. To clear a
latched flag, write 1 to the applicable bit location. The ALERT pin status is re-evaluated whenever an applicable
latched flag gets set or is cleared.
The response time for ALERT pin can be estimated by 公式 6
tresponse = [1 + k x (PRE_ALT_MAX_EVENT_COUNT + 1) ] x nCLK x Oscillator TimePeriod
where
•
•
•
k is number of channels enabled in device sequence
nCLK is number of clocks used by device for one conversion cycle.
Oscillator Timer Period is tLPO or tHSO depending on OSC_SEL value . Refer to the Specifications for tLPO or
tHSO .
(6)
7.3.10 I2C Protocol Features
7.3.10.1 General Call
On receiving a general call (00h), the device provides an ACK.
7.3.10.2 General Call with Software Reset
On receiving a general call (00h) followed with Software Reset (06h), the device resets itself.
7.3.10.3 General Call with Write Software programmable part of slave address
On receiving a general call (00h) followed by 04h, the device configures its own I2C address configured by the
ADDR pin. During this operation, the device keeps BUSY/RDY Pin high and does not respond to other I2C
commands except general call.
7.3.10.4 Configuring Device into High Speed I2C mode
The device can be configured in High Speed I2C mode by providing an I2C frame with one of the HS-mode
master codes (08h to 0Fh).
After receiving one of the HS-mode master codes, the device sets the HS_MODE bit in
OPMODE_I2CMODE_STATUS register and remains in High Speed I2C mode until a STOP condition is received
in an I2C frame.
7.3.10.5 Bus Clear
If the SDA line is stuck LOW due to an incomplete I2C frame, providing nine clocks on SCL is recommended.
The device releases the SDA line within these nine clocks, and then the next I2C frame can be started.
版权 © 2017, Texas Instruments Incorporated
27
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7.3.11 Device Programming
表 3 provides the acronyms for different conditions in an I2C Frame.
表 3. I2C Frame Acronyms
Symbol
Description
S
Start condition for I2C Frame
Sr
Re-start condition for I2C Frame
P
Stop condition for I2C Frame
A
ACK (Low)
N
NACK (High)
R
Read Bit (High)
W
Write Bit (Low)
表 4. Opcodes for Commands
Opcode
Command Description
00010000b
Single Register Read
00001000b
Single Register Write
00011000b
Set Bit
00100000b
Clear Bit
00110000b
Reading a continuous block of registers
00101000b
Writing a continuous block of registers
7.3.11.1 Reading Registers
The I2C master can either read a single register or a continuous block registers from the device as described in
Single Register Read and in Reading a Continuous Block of Registers.
7.3.11.1.1 Single Register Read
To read a single register from the device, the I2C master has to first provide an I2C command with three frames
(of 8-bits each) to set the address as illustrated in 图 49. The register address is the address of the register
which must be read. The opcode for register read command is listed in 表 4.
S
Device Address (7 Bits)
W
A
Register Read or Block Read
Opcode (8 Bits)
A
Register Address (8 Bits)
A
P/Sr
Data from Host to Device
Data from Device to Host
图 49. Setting Register Address for Reading Registers
After this, the I2C master has to provide another I2C frame containing the device address and read bit as
illustrated in 图 50. After this frame, the device provides register data. If the host provides more clocks, the
device provides same register data. To end the register read command, the master has to provide a STOP or a
RESTART condition in the I2C frame.
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S
Device Address (7 Bits)
R
A
Register Data (8 Bits)
A
P/Sr
Data from Host to Device
Data from Device to Host
图 50. Reading Register Data
7.3.11.1.2 Reading a Continuous Block of Registers
To read a continuous block of registers, the I2C master has to first provide an I2C command to set the address as
illustrated in 图 49. The register address is the address of the first register in the block which must be read. The
opcode for reading a continuous block of register is listed in 表 4.
Next, the I2C master has to provide another I2C frame containing the device address and read bit as illustrated in
图 51. After this frame, the device provides register data. On providing more clocks, the device provides data for
next register. On reading data from addresses which does not exist in the Register Map of the device, the device
returns zeros. If the device does not have any further registers to provide the data, it provides zeros. To end the
register read command, the master has to provide a STOP or a RESTART condition in the I2C frame.
S
Device Address (7 Bits)
R
A
Register Data (8 Bits) for Register N
A
Register Data (8 Bits) for Register N+1
A
Register Data (8 Bits) for Register N+2
A
Register Data (8 Bits) for Register N+k
A
P/Sr
Data from Host to Device
Data from Device to Host
图 51. Reading a Continuous Block of Registers
7.3.11.2 Writing Registers
The I2C master can either write a single register or a continuous block registers to the device. It can also set a
few bits in a register or clear a few bits in a register.
7.3.11.2.1 Single Register Write
To write to a single register in the device, the I2C master has to provide an I2C command with four frames as
illustrated in 图 52. The register address is the address of the register which must be written and register data is
the value that must be written. The opcode for single register write is listed in 表 4. To end the register write
command, the master has to provide a STOP or a RESTART condition in the I2C frame.
S
Device Address (7 Bits)
W
A
Write Register or Set Bit or Clear Bit
Opcode (8 Bits)
A
Register Address (8 Bits)
A
Register Data (8 Bits)
A
P/Sr
Data from Host to Device
Data from Device to Host
图 52. Writing a Single Register
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7.3.11.2.2 Set Bit
To set bits in a register without changing the other bits, the I2C master has to provide an I2C command with four
frames as illustrated in 图 52. The register address is the address of the register in which the bits needs to be set
and register data is the value representing the bits which need to be set. Bits with value as 1 in register data are
set and bits with value as 0 in register data are not changed. The opcode for set bit is listed in 表 4. To end this
command, the master has to provide a STOP or RESTART condition in the I2C frame.
7.3.11.2.3 Clear Bit
To clear bits in a register without changing the other bits, the I2C master has to provide an I2C command with
four frames as illustrated in 图 52. The register address is the address of the register in which the bits needs to
be cleared and register data is the value representing the bits which need to be cleared. Bits with value as 1 in
register data are cleared and bits with value as 0 in register data are not changed. The opcode for clear bit is
listed in 表 4. To end this command, the master has to provide a STOP or a RESTART condition in the I2C
frame.
7.3.11.2.4 Writing a continuous block of registers
To write to a continuous block of registers, the I2C master has to provide an I2C command as illustrated in 图 53.
The register address is the address of the first register in the block which needs to be written. The I2C master
has to provide data for registers in subsequent I2C frames in an ascending order of register addresses. Writing
data to addresses which do not exist in the Register Map of the device has no effect. The opcode for writing a
continuous block of registers is listed in 表 4. If the data provided by the I2C master exceeds the address space
of the device, the device neglects the data beyond the address space. To end the register write command, the
master has to provide a STOP or a RESTART condition in the I2C frame.
S
Device Address (7 Bits)
Register Data (8 Bits) for Register N+1
W
A
Block Write Opcode (8 Bits)
A
Register Address (8 Bits)
A
A
Register Data (8 Bits) for Register N
A
Register Data (8 Bits) for Register N+k
A
P/Sr
Data from Host to Device
Data from Device to Host
图 53. Writing a continuous block of registers
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7.4 Device Functional Modes
The device has below functional modes:
• Manual Mode
• Autonomous Modes
– Autonomous Mode with Threshold Monitoring and Diagnostics.
– Autonomous Mode with Burst Data
• High Precision Mode
Device powers up in Manual Mode and can be configured into one of the other modes of these modes by writing
the configuration registers for the desired mode. Steps for configuring device into different modes are illustrated
in 图 54
Device Power Up or
Reset
OFFSET Calibration
on Power Up(1)
Select the Channel
Input
Configurations(2)
Select the Operation
Mode of the device(3)
Set the I2C Mode to
High Speed
(Optional)(4)
Manual Mode(5)
Autonomous Modes(5)
High Precision
Mode(5)
(1)
Offset can also be calibrated anytime during normal operation by setting the bit in the OFFSET_CAL register.
(2)
Configure the CHANNEL_INPUT_CFG register.
(3)
Configure the OPMODE_SEL register for the desired operation mode.
(4)
Refer to Configuring Device into High Speed I2C mode section.
(5)
Operating mode is selected by configuring the OPMODE_SEL register in step 3.
(6)
For reading and writing registers, Refer to Device Programming section.
图 54. Configuring Device into different modes
7.4.1 Device Power Up and Reset
On power up, the device calibrates its own offset and calculates the address from the resistors connected on
ADDR pin. During this time, the device keeps BUSY/RDY high.
The device can be reset by recycling power on AVDD pin, by General Call(00h) followed by software reset (06h),
or by writing the WKEY register followed by setting the bit in DEVICE_RESET register.
Recycling power on the AVDD pin and on General call(00h) followed by software reset (06h), all the device
configurations are reset, and the device initiates offset calibration and re-evaluates its I2C address.
When setting the bit in DEVICE_RESET register, all the device configurations except latched flags for the Digital
Window Comparator and WKEY register are reset, The device does not initiate offset calibration and does not reevaluate its I2C address.
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Device Functional Modes (接
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7.4.2 Manual Mode
On power-up, the device is in Manual Mode using the single ended and dual channel configuration and starts by
sampling the analog input applied on Channel 0. In this mode, the device uses the high frequency oscillator for
conversions. Manual mode allows the external host processor to directly request and control when the data is
sampled. The data capture is initiated by an I2C command from the host processor and the data is then returned
over the I2C bus at a throughput rate of up to 140-kSPS. Applications that could take advantage of this type of
functionality include traditional ADC applications that require 1 or 2 channels of continuous data output.
After setting the operation mode to Manual Mode as illustrated in 图 54, steps for operating the device to be in
Manual Mode and reading data are illustrated in 图 55. The host can either configure the device to scan through
one channel or both channels by configuring the CHANNEL_INPUT_CFG register and AUTO_SEQ_CFG
register.
7.4.2.1 Manual Mode with CH0 Only
Set the OPMODE_SEL register to 000b or 001b for Manual Mode with CH0 only. The host has to provide device
address and read bit to start the conversions. To continue with conversions and reading data to the host must
provide continuous SCL (图 56). In this mode, a NACK followed by a STOP condition in I2C frame is required to
abort the operation. Then the device operation mode can be changed to another operation mode.
7.4.2.2 Manual Mode with AUTO Sequence
Set the OPMODE_SEL register to 100b or 101b for Manual Mode with AUTO Sequence. The host has to set the
SEQ_START bit in START_SEQUENCE register and provide the device address and read bit to start the
conversions. To continue with conversions and reading data, the host must provide continuous SCL (图 56). In
this mode, the SEQ_ABORT bit in ABORT_SEQUENCE register must be set to abort the operation. Then the
device operation mode can be changed to another operation mode. In this mode, a register read aborts the
AUTO sequence.
In Manual Mode, the device always uses the High Speed Oscillator and the nCLK parameter has no effect. The
maximum scan rate is given by 公式 7:
1000
fS
>18 u TSCL k @
•
•
•
•
32
fs = Maximum sampling Speed in kSPS
TSCL= Time period of SCL clock (in µsec)
if TSCL-LOW (Low period of SCL) < 1.8.µsec, k = (1.8 - TSCL-LOW) and Device stretches clock in Manual Mode. Not
Applicable for Standard I2C Mode (100 kHz).
if TSCL-LOW (Low period of SCL) ≥ 1.8.µsec, k = 0 and Device does not stretch clock in Manual Mode.
(7)
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Device Functional Modes (接
接下页)
Manual Mode(1)
AUTO
Sequence
Scan CH0
Only
No
Select Manual Mode
with AUTO Sequence
and Select Channels
in AUTO Sequence(2)
Yes
CH0 Only (Default)
Set SEQ_START Bit(3)
Provide Device Address
and Read Bit to Start
Conversions(4)
Provide Device Address
and Read Bit to Start
Conversions(4)
Provide Continuous
SCL to the device(4)
Provide Continuous
SCL to the device(4)
Yes
Yes
Continue with
conversions and
reading data
Continue with
conversions and
reading data
No
Provide STOP
Condition on I2C Bus(4)
No
No
Set SEQ_ABORT Bit(5)
Yes
Continue in
same Operation
Mode
Yes
Continue in
same Operation
Mode
No
No
Exit to another Operation Mode(6)
(1)
For setting the operation mode to Manual mode, Refer to 图 54
(2)
Select Manual mode with AUTO sequence in OPMODE_SEL register. Select channels in AUTO_SEQ_CFG register.
(3)
Set the bit SEQ_START bit in the START_SEQUENCE register.
(4)
Refer to 图 56 .
(5)
Set the bit SEQ_ABORT bit in the ABORT_SEQUENCE register .
(6)
Select another operation mode in the OPMODE_SEL register.
(7)
For reading and writing registers, Refer to Device Programming section.
图 55. Device Operation in Manual Mode
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Device Functional Modes (接
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Data can be read from the device by providing a device address and read bit followed by continuous SCL as
shown in 图 56.
Sample A
Sample A+1
Device I2C Address from Host
SDA
SCL
S
ADC Data for Sample A
A6
A5
A4
A3
A2
A1
A0
R
ACK
1
2
3
4
5
6
7
8
9
ADC Data for Sample A
D11
D10
D9
D8
D7
D6
D5
1
2
3
4
5
6
7
Optional
Clock
Stretch
Device in Acquisition
Sample A+2
ADC Data for Sample A+1
D4
ACK
D3
D2
D1
D0
0
0
0
8
9
10
11
12
13
14
15
16
0
ACK
D11
D10
0
NA
CK
17
18
1
2
17
18
Optional
Clock
Stretch
Device in Acquisition
Device in Acquisition
Data from Host to Device
Data from Device to Host
(1)
Refer to 公式 7 for sampling speed in Manual Mode.
(2)
If device scans both channels in AUTO sequence, first data (For Sample A) is from CH0 and second data(For Sample
A +1) is from CH1.
图 56. Starting Conversion and Reading Data in Manual Mode
7.4.3 Autonomous Modes
In Autonomous Mode, the device can be programmed to monitor the voltage applied on the analog input pins of
the device and generate a signal on the ALERT pin when the programmable high or low threshold values are
crossed and store the conversion results in the data buffer before or after the crossing a threshold or before
setting the SEQ_ABORT bit (Start Burst) or after setting the START_SEQUENCE bit.
In Autonomous mode, the device generates the start of conversion using the internal oscillator. The first start of
conversion must be provided by the host and the device generates the subsequent start of conversions.
After configuring the operation mode to autonomous mode (Set OPMODE_SEL register to 110b) as illustrated in
图 54, steps for operating the device to be in different autonomous modes are illustrated in 图 57
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Device Functional Modes (接
接下页)
Autonomous Modes(1)
Select the Channels in AUTO
Sequence(2)
Select the Oscillator
& Set the nCLK value(3)
Select the Data Buffer Configuration(4)
Autonomous Mode with Threshold Monitoring and Diagnostics
Autonomous Mode with Burst Data
Stop Burst
Pre Alert
Post Alert
Start Burst
Set the
Thresholds,
Hysteresis and
Enable Alert(5)
Set the
Thresholds,
Hysteresis and
Enable Alert(5)
Set the
SEQ_START Bit(6)
Set the SEQ_Start
Bit(6)
Set the
SEQ_START Bit(6)
Set the
SEQ_START Bit(6)
Device Starts
conversions and
starts Filling Data
Buffer
Device Starts
Conversions
Device Starts
conversions and
starts Filling Data
Buffer
Device Starts
conversions and
starts Filling Data
Buffer
No
No
Yes
Is Alert Set?
Is Alert Set or
SEQ_ABORT bit
set ?
No
Is Data Buffer
Filled or
SEQ_ABORT
bit Set?
No
Yes
Device Starts
Filling Data Buffer
Is
SEQ_ABORT
Bit Set ?
Yes
Yes
Yes
Is Data Buffer
Filled or
SEQ_ABORT
bit Set?
No
Device Stops
Conversions &
Stops Filling Data
Buffers
Yes
Device Stops
Conversions &
Stops Filling Data
Buffers
Read the latched
flags of Digital
Window
Comparator(7)
Read the latched
flags of Digital
Window
Comparator(7)
Reset the latched
flags by writing 1(8)
Reset the latched
flags by writing 1(8)
Device Stops
Conversions &
Stops Filling Data
Buffer
Device Stops
Conversions &
Stops Filling Data
Buffer
Read the Data Buffer(9)
Continue in
same operation
mode
No
Exit to another
Operation Mode(10)
Yes
Set the
SEQ_START Bit(6)
(1)
For setting the operation mode to Autonomous modes, Refer to 图 54
(2)
Select channels in the AUTO_SEQ_CFG register.
(3)
Select the oscillator by configuring the OSC_SEL register and configure the nCLK register.
(4)
Select the data buffer mode in the DATA_BUFFER_OPMODE register.
(5)
Configure the thresholds in the DWC_xTH_CHx_xxx registers and hysteresis in the DWC_HYS_CHx registers.
Enable the alert for channels in the ALERT_CHEN register and set the DWC_BLOCK_EN bit in the
ALERT_DWC_EN register.
(6)
Set the bit SEQ_START bit in the START_SEQUENCE register.
(7)
Read the ALERT_LOW_FLAGS and/or ALERT_HIGH_FLAGS registers.
(8)
Reset the ALERT_LOW_FLAGS and/or ALERT_HIGH_FLAGS registers by writing 03h.
(9)
Refer to Reading data from the Data Buffer section.
(10) Select another operation mode in the OPMODE_SEL register.
(11) For reading and writing registers, Refer to Device Programming section.
图 57. Configuring Device in Autonomous Modes
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Device Functional Modes (接
接下页)
TI recommends aborting the present sequence by setting the SEQ_ABORT bit before changing the device
operation mode or device configuration.
7.4.3.1 Autonomous Mode with Threshold Monitoring and Diagnostics
The Threshold Monitoring Mode automatically scans the input voltage on the input channel(s) and generates a
signal when the programmable high or low threshold values are crossed. This mode is useful for applications
where the output of the sensor needs to be continuously monitored and action only taken when the sensor output
deviates outside of an acceptable range. Applications that could take advantage of this type of functionality
include wireless sensor nodes, environmental sensors, smoke and heat detectors, motion detectors, and so on.
In this mode, the data buffer can be configured to store the conversion results of the ADC in two different ways.
7.4.3.1.1
Autonomous Mode with Pre Alert Data
In this mode, the device stores the sixteen conversion prior to the activation of the Alert. Upon activation of Alert,
conversion stops. For this mode, Set DATA_BUFFER_OPMODE to 100b. In this mode, the device starts
converting and stores the data on setting the bit in the SEQ_START register and continues to store the data into
the data buffer until one of the digital comparator flags is set for crossing a high threshold or a low threshold for
the channels selected in the sequence. If the SEQ_ABORT bit is set before the data buffer is filled, the device
aborts the sequence and stops storing the conversion results. If more than 16 conversions occur between start of
sequence and alert output, the first entries written into the data buffer are over-written.
Device stops conversions and Sets the Latched
flag and alert pin after count(=4) is reached
Conversion [N+ 15] for CHx
High Threshold
Sets the Output of the Comparator
Hysteresis
ADC Conversion Result
ADC Conversion Result
图 58 and 图 59 illustrates the filling of data buffer in autonomous mode with Pre alert Data.
Device stops conversions and
stops storing data in the buffer
after the count is reached
Conversion [N+ 15] for CHy
High Threshold - Hysteresis
Sets the Output of the
Comparator
Data Buffer
Conversion [N] for CHx
tCC
Conversion [N] for CHx
Conversion [N + 14] for CHx
Conversion [N + 15] for CHy
Conversion [N+1] for CHy
Conversion [N] for CHx
Conversion [0] for CHx
Data Buffer
Conversion [N] for CHx
Conversion [N + 1] for CHy
tCC
SEQ_START bit is set
by user
High Threshold
CHy is the channel which first triggered the ALERT
Conversion [N + 14] for CHx
Conversion [N + 15] for CHx
SEQ_START bit is set
by user
Conversion [0] for CHx
Conversion [1] for CHy
BUSY/RDY
BUSY/RDY
Time
Time
图 58. Pre Alert Data for Single Channel
Configurations
36
图 59. Pre Alert Data for Dual Channel
Configuration
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Autonomous Mode with Post Alert Data
In this mode, the device captures the next sixteen conversion results after the Alert is active. Once these sixteen
conversions are stored in the data buffer, all conversion stops. For this mode, Set DATA_BUFFER_OPMODE to
110b. In this mode, the device starts converting the data on setting the SEQ_START bit and stores the data in
the data buffer when one of the digital comparator flags is set after the crossing a high threshold or a low
threshold for the channels selected in the sequence. if the SEQ_ABORT bit is set before the data buffer is filled,
the device aborts the sequence and stops storing the conversion results.
ADC Conversion Result
图 60 and 图 61 illustrates the filling of the data buffer in autonomous mode with Post Alert Data.
Conversion [N+ 14] for CHx
Conversion [N+ 15] for CHx
Sets the Output of the
Comparator
SEQ_START bit is set
by user
Conversion [N] for CHx
tCC
Data Buffer
Conversion [N] for CHx
Device Starts storing data in
buffer and sets the Latched flag
and alert pin after the count is
reached
Conversion [N] for CHx
Hysteresis
Data Buffer
Conversion [N] for CHx
Conversion [N + 14] for CHx
Conversion [N + 15] for CHx
SEQ_START bit is set
by user
High Threshold - Hysteresis
Conversion [0] for CHx
Conversion [N+1] for CHy
Conversion [N + 14] for CHx
Conversion [N + 15] for CHy
CHx is the channel which first triggered the ALERT
Sets the Output of the
Comparator
High Threshold
Conversion [N+ 15] for CHy
Conversion [N + 1] for CHy
tCC
Device Starts storing data in
buffer and sets the Latched flag
and alert pin after count(=4) is
reached
Device stops conversions and
stops storing data in the buffer
after the data buffer is filled
ADC Conversion Result
Device stops conversions and
stops storing data in buffer after
the data buffer is filled
High Threshold
Conversion [0] for CHx
Conversion [1] for CHy
BUSY/RDY
Time
BUSY/RDY
Time
图 61. Post Alert Data for Dual Channel
Configuration
图 60. Post Alert Data for Single Channel
Configurations
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7.4.3.2 Autonomous Mode with Burst Data
In this mode, the device can be configured to store up-to 16 conversion results in the data buffer based on user
command. Applications that could take advantage of this mode are remote data loggers, environmental sensing
and patient monitors. In this mode, the user can either start the burst or stop the burst of data as described in the
following sections:
7.4.3.2.1 Autonomous Mode with Start Burst
Device stops conversions and stops filling
the data buffer after the buffer is filled
Conversion [15] for CHx
ADC Conversion Result
ADC Conversion Result
For this mode, set DATA_BUFFER_OPMODE to 001b. With Start Burst, the user can configure the device to
start the filling of data buffer with conversion results by setting the SEQ_START bit and the device stops
converting data and filling the data buffer after the data buffer is filled.
Conversion [14] for CH0
Device stops conversions and
stops storing data after the data
buffer is filled
Conversion [15] for CH1
Data Buffer
Conversion [0] for CH0
Conversion [1] for CH1
tCC
Data Buffer
Conversion [0] for CHx
tCC
SEQ_START bit is set
by user
Conversion [0] for CHx
Conversion [14] for CHx
Conversion [15] for CHx
Device starts
conversions and starts
storing data in the buffer
on setting the
SEQ_START bit
Conversion [14] for CH0
Conversion [15] for CH1
Conversion [0] for CH0
Conversion [1] for CH1
BUSY/RDY
BUSY/RDY
Time
Time
图 62. Start Burst with Single Channel
Configurations
38
图 63. Start Burst with Dual Channel
Configuration
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7.4.3.2.2 Autonomous Mode with Stop Burst
Device stops conversions and stops filling the
data buffer on setting the SEQ_ABORT bit
Conversion [N+ 15] for CHx
ADC Conversion Result
ADC Conversion Result
For this mode, Set DATA_BUFFER_OPMODE to 000b. With Stop Burst, the user can configure the device to
stop filling the data buffer with conversion results by setting the SEQ_ABORT bit. If more than 16 conversions
occur between start of sequence and abort of sequence, the entries first written into the data buffer are overwritten. 图 64 and 图 65 illustrate the filling of the data buffer in autonomous mode with Stop Burst.
Conversion [N+ 14] for CH0
Device stops conversions and
stops storing data on setting the
SEQ_ABORT bit
Conversion [N+ 15] for CH1
tCC
Data Buffer
Conversion [N] for CH0
tCC
Conversion [N + 1] for CH1
Data Buffer
Conversion [N] for CHx
Conversion [N] for CH0
Conversion [N] for CHx
SEQ_START bit is set
by user
Conversion [0] for CHx
Conversion [N + 14] for CH0
Conversion [N + 15] for CH1
Conversion [N+1] for CH1
Conversion [N + 14] for CHx
Conversion [N + 15] for CHx
SEQ_START bit is set
by user
Conversion [0] for CH0
Conversion [1] for CH1
BUSY/RDY
BUSY/RDY
Time
图 64. Stop Burst with Single Channel
Configurations
Time
图 65. Stop Burst with Dual Channel
Configuration
7.4.4 High Precision Mode
The High Precision Mode increases the accuracy of the data measurement to 16-bit accuracy. This is useful for
applications where the level of precision required to accurately measure the sensor output needs to be higher
than 12 bits. Applications that could take advantage of this type of functionality include gas detectors, air quality
testers, water quality testers, and so on.
For this mode, Set OPMODE_SEL register to 111b. In this mode, the device starts converting and starts
accumulating the conversion results in an accumulator on setting the SEQ_START bit. The device stops
accumulating the conversion results in accumulator after 16 conversions or when the SEQ_ABORT bit is set.
Upon accumulating 16 twelve bit conversions, the accumulator contains one 16 bit conversion result. The device
has an accumulator for each channel and the device accumulates conversion results from each channel into the
respective accumulator. If the operation of the device is aborted in high precision mode before the BUSY/RDY
pin goes low, the device provides invalid data. In this mode, on providing a device address and read bit for
reading data buffer (图 46), the device provides zeroes as output. In this mode, the BUSY/RDY can be used to
wake up the MCU or host from sleep or hibernation on completion of accumulation. The steps for configuring the
device into High Precision Mode are illustrated in 图 66 .
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High Precision Mode(1)
Select the Channels in AUTO
Sequence(2)
Select the Oscillator
& Set the nCLK value(3)
Enable the accumulator(4)
Set the SEQ_START Bit(5)
Device Starts Conversions
& Starts Accumulating Data
Check Busy/RDY
pin to see if 16
accumulations are
completed
No
Yes
Read the Accumulated Results(6)
Continue in High
Presicion Mode
Yes
No
Exit to another Operation Mode(7)
(1)
For setting the operation mode to High Precision mode, Refer to 图 54
(2)
Select the channels in the AUTO_SEQ_CFG register.
(3)
Select the oscillator by configuring the OSC_SEL register and configure the nCLK register.
(4)
Enable the accumulator by setting bits in the ACC_EN register.
(5)
Set the bit SEQ_START bit in the START_SEQUENCE register.
(6)
Read the ACC_CHx_xxx registers.
(7)
Select another operation mode in the OPMODE_SEL register.
(8)
For reading and writing registers, Refer to Device Programming section.
图 66. Configuring Device in High Precision Mode
It is recommended to abort the present sequence by setting the SEQ_ABORT bit before changing the device
operation mode or device configuration.
40
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ADC Conversion Result
ADC Conversion Result
图 67 illustrates the accumulation of conversion results in high precision mode.
Device stops after
accumulating 16
conversion results
Device starts
accumulating on setting
the SEQ_START bit
tCC
Accumulated in
Accumulator for CH0
Device starts
accumulating on setting
the SEQ_START bit
Device stops after
accumulating 16
conversion results
tCC
Conversion [15] for CHx
Conversion [15] for CH0
Conversion [0] for CHx
Conversion [0]
for CH0
Conversion [15] for CH1
Conversion [0] for CH1
BUSY/RDY
Accumulated in
Accumulator for CH1
BUSY/RDY
Time
Time
图 67. High Precision Mode with Single Channel
Configurations
图 68. High Precision Mode with Dual Channel
Configurations
7.5 Optimizing Power Consumed by the Device
IAVDD (PA)
•
•
Keep the analog supply voltage (AVDD) as close as possible to the analog input signal to the device. Set
AVDD to be greater than or equal to the analog input signal to the device.
Keep the digital supply voltage (DVDD) at the lowest permissible value.
In Manual Mode, run the device at the optimum sampling speed. Power consumption scales with Sampling
Speed. In Manual Mode, the sampling speed is dependent on time period (or frequency) of SCL (公式 7). 图
69 and 图 70 illustrate scaling of IAVDD and IDVDD with SCL in Manual Mode.
300
30
240
24
IDVDD (PA)
•
180
120
60
0
100
18
12
6
760
1420
2080
SCL (kHz)
2740
3400
0
100
760
D027
1420
2080
SCL (kHz)
2740
3400
D028
DVDD = 3.3 V
图 69. IAVDD in Manual Mode with SCL
•
图 70. IDVDD in Manual Mode with SCL
In Autonomous Modes and High Precision Mode, the balance between sampling speed and power
consumption can be obtained by selecting the oscillator for conversion and setting the nCLK value. The
device sampling speed and power consumption reduce by increasing the nCLK value. Refer to 图 71, 图 72,
图 73 and 图 74 for current consumption in Autonomous modes and High Precision mode with different nCLK
values.
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Optimizing Power Consumed by the Device (接
接下页)
1000
1
AVDD = 1.8 V
AVDD = 3 V
AVDD = 1.8 V
AVDD = 3 V
860
IAVDD (PA)
IAVDD (PA)
0.8
0.6
0.4
720
580
440
0.2
300
0
0
50
100
150
200
nCLK
Stop Burst Mode
0
250
50
100
150
200
250
nCLK
D032
With Low Power Oscillator
Stop Burst Mode
图 71. IAVDD in Autonomous Modes with nCLK
D033
With High Speed Oscillator
图 72. IAVDD in Autonomous Modes with nCLK
1000
0.6
AVDD = 1.8 V
AVDD = 3 V
800
IAVDD (PA)
IAVDD (PA)
0.48
0.36
0.24
600
400
200
0.12
AVDD = 1.8 V
AVDD = 3 V
0
0
0
50
100
150
200
250
nCLK
With Low Power Oscillator
图 73. IAVDD in High Precision Mode with nCLK
42
D043
0
50
100
150
200
250
nCLK
D044
With High Speed Oscillator
图 74. IAVDD in High Precision Mode with nCLK
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7.6 Register Map
表 5 provides the list of registers in the device. All the registers reset to their default values on power up and on
receiving a General Call with Software Reset. (See Reset section).
表 5. Register Map
S.NO.
ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
RESET REGISTERS
1
17h
WKEY
Write Key for writing into DEVICE_RESET register
2
14h
DEVICE_RESET
Resets the device
FUNCTIONAL MODE SELECT REGISTERS
3
15h
OFFSET_CAL
Initiates Internal Offset Calibration Cycle
4
1Ch
OPMODE_SEL
Sets the operation mode and enables auto-sequencing
5
00h
OPMODE_I2CMODE_STATUS
Provides the present Operating Mode and I2C mode information
CHANNEL_INPUT_CFG
Configures the analog input channels
INPUT CONFIG REGISTER
6
24h
ANALOG MUX and SEQUENCER REGISTERS
7
20h
AUTO_SEQ_CHEN
Enables Auto sequencing for selected channels
8
1Eh
START_SEQUENCE
Starts the channel scanning sequence
9
1Fh
ABORT_SEQUENCE
Aborts the channel scanning sequence
10
04h
SEQUENCE_STATUS
Provides the status of sequence in device
OSCILLATOR and TIMING CONTROL REGISTERS
11
18h
OSC_SEL
Selects the oscillator for the conversion process
12
19h
nCLK_SEL
Sets the nCLK for the device
DATA BUFFER CONTROL REGISTER
13
2Ch
DATA_BUFFER_OPMODE
Selects Data Buffer operation mode
14
28h
DOUT_FORMAT_CFG
Configures the data output format for data buffer
15
01h
DATA_BUFFER_STATUS
Provides the present status of Data Buffer
ACCUMULATOR CONTROL REGISTERS
16
30h
ACC_EN
Enables the Accumulator
17
08h
ACC_CH0_LSB
Provides the LSB of accumulated data for CH0 (Read Only)
18
09h
ACC_CH0_MSB
Provides the MSB of accumulated data for CH0 (Read Only)
19
0Ah
ACC_CH1_LSB
Provides the LSB of accumulated data for CH1 (Read Only)
20
0Bh
ACC_CH1_MSB
Provides the MSB of accumulated data for CH1 (Read Only)
21
02h
ACCUMULATOR_STATUS
Provides the present status of Accumulator
DIGITAL WINDOW COMPARATOR REGISTERS
22
37h
ALERT_DWC_EN
Enables the Alert and Digital Window Comparator block
23
34h
ALERT_CHEN
Enables Alert functionality for individual channels
24
39h
DWC_HTH_CH0_MSB
Sets the MSB for High threshold for CH0
25
38h
DWC_HTH_CH0_LSB
Sets the LSB for High Threshold for CH0
26
3Bh
DWC_LTH_CH0_MSB
Sets the MSB for Low threshold for CH0
27
3Ah
DWC_LTH_CH0_LSB
Sets the LSB for Low threshold for CH0
28
40h
DWC_HYS_CH0
Sets Hysteresis for CH0
29
3Dh
DWC_HTH_CH1_MSB
Sets the MSB for High threshold for CH1
30
3Ch
DWC_HTH_CH1_LSB
Sets the LSB for High threshold for CH1
31
3Fh
DWC_LTH_CH1_MSB
Sets the MSB for Low threshold for CH1
32
3Eh
DWC_LTH_CH1_LSB
Sets the LSB for Low threshold for CH1
33
41h
DWC_HYS_CH1
Sets Hysteresis for CH1
34
36h
PRE_ALT_MAX_EVENT_COUNT
Sets the Pre-Alert Event Counter for both channels
Provides the channel ID of channel which was first to set the alert output
35
03h
ALERT_TRIG_CHID
36
0Ch
ALERT_LOW_FLAGS
Latched flags for Low alert
37
0Eh
ALERT_HIGH_FLAGS
Latched flags for High alert
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7.6.1 RESET REGISTERS
These registers control the device reset operation (see Reset section).
7.6.1.1 WKEY Register (address = 17h), [reset = 00h]
A write to this register enables write access to the DEVICE_RESET register.
注
WKEY register is not reset to default value on device reset (see Reset section). After
coming out of device reset, write 00h to the WKEY register to prevent erroneous reset.
图 75. WKEY Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
2
1
0
KEYWORD[3:0]
R/W-0000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 6. WKEY Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved Bits. Do not write. Read returns 0000b
3-0
KEYWORD[3:0]
R/W
0000b
Write 1010b into these bits to get write access for the
DEVICE_RESET register.
7.6.1.2 DEVICE_RESET Register (address = 14h), [reset = 00h]
A write to this register resets the device (see Reset section).
注
KEYWORD[3:0] bits in the WKEY register must be programmed to 1010b to enable write
into the DEVICE_RESET register.
图 76. DEVICE_RESET Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
0
R-0b
1
0
R-0b
0
DEV_RST
W-0b
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 7. DEVICE_RESET Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0000000b
Reserved Bits. Read returns 0000000b
DEV_RST
W
0b
Writing 1 into this bit resets the device.
0
44
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7.6.2 FUNCTIONAL MODE SELECT REGISTERS
These set of registers select the functional mode of the device.
7.6.2.1 OFFSET_CAL Register (address = 15h), [reset = 00h]
Write to this register initiates internal offset calibration cycle (see Offset Calibration).
图 77. OFFSET_CAL Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
0
R-0b
1
0
R-0b
0
TRIG_OFFCAL
W-0b
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 8. OFFSET_CAL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0000000b
Reserved Bits. Read returns 0000000b
TRIG_OFFCAL
W
0b
Writing 1 into this bit triggers internal offset calibration.
0
7.6.2.2 OPMODE_SEL Register (address = 1Ch), [reset = 00h]
Write to this register sets the Operation Mode of the device.
图 78. OPMODE_SEL Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
1
SEL_OPMODE[2:0]
R/W-000b
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 9. OPMODE_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
00000b
Reserved Bits. Read returns 00000b
2-0
SEL_OPMODE[2:0]
R/W
000b
These bits set the functional mode for the device
000b = Manual Mode with CH0 only. (Default Mode).
001b = Same as 000b.
010b = Reserved, Do not use.
011b = Reserved, Do not use.
100b = Manual Mode with AUTO Sequencing enabled.
101b = Manual Mode with AUTO Sequencing enabled.
110b = Autonomous Monitoring Mode with AUTO Sequencing
enabled.
111b = High Precision Mode with AUTO Sequencing enabled.
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7.6.2.3 OPMODE_I2CMODE_STATUS Register (address = 00h), [reset = 00h]
This register provides the present operation mode and I2C mode information (Read Only).
图 79. OPMODE_I2CMODE_STATUS Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
HS_MODE
R-0b
1
0
DEV_OPMODE[1:0]
R-00b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. OPMODE_I2CMODE_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
00000b
Reserved bits. Reads return 00000b.
2
HS_MODE
R
0b
Indicates when device in High speed mode for I2C Interface.
0b = Device is not in High speed mode for I2C Interface.
1b = Device is in High speed mode for I2C Interface.
DEV_OPMODE[1:0]
R
00b
Indicates the functional mode of the device.
00b = Device is operating in Manual Mode
01b = Not Used
10b = Device is operating in Autonomous Monitoring Mode
11b = Device is operating in High Precision Mode
1-0
7.6.3 INPUT CONFIG REGISTER
This register configures the analog input pins of the device (see Analog Input and Multiplexer).
7.6.3.1 CHANNEL_INPUT_CFG Register (address = 24h), [reset = 00h]
Write to this register configures the analog input channels. .
图 80. CHANNEL_INPUT_CFG Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
0
R-0b
1
0
CH0_CH1_IP_CFG[1:0]
R/W-00b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 11. CHANNEL_INPUT_CFG Register Field Descriptions
46
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000b
Reserved Bits. Read returns 000000b
1-0
CH0_CH1_IP_CFG[1:0]
R/W
00b
Selects configuration for the input pins
00b = Two-Channel, Single-Ended configuration
01b = Single-Channel, Single-Ended configuration with Remote
Ground Sensing
10b = Single-Channel, Pseudo-Differential configuration
11b = Two-Channel, Single-Ended configuration
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7.6.4 ANALOG MUX and SEQUENCER REGISTERS
These registers configure the analog multiplexer and channel sequencing.
7.6.4.1 AUTO_SEQ_CHEN Register (address = 20h), [reset = 03h]
This register selects the channels that are scanned when Auto-Sequencing is enabled. By default, both channels
are selected at power up.
图 81. AUTO_SEQ_CHEN Register
7
0
6
0
5
0
4
0
3
0
2
0
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
1
AUTOSEQ_EN
_CH1
R/W-1b
0
AUTOSEQ_EN
_CH0
R/W-1b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 12. AUTO_SEQ_CHEN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000b
Reserved Bits. Read returns 000000b
1
AUTO_SEQ_CH1
R/W
1b
0 = Channel 1 is not selected for auto sequencing
1= Channel 1 is selected for auto sequencing
0
AUTO_SEQ_CH0
R/W
1b
0 = Channel 0 is not selected for auto sequencing
1= Channel 0 is selected for auto sequencing
7.6.4.2 START_SEQUENCE Register (address = 1Eh), [reset = 00h]
A write to this register starts the channel scanning sequence.
图 82. START_SEQUENCE Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
0
R-0b
1
0
R-0b
0
SEQ_START
W-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 13. START_SEQUENCE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0000000b
Reserved Bits. Read returns 0000000b
0
SEQ_START
W
0b
Setting this bit = 1 brings the BUSY/RDY pin high and starts the first
conversion in the sequence
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7.6.4.3 ABORT_SEQUENCE Register (address = 1Fh), [reset = 00h]
A write to this register aborts the channel scanning sequence. Once sequence is aborted using this register, it is
recommended to read the DATA_BUFFER_STATUS register to know the number of entries filled in the data
buffer or ACCUMULATOR_STATUS register to know number of accumulations finished before the abort.
图 83. ABORT_SEQUENCE Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
0
R-0b
1
0
R-0b
0
SEQ_ABORT
W-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 14. ABORT_SEQUENCE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0000000b
Reserved Bits. Read returns 0000000b
SEQ_ABORT
W
0b
Setting this bit = 1 aborts the ongoing conversion and brings the
BUSY/RDY pin low
0
7.6.4.4 SEQUENCE_STATUS Register (address = 04h), [reset = 00h]
Provides the status of sequence in device (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 84. SEQUENCE_STATUS Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
1
SEQ_ERR_ST[1:0]
R-00b
0
0
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 15. SEQUENCE_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
00000b
Reserved bits. Reads return 00000b.
2-1
SEQ_ERR_ST[1:0]
R
00b
Status of device sequence
00b = Auto Sequencing disabled, no error.
01b = Auto Sequencing enabled, no error.
10b = Not used
11b = Auto Sequencing enabled, device in error.
0
R
0b
Reserved bit. Reads return 0.
0
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7.6.5 OSCILLATOR and TIMING CONTROL REGISTERS
These registers select the oscillator used for the conversion process and cycle time for a single conversion (see
Oscillator and Timing Control section).
7.6.5.1 OSC_SEL Register (address = 18h), [reset = 00h]
A write to this register selects the oscillator used for the conversion process.
图 85. OSC_SEL Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
0
R-0b
1
0
R-0b
0
HSZ_LP
R/W-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 16. OSC_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0000000b
Reserved Bits. Read returns 0000000b
HSZ_LP
R/W
0b
0b = Device uses High Speed Oscillator
1b = Device uses Low Power Oscillator
0
7.6.5.2 nCLK_SEL Register (address = 19h), [reset = 00h]
This register controls the cycle time for a single conversion by setting the nCLK parameter. nCLK is the number
of clocks of the selected oscillator that the device uses for one conversion cycle.
图 86. nCLK_SEL Register
7
6
5
4
3
2
1
0
nCLK[7:0]
R/W-00000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 17. nCLK_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
nCLK[7:0]
R/W
00000000b
Sets number of clocks of the oscillator that the device uses for one
conversion cycle.
When using the High Speed Oscillator: For Value x written into the
nCLK register
•
if x ≤ 21, nCLK is set to 21 (00010101b)
•
if x > 21, nCLK is set to x
When using the Low Power Oscillator, For Value x written into the
nCLK register:
•
if x ≤ 18, nCLK is set to 18 (00010010b)
•
if x > 18, nCLK is set to x
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7.6.6 DATA BUFFER CONTROL REGISTER
This register controls the operation of the Data Buffer (see Data Buffer section).
7.6.6.1 DATA_BUFFER_OPMODE Register (address = 2Ch), [reset = 01h]
A write to this register selects the operation mode of the Data Buffer.
图 87. DATA_BUFFER_OPMODE Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
1
STARTSTOP_CNTRL[2:0]
R/W-001b
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 18. DATA_BUFFER_OPMODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
00000b
Reserved Bits. Read returns 00000b
2-0
STARTSTOP_CNTRL [2:0]
R/W
001b
000b = Stop Burst Mode
001b = Start Burst Mode, default
010b = Reserved, do not use
011b = Reserved, do not use
100b = Pre Alert Data Mode
101b = Reserved, do not use
110b = Post Alert Data Mode
111b = Reserved, do not use
7.6.6.2 DOUT_FORMAT_CFG Register (address = 28h), [reset = 00h]
This register controls the 16-bit contents of the data word in the data buffer.
图 88. DOUT_FORMAT_CFG Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
0
R-0b
2
0
R-0b
1
0
DOUT_FORMAT[1:0]
R/W-00b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 19. DOUT_FORMAT_CFG Register Field Descriptions
50
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000b
Reserved Bits. Read returns 000000b
1-0
DOUT_FORMAT[1:0]
R/W
00b
00b = 12-bit conversion result followed by 0000b
01b = 12-bit conversion result followed by 3-bit Channel ID (000b for
CH0, 001b for CH1)
10b = 12-bit conversion result followed by 3-bit Channel ID (000b for
CH0, 001b for CH1) followed by DATA_VALID bit
11b = 12-bit conversion result followed by 0000b
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7.6.6.3 DATA_BUFFER_STATUS Register (address = 01h), [reset = 00h]
Provides the number of entries filled in the data buffer till last conversion. (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 89. DATA_BUFFER_STATUS Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
3
2
DATA_WORDCOUNT[4:0]
R-00000b
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 20. DATA_BUFFER_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
000b
Reserved Bits. Read returns 000b
4-0
DATA_WORDCOUNT R
[4:0]
00000b
DATA_WORDCOUNT [00000] to [10000] = Number of entries filled
in data buffer (0 to 16)
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7.6.7 ACCUMULATOR CONTROL REGISTERS
These registers control the operation of the Accumulator (see Accumulator section).
7.6.7.1 ACC_EN Register (address = 30h), [reset = 00h]
This register enables the accumulator.
图 90. ACC_EN Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
2
1
0
EN_ACC[3:0]
R/W-0000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 21. ACC_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved Bits. Read returns 0000b
3-0
EN_ACC[3:0]
R/W
0000b
0000b = Accumulator is disabled
0001b to 1110b = Reserved, do not use
1111b = Accumulator is enabled
7.6.7.2 ACC_CH0_LSB Register (address = 08h), [reset = 00h]
Provides the LSB of accumulated data for CH0 (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 91. ACC_CH0_LSB Register
7
6
5
4
3
2
1
0
CH0_LSB[7:0]
R-00000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 22. ACC_CH0_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH0_LSB[7:0]
R
00000000b
LSB of accumulated data for CH0
7.6.7.3 ACC_CH0_MSB Register (address = 09h), [reset = 00h]
Provides the MSB of accumulated data for CH0 (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 92. ACC_CH0_MSB Register
7
6
5
4
3
2
1
0
CH0_MSB[7:0]
R-00000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 23. ACC_CH0_MSB Register Field Descriptions
52
Bit
Field
Type
Reset
Description
7-0
CH0_MSB[7:0]
R
00000000b
MSB of accumulated data for CH0
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7.6.7.4 ACC_CH1_LSB Register (address = 0Ah), [reset = 00h]
Provides the LSB of accumulated data for CH1 (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 93. ACC_CH1 LSB Register
7
6
5
4
3
2
1
0
CH1_LSB[7:0]
R-00000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. ACC_CH1 LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH1_LSB[7:0]
R
00000000b
LSB of accumulated data for CH1
7.6.7.5 ACC_CH1_MSB Register (address = 0Bh), [reset = 00h]
Provides the MSB of accumulated data for CH1 (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 94. ACC_CH1 MSB Register
7
6
5
4
3
2
1
0
CH1_MSB[7:0]
R-00000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 25. ACC_CH1 MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH1_MSB[7:0]
R
00000000b
MSB of accumulated data for CH1
7.6.7.6 ACCUMULATOR_STATUS Register (address = 02h), [reset = 00h]
Provides the present status of Accumulator (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 95. ACCUMULATOR_STATUS Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
2
1
ACC_COUNT[3:0]
R-0000b
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 26. ACCUMULATOR_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved Bits. Read returns 0000b
3-0
ACC_COUNT[3:0]
R
0000b
ACC_COUNT = Number of accumulation completed till last finished
conversion.
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7.6.8 DIGITAL WINDOW COMPARATOR REGISTERS
These registers control the operation of the Digital Window Comparator (see Digital Window Comparator
section).
7.6.8.1 ALERT_DWC_EN Register (address = 37h), [reset = 00h]
Write to this register enables the Alert and Digital Window Comparator block.
图 96. ALERT_DWC_EN Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
0
DWC_BLOCK_
EN
R/W-0b
1
ALERT_EN_C
H1
R/W-1b
0
ALERT_EN_C
H0
R/W-1b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 27. ALERT_DWC_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0000000b
Reserved Bits. Read returns 0000000b
DWC_BLOCK_EN
R/W
0b
0 = Disables Digital Window Comparator
1 = Enables Digital Window Comparator
0
7.6.8.2 ALERT_CHEN (address = 34h), [reset = 00h]
This register enables Alert functionality for individual channels.
图 97. ALERT_CHEN Register
7
0
6
0
5
0
4
0
3
0
2
0
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 28. ALERT_CHEN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000b
Reserved Bits. Read returns 000000b
1
ALERT_EN_CH1
R/W
0b
Enables alert functionality for CH1
0b = Alert is disabled for CH1, default
1b = Alert is enabled for CH1
0
ALERT_EN_CH0
R/W
0b
Enables alert functionality for CH0
0b = Alert is disabled for CH0, default
1b = Alert is enabled for CH0
7.6.8.3 DWC_HTH_CH0_MSB Register (address = 39h), [reset = 00h]
This register sets the four most significant bits of high threshold for CH0.
图 98. DWC_HTH_CH0_MSB Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
2
1
HTH_CH0_MSB[3:0]
R/W-0000b
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 29. DWC_HTH_CH0_LSB Register Field Descriptions
54
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved Bits. Read returns 0000b
3-0
HTH_CH0_MSB[3:0]
R/W
0000b
4 most significant bits of high threshold for CH0
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7.6.8.4 DWC_HTH_CH0_LSB Register (address = 38h), [reset = 00h]
This register sets the eight least significant bits of high threshold for CH0.
图 99. DWC_HTH_CH0_LSB Register
7
6
5
4
3
HTH_CH0_LSB[7:0]
R/W-00000000b
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 30. DWC_HTH_CH0_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
HTH_CH0_LSB[7:0]
R/W
00000000b
8 least significant bits of high threshold for CH0
7.6.8.5 DWC_LTH_CH0_MSB Register (address = 3Bh), [reset = 00h]
This register sets the four most significant bits of low threshold for CH0.
图 100. DWC_LTH_CH0_MSB Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
2
1
LTH_CH0_MSB[3:0]
R/W-0000b
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 31. DWC_LTH_CH0_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved Bits. Read returns 0000b
3-0
LTH_CH0_MSB[3:0]
R/W
0000b
4 most significant bits of low threshold for CH0
7.6.8.6 DWC_LTH_CH0_LSB Register (address = 3Ah), [reset = 00h]
This register sets the eight least significant bits of low threshold for CH0.
图 101. DWC_LTH_CH0_LSB Register
7
6
5
4
3
LTH_CH0_LSB[7:0]
R/W-00000000b
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 32. DWC_LTH_CH0_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LTH_CH0_LSB[7:0]
R/W
00000000b
8 least significant bits of low threshold for CH0
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7.6.8.7 DWC_HYS_CH0 (address = 40h), [reset = 00h]
This register sets the hysteresis for both comparators for CH0.
图 102. DWC_HYS_CH0 Register
7
0
R-0b
6
0
R-0b
5
4
3
2
1
0
HYS_CH0[5:0]
R/W-000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 33. DWC_HYS_CH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
00b
Reserved Bits. Read returns 0000000b
5-0
HYS_CH0[5:0]
R/W
000000b
Hysteresis for both comparators for CH0
7.6.8.8 DWC_HTH_CH1_MSB Register (address = 3Dh), [reset = 00h]
This register sets the four most significant bits of high threshold for CH1.
图 103. DWC_HTH_CH1_MSB Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
2
1
HTH_CH1_MSB[3:0]
R/W-0000b
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 34. DWC_HTH_CH1_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved Bits. Read returns 0000b
3-0
HTH_CH1_MSB[3:0]
R/W
0000b
4 most significant bits of high threshold for CH1
7.6.8.9 DWC_HTH_CH1_LSB Register (address = 3Ch), [reset = 00h]
This register sets the eight least significant bits of high threshold for CH1.
图 104. DWC_HTH_CH1_LSB Register
7
6
5
4
3
HTH_CH1_LSB[7:0]
R/W-00000000b
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 35. DWC_HTH_CH1_LSB Register Field Descriptions
56
Bit
Field
Type
Reset
Description
7-0
HTH_CH1_LSB[7:0]
R/W
00000000b
8 least significant bits of high threshold for CH1
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7.6.8.10 DWC_LTH_CH1_MSB Register (address = 3Fh), [reset = 00h]
This register sets the four most significant bits of low threshold for CH1.
图 105. DWC_LTH_CH1_MSB Register
7
0
R-0b
6
0
R-0b
5
0
R-0b
4
0
R-0b
3
2
1
LTH_CH1_MSB[3:0]
R/W-0000b
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 36. DWC_LTH_CH1_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved Bits. Read returns 0000b
3-0
LTH_CH1_MSB[3:0]
R/W
0000b
4 most significant bits of low threshold for CH1
7.6.8.11 DWC_LTH_CH1_LSB Register (address = 3Eh), [reset = 00h]
This register sets the eight least significant bits of low threshold for CH1.
图 106. DWC_LTH_CH1_LSB Register
7
6
5
4
3
LTH_CH1_LSB[7:0]
R/W-00000000b
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 37. DWC_LTH_CH1_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LTH_CH1_LSB[7:0]
R/W
00000000b
8 least significant bits of low threshold for CH1
7.6.8.12 DWC_HYS_CH1 (address = 41h), [reset = 00h]
This register sets the hysteresis for both comparators for CH1.
图 107. DWC_HYS_CH1 Register
7
0
R-0b
6
0
R-0b
5
4
3
2
1
0
HYS_CH1[5:0]
R/W-000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 38. DWC_HYS_CH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
00b
Reserved Bits. Read returns 0000000b
5-0
HYS_CH1[5:0]
R/W
000000b
Hysteresis for both comparators for CH1
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PRE_ALT_MAX_EVENT_COUNT Register (address = 36h), [reset = 00h]
This register sets the Pre-Alert Event Count for both, high and low comparators, for both the channels.
图 108. PRE_ALT_MAX_EVENT_COUNT Register
7
6
5
PREALERT_COUNT[3:0]
R/W-0000b
4
3
0
R-0b
2
0
R-0b
1
0
R-0b
0
0
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 39. PRE_ALT_MAX_EVENT_COUNT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
PREALERT_COUNT[3:0]
R/W
0000b
Sets the Pre-Alert Event Count = PREALERT_COUNT[3:0] + 1
3-0
RESERVED
R
0000b
Reserved Bits. Read returns 0000b
7.6.8.14 ALERT_TRIG_CHID Register (address = 03h), [reset = 00h]
Provides the channel ID of channel which was first to set the alert output (Read Only).
This register is cleared at power-up, on receiving general call reset, on device reset or when SEQ_START bit in
START_SEQUENCE register is set to 1.
图 109. ALERT_TRIG_CHID Register
7
6
5
ALERT_TRIG_CHID[3:0]
R-0000b
4
3
0
R-0b
2
0
R-0b
1
0
R-0b
0
0
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 40. ALERT_TRIG_CHID Register Field Descriptions
58
Bit
Field
Type
Reset
Description
7-4
ALERT_TRIG_CHID[3:0]
R
0000b
Provides the channel ID of channel which was first to set the
alert output
0000b = Channel 0
0001b = Channel 1
0010b to 1111b = Not used
3-0
RESERVED
R
0000b
Reserved bits. Reads return 0000b.
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7.6.8.15 ALERT_LOW_FLAGS Register (address = 0C), [reset = 00h]
This register provides the status of latched flags for low alert. All flags are cleared at power up, on general call
reset (General Call with Software Reset), or by writing FFh to this register. To clear individual alert flag, write 1 to
the corresponding bit location. It is recommended to reset the flags when device is not busy (BUSY/RDY pin is
low).
图 110. ALERT_LOW_FLAGS Register
7
0
6
0
5
0
4
0
3
0
2
0
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
1
ALERT_LOW_
CH1
R/W-0b
0
ALERT_LOW_
CH0
R/W-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 41. ALERT_LOW_FLAGS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000b
Reserved Bits. Read returns 000000b
1
ALERT_LOW_CH1
R/W
0b
Indicates alert on low side comparator for CH1
0b = Alert is not set for low side comparator for CH1
1b = Alert is set for low side comparator for CH1.
0
ALERT_LOW_CH0
R/W
0b
Indicates alert on low side comparator for CH0
0b = Alert is not set for low side comparator for CH0
1b = Alert is set for low side comparator for CH0.
7.6.8.16 ALERT_HIGH_FLAGS Register (address = 0Eh), [reset = 00h]
This register provides the status of latched flags for high alert. All flags are cleared at power up, on general call
reset (General Call with Software Reset), or by writing FFh to this register. To clear individual alert flag, write 1 to
the corresponding bit location. It is recommended to reset the flags when device is not busy (BUSY/RDY pin is
low).
图 111. ALERT_HIGH_FLAGS Register
7
0
6
0
5
0
4
0
3
0
2
0
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
1
ALERT_HIGH_
CH1
R/W-0b
0
ALERT_HIGH_
CH0
R/W-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 42. ALERT_HIGH_FLAGS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000b
Reserved Bits. Read returns 000000b
1
ALERT_HIGH_CH1
R/W
0b
Indicates alert on high side comparator for CH1
0b = Alert is not set for high side comparator for CH1
1b = Alert is set for high side comparator for CH1.
0
ALERT_HIGH_CH0
R/W
0b
Indicates alert on high side comparator for CH0
0b = Alert is not set for high side comparator for CH0
1b = Alert is set for high side comparator for CH0.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
In an increasing number of industrial applications, data acquisition sub-systems are collecting more data about
the environment in which the system is operating and applying deep learning algorithms in order to improve
system reliability, implement preventative maintenance, and/or enhance the quality of data collected by the
system. The ADS7142 can be used to connect to a variety of sensors and can provide deeper data analytics at
lower power levels than existing solutions. The depth of analysis that can be performed on the data collected by
the ADS7142 is enhanced by the internal data buffer, programmable alarm thresholds and hysteresis, event
counter, and internal calibration circuitry. The applications circuits described in this section highlight specific usecases of the ADS7142 for data collection that can further increase the depth and quality of the data being
measured by the system.
8.2 Typical Applications
8.2.1 ADS7142 as a Programmable Comparator with False Trigger Prevention and Diagnostics
+VDD
R
RL
No 1
VREF(UPPER)
+
A1
VOUT
VIN
R
+
VREF(LOWER)
A2
R
Copyright © 2017, Texas Instruments Incorporated
图 112. Analog Window Comparator
8.2.1.1 Design Requirements
In many applications such as industrial alarms, sensor monitors, and level sensors, there is a need to make a
decision at the system-level when the input signal crosses a predefined threshold. Analog window comparators
are being used extensively in such applications.
An analog window comparator has a set of comparators. The external input signal is connected to the inverting
terminal of one comparator and the noninverting terminal of the other comparator. The remaining input of each
comparator is connected to the internal reference. The outputs are tied together and are often connected to a
reset or general-purpose input of a processor (such as a digital signal processor, field-programmable gate array,
or application-specific integrated circuit) or the enable input of a voltage regulator (such as a DC-DC or lowdropout regulator). 图 112 shows the circuit diagram for an analog window comparator.
60
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Typical Applications (接
接下页)
Though analog comparators are easy to design, there are certain disadvantages associated with analog
comparators.
8.2.1.1.1 Higher Power Consumption
If the voltage that is monitored is greater than the window comparator supply voltage, then there is a need for a
resistive divider ladder to scale down that voltage. This resistive ladder draws a constant current and adds to the
power consumption of the system. In battery powered applications, this becomes a challenge and can adversely
affect the battery life.
8.2.1.1.2
Fixed Threshold Voltages
The window comparator thresholds cannot be changed on-the-fly since these are set by hardware (typically with
a resistive ladder). This may add a limitation if the user wants to change the comparator thresholds during
operation without switching in a new resistor ladder.
Many applications in the field of preventive maintenance, building automation, and Internet of Things (IoT)
require a sensor monitor which operates autonomously and gives an alert/interrupt to the host MCU only when
the sensor output crosses a predefined, programmable threshold. Typically battery-operated, wireless sensor
nodes like smoke detectors, temperature monitors, ambient light sensors, proximity sensors and gas sensors fall
under this category. The ADS7142 is an excellent fit for such sensor monitoring systems due to its ability to
autonomously monitor sensor output and wake up the host controller whenever the sensor output crosses predefined thresholds. Additionally, the ADS7142 has an internal data buffer which can store 16 sample data which
the user can read if further analysis is required. 图 113 shows typical block diagram of ADS7142 as sensor
monitor. As is shown in 图 113, the sensor can be connected directly to the input of the ADC (depending on the
sensor output signal characteristics).
3V3
+
RFLT
SCL
C
Sensor 1
AIN0
SDA
ADS7142
GND
GND
AIN1
BUSY/RDY
+
RFLT
Host MCU
ALERT
C
Sensor 2
GND
GND
GND
GND
Copyright © 2017, Texas Instruments Incorporated
图 113. Sensor Monitor Circuit with ADS7142
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Typical Applications (接
接下页)
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Programmable Thresholds and Hysteresis
The ADS7142 can be programmed to monitor sensor output voltages and generate an ALERT signal for the host
controller if the sensor output voltage crosses a threshold.
The device can be configured to monitor for signals rising above a programmed threshold. 图 114 illustrates the
operation of the device when monitoring for signal crossings on the low threshold by setting the high threshold to
0xFFF. In this example, the output of the low-side comparator is set whenever the ADC conversion result is less
than or equal to the low threshold, and the output of the high-side comparator is only set when the ADC
conversion result is equal to 0xFFF.
The device can also be configured to monitor for signals falling below a programmed threshold. 图 115 illustrates
the operation of the device when monitoring for signal crossings on the high threshold by setting the low
threshold to 0x000. In this example, the output of high-side comparator is set whenever the ADC conversion
result is greater than or equal to the high threshold and the output of the low-side comparator is only set when
the ADC conversion result is equal to 0x000.
High Threshold = 0xFFF
Hysteresis
High Threshold - Hysteresis
PRE_ALT_MAX_EVENT_COUNT = 50h
±
Conversion [N+9] for CHx
+
High Side Comparator
Conversion [N+4] for CHx
Conversion [N] for CHx
Low Threshold + Hysteresis
Low Side Comparator
±
Hysteresis
High Threshold
High Threshold - Hysteresis
High Side Comparator
+
Conversion [N+5] for CHx
High Side Comparator Output
(Internal Signal Only)
±
+
Low Threshold
Conversion [N+10] for CHx
PRE_ALT_MAX_EVENT_COUNT = 50h
Low Threshold + Hysteresis
Conversion [N] for CHx
Low Side Comparator
±
+
Low Threshold = 0x000
Low Side Comparator Output
(Internal Signal Only)
Low Side Comparator Output
(Internal Signal Only)
ALERT
图 114. Low Alert with ADS7142
High Side Comparator Output
(Internal Signal Only)
ALERT
图 115. High Alert with ADS7142
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The device can also be configured to monitor for signals falling outside of a programmed window. 图 116
illustrates the operation of the device for an out-of-range alert where the signal leaves the pre-defined window
and crosses either the high or low threshold. In this example, the output of low side comparator is set whenever
the ADC conversion result is less than or equal to the low threshold, and the output of high side comparator is
set when the ADC conversion result is greater than or equal to the high threshold.
PRE_ALT_MAX_EVENT_COUNT = 50h
Conversion [N+12] for CHx
Conversion [N+7] for CHx
Hysteresis
High Threshold
High Threshold - Hysteresis
±
+
High Side Comparator
Low Threshold + Hysteresis
Low Side Comparator
±
+
Conversion [N] for CHx
Low Threshold
Low Side Comparator Output
(Internal Signal Only)
High Side Comparator Output
(Internal Signal Only)
ALERT
图 116. Out of Range Alert with ADS7142
8.2.1.2.2 False Trigger Prevention with Event Counter
The Pre-Alert event counter in the Digital Window Comparator helps to prevent false triggers. The alert output is
not set until the output of the comparator remains set for a pre-defined number (count) of consecutive
conversions.
8.2.1.2.3 Fault Diagnostics with Data Buffer
The modes which are specifically designed for autonomous sensor monitor applications are Pre-Alert mode and
Post-Alert mode. In Pre-Alert mode, the ADS7142 can be configured to monitor sensor outputs and continuously
fill the internal data buffer until a threshold crossing occurs. The ADS7142 generates an ALERT signal when the
sensor output falls outside of the predefined window of operation. In this particular mode, the ADS7142 stops
filling the data buffer when the threshold is crossed and provides the last 16 samples (15 sample data preceding
the sample at which the ALERT is generated and 1 sample data for which the ALERT is generated). 图 117
shows the ADS7142 operation in Pre-Alert mode showing 16 data samples before the sensor output crosses the
low threshold. This is useful for applications where the state of the signal before the threshold is crossed is
important to capture. Using the data captured before the alert, deep data analysis can be performed to determine
the state of the system before the alert. This type of data is not available with analog comparators.
In Post-Alert mode, ADS7142 can be configured to monitor sensor outputs and start filling the internal data buffer
after a threshold crossing occurs. The ADS7142 generates an ALERT signal when the sensor output falls outside
of the predefined window of operation. In this particular mode, the ADS7142 continues to fill the data buffer after
the threshold is crossed for a total of 16 samples (1 sample data for which ALERT is generated and 15 sample
data after the sample at which ALERT is generated). 图 118 shows the ADS7142 operation in Post-Alert mode
showing 16 data samples after the sensor output crosses the high threshold. This is useful for applications where
the state of the signal after the threshold is crossed is important to capture. Using the data captured after the
alert, deep data analysis can be performed for to determine the state of the system after the alert to detect
system-level events such as saturation. This data is not available with analog comparators.
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www.ti.com.cn
8.2.1.3 Application Curve
图 117. Pre-Alert Data Capture
图 118. Post Alert Data Capture
64
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ADS7142
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ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
8.2.2 Event-triggered PIR sensing with ADS7142
PIR
Sensor
1.8V to 3.3V
PIR OUTPUT
SCL
R
LPV812
C
ADS7142
SDA
HOST MCU
ALERT
Copyright © 2017, Texas Instruments Incorporated
图 119. PIR Sensor with ADS7142
8.2.2.1 Design Requirements
A passive infrared (PIR) sensor is a commonly used sensor to detect motion by measuring infrared light emitted
from any object that generates heat. PIR sensors are small, inexpensive, low-power, rugged, have a wide lens
range, and are easy to use. PIR sensors are commonly used in security lighting and alarm systems used in
indoor environments. When there is no motion or heat-emitting object in the vicinity of the sensor, the PIR sensor
output is a DC voltage which is typically specified in the PIR datasheet. When a source of heat, such as a person
or animal, comes into the sensor field of view, then the PIR sensor output changes. The amplitude of this signal
is proportional to the speed and distance of the object relative to the sensor and is in the range of millivolts peakto-peak. PIR sensors are often followed by a signal conditioning stage which amplifies the IR sensor output. A
PIR sensor can be interfaced with the ADS7142 to make an ultra-low-power, autonomous PIR motion detector.
The Autonomous Modes of the ADS7142 with threshold monitoring enables the system to put the host MCU into
a low-power sleep mode and wake up the MCU only when motion is detected by the PIR sensor. 图 119 shows a
typical block diagram for an autonomous PIR motion detector using the ADS7142.
8.2.2.2 Detailed Design Procedure
The analog signal conditioning circuit is shown in the schematic in 图 120. The first stage of the amplifier filter
acts as a bandpass filter while the second stage applies an inverting gain. Components R10 and C5 serve as a
low-pass filter to stabilize the supply voltage at the input to the sensor. Resistor R5 sets the bias current in the
JFET output transistor of the PIR motion sensor. To save power, R5 is larger than recommended and essentially
current starves the sensor. This comes at the expense of decreased sensitivity and higher output noise at the
sensor output, which is a fair tradeoff for increased battery lifetime. Some of the loss in sensitivity at the sensor
output can be compensated by a gain increase in the filter stages. Stage 1 of 图 120 is arranged as a noninverting gain filter stage. This provides a high-impedance load to the sensor so its bias point remains fixed.
Because this stage has an effective DC gain of one due to C2, the sensor output bias voltage provides the DC
bias for the first filter stage. Feedback diodes D1 and D2 provide clamping so that the op amps in both filter
stages stay out of saturation for motion events which are close to the sensor. Stage 1 has a low and high cutoff
frequency of 0.7 Hz and 10.6 Hz respectively and a gain of 220. Stage 2 is arranged as an inverting summer
gain stage and is AC-coupled to Stage 1. A DC bias of VCC/2 is connected to the non-inverting input of the
amplifier in this stage. Due to the higher gain in the filter stages and higher output noise from the sensor, care
must be taken to optimize the placement of the high-frequency filter pole and the window comparator thresholds
to avoid false detection.
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VCC
R10
619 NŸ
15 0Ÿ
R3
C3
C5
100 µF
VCC
0.1 µF
PIR
PIR =
IRS-B345ST03-R1
1000 pF
VCC
0.1 µF
+
C4
R4
A1
R5
1.3 0Ÿ
3.3 µF 68.1 NŸ
R1
C1
To Analog Input
of ADS7142
A2
+
1.5 0Ÿ
0.01 µF
C6
0.1 µF
VCC/2
D1
VCC = 1.8 to 3.3 V
D2
A1 and A2 = LPV812
R2
6.81 NŸ
C2
33 µF
Stage1
Stage2
Copyright © 2017, Texas Instruments Incorporated
图 120. Signal Conditioning Circuit for PIR Sensor
8.2.2.3 Application Curves
When the PIR sensor detects motion, its output crosses the threshold and is detected by the ADS7142 as shown
on Channel 1 in 图 121.
图 121. Alert Output from ADS7142 with PIR Sensor
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ADS7142
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ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
9 Power-Supply Recommendations
9.1 AVDD and DVDD Supply Recommendations
The ADS7142 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges. The AVDD supply also defines the full-scale input range of the device. Always set the AVDD supply to
be greater than or equal to the maximum input signal to avoid saturation of codes. Decouple the AVDD and
DVDD pins respectively with 220-nF and 100-nF ceramic decoupling capacitors, as shown in 图 122 .
AVDD
CAVDD
GND
CDVDD
DVDD
Copyright © 2016, Texas Instruments Incorporated
图 122. Power-Supply Decoupling
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10 Layout
10.1 Layout Guidelines
图 124 shows a board layout example for the circuit illustrated in 图 123. The key considerations for layout are:
• Use a solid ground plane underneath the device and partition the PCB into analog and digital sections.
• Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference
input signals away from noise sources.
• The power sources to the device must be clean and well-bypassed. Use CAVDD decoupling capacitors in close
proximity to the analog (AVDD) power supply pin.
• Use a CDVDD decoupling capacitor close to the digital (DVDD) power-supply pin.
• Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors.
• Connect the ground pin to the ground plane using a short, low-impedance path.
• Place the charge kickback filter components close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors are recommended because these
components provide the most stable electrical properties over voltage, frequency, and temperature changes.
10.2 Layout Example
CDVDD
CAVDD
AVDD
DVDD
10
1
GND
RFLT0
From Sensor
Output
From Sensor
Output
AVDD
2
RFLT1
AINP/AIN0
DVDD
9
SCL
8
SDA
7
ALERT
6
RSCL
RSDA
RALERT
To I2C Master or Host
Device
CFLT0
3
AINM/AIN1
4
ADDR
To I2C Master or Host
CFLT1
RADDR1
AVDD
RADDR2
BUSY/RDY
To I2C Master or Host
5
To I2C Master or Host
图 123. Example Circuit
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ADS7142
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ZHCSH75A – SEPTEMBER 2017 – REVISED DECEMBER 2017
Layout Example (接
接下页)
图 124. Example Layout
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11 器件和文档支持
11.1 文档支持
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。数据如有变更，恕不另
行通知和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7142IRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
18M
ADS7142IRUGT
ACTIVE
X2QFN
RUG
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
18M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
