ADS7230IRSAT

ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE FEATURES APPLICATIONS • 2.7V to 5.5V Analog Supply, Low Power: – 13.7mW (1MHz, +VA = 3V, +VBD = 1.8V) • 1MHz Sampling Rate 3V ≤ +VA ≤ 5.5V, 900kHz Sampling Rate 2.7V ≤ +VA ≤ 3V • Excellent DC Performance: – ±0.15LSB Typ, ±0.5LSB Max INL – ±0.12LSB Typ, ±0.5LSB Max DNL – ±0.8mV Max Offset Error at 3V – ±1.25mV Max Offset Error at 5V • Excellent AC Performance at fI = 10kHz with 73.9dB SNR, 93.4dB SFDR, –88.5dB THD • Built-In Conversion Clock (CCLK) • 1.65V to 5.5V I/O Supply: – SPI™/DSP-Compatible Serial Interface – SCLK up to 50MHz • Comprehensive Power-Down Modes: – Deep Power-Down – Nap Power-Down – Auto Nap Power-Down • Unipolar Input Range: 0V to VREF • Software Reset • Global CONVST (Independent of CS) • Programmable Status/Polarity EOC/INT • 4 × 4 QFN-16 and TSSOP-16 Packages • Multi-Chip Daisy-Chain Mode • Programmable TAG Bit Output • Auto/Manual Channel Select Mode (ADS7230) • • • • • • • 1 23 Communications Transducer Interface Medical Instruments Magnetometers Industrial Process Control Data Acquisition Systems Automatic Test Equipment DESCRIPTION The ADS7229 is a low-power, 12-bit, 1MSPS analog-to-digital converter (ADC) with a unipolar input. The device includes a 12-bit capacitor-based successive approximation register (SAR) ADC with inherent sample-and-hold. The ADS7230 is based on the same core and includes a 2-to-1 input MUX with a programmable TAG bit output option. Both the ADS7229 and ADS7230 offer a high-speed, wide voltage serial interface and are capable of daisy-chain mode operation when multiple converters are used. These devices are available in 4 × 4 QFN and TSSOP-16 packages, and are fully specified for operation over the industrial –40°C to +85°C temperature range. Low Power, High-Speed SAR Converter Family Type/Speed 16-bit single-ended 14-bit single-ended 12-bit single-ended ADS7230 ADS7229 +IN1 NC +IN0 COM +IN -IN REF+ REF OUTPUT LATCH and TRI-STATE DRIVER SAR + _ CDAC COMPARATOR OSC CONVERSION and CONTROL LOGIC 500 kSPS 1 MSPS Single ADS8327 ADS8329 Dual ADS8328 ADS8330 Single — ADS7279 Dual — ADS7280 Single — ADS7229 Dual — ADS7230 SDO FS/CS SCLK SDI CONVST EOC/INT/CDI 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) MAXIMUM INTEGRAL LINEARITY (LSB) MODEL ADS7229I MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±0.5 ±0.5 MAXIMUM OFFSET ERROR (mV) PACKAGE TYPE PACKAGE DESIGNATOR 4 × 4 QFN-16 RSA ±1.25 4 × 4 QFN-16 ±0.5 ±0.5 TRANSPORT MEDIA, QUANTITY ADS7229IRSAT Small tape and reel, 250 ADS7229IRSAR Tape and reel, 3000 ADS7229IPW Tube, 90 ADS7229IPWR Tape and reel, 2000 ADS7230IRSAT Small tape and reel, 250 ADS7230IRSAR Tape and reel, 3000 PW RSA ±1.25 –40°C to +85°C TSSOP-16 (1) ORDERING INFORMATION –40°C to +85°C TSSOP-16 ADS7230I TEMPERATURE RANGE ADS7230IPW Tube, 90 ADS7230IPWR Tape and reel, 2000 PW For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Voltage Voltage range ADS7229, ADS7230 UNIT +IN to AGND –0.3 to +VA + 0.3 V –IN to AGND –0.3 to +VA + 0.3 V +VA to AGND –0.3 to 7 V +REF to AGND –0.3 to +VA + 0.3 V –REF to AGND –0.3 to 0.3 V +VBD to BDGND –0.3 to 7 V AGND to BDGND –0.3 to 0.3 V Digital input voltage to BDGND –0.3 to +VBD + 0.3 V Digital output voltage to BDGND –0.3 to +VBD + 0.3 V TA Operating free-air temperature range –40 to +85 °C TSTG Storage temperature range –65 to +150 °C TJ max Junction temperature +150 °C (1) 2 4 × 4 QFN-16 package Power dissipation TSSOP-16 package Power dissipation (TJmax – TA)/θJA θJA thermal impedance 47 °C/W (TJmax – TA)/θJA θJA thermal impedance 86 °C/W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, +VA = 4.5V to 5.5V, +VBD = +1.65V to +5.5V, VREF = 5V, and fSAMPLE = 1MHz, unless otherwise noted. ADS7229, ADS7230 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF V ANALOG INPUT Full-scale input voltage (1) FSR Absolute input voltage +IN – (–IN) or (+INx – COM) 0 +IN, +IN0, +IN1 AGND – 0.2 +VA + 0.2 –IN or COM AGND – 0.2 AGND + 0.2 Input capacitance Input leakage current Input channel isolation, ADS7230 only 45 No ongoing conversion, dc input 50 At dc 109 VI = ±1.25VPP at 50kHz 101 V pF nA dB SYSTEM PERFORMANCE Resolution 12 Bits NMC No missing codes INL Integral linearity –0.5 ±0.15 0.5 LSB (2) DNL Differential linearity –0.5 ±0.12 0.5 LSB (2) –1.25 ±0.3 1.25 EO Offset error (3) Offset error drift EG 12 FSR = 5V Gain error ±0.2 –0.1 Gain error drift CMRR Common-mode rejection ratio Power-supply rejection ratio ±0.002 At dc 70 VI = 0.4VPP at 1MHz 50 At FFFFh output code (3) mV ppm/°C 0.1 ±0.5 Noise PSRR Bits %FSR ppm/°C dB 33 µVRMS 78 dB 18 CCLK SAMPLING DYNAMICS tCONV tSAMPLE1 tSAMPLE2 Conversion time Acquisition time Manual trigger Auto trigger 3 Throughput rate (1) (2) (3) CCLK 3 1 MHz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns Ideal input span; does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input [(+IN) – (–IN)] of 4.096V when +VA = 5V. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 3 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, +VA = 4.5V to 5.5V, +VBD = +1.65V to +5.5V, VREF = 5V, and fSAMPLE = 1MHz, unless otherwise noted. ADS7229, ADS7230 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS THD Total harmonic distortion (4) SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range VIN = 5VPP at 10kHz –88.5 VIN = 5VPP at 100kHz –85.5 VIN = 5VPP at 10kHz dB 73.9 VIN = 5VPP at 100kHz 72 VIN = 5VPP at 10kHz 73.7 VIN = 5VPP at 100kHz 73.3 VIN = 5VPP at 10kHz 93.4 VIN = 5VPP at 100kHz 90.5 –3dB small-signal bandwidth dB 73.8 dB dB 30 MHz CLOCK Internal conversion clock frequency SCLK external serial clock 21 23 Used as I/O clock only 24.5 50 As I/O clock and conversion clock 1 42 0.3 +VA –0.1 0.1 MHz MHz EXTERNAL VOLTAGE REFERENCE INPUT VREF Input reference range VREF [(REF+) – (REF–)] (REF–) – AGND Resistance (5) Reference input 40 V kΩ DIGITAL INPUT/OUTPUT Logic family—CMOS VIH High-level input voltage 5.5V ≥ +VBD ≥ 4.5V 0.65 × (+VBD) +VBD + 0.3 V V nA VIL Low-level input voltage 5.5V ≥ +VBD ≥ 4.5V –0.3 0.35 × (+VBD) II Input current VI = +VBD or BDGND –50 50 CI Input capacitance 5 VOH High-level output voltage 5.5V ≥ +VBD ≥ 4.5V, IO = 100µA VOL Low-level output voltage 5.5V ≥ +VBD ≥ 4.5V, IO = 100µA CO Output capacitance CL Load capacitance pF +VBD – 0.6 +VBD V 0 0.4 V 5 pF 30 pF Data format—straight binary POWER-SUPPLY REQUIREMENTS Power-supply voltage +VBD 1.65 3.3 5.5 V 4.5 5 5.5 V 1MHz sample rate 5.7 7.0 Nap or Auto Nap mode 0.3 0.5 +VA Supply current Deep power-down mode Buffer I/O supply current Power dissipation 4 1 1MSPS, BVDD = 1.8V 0.1 0.5 1MSPS, BVDD = 3V 0.5 1.2 AVDD = 5V, BVDD = 1.8V 28.8 36.5 AVDD = 5V, BVDD = 3V 30.0 38.6 mA µA mA mW TEMPERATURE RANGE TA (4) (5) 4 Operating free-air temperature –40 +85 °C Calculated on the first nine harmonics of the input frequency. Can vary ±30%. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, +VA = 2.7V to 3.6V, +VBD = 1.65V to 1.5 × (+VA), VREF = 2.5V, fSAMPLE = 1MHz for 3V ≤ +VA ≤ 3.6V, and fSAMPLE = 900kHz for 3V < +VA ≤ 2.7V using external clock, unless otherwise noted. ADS7229, ADS7230 PARAMETER TEST CONDITIONS MIN Full-scale input voltage (1) +IN – (–IN) or (+INx – COM) 0 TYP MAX UNIT VREF V ANALOG INPUT FSR Absolute input voltage +IN, +IN0, +IN1 AGND – 0.2 +VA + 0.2 –IN or COM AGND – 0.2 AGND + 0.2 Input capacitance 45 No ongoing conversion, dc Input Input leakage current Input channel isolation, ADS7230 only 50 At dc 108 VI = ±1.25VPP at 50kHz 101 V pF nA dB SYSTEM PERFORMANCE Resolution 12 No missing codes Bits 12 Bits INL Integral linearity –0.5 ±0.15 0.5 LSB (2) DNL Differential linearity –0.5 ±0.12 0.5 LSB (2) –0.8 ±0.07 0.8 EO Offset error (3) Offset error drift EG FSR = 2.5V Gain error ±0.1 –0.1 Gain error drift CMRR 0.1 ±0.3 Common-mode rejection ratio At dc 70 VI = 0.4VPP at 1MHz 50 Noise PSRR ±0.008 At FFFFh output code (3) Power-supply rejection ratio mV ppm/°C %FSR ppm/°C dB 33 µVRMS 78 dB 18 CCLK SAMPLING DYNAMICS tCONV tSAMPLE1 tSAMPLE2 Conversion time Manual trigger Acquisition time Auto trigger CCLK 3 2.7V ≤ +VA < 3.0V Throughput rate (1) (2) (3) 3 0.9 3.0V ≤ +VA ≤ 3.64V 1 MHz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns Ideal input span; does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input [(+IN) – (–IN)] of 2.5V when +VA = 3V. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 5 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, +VA = 2.7V to 3.6V, +VBD = 1.65V to 1.5 × (+VA), VREF = 2.5V, fSAMPLE = 1MHz for 3V ≤ +VA ≤ 3.6V, and fSAMPLE = 900kHz for 3V < +VA ≤ 2.7V using external clock, unless otherwise noted. ADS7229, ADS7230 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS THD Total harmonic distortion (4) SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range VIN = 2.5VPP at 10kHz –96.8 VIN = 2.5VPP at 100kHz –88.4 VIN = 2.5VPP at 10kHz 72 VIN = 2.5VPP at 100kHz dB 73.2 dB 72 VIN = 2.5VPP at 10kHz 73.1 VIN = 2.5VPP at 100kHz 72.1 VIN = 2.5VPP at 10kHz 95.9 VIN = 2.5VPP at 100kHz 91.5 –3dB small-signal bandwidth dB dB 30 MHz CLOCK Internal conversion clock frequency 21 23 Used as I/O clock only SCLK external serial clock 23.5 42 As I/O clock and conversion clock 1 42 fSAMPLE ≤ 500kSPS, 2.7V ≤ +VA < 3V 0.3 2.525 fSAMPLE ≤ 500kSPS, 3V ≤ +VA < 3.6V 0.3 3 fSAMPLE > 500kSPS, 2.7V ≤ +VA < 3V 2.475 2.525 fSAMPLE > 500kSPS, 3V ≤ +VA ≤ 3.6V 2.475 3 MHz MHz EXTERNAL VOLTAGE REFERENCE INPUT VREF Input reference range VREF [(REF+) – (REF–)] (REF–) – AGND Resistance (5) –0.1 Reference input V 0.1 40 kΩ DIGITAL INPUT/OUTPUT Logic family—CMOS VIH High-level input voltage (+VA × 1.5)V ≥ +VBD ≥ 1.65V 0.65 × (+VBD) +VBD + 0.3 VIL Low-level input voltage (+VA × 1.5)V ≥ +VBD ≥ 1.65V –0.3 0.35 × (+VBD) V II Input current VI = +VBD or BDGND –50 50 nA CI Input capacitance 5 VOH High-level output voltage (+VA × 1.5)V ≥ +VBD ≥ 1.65V, IO = 100µA VOL Low-level output voltage (+VA × 1.5)V ≥ +VBD ≥ 1.65V, IO = 100µA CO Output capacitance CL Load capacitance V pF +VBD – 0.6 +VBD V 0 0.4 V 5 pF 30 pF Data format—straight binary (4) (5) 6 Calculated on the first nine harmonics of the input frequency. Can vary ±30%. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, +VA = 2.7V to 3.6V, +VBD = 1.65V to 1.5 × (+VA), VREF = 2.5V, fSAMPLE = 1MHz for 3V ≤ +VA ≤ 3.6V, and fSAMPLE = 900kHz for 3V < +VA ≤ 2.7V using external clock, unless otherwise noted. ADS7229, ADS7230 PARAMETER TEST CONDITIONS MIN TYP MAX 1.65 +VA 1.5 × (+VA) UNIT POWER-SUPPLY REQUIREMENTS +VBD Power-supply voltage fs ≤ 1MHz +VA fs ≤ 900kHz Supply current 3 3.6 2.7 3.6 1MHz sample rate, 3V ≤ +VA ≤ 3.6V 4.5 900kHz sample rate, 2.7V ≤ +VA ≤ 3V 4.2 Nap or Auto Nap mode 0.25 Deep power-down mode Buffer I/O supply current Power dissipation V V 6.0 mA 0.4 0.001 1 1MSPS, BVDD = 1.8V 0.1 0.5 1MSPS, BVDD = 3V 0.5 1.2 AVDD = 3V, BVDD = 1.8V 13.7 18.9 AVDD = 3V, BVDD = 3V 15.0 21.6 µA mA mW TEMPERATURE RANGE TA Operating free-air temperature –40 Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 +85 Submit Documentation Feedback °C 7 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS (1) (2): 5V All specifications typical at –40°C to +85°C and +VA = +VBD = 5V, unless otherwise noted. ADS7229, ADS7230 PARAMETER fCCLK Frequency, conversion clock, CCLK MIN External, fCCLK = 1/2 fSCLK 0.5 Internal, fCCLK = 1/2 fSCLK 21 TYP MAX UNIT 21 MHz 23 24.5 t1 Setup time, falling edge of CS to EOC 1 CCLK t2 Hold time, falling edge of CS to EOC 0 ns tCL Pulse duration, CONVST low 40 ns t3 Hold time, falling edge of CS to EOS 20 ns t4 Setup time, rising edge of CS to EOS 20 ns t5 Hold time, rising edge of CS to EOS 20 ns t6 Setup time, falling edge of CS to first falling SCLK 5 ns tSCLKL Pulse duration, SCLK low 8 tSCLK – 8 ns tSCLKH Pulse duration, SCLK high 8 tSCLK – 8 ns I/O clock only 20 I/O and conversion clock tSCLK Cycle time, SCLK 23.8 I/O clock, chain mode 2000 ns 20 I/O and conversion clock, chain mode 23.8 2000 tH2 Hold time, falling edge of SCLK to SDO invalid 10pF load tD1 Delay time, falling edge of SCLK to SDO valid 10pF load 10 ns tD2 Delay time, falling edge of CS to SDO valid, SDO MSB output 10pF load 8.5 ns tS1 Setup time, SDI to falling edge of SCLK 8 ns tH1 Hold time, SDI to falling edge of SCLK 4 ns tD3 Delay time, rising edge of CS/FS to SDO tD3 3-state t7 Setup time, 16th falling edge of SCLK before rising edge of CS/FS (1) (2) 8 2 ns 5 10 ns ns All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 TIMING CHARACTERISTICS (1) (2): 1.8V All specifications typical at –40°C to 85°C, +VA = 2.7 V, and +VBD = 1.8V, unless otherwise noted. ADS7229, ADS7230 PARAMETER fCCLK Frequency, conversion clock, CCLK MIN TYP MAX External, 3V ≤ +VA ≤ 3.6V, fCCLK = 1/2 fSCLK 0.5 21 External, 2.7V ≤ +VA ≤ 3V, fCCLK = 1/2 fSCLK 0.5 18.9 Internal, fCCLK = 1/2 fSCLK 20 22.3 UNIT MHz 23.5 t1 Setup time, falling edge of CS to EOC 1 CCLK t2 Hold time, falling edge of CS to EOC 0 ns tCL Pulse duration, CONVST low 40 ns t3 Hold time, falling edge of CS to EOS 20 ns t4 Setup time, rising edge of CS to EOS 20 ns t5 Hold time, rising edge of CS to EOS 20 ns t6 Setup time, falling edge of CS to first t6 falling SCLK 5 ns tSCLKL Pulse duration, SCLK low 8 tSCLK – 8 ns tSCLKH Pulse duration, SCLK high ns tSCLK Cycle time, SCLK 8 tSCLK – 8 All modes, 3V ≤ +VA ≤ 3.6V 23.8 2000 All modes, 2.7V ≤ +VA < 3V 26.5 2000 tH2 Hold time, falling edge of SCLK to SDO invalid 10pF load tD1 Delay time, falling edge of SCLK to SDO valid tD2 Delay time, falling edge of CS to SDO valid, SDO MSB output ns 7.5 ns 10pF load 16 10pF load, 2.7V ≤ +VA ≤ 3V 13 10pF load, 3V ≤ +VA ≤ 3.6V 11 ns ns tS1 Setup time, SDI to falling edge of SCLK 8 ns tH1 Hold time, SDI to falling edge of SCLK 4 ns tD3 Delay time, rising edge of CS/FS to SDO 3-state t7 Setup time, 16th falling edge of SCLK t7 before rising edge of CS/FS (1) (2) 8 10 ns ns All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 9 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com PIN ASSIGNMENTS AGND COM +IN0 15 14 13 2 11 +VA CONVST 3 10 +VBD EOC/INT/CDI 4 9 SCLK 8 SCLK NC BDGND 9 +IN1 7 4 12 SDO EOC/INT/CDI 1 6 +VBD REF+ (REFIN) SDI 10 REF- +IN 13 3 BDGND CONVST 8 +VA 16 -IN 14 11 7 2 SDO NC 6 RESERVED SDI 12 5 1 FS/CS REF+ (REFIN) 5 AGND 15 ADS7230 RSA PACKAGE (QFN) (TOP VIEW) FS/CS REF16 ADS7229 RSA PACKAGE (QFN) (TOP VIEW) CAUTION: The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. ADS7229 PW PACKAGE (TSSOP) (TOP VIEW) +VA RESERVED +IN -IN AGND REFREF+ (REFIN) NC 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 ADS7230 PW PACKAGE (TSSOP) (TOP VIEW) +VBD SCLK BDGND SDO SDI FS/CS EOC/INT/CDI CONVST +VA +IN1 +IN0 COM AGND REFREF+ (REFIN) NC 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 +VBD SCLK BDGND SDO SDI FS/CS EOC/INT/CDI CONVST NC = No internal connection 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 ADS7229 Terminal Functions NO. QFN TSSOP I/O AGND NAME 15 5 — Analog ground DESCRIPTION BDGND 8 14 — Interface ground CONVST 3 9 I Freezes sample-and-hold, starts conversion with next rising edge of internal clock Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and valid data are to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in daisy-chain mode. EOC/INT/CDI 4 10 I/O FS/CS 5 11 I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface slave select (SS–). +IN 13 3 I Noninverting input –IN 14 4 I Inverting input; usually connected to ground NC 2 8 — REF+ (REFIN) 1 7 I External reference input REF– 16 6 I Connect to AGND through individual via RESERVED 12 2 I Connect to AGND or +VA SCLK 9 15 I Clock for serial interface SDI 6 12 I Serial data in SDO 7 13 O Serial data out +VA 11 1 Analog supply, +2.7V to +5.5VDC +VBD 10 16 Interface supply No connection ADS7230 Terminal Functions NO. NAME QFN TSSOP I/O 15 5 — Analog ground BDGND 8 14 — Interface ground COM 14 4 I Common inverting input; usually connected to ground CONVST 3 9 I Freezes sample-and-hold, starts conversion with next rising edge of internal clock AGND DESCRIPTION Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and valid data are to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in daisy-chain mode. EOC/INT/CDI 4 10 I/O FS/CS 5 11 I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface +IN1 12 2 I Second noninverting input +IN0 13 3 I First noninverting input NC 2 8 — REF+ (REFIN) 1 7 I External reference input REF– 16 6 I Connect to AGND through individual via SCLK 9 15 I Clock for serial interface SDI 6 12 I Serial data in (conversion start and reset possible) SDO 7 13 O Serial data out +VA 11 1 Analog supply, +2.7V to +5.5VDC +VBD 10 16 Interface supply No connection. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 11 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com MANUAL TRIGGER/READ While Sampling (use internal CCLK, EOC, and INT polarity programmed as active low) Nth CONVST EOC EOS EOC EOC (active low) tCL Nth Nth - 1 tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs Min INT (active low) t4 t2 FS/CS 1……………………16 1 SCLK Nth - 1 SDO Nth 1101b READ Result SDI 1101b READ Result Figure 1. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read While Sampling) MANUAL TRIGGER/READ While Converting (use internal CCLK, EOC, and INT polarity programmed as active low) Nth tCL EOC (active low) EOS N + 1st EOC EOS CONVST Nth + 1 Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs Min INT (active low) t4 t3 FS/CS 1……………………16 1 SCLK SDO SDI Nth - 1 Nth 1101b READ Result 1101b READ Result Figure 2. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read While Converting) 12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 AUTO TRIGGER/READ While Converting (use internal CCLK, EOC, and INT polarity programmed as active low) EOC (active low) EOS EOC EOS EOC EOS CONVST = 1 N - 1th Nth tSAMPLE2 = 3 CCLKs tCONV = 18 CCLKs INT (active low) Nth + 1 tSAMPLE2 = 3 CCLKs tCONV = 18 CCLKs t4 t3 FS/CS 1……………………16 1……………………16 SCLK N - 2nd SDO N - 1st 1101b READ Result SDI 1101b READ Result Figure 3. Timing for Conversion and Acquisition Cycles for Autotrigger (Read While Converting) 1 2 3 4 11 12 14 13 15 16 SCLK tSCLKH tSCLKL tSCLK t6 t7 FS/CS tH2 tD2 SDO MSB MSB-1 MSB-2 tD3 MSB-3 LSB+1 LSB tD1 tH1 SDI or CDI MSB MSB-1 MSB-2 MSB-3 LSB+5 LSB+4 LSB+3 LSB+2 LSB+1 LSB tS1 Figure 4. Detailed SPI Transfer Timing Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 13 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com MANUAL TRIGGER/READ While Converting (use internal CCLK, EOC, and INT polarity programmed as active low, TAG enabled, auto channel select) Nth CH0 EOC (active low) Nth CH1 Nth CH0 tSAMPLE1 = 3 CCLKs Min EOC tCL EOS tCL Nth CH1 EOC EOS EOC CONVST tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs Min tCONV = 18 CCLKs INT (active low) t4 t3 FS/CS 1……………………16 17 1……………………16 17 SCLK SDO High-Z High-Z N - 1st CH1 TAG = 1 1101b READ Result SDI High-Z Nth CH0 TAG = 0 1101b READ Result Figure 5. Simplified Dual Channel Timing 14 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 110 0.30 105 0.25 100 0.20 DNL (LSB) Crosstalk (dB) CROSSTALK vs FREQUENCY 95 5V 3V 0.15 90 0.10 85 0.05 5V 3V 80 0 20 40 60 80 0 -40 100 120 140 160 180 200 10 -15 35 60 Frequency (kHz) Temperature (°C) Figure 6. Figure 7. INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY 0.30 0.50 85 +VA = 5V 0.25 0.25 3V DNL (LSB) INL (LSB) 0.20 0.15 0.10 DNL+ 0 DNL- 5V -0.25 0.05 0 -40 -0.50 10 -15 35 60 85 0.1 1 Temperature (°C) 0.50 Figure 8. Figure 9. INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY 0.50 +VA = 5V 0.25 100 +VA = 3V 0.25 INL+ DNL (LSB) INL (LSB) 10 fSCLK (MHz) 0 INL-0.25 DNL+ 0 DNL-0.25 -0.50 -0.50 0.1 1 10 100 0.1 1 10 fSCLK (MHz) fSCLK (MHz) Figure 10. Figure 11. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 100 15 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 0.50 0.50 +VA = 3V 5V Offset Voltage (mV) INL (LSB) 0.25 0.25 INL+ 0 INL- 3V 0 -0.25 -0.25 -0.50 -40 -0.50 0.1 1 10 100 10 -15 35 60 85 Temperature (°C) fSCLK (MHz) Figure 12. Figure 13. OFFSET VOLTAGE vs SUPPLY VOLTAGE GAIN ERROR vs FREE-AIR TEMPERATURE 0.050 0.5 0.025 Gain Error (%FSR) Offset Voltage (mV) 0.4 0.3 0.2 0.1 3V 0 5V -0.025 0 -0.1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.050 -40 10 -15 35 85 60 Temperature (°C) +VA Supply Voltage (V) Figure 14. Figure 15. GAIN ERROR vs SUPPLY VOLTAGE POWER-SUPPLY REJECTION RATIO vs SUPPLY RIPPLE FREQUENCY 0.10 -70 -72 0.05 PSRR (dB) Gain Error (%FSR) 5V 0 3V -74 -76 -0.05 -78 -0.10 -80 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 10 20 +VA Supply Voltage (V) Submit Documentation Feedback 40 50 60 70 80 90 100 Frequency (kHz) Figure 16. 16 30 Figure 17. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY 80 80 78 78 SINAD (dB) SNR (dB) SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 76 5V 74 72 76 5V 74 72 3V 70 3V 70 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 Input Frequency (kHz) Input Frequency (kHz) Figure 18. Figure 19. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY 90 100 90 100 100 -80 3V 95 5V SFDR (dB) SINAD (dB) -85 -90 90 5V 85 -95 3V 80 -100 0 76 10 20 fIN = 10kHz 30 40 50 60 70 80 90 0 100 20 30 40 50 60 70 80 Input Frequency (kHz) Figure 20. Figure 21. SIGNAL-TO-NOISE RATIO vs FULL-SCALE RANGE SIGNAL-TO-NOISE AND DISTORTION vs FULL-SCALE RANGE 76 fIN = 10kHz 5V 5V 74 SINAD (dB) 74 SNR (dB) 10 Input Frequency (kHz) 72 3V 70 68 72 3V 70 68 66 66 0 1 2 3 4 5 0 1 2 3 Full-Scale Range (V) Full-Scale Range (V) Figure 22. Figure 23. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 4 Submit Documentation Feedback 5 17 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. TOTAL HARMONIC DISTORTION vs FULL-SCALE RANGE -75 SPURIOUS-FREE DYNAMIC RANGE vs FULL-SCALE RANGE 100 fIN = 10kHz fIN = 10kHz -80 95 SFDR (dB) THD (dB) 3V -85 5V -90 5V 90 3V 85 -95 80 -100 0 1 2 3 4 5 0 1 Full-Scale Range (V) 2 3 4 5 Full-Scale Range (V) Figure 24. Figure 25. TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE SPURIOUS-FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 100 -80 3V 95 5V SFDR (dB) THD (dB) -85 -90 -95 -100 -40 10 5V 85 3V -15 90 35 60 80 -40 85 -15 10 35 60 Temperature (°C) Temperature (°C) Figure 26. Figure 27. SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 75 85 75 74 SINAD (dB) SNR (dB) 5V 3V 73 74 5V 73 3V 72 -40 18 -15 10 35 60 85 72 -40 -15 10 35 Temperature (°C) Temperature (°C) Figure 28. Figure 29. Submit Documentation Feedback 60 85 Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE INTERNAL CLOCK FREQUENCY vs SUPPLY VOLTAGE 12.50 Internal Clock Frequency (MHz) 24.0 ENOB (Bits) 12.25 5V 12.00 11.75 3V 11.50 -40 23.5 23.0 22.5 22.0 21.5 21.0 10 -15 35 60 2.5 85 3.0 4.5 Figure 31. INTERNAL CLOCK FREQUENCY vs FREE-AIR TEMPERATURE ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 7.0 23.5 6.5 5.0 5.5 fS = 1MSPS Analog Supply Current (mA) Internal Clock Frequency (MHz) 4.0 Figure 30. 24.0 23.0 22.5 22.0 21.5 22.0 -40 6.0 5.5 5.0 4.5 4.0 10 -15 35 60 85 2.5 3.0 3.5 4.0 4.5 Temperature (°C) +VA Supply Voltage (V) Figure 32. Figure 33. ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 400 5.0 5.5 5.0 5.5 10 PD Mode Analog Supply Current (nA) NAP Mode Analog Supply Current (mA) 3.5 +VA Supply Voltage (V) Temperature (°C) 360 320 280 240 200 8 6 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 +VA Supply Voltage (V) +VA Supply Voltage (V) Figure 34. Figure 35. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 19 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. ANALOG SUPPLY CURRENT vs SAMPLE RATE ANALOG SUPPLY CURRENT vs SAMPLE RATE 1.4 7 PD Mode 6 Analog Supply Current (mA) Analog Supply Current (mA) Auto NAP 5 4 3 5V 2 3V 1 1.2 1.0 5V 0.8 0.6 3V 0.4 0.2 0 0 1 10 0 1000 100 20 10 50 60 70 Figure 37. ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.35 5V 6.0 5.5 5.0 4.5 3V 4.0 80 90 NAP Mode fS = 1MSPS Analog Supply Current (mA) Analog Supply Current (mA) 40 Figure 36. 7.0 6.5 30 Sample Rate (kSPS) Sample Rate (kSPS) 5V 0.30 0.25 3V 0.20 3.5 3.0 -40 -15 10 35 60 0.15 -40 85 Figure 39. 85 +VA = 5V 0.20 0.15 0.15 0.10 0.10 DNL (Bits) INL (Bits) 60 DIFFERENTIAL NONLINEARITY 0.25 0.05 0 -0.05 0.05 0 -0.05 -0.10 -0.10 -0.15 -0.15 -0.20 -0.20 -0.25 -0.25 0 20 35 Figure 38. +VA = 5V 0.20 10 Temperature (°C) INTEGRAL NONLINEARITY 0.25 -15 Temperature (°C) 1000 2000 3000 4000 0 1000 2000 Code Code Figure 40. Figure 41. Submit Documentation Feedback 3000 4000 Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY 0.25 +VA = 3V 0.20 0.20 0.15 0.15 0.10 0.10 DNL (Bits) INL (Bits) 0.25 0.05 0 -0.05 +VA = 3V 0.05 0 -0.05 -0.10 -0.10 -0.15 -0.15 -0.20 -0.20 -0.25 -0.25 0 1000 2000 3000 4000 0 1000 2000 Code Figure 42. Figure 43. FFT -20 -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 -140 100 200 300 400 10kHz Input +VA = 3V fS = 1MSPS VREF = 2.5V -20 Amplitude (dB) -40 Amplitude (dB) 0 5kHz Input +VA = 3V fS = 1MSPS VREF = 2.5V 0 -160 500 0 100 200 Frequency (kHz) Figure 44. Figure 45. FFT 400 500 FFT 0 100kHz Input +VA = 3V fS = 1MSPS VREF = 2.5V -40 -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 0 100 200 300 400 5kHz Input +VA = 5V fS = 1MSPS VREF = 5V -20 Amplitude (dB) -20 Amplitude (dB) 300 Frequency (kHz) 0 -160 4000 FFT 0 -160 3000 Code 500 -160 0 100 200 300 Frequency (kHz) Frequency (kHz) Figure 46. Figure 47. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 400 Submit Documentation Feedback 500 21 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, VREF [(REF+) – (REF–)] = 5V when +VA = +VBD = 5V or VREF [(REF+) – (REF–)] = 2.5V when +VA = +VBD = 3V, fSCLK = 42MHz, or VREF = 2.5 when +VA = +VBD = 2.7V, fSCLK = 37.8MHz, and fI = dc for dc curves, fI = 100kHz for ac curves with 5V supply, and fI = 10kHz for ac curves with 3V supply, unless otherwise noted. FFT FFT 0 10kHz Input +VA = 5V fS = 1MSPS VREF = 5V -40 -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 0 100 200 300 400 100kHz Input +VA = 5V fS = 1MSPS VREF = 5V -20 Amplitude (dB) -20 Amplitude (dB) 0 -160 500 0 200 100 300 Frequency (kHz) Frequency (kHz) Figure 48. Figure 49. I/O SUPPLY CURRENT vs I/O SUPPLY VOLTAGE 400 500 CODE HISTOGRAM 9000 3.0 REF = 2.5V 8000 2.5 7000 Hits per Code IBVDD (mA) 2.0 1.5 1.0 6000 5000 4000 3000 2000 0.5 1000 0 0 4 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 3 5 6 7 Output Code BVDD (V) Figure 50. Figure 51. CODE HISTOGRAM 9000 REF = 5V 8000 Hits per Code 7000 6000 5000 4000 3000 2000 1000 0 2330 2331 2332 2333 2334 Output Code Figure 52. 22 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 THEORY OF OPERATION The ADS7229 and ADS7230 are two high-speed, low power, successive approximation register (SAR) analog-to-digital converters (ADCs) that use an external reference. The architecture is based on charge redistribution, which inherently includes a sample-and-hold function. These devices have an internal clock that is used to run the conversion; these devices can also be programmed to run the conversion based on the external serial clock, SCLK. The ADS7229 has one analog input. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and –IN inputs are disconnected from any internal function. The ADS7230 has two inputs. Both inputs share the same common pin, COM. The negative input is the same as the –IN pin for the ADS7229. The ADS7230 can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep between channel 0 and channel 1 automatically. Throughout this document, the term ADS7229/30 refers to both devices, unless specifically noted otherwise. ANALOG INPUT When the converter enters before hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between AGND – 0.2V and AGND + 0.2V, allowing the input to reject small signals that are common to both the +IN and –IN inputs. The +IN input has a range of –0.2V to (VREF + 0.2V). The input span [(+IN) – (–IN)] is limited to 0V to VREF. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS7229/30 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45pF) to a 12-bit settling level within the minimum acquisition time (120ns). When the converter goes into hold mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and –IN inputs and the span [(+IN) – (–IN)] should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this input matching is not observed, the two inputs could have different settling times. This difference may result in an offset error, gain error, and linearity errors that change with temperature and input voltage. Device in Hold Mode 150W 40pF +IN 4pF +VA AGND 4pF 150W 40pF AGND -IN Figure 53. Input Equivalent Circuit Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 23 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com Driver Amplifier Choice The analog input to the converter must be driven with a low-noise operational amplifier such as the THS4031 or OPA365. An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two 20Ω resistors and a 470pF capacitor are recommended. The input to the converter is a unipolar input voltage in the range of 0V to VREF. The minimum –3dB bandwidth of the driving operational amplifier can be calculated as: f3db = (ln(2) ×(n + 1))/(2π × tACQ) where n is equal to 12, the resolution of the ADC (in the case of the ADS7229/30). When tACQ = 120ns (minimum acquisition time), the minimum bandwidth of the driving amplifier is 12MHz. The bandwidth can be relaxed if the acquisition time is increased by the application. The OPA365 or THS4031 from Texas Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is shown in a typical input drive configuration, Figure 54. For the ADS7230, a series resistor of 0Ω should be used on the COM input (or no resistor at all). Bipolar to Unipolar Driver In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional dc bias applied to its positive input to keep the input to the ADS7229/30 within the rated operating voltage range. This configuration is also recommended when the ADS7229/30 is used in signal processing applications where good SNR and THD performance are required. The dc bias can be derived from the REF5025 or the REF5040 reference voltage ICs. The input configuration shown in Figure 55 is capable of delivering better than 72dB SNR and –88.5dB THD at an input frequency of 10kHz. If bandpass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small in order to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 55 can be increased to keep the input to the ADS7229/30 large in order to maintain a high SNR of the system. Note that the gain of the system from the positive input to the output of the THS4031 in such a configuration is a function of the ac signal gain. A resistor divider can be used to scale the output of the REF5025 or REF5040 to reduce the voltage at the dc input to the THS4031 to maintain the voltage at the converter input within its rated operating range. Input Signal (0V to 4V) 5V ADS7229 +VA THS4031 20W +IN 470pF 50W -IN 20W Figure 54. Unipolar Input Drive Configuration 5V ADS7229 1V DC +VA THS4031 20W +IN 470pF Input Signal (-2V to 2V) -IN 20W Figure 55. Bipolar Input Drive Configuration 24 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 REFERENCE The ADS7229/30 must operate with an external reference with a range from 0.3V to 5V. A clean, low-noise, well-decoupled reference voltage on this pin is required to ensure good converter performance. A low-noise bandgap reference such as the REF5040 can be used to drive this pin. A 22µF ceramic decoupling capacitor is required between the REF+ and REF– pins of the converter. These capacitors should be placed as close as possible to the device pins. REF– should be connected to its own via to the analog ground plane with the shortest possible distance. A series resistor between the reference and the REF50xx is neither required (because the REF50xx is capable of driving a 22µF capacitor while maintaining stability) nor recommended (due to additional nonlinearity); see also Figure 68. CONVERTER OPERATION The ADS7229/30 has an oscillator that is used as an internal clock that controls the conversion rate. The frequency of this clock is 21MHz minimum. The oscillator is always on unless the device is in the deep power-down state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time takes 3 CCLKs (equivalent to 143ns at 21MHz) and the conversion time takes 18 conversion clocks (CCLK) or approximately 857ns at 21MHz to complete one conversion. The conversion can also be programmed to run based on the external serial clock, SCLK. This option allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its frequency before it is used as the conversion clock (CCLK). For example, with a 42MHz SCLK, this reduction provides a 21MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of SCLK when the external SCLK is programmed as the source of the conversion clock (and manual conversion start is selected), the setup time between CONVST and that rising SCLK edge should be observed. This configuration ensures that the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20ns to ensure synchronization between CONVST and SCLK. In many cases, the conversion can start one SCLK period (or CCLK) later, which results in a conversion of 19 CCLKs (or 37 SCLKs). The 20ns setup time is not required if the synchronization is not critical in the application. The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8ns. The ADS7229/30 is designed for high-speed applications; therefore, a higher serial clock (SCLK) must be supplied to be able to sustain the high throughput with the serial interface. As a result, the clock period of SCLK must be at most 1µs (when used as the conversion clock, CCLK). The minimum clock frequency is also governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS7229/30. CFR_D10 Conversion Clock (CCLK) =1 OSC =0 Divider 1/2 SPI Serial Clock (SCLK) Figure 56. Converter Clock Manual Channel Select Mode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register, CMR. The command length can be as short as four SCLKs. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 25 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com Auto Channel Select Mode Channel selection can also be done automatically if auto channel select mode is enabled. This mode is the default channel select mode. The dual channel converter, ADS7230, has an onboard 2-to-1 MUX. If the device is programmed for auto channel select mode, then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to '1' for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to '0'. Start of a Conversion The end of sampling instance (EOS) or acquisition is the same as the start of a conversion. This event is initiated by bringing the CONVST pin low for a minimum of 40ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that require a simultaneous sample/hold with multiple converters. The ADS7229/30 switches from sample to hold mode on the falling edge of the CONVST signal. The ADS7229/30 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 857ns with a 21MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as an auto trigger, the next conversion automatically starts three conversion clocks (CCLK) after the end of a conversion. These three conversion clocks are used as the acquisition time. In this case, the time to complete one acquisition and conversion cycle is 21 CCLKs. Table 1 summarizes the different conversion modes. Table 1. Different Types of Conversion MODE SELECT CHANNEL START CONVERSION (1) Auto Channel Select Automatic No need to write channel number to the CMR. Use internal sequencer for the ADS7230. Manual (1) Auto Trigger Start a conversion based on the conversion clock CCLK. Manual Channel Select Manual Trigger Write the channel number to the CMR. Start a conversion with CONVST. Auto channel select should be used with the TAG bit enabled. Status Output EOC/INT When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes low immediately after CONVST goes low when the manual trigger is programmed. EOC stays low throughout the conversion process and returns high when the conversion ends. The EOC output goes low for three conversion clocks after the previous rising edge of EOC, if auto trigger is programmed. This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can also be used as INT (CFR_D[7:6] = 1, 0), which is set low as the end of a conversion is brought high (cleared) by the next read cycle. The polarity of this pin, used as either function (EOC or INT), is programmable through CFR_D7. 26 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 Power-Down Modes The ADS7229/30 has a comprehensive, built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and Auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, resumes device operation from a power-down mode. Auto nap power-down mode works slightly differently. When the converter is enabled in Auto nap power-down mode, an end of conversion instance (EOC) puts the device into auto nap power-down. The beginning of sampling resumes converter operation. The contents of the configuration register are not affected by any of the power-down modes. Any ongoing conversion when nap or deep power-down is activated is aborted. +VA Supply Current (mA) 100 10 1 0.1 0 10000 20000 30000 40000 Settling Time (ns) Figure 57. Typical Analog Supply Current Drop versus Time After Power-Down Deep Power-Down Mode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in Deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, supply current falls from 5.7mA to 4nA in 100ns. The wake-up time after a deep power-down is 1µs. When bit D2 in the configuration register is set to '0', the device is in Deep power-down. Setting this bit to '1' or sending a wake-up command resumes the converter operation from the Deep power-down state. Nap Mode In Nap mode, the ADS7229/30 turns off biasing of the comparator and the mid-voltage buffer. In this mode, supply current falls from 5.7mA in normal mode to about 0.3mA in 200ns after the configuration cycle. The wake-up (resume) time from Nap power-down mode is 3 CCLKs (143ns with a 21MHz conversion clock). As soon as the CFR_D3 bit in the control register is set to '0', the device goes into Nap power-down mode, regardless of the conversion state. Setting this bit to '1' or sending a wake-up command resumes converter operation from the Nap power-down state. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 27 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com Auto Nap Mode Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually powered down and the method used to wake up the device. Configuration register bit D4 is only used to enable/disable Auto nap mode. If Auto nap mode is enabled, the device turns off the biasing after the conversion has finished; that is, the end of conversion activates Auto nap power-down mode. Supply current falls from 5.7mA in normal mode to about 0.3mA in 200ns. A CONVST command resumes the device and turns on the biasing on again in 3 CCLKs (143ns with a 21MHz conversion clock). The device can also be woken up by disabling auto nap mode when bit D4 of the configuration register is set to '1'. Any channel select command 0XXXb, a wake-up command, or the set default mode command 1111b can also wake up the device from Auto nap power-down. Table 2 compares the various power-down modes. NOTE: 1. This wake-up command is the word 1011b in the command word. This command sets bits D2 and D3 to '1' in the configuration register, but not D4. A wake-up command removes the device from any of these power-down states, Deep/Nap/Auto nap power-down. 2. Wake-up time is defined as the time between when the host processor tries to wake up the converter and when a conversion start can occur. Table 2. Power-Down Mode Comparisons TYPE OF POWER-DOWN SUPPLY CURRENT AT 5V/3V Normal operation 5.7mA/4.5mA ACTIVATED BY TIME TO POWER-DOWN (ns) WAKE-UP BY WAKE-UP TIME ENABLE Deep power-down 4nA/1nA Setting CFR 100 Woken up by command 1011b 1µs Set CFR Nap power-down 0.3mA/0.25mA Setting CFR 200 Woken up by command 1011b 3 CCLKs Set CFR 200 Woken up by CONVST, any channel select command, default command 1111b, or wake up command 1011b. 3 CCLKs Set CFR Auto nap power-down 28 0.3mA/0.25mA Submit Documentation Feedback EOC (end of conversion) Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 N Converter State N+1 EOS EOC EOC Converter State EOS CONVST N+1 −th Sampling N −th Conversion N+1 −th Conversion Read While Converting 20ns MIN CS (For Read Result) 1 CCLK MIN = t1 Read N−1 −th Result Read While Sampling 0ns MIN 20ns MIN CS (For Read Result) Read N −th Result Figure 58. Read While Converting versus Read While Sampling (Manual Trigger) Manual Trigger Converter State Wake-Up N −th Sampling >=3CCLK N −th Conversion Activation Wake-Up =18 CCLK N+1 −th Sampling >=3CCLK EOC EOC EOS N+1 EOS N CONVST N+1 −th Conversion Activation =18 CCLK 20ns MIN 20ns MIN 1 CCLK MIN Read While Converting Read N−1 −th CS Read N −th Result Result 20ns MIN 20ns MIN Read While Sampling 20ns MIN Read N−1 −th CS 0ns MIN 20ns MIN Read N −th Result Result 20ns MIN 20ns MIN Figure 59. Read While Converting versus Read While Sampling with Deep or Nap Power-Down Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 29 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com 40ns MIN Manual Trigger (wake up by CONVST) N N+1 Converter State Wake-Up N −th Sampling >=3CCLK N −th Conversion =18 CCLK EOS POWERDOWN Wake-Up EOC EOS EOC (programmed Active Low) EOC CONVST N+1 −th Sampling N+1 −th Conversion >=3CCLK =18 CCLK 6 CCLKs POWERDOWN 6 CCLKs Read While Converting 20ns MIN 20ns MIN Read N −th Result Read N−1 −th Result CS Figure 60. Read While Converting with Auto Nap Power-Down Total Acquisition + Conversion Cycle Time: Auto trigger: = 21 CCLKs Manual: ≥ 21 CCLKs Manual + deep ≥ 4 SCLK + 100µs + 3 CCLK + 18 CCLK +16 SCLK + 1µs power-down: Manual + nap power-down: ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK Manual + auto nap ≥ 1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use CONVST to resume) power-down: Manual + auto nap ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use wake up to resume) power-down: 30 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 DIGITAL INTERFACE The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to 50MHz. Each cycle starts with the falling edge of FS/CS. The internal data register content that is made available to the output register at the EOC (presented on the SDO output pin at the falling edge of FS/CS) is the MSB. Output data are valid at the falling edge of SCLK with a td(SCLKF-SDOVALID) delay so that the host processor can read it at the falling edge. Serial data input is also read at the falling edge of SCLK. The complete serial I/O cycle starts with the first falling edge of SCLK after the falling edge of FS/CS and ends 16 falling edges of SCLK later (see NOTE). The serial interface is very flexible. It works with CPOL = 0 , CPHA = 1 or CPOL = 1, CPHA = 0. This flexibility means the falling edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK falling edge occurs before the rising edge of FS/CS. NOTE: There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read mode combination. See Table 3 and Table 6 for details. Internal Register The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration data register (CFR). Table 3. Command Set Defined by Command Register (CMR) (1) D[15:12] HEX COMMAND D[11:0] (2) WAKE-UP FROM AUTO NAP MINIMUM SCLKs REQUIRED R/W 0000b 0h Select analog input channel 0 Don't care Y 4 W 0001b 1h Select analog input channel 1 (2) Don't care Y 4 W 0010b 2h Don't care Don't care – – – 0011b 3h Don't care Don't care – – – 0100b 4h Don't care Don't care – – – 0101b 5h Don't care Don't care – – – 0110b 6h Don't care Don't care – – – 0111b 7h Don't care Don't care – – – 1000b 8h Reserved for factory test, don't use Reserved – – – 1001b 9h Reserved for factory test, don't use Reserved – – – 1010b Ah Reserved for factory test, don't use Reserved – – – 1011b Bh Wake up Don't care Y 4 W 1100b Ch Read CFR Don't care – 16 R 1101b Dh Read data Don't care – 12 R 1110 Eh Write CFR CFR value – 16 W 1111b Fh Default mode (load CFR with default value) Don't care Y 4 W (1) (2) When SDO is not in 3-state mode (FS/CS low), the bits from SDO are always part of a conversion result (depending on how many SCLKs are supplied). These two commands apply to the ADS7230 only. WRITING TO THE CONVERTER There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 3. A simple command requires only 4 SCLKs and the write takes effect at the fourth falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 6 for exceptions that require more than 16 SCLKs). Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 31 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com Configuring the Converter and Default Mode The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12 bits of data. A 4-bit command takes effect at the fourth falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK. A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected, at least four '1's are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the fourth falling edge of SCLK. CFR default values are all 1s (except for CFR_D1 on the ADS7229; this bit is ignored by the device and is always read as a '0'). The same default values apply for the CFR after a power-on reset (POR) and software reset. READING THE CONFIGURATION REGISTER The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result, except that CONVST is not used and there is no activity on the EOC/INT pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents. Table 4 shows the Configuration Register Map. Table 4. Configuration Register (CFR) Map SDI BIT CFR - D[11 - 0] DEFINITION Channel select mode D11 default = 1 D10 default = 1 D9 default = 1 D8 default = 1 D7 default = 1 D6 default = 1 D5 default = 1 D4 default = 1 D3 default = 1 D2 default = 1 D1 default = 0: ADS7229 1: ADS7230 D0 default = 1 0: Manual channel select enabled. Use channel select commands to access a different channel. 1: Auto channel select enabled. All channels are sampled and converted sequentially until the cycle after this bit is set to 0. Conversion clock (CCLK) source select 0: Conversion clock (CCLK) = SCLK/2 1: Conversion clock (CCLK) = Internal OSC Trigger (conversion start) select: start conversion at the end of sampling (EOS). If D9 = 0, the D4 setting is ignored. 0: Auto trigger automatically starts (4 internal clocks after EOC inactive) 1: Manual trigger manually started by falling edge of CONVST Don't care Don't care Pin 10 polarity select when used as an output (EOC/INT) 0: EOC Active high / INT active high 1: EOC active low / INT active low Pin 10 function select when used as an output (EOC/INT) 0: Pin used as INT 1: Pin used as EOC Pin 10 I/O select for chain mode operation 0: Pin 10 is used as CDI input (chain mode enabled) 1: Pin 10 is used as EOC/INT output Auto nap power-down enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0. 0: Auto nap power-down enabled (not activated) 1: Auto nap power-down disabled Nap power-down (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in nap power-down 1: Remove device from nap power-down (resume) Deep power-down. This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in deep power-down 1: Remove device from deep power-down (resume) TAG bit enable. This bit is ignored by the ADS7229 and is always read 0. 0: TAG bit disabled. 1: TAG bit output enabled. TAG bit appears at the 17th SCLK. Reset 0: System reset 1: Normal operation READING CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out via the SDO pin any time except during the quiet zone. This quite zone is 20ns before and 20ns after the end of sampling (EOS) period. In the quiet zone the FS/CS should be high, to avoid performance loss when switching from sampling-mode to hold-mode. End of sampling (EOS) is defined as the falling edge of CONVST when manual trigger is used or the end of the third conversion clock (CCLK) after EOC if auto trigger is used. 32 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 The falling edge of FS/CS should not be placed at the precise moment of the end of a conversion; otherwise, the data may be corrupt. There must be a minimum of at least one conversion clock (CCLK) delay at the end of a conversion. If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion result is read. The conversion result is 12-bit data in straight binary format as shown in Table 5. Generally, 12 SCLKs are necessary, but there are exceptions where more than 12 SCLKS are required (see Table 6). Data output from the serial output (SDO) is left-adjusted, MSB first. The 12-bit conversion result is followed by '0000', the TAG bit (if enabled), and additional zeros. SDO remains low until FS/CS is brought high again. Table 5. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE Full-scale range VREF Least significant bit (LSB) VREF/4096 Full-scale Midscale DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE HEX CODE +VREF – 1LSB 1111 1111 1111 FFF VREF/2 1000 0000 0000 800 Midscale – 1LSB VREF/2 – 1LSB 0111 1111 1111 7FF Zero 0V 0000 0000 0000 000 SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output. NOTE: Whenever SDO is not in 3-state mode (that is, when FS/CS is low), a portion of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are supplied. For example, a manual select channel command cycle requires 4 SCLKs; therefore, 4MSBs of the conversion result are output at SDO. The exception is that SDO outputs all 1s during the cycle immediately after any reset (POR or software reset). If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all 12 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case, it is better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in Auto nap mode). TAG Mode The ADS7230 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the converted result. An address bit is added after the LSB read out from SDO that indicates which channel the result came from if TAG mode is enabled. This address bit is '0' for channel 0 and '1' for channel 1. The converter requires more than the 16 SCLKs that are required for a 4-bit command plus 12-bit CFR or 12 data bits followed by '0000' because of the additional TAG bit. Chain Mode The ADS7229/30 can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple, high-speed, SPI-compatible serial interface by cascading the devices in a daisy-chain when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as a secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This configuration is chain mode operation. A typical connection of three converters is shown in Figure 61. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 33 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com Micro Controller INT GPIO1 GPIO2 SDI SCLK CONVST CS ADS7229 #1 SDO EOC/INT SDOSCLK GPIO3 SDI SCLK CONVST CS ADS7229 #3 CDI SDO SDI SCLK CONVST CS ADS7229 #2 CDI SDO Program device #1 CFR_D[7:5] = XX0b SDI Program device #2 and #3 CFR_D[7:5] = XX1b Figure 61. Multiple Converters Connected Using Chain Mode When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while the other converters are configured in chain mode. When a converter is configured in chain mode, the CDI input data go straight to the output register; therefore, the serial input data passes through the converter with a 16 SCLK delay (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. Figure 62 shows a detailed timing diagram. In this timing, the conversions in each device are performed simultaneously. Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC, and INT programmed as active low) CS held low during the N times 16 bits transfer cycle EOS EOS EOC #1 (active low) EOC Common CONVST Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs Min INT (active low) t4 FS/CS #1 1……………………16 1……………………16 1……………………16 Common SCLK SDO #1 Nth from #1 t4 FS/CS #2 FS/CS #3 SDO #2 Nth from #2 Nth from #1 SDO #3 Nth from #3 Nth from #2 SDI 1101b READ Result Nth from #1 1101b READ Result 1101b READ Result Figure 62. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS Care must be given to handle the multiple CS signals when the converters operate in daisy-chain mode. The different chip select signals must be low for the entire data transfer (in this example, 48 bits for three converters). The first 16-bit word after the falling chip select is always the data from the chip that received the chip select signal. 34 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and so on. This configuration is shown in Figure 62. If there is no upstream converter in the chain, as with converter #1 in the example, the same data from the converter are going to be shown repeatedly. Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 63, the same data from the converter are read out again and again in all three discrete 16-bit cycles. This result is not a desired outcome. Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC, and INT programmed as active low) EOS EOS EOC #1 (active low) EOC Common CONVST Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs Min INT (active low) t4 FS/CS #1 1……………………16 1……………………16 1……………………16 Common SCLK Nth from #1 SDO #1 Nth from #1 Nth from #1 t4 FS/CS #2 SDO #2 Nth from #2 Nth from #1 Nth from #1 Nth from #3 Nth from #3 Nth from #3 t4 FS/CS #3 SDO #3 SDI 1101b READ Result 1101b READ Result 1101b READ Result Figure 63. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 35 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com Figure 64 shows a slightly different scenario where CONVST is not shared by the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes the previous conversion data downstream. Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC, and INT programmed as active low) CS held low during the N times 16 bits transfer cycle CONVST #1 CONVST #3 EOS EOS EOC #1 (active low) EOC CONVST #2 = 1 Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs Min INT (active low) t4 FS/CS #1 1……………………16 1……………………16 1……………………16 Common SCLK SDO #1 Nth from #1 t4 FS/CS #2 FS/CS #3 SDO #2 N - 1th #2 Nth from #1 SDO #3 Nth from #3 N - 1th #2 SDI 1101b READ Result Nth from #1 1101b READ Result 1101b READ Result Figure 64. Simplified Cascade Timing (Separate CONVST) The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG bit, chain mode, and the way a channel is selected (that is, auto channel select). These possible configurations are listed in Table 6. Table 6. Required SCLKs For Different Read Out Mode Combinations CHAIN MODE AUTO CHANNEL ENABLED CFR.D5 SELECT CFR.D11 36 TAG ENABLED CFR.D1 NUMBER OF SCLK PER SPI READ TRAILING BITS 0 0 0 12 0 0 1 ≥ 17 0 1 0 12 0 1 1 ≥ 17 1 0 0 16 None 1 0 1 24 TAG bit plus seven zeros 1 1 0 16 None 1 1 1 24 TAG bit plus seven zeros Submit Documentation Feedback None MSB is TAG bit plus zero(s) None TAG bit plus seven zeros Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in chain mode. Figure 65 shows a typical delay process through multiple converters linked in daisy-chain mode. ADS7229 # 3 CDI SDO Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7ns Serial data output Logic Delay Plus PAD 8.3ns Q CLK ADS7229 # 2 SDO CDI Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7ns Logic Delay Plus PAD 8.3ns Q CLK ADS7229 # 1 CDI Serial data input SDO Logic Delay Plus PAD 2.7ns D Logic Delay < = 8 .3 ns Logic Delay Plus PAD 8.3ns Q CLK SCLK input Figure 65. Typical Delay Through Converters Configured in Chain Mode RESET The converter has two reset mechanisms: a power-on reset (POR) and a software reset using CFR_D0. These two mechanisms are NOR-ed internally. When a reset (software or POR) is issued, all register data are set to the default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state machine is reset to the power-on state. Figure 66 illustrates the digital output under a reset condition. SW RESET CDI POR SET SAR Shift Register Intermediate Latch Output Register Conversion Clock Latched by End Of Conversion SDO SCLK Latched by Falling Edge of CS CS EOC EOC Figure 66. Digital Output Under Reset Condition Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 37 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com When the device is powered up, the POR sets the device to default mode when AVDD reaches 1.5V. When the device is powered down, the POR circuit requires AVDD to remain below 125mV for at least 350ms to ensure proper discharging of internal capacitors and to correct the behavior of the ADC when powered up again. If AVDD drops below 400mV but remains above 125mV, the internal POR capacitor does not discharge fully and the device requires a software reset to perform correctly after the recovery of AVDD (this condition is shown as the undefined zone in Figure 67). AVDD (V) 5.500 5.000 Specified Supply Voltage Range 4.000 3.000 2.700 2.000 POR Trigger Level 1.500 1.000 0.400 0.125 Undefined Zone 0 0.350 t (s) Figure 67. Relevant Voltage Levels for POR 38 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 ADS7229 ADS7230 www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009 APPLICATION INFORMATION TYPICAL CONNECTION Figure 68 shows a typical circuit configuration for the device. Analog Supply 4.7mF AGND Ext Ref Input 100nF 22mF Analog Input AGND +VA REF+ REF- AGND IN+ INFS/CS SDO SDI SCLK Host Processor Interface Supply ADS7229 BDGND CONVST EOC/INT/CDI 4.7mF +VBD 100nF Figure 68. Typical Circuit Configuration Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 Submit Documentation Feedback 39 ADS7229 ADS7230 SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2008) to Revision A ........................................................................................................... Page • • • • • • • • • • • • • • • • 40 Added +REF to AGND and –REF to AGND specifications to Voltage range section of Absolute Maximum Ratings table . 2 Changed Revised conditions of the 5V Electrical Characteristics to +VA = 4.5V to 5.5V..................................................... 3 Changed Revised conditions of the 5V Electrical Characteristics to +VA = 4.5V to 5.5V..................................................... 4 Deleted typical specification from Input reference range, VREF [(REF+) – (REF–)] row of the External Voltage Reference Input section of the 5V Electrical Characteristics ................................................................................................ 4 Changed test condition of Supply current, PD mode to Deep power-down mode in Power-Supply Requirements section of the 5V Electrical Characteristics............................................................................................................................ 4 Changed VREF row of External Voltage Reference Input section in the 2.5V Electrical Characteristics................................ 6 Changed test condition of Supply current, PD mode to Deep power-down mode in Power-Supply Requirements section of the 2.5V Electrical Characteristics......................................................................................................................... 7 Corrected typo in Figure 2 ................................................................................................................................................... 12 Corrected typo in Figure 3 ................................................................................................................................................... 13 Corrected typo in Figure 5 ................................................................................................................................................... 14 Added last sentence to the Driver Amplifier Choice section................................................................................................ 24 Updated Figure 54 ............................................................................................................................................................... 24 Updated Figure 55 ............................................................................................................................................................... 24 Changed fifth sentence of the Deep Power-Down Mode section ........................................................................................ 27 Changed Supply Current specification of Auto nap power-down row of Table 2 ................................................................ 28 Added Figure 67 and corresponding paragraph to the RESET section .............................................................................. 38 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7229 ADS7230 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS7229IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7229I A Samples ADS7229IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7229I A Samples ADS7229IRSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7229I A Samples ADS7229IRSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7229I A Samples ADS7230IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7230I A Samples ADS7230IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7230I A Samples ADS7230IRSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7230I A Samples ADS7230IRSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 7230I A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of