ADS7800BH

® ADS7800 12-Bit 3µs Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q 333k SAMPLES PER SECOND q STANDARD ±10V AND ±5V INPUT RANGES q DC PERFORMANCE OVER TEMP: No Missing Codes 1/2LSB Integral Linearity Error 3/4LSB Differential Linearity Error q AC PERFORMANCE OVER TEMP: 72dB Signal-to-Noise Ratio 80dB Spurious-free Dynamic Range –80dB Total Harmonic Distortion q INTERNAL SAMPLE/HOLD, REFERENCE, CLOCK, AND 3-STATE OUTPUTS q POWER DISSIPATION: 215mW max q PACKAGE: 24-Pin Single-wide DIP 24-Lead SOIC DESCRIPTION The ADS7800 is a complete 12-bit sampling analogto-digital converter using state-of-the-art CMOS structures. It contains a complete 12-bit successive approximation A/D converter with internal sample/hold, reference, clock, digital interface for microprocessor control, and three-state output drivers. The ADS7800 is specified at a 333kHz sampling rate. Conversion time is factory set for 2.70µs max over temperature, and the high speed sampling input stage insures a total acquisition and conversion time of 3µs max over temperature. Precision, laser-trimmed scaling resistors provide industry-standard input ranges of ±5V or ±10V. AC and DC performance are completely specified. Two grades based on linearity and dynamic performance are available to provide the optimum price/ performance fit in a wide range of applications. The 24-pin ADS7800 is available in plastic and sidebraze hermetic 0.3" wide DIPs, and in an SOIC package. It operates from a +5V supply and either a –12V or –15V supply. The ADS7800 is available in grades specified over 0°C to +70°C and –40°C to +85°C temperature ranges. Control Logic Clock SAR Output Latches And Three State Drivers Comparator BUSY ±10VIN ±5VIN Internal Ref CDAC 2V Reference Out Three State Parallel Output Data Bus International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1989 Burr-Brown Corporation PDS-1018E Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL At TA = TMIN to TMAX, Sampling Frequency, fS, = 333kHz, –VS = –15V, VS = +5V, unless otherwise specified. ADS7800JP/JU/AH PARAMETER RESOLUTION ANALOG INPUT Voltage Ranges Impedance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Full Scale Error (1) Full Scale Error Drift Integral Linearity Error Differential Linearity Error No Missing Codes Bipolar Zero(1) Bipolar Zero Drift Power Supply Sensitivity –16.5V < –VS < –13.5V –12.6V < –VS < –11.4V +4.75V < VS < +5.25V Transition Noise(3) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Two-tone Intermodulation Distortion Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio (SNR) SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response (5) Overvoltage Recovery (6) INTERNAL REFERENCE VOLTAGE Voltage Source Current Available for External Loads DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH ILEAKAGE (High-Z State) POWER SUPPLIES Rated Voltage –VS VS (VSA and VSD) Current –IS IS Power Consumption 1.9 fIN = 47kHz fIN = 47kHz = 24.4kHz (–6dB) = 28.5kHz (–6dB) fIN = 47kHz fIN = 47kHz 74 0.1 77 –77 –77 70 71 13 150 130 150 2.0 10 2.1 * 77 –74 –74 69 70 ±10V/±5V 6.3 4.2 2.5 2.6 380 CONDITIONS MIN TYP MAX 12 * * * * * * ADS7800KP/KU/BH MIN TYP MAX * UNITS Bits V kΩ kΩ µs µs kHz % ppm/°C LSB(2) LSB LSB ppm/°C LSB LSB LSB LSB dB (4) dB dB dB dB ns ps, rms ns ns * V µA ±10V Range ±5V Range Conversion Alone Acquisition + Conversion 4.4 2.9 8.1 5.4 2.7 3.0 * * * * * * 333 * ±0.50 ±0.35 * ±1/2 ±3/4 Guaranteed ±2 * 6 ±1 ±1 Guaranteed ±4 1 ±1/2 ±1/2 ±1 * * ±1/2 * 80 –80 –80 72 73 * * * * * * fIN1 fIN2 –77 –77 67 68 –0.3 +2.4 –5 +5 +0.8 +5.3 * * * * * * V V µA µA ISINK = 1.6mA ISOURCE = 500µA 0.0 +2.4 ±0.1 Parallel, 12-bit or 8-bit/4-bit Binary Offset Binary +0.4 * +5.0 * ±5 * * * * V V µA –11.4 +4.75 –15 +5.0 3.5 18 135 –16.5 +5.25 6 25 215 * * * * * * * * * * * * V V mA mA mW ® ADS7800 2 SPECIFICATIONS ELECTRICAL (CONT) At TA = TMIN to TMAX, Sampling Frequency, fS, = 333kHz, –VS = –15V, VS = +5V, unless otherwise specified. ADS7800JP/JU/AH PARAMETER TEMPERATURE RANGE Specification Operating Storage CONDITIONS JP/JU/KP/KU AH/BH JP/KP/JU/KU MIN 0 –40 –40 –65 TYP MAX +70 +85 +85 +150 ADS7800KP/KU/BH MIN * * * * TYP MAX * * * * UNITS °C °C °C °C * Same as specification for ADS7800JP/JU/AH. NOTES: (1) Adjustable to zero with external potentiometer. (2) LSB means Least Significant Bit. For ADS7800, 1LSB = 2.44mV for the ±5V range, 1LSB = 4.88mV for the ±10V range. (3) Noise was characterized over temperature near full scale, 0V, and negative full scale. 0.1LSB represents a typical rms level of noise at the worst case, which was near full scale input at +125°C. (4) All specifications in dB are referred to a full-scale input, either ±10V or ±5V. (5) For full scale step input, 12-bit accuracy attained in specified time. (6) Recovers to specified performance in specified time after 2 x FS input overvoltage. ABSOLUTE MAXIMUM RATINGS –VS to ANALOG COMMON ............................................................ –16.5V VS to DIGITAL COMMON .................................................................... +7V Pin 23 (VSD ) to Pin 24 (VSA ) ........................................................... ±0.3V ANALOG COMMON to DIGITAL COMMON ........................................ ±1V Control Inputs to DIGITAL COMMON ............................. –0.3 to VS + 0.3V Analog Input Voltage .......................................................................... ±20V Maximum Junction Temperature ..................................................... 160°C Internal Power Dissipation ............................................................. 750mW Lead Temperature (soldering, 10s) ................................................ +300°C Thermal Resistance, θJA: Plastic DIP ................................................................................ 100°C/W SOIC ......................................................................................... 100°C/W Ceramic ...................................................................................... 50°C/W ELECTROSTATIC DISCHARGE SENSITIVITY The ADS7800 is an ESD (electrostatic discharge) sensitive device. The digital control inputs have a special FET structure, which turns on when the input exceeds the supply by 18V, to minimize ESD damage. However, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. When not in use, devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. PACKAGE/ORDERING INFORMATION INTEGRAL LINEARITY ERROR (LSB) ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 SIGNAL-TO(NOISE+DISTORTION) RATIO (dB min) 67 69 67 69 67 69 SPECIFICATION TEMPERATURE RANGE (°C) 0 to +70 0 to +70 0 to +70 0 to +70 –40 to +85 –40 to +85 PACKAGE DRAWING NUMBER(1) 243 243 239 239 245 245 PRODUCT ADS7800JP ADS7800KP ADS7800JU ADS7800KU ADS7800AH ADS7800BH PACKAGE 24-Pin Plastic DIP 24-Pin Plastic DIP 24-Pin Plastic SOIC 24-Pin Plastic SOIC 24-Pin Ceramic DIP 24-Pin Ceramic DIP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS7800 PIN ASSIGNMENTS PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NAME IN1 IN2 REF AGND D11 D10 D9 D8 D7 D6 D5 D4 DGND D3 D2 D1 D0 HBE DESCRIPTION ±10V Analog Input. Connected to GND for ±5V range. ±5V Analog Input. Connected to GND for ±10V range. +2V Reference Output. Bypass to GND with 22µF to 47µF Tantalum. Buffer for external loads. Analog Ground. Connect to pin 13. Data Bit 11. Most Significant Bit (MSB). Data Bit 10. Data Bit 9. Data Bit 8. Data Bit 7 if HBE is LOW; LOW if HBE is HIGH. Data Bit 6 if HBE is LOW; LOW if HBE is HIGH. Data Bit 5 if HBE is LOW; LOW if HBE is HIGH. Data Bit 4 if HBE is LOW; LOW if HBE is HIGH. Digital Ground. Connect to pin 4. Data Bit 3 if HBE is LOW; Data Bit 11 if HBE is HIGH. Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH. Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH. Data Bit 0 if HBE is LOW. Least Significant Bit (LSB); Data Bit 8 if HBE is HIGH. High Byte Enable. When held LOW, data output as 12bits in parallel. When held HIGH, four MSBs presented on pins 14-17, pins 9-12 output LOWs. Must be LOW to initiate conversion. Read/Convert. Falling edge initiates conversion when CS is LOW, HBE is LOW, and BUSY is HIGH. Chip Select. Outputs in Hi-Z state when HIGH. Must be LOW to initiate conversion or read data. Busy. Output LOW during conversion. Data valid on rising edge in Convert Mode. Negative Power Supply. –12V or –15V. Bypass to GND. Positive Digital Power Supply. +5V. Connect to pin 24, and bypass to GND. Positive Analog Power Supply. +5V. Connect to pin 23, and bypass to GND. PIN CONFIGURATION Top View DIP/SOIC IN1 IN2 REF AGND D11 D10 D9 D8 D7 D6 D5 D4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VSA VSD –VS BUSY CS R/C HBE D0 D1 D2 D3 DGND 19 20 21 22 23 24 R/C CS BUSY –VS VSD VSA ® ADS7800 4 TYPICAL PERFORMANCE CURVES At +VS = +5V, –VS = –15V, and TA = +25° C, unless otherwise noted. All plots use 1024 point FFTs. FREQUENCY SPECTRUM (10kHz fIN ) 0 –20 0 FREQUENCY SPECTRUM (50kHz fIN ) fIN = 50kHz fSAMPLING = 330kHz TA = 25°C fIN = 10kHz fSAMPLING = 330kHz TA = 25°C Magnitude (dB) 0 150 165 –20 –40 –60 –80 –100 –120 Magnitude (dB) –40 –60 –80 –100 –120 50 100 Frequency (kHz) 0 50 100 Frequency (kHz) 150 165 SIGNAL/(NOISE + DISTORTION) vs INPUT FREQUENCY AND AMBIENT TEMPERATURE 75 Spurious Free Dynamic Range (dB) SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY AND AMBIENT TEMPERATURE 95 90 85 80 75 70 65 5°C +2 5° +1 C 25 °C –5 Signal/(Noise + Distortion) (dB) –55°C 70 +2 5° C +1 25 °C 65 1 10 Input Frequency (kHz) 50 150 1 10 Input Frequency (kHz) 50 150 SIGNAL/(NOISE + DISTORTION) vs FREQUENCY AND AMPLITUDE 80 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY AND NEGATIVE SUPPLY VOLTAGE 95 Signal/(Noise + Distortion) (dB) 0dB 60 –20dB 40 –40dB 20 –60dB 0 1 10 Input Frequency (kHz) 50 150 Spurious Free Dynamic Range (dB) 90 85 80 75 70 65 1 10 Input Frequency (kHz) –V S = –12V –V S = –15V 50 150 ® 5 ADS7800 ® ADS7800 6 THEORY OF OPERATION The ADS7800 combines the advantages of advanced CMOS technology (logic density, stable capacitors, and good analog switches) with Burr-Brown’s proven skills in lasertrimmed thin-film resistors to provide a complete sampling A/D converter. A basic charge-redistribution successive approximation architecture converts analog input voltages into digital words. Figure 1 shows the operation of a simplified three bit charge redistribution A/D. Precision laser-trimmed scaling resistors at the input divide standard input ranges (±10V or ±5V for the ADS7800) into levels compatible with the CMOS characteristics of the internal capacitor array. While in the sampling mode, the capacitor array switch for the MSB capacitor (S1) is in position “S”, so that the charge on the MSB capacitor is proportional to the voltage level of the analog input signal, and the remaining array switches (S2 and S3) are set to position “R” to provide an accurate bipolar offset from the reference source REF. At the same time, switch SC is also in the closed position to auto-zero any offset errors in the CMOS comparator. When a convert command is received, switch S1 is opened to trap a charge on the MSB capacitor proportional to the input level at the time of the sampling command, switches S2 and S3 are opened to trap an offset charge, and switch SC is opened to float the comparator input. The charge trapped on the capacitor array can now be moved between the three capacitors in the array by connecting switches S1, S2 and S3 to positions “R” (to connect to REF) or “G” (to connect to GND) successively, changing the voltage generated at the comparator input node. The first approximation connects the MSB capacitor via switch S1 to REF, while switches S2 and S3 are connected to GND. Depending on whether the comparator output is HIGH or LOW, the logic will then latch S1 in position “R” or “G”, and moves on to make the next approximation by connecting S2 to REF and S3 to GND. When the three successive approximation steps are made for this simple converter, the voltage level at the comparator will be within 1/2LSB of GND, and the data output word will be based on reading the positions of S1, S2 and S3. 1 IN 1 IN 2 REF AGND +5V +5V –15V BUSY 24 23 22 21 20 19 18 17 16 15 14 13 +5V 6.8µF + 0.1µF Input 2 47µF + 3 4 5 6 7 8 9 1µF + –15V Busy D11 (MSB) CS D10 D9 D8 D7 R/C HBE D0 (LSB) D1 D2 D3 DGND Convert Command 10 D6 11 D5 12 D4 D11 (MSB) Data Out D0 (LSB) FIGURE 2. Basic ±10V Operation. OPERATION BASIC OPERATION Figure 2 shows the simple hookup circuit required to operate the ADS7800 in a ±10V range in the Convert Mode. A convert command arriving on pin 19, R/C, (a pulse taking pin 19 LOW for a minimum of 40ns) puts the ADS7800 in the hold mode, and a conversion is started. Pin 21, BUSY, will be held LOW during the conversion, and rises only after the conversion is completed and the data has been transferred to the output latches. Thus, the rising edge of the signal on pin 21 can be used to read the data from the conversion. Also, during conversion, the BUSY signal puts the output data lines in Hi-Z states and inhibits input lines. This means that pulses on pin 19 are ignored, so that new conversions cannot be initiated during a conversion, either as a result of spurious signals or to short-cycle the ADS7800. In the Read Mode, the input to pin 19 is kept normally LOW, and a HIGH pulse is used to read data and initiate a conversion. In this mode, the rising edge of R/C on pin 19 will enable the output data pins, and the data from the previous conversion becomes valid. The falling edge then puts the ADS7800 in a hold mode, and initiates a new conversion. The ADS7800 will begin acquiring a new sample as soon as the conversion is completed, even before the BUSY output rises on pin 21, and will track the input signal until the next conversion is started, whether in the Convert Mode or the Read Mode. ® Input Signal 4C S R S1 G R 2C S2 G SC C S3 Comparator L o g i c Out To Switches R G + – Ref FIGURE 1. 3-Bit Charge Redistribution A/D. 7 ADS7800 CS R/C tB BUSY tDBC tC Converter Acquisition Mode tAP Hold Time Conversion Acquisition Conversion R/C X 1 ↓0 1 1 1 ↓0 0 X HBE BUSY X 0 0 1 1 1 X 1 1 1 1 1 1 0 OPERATION None - Outputs in Hi-Z State. Holds Signal and Initiates Conversion. Output Three-State Buffers Enabled once Conversion has Finished. Enable Hi-Byte in 8-bit Bus Mode. Inhibit Start of Conversion. None - Outputs in Hi-Z State. Conversion in Progress. Outputs Hi-Z State. New Conversion Inhibited until Present Conversion has Finished. 1 0 0 0 0 0 X TABLE II. Control Line Functions. For stand-alone operation, control of the ADS7800 is accomplished by a single control line connected to R/C. In this mode, CS and HBE are connected to GND. The output data are presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. Conversion is initiated by a HIGH-to-LOW transition on R/C. The three-state data output buffers are enabled when R/C is HIGH and BUSY is HIGH. Thus, there are two possible modes of operation: conversion can be initiated with either positive or negative pulses. In either case, the R/C pulse must remain LOW a minimum of 40ns. Figure 6 illustrates timing when conversion is initiated by an R/C pulse which goes LOW and returns HIGH during the conversion. In this case (Convert Mode), the three-state outputs go into the Hi-Z state in response to the falling edge of R/C, and are enabled for external access of the data after completion of the conversion. Figure 7 illustrates the timing when conversion is initiated by a positive R/C pulse. In this mode (Read Mode), the output data from the previous conversion is enabled during the HIGH portion of R/C. A new conversion starts on the falling edge of R/C, and the three-state outputs return to the Hi-Z state until the next occurrence of a HIGH on R/C. FIGURE 3. Acquisition and Conversion Timing. SYMBOL tDBC tB tAP ∆tAP tC PARAMETER BUSY delay from R/C BUSY Low Aperture Delay Aperture Jitter Conversion Time MIN TYP 80 2.5 13 150 2.47 MAX 150 2.7 UNITS ns µs ns ps, rms µs 2.70 TABLE I. Acquisition and Conversion Timing. For use with an 8-bit bus, the data can be read out in two bytes under the control of pin 18, HBE. With a LOW input on pin 18, at the end of a conversion, the 8 LSBs of data are loaded into the latches on pins 9 through 12 and 14 through 17. Taking pin 18 HIGH then loads the 4 MSBs on pins 14 through 17, with pins 9 through 12 being forced LOW. ANALOG INPUT RANGES The ADS7800 offers two standard bipolar input ranges: ±10V and ±5V. If a ±10V range is required, the analog input signal should be connected to pin 1. A signal requiring a ±5V range should be connected to pin 2. In either case, the other pin of the two must be grounded or connected to the adjustment circuits described in the section on calibration. (See Figures 4 and 5, or 10 and 11.) CONVERSION START CONTROLLING THE ADS7800 The ADS7800 can be easily interfaced to most microprocessor-based and other digital systems. The microprocessor may take full control of each conversion, or the ADS7800 may operate in a stand-alone mode, controlled only by the R/C input. Full control consists of initiating the conversion and reading the output data at user command, transmitting data either all 12-bits in one parallel word, or in two 8-bit bytes. The three control inputs (CS, R/C and HBE) are all TTL/CMOS compatible. The functions of the control lines are shown in Table II. A conversion is initiated on the ADS7800 only by a negative transition occurring on R/C, as shown in Table I. No other combination of states or transitions will initiate a conversion. Conversion is inhibited if either CS or HBE are HIGH, or if BUSY is LOW. CS and HBE should be stable a minimum of 25ns prior to the transition on R/C. Timing relationships for start of conversion are illustrated in Figure 8. The BUSY output indicates the current state of the converter by being LOW only during conversion. During this time the three-state output buffers remain in a Hi-Z state, and therefore data cannot be read during conversion. During this period, additional transitions on the three digital inputs (CS, R/C and HBE) will be ignored, so that conversion cannot be prematurely terminated or restarted. ® ADS7800 8 INTERNAL CLOCK The ADS7800 has an internal clock that is factory trimmed to achieve a typical conversion time of 2.47µs, and a maximum conversion time over the full operating temperature range of 2.7µs. No external adjustments are required, and with the guaranteed maximum acquisition time of 300ns, throughput performance is assured with convert pulses as close as 3µs. READING DATA After conversion is initiated, the output buffers remain in a Hi-Z state until the following three logic conditions are simultaneously met: R/C is HIGH, BUSY is HIGH and CS is LOW. Upon satisfaction of these conditions, the data lines are enabled according to the state of HBE. See Figure 9 and Table III for timing relationships and specifications. 1 ADS7800 ±5V Input 2 FIGURE 5. ±5V Range Without Trims. CALIBRATION PROCEDURE First, trim offset, by applying at the input (pin 1 or 2) the mid-point transition voltage (–2.44mV for the ±10V range, –1.22mV for the ±5V range.) With the ADS7800 converting continually, adjust potentiometer R1 until the MSB (D11 on pin 5) is toggling alternately HIGH and LOW. Next adjust full scale, by applying at the input a DC input signal that is 3/2LSB below the nominal full scale voltage (+9.9927V for the ±10V range, +4.9963V for the ±5V range.) With the ADS7800 converting continually, adjust R2 until the LSB (D0 on pin 17) is toggling HIGH and LOW with all of the other bits HIGH. CALIBRATION OPTIONAL EXTERNAL GAIN AND OFFSET TRIM Offset and full-scale errors may be trimmed to zero using external offset and full-scale trim potentiometers connected to the ADS7800 as shown in Figures 10 and 11. If adjustment of offset and full scale is not required, connections as shown in Figures 4 and 5 should be used. LAYOUT CONSIDERATIONS Because of the high resolution and linearity of the ADS7800, system design problems such as ground path resistance and contact resistance become very important. ANALOG SIGNAL SOURCE IMPEDANCE The input resistance of the ADS7800 is 6.3kΩ or 4.2kΩ (for the ±10V and ±5V ranges respectively.) To avoid introducing distortion, the source resistance must be very low, or constant with signal level. The output impedance provided by most op amps is ideal. Pins 23 (VSD ) and 24 (VSA ) are not connected internally on the ADS7800, to maximize accuracy on the chip. They should be connected together as close as possible to the unit. ±10V Input 1 ADS7800 2 FIGURE 4. ±10V Range Without Trims. R/C tW tB BUSY tDBC tAP Converter Mode Acquire Convert tC tHDR and tHL Data BUS Data Valid Hi-Z State tDBE Acquire tA tDB Data Valid Hi-Z State Convert FIGURE 6. Convert Mode: R/C Pulse LOW — Outputs Enabled After Conversion. ® 9 ADS7800 R/C tW tB BUSY tDBC tAP tDBE Convert tC tHDR and tHL Data Valid Acquire tA Data Valid tAP Convert Converter Mode tDD Data BUS Acquire Hi-Z State Hi-Z State Hi-Z State FIGURE 7. Read Mode: R/C Pulse HIGH— Outputs Enabled Only When R/C is High. SYMBOL tW tDBC tB tAP ∆tAP tC tDBE tDB tA tA+tC tHDR tS tH tDD tHDR tHL PARAMETER R/C Pulse Width BUSY delay from R/C BUSY LOW Aperture Delay Aperture Jitter Conversion Time BUSY from End of Conversion BUSY Delay after Data Valid Acquisition Time Throughput Time Valid Data Held After R/C LOW CS or HBE LOW before R/C Falls CS or HBE LOW after R/C Falls Data Valid from CS LOW, R/C HIGH, and HBE in Desired State (Load = 100pF) Valid Data Held After R/C Low Delay to Hi-Z State after R/C Falls or CS Rises (3kΩ Pullup or Pulldown) 20 20 25 25 25 MIN 40 TYP 10 80 2.5 13 150 2.47 100 75 130 2.6 50 5 0 65 50 50 150 150 200 300 3.0 2.70 150 2.7 MAX UNITS ns ns µs ns ps, rms µs ns ns ns µs ns ns ns ns ns ns TABLE III. Timing Specifications (TMIN to TMAX). Pin 24 may be slightly more sensitive than pin 23 to supply variations, but to maintain maximum system accuracy, both should be well isolated from digital supplies with wide load variations. To limit the effects of digital switching elsewhere in a system on the analog performance of the system, it often makes sense to run a separate +5V supply conductor from the supply regulator to any analog components requiring +5V, including the ADS7800. The VS pins (23 and 24) should be connected together and bypassed with a parallel combination of a 6.8µF tantalum capacitor and a 0.1µF ceramic capacitor located close to the converter to obtain noise-free operation. (See Figure 2.) The –VS pin 22 should be bypassed with a 1µF tantalum capacitor, again as close as possible to the ADS7800. Noise on the power supply lines can degrade converter performance, especially noise and spikes from a switching power supply. Appropriate supplies or filters must be used. The GND pins (4 and 13) are also separated internally, and should be directly connected to a ground plane under the CS or HBE tS tH R/C tW BUSY tDBC Data Bus Data Valid Hi-Z State tHDR and tHL FIGURE 8. Conversion Start Timing. ® ADS7800 10 converter if at all possible. A ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. Where any compromises must be made, the common return of the analog input signal should be referenced to pin 4, AGND, on the ADS7800, which prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. Coupling between analog input and digital lines should be minimized by careful layout. For instance, if the lines must cross, they should do so at right angles. Parallel analog and digital lines should be separated from each other by a pattern connected to common. If external full scale and offset potentiometers are used, the potentiometers and related resistors should be located as close to the ADS7800 as possible. External Gain Adjust ±10V Input R2 100Ω 1 2 3 4 ADS7800 +5V Bipolar Zero Adjust R1 10kΩ 6.65kΩ –15V 10k 49.9Ω 5 6 7 FIGURE 10. ±10V Range With External Trims. MINIMIZING “GLITCHES” Coupling of external transients into an A/D converter can cause errors which are difficult to debug. In addition to the discussions earlier on layout considerations for supplies, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance out of a system using the ADS7800. These potential system problem sources are particularly important to consider when developing a new system, and looking for the causes of errors in breadboards. First, care should be taken to avoid glitches during critical times in the sampling and conversion process. Since the ADS7800 has an internal sample/hold function, the signal that puts it into the hold state (R/C going LOW) is critical, as it would be on any sample/hold amplifier. The R/C falling edge should be sharp and have minimal ringing, especially during the 20ns after it falls. Although not normally required, it is also good practice to avoid glitching the ADS7800 while bit decisions are being made. Since the above discussion calls for a fast, clean rise and fall on R/C, it makes sense to keep the rising edge of the convert pulse outside the time when bit decisions are being made. In other words, the convert pulse should either be short (under 100ns so that it transitions before the MSB decision), or relatively long (over 2.75µs to transition after the LSB decision). CS R/C HBE BUSY tDB DB11-DB0 tDD Data Valid tHL & tHDR FIGURE 9. Read Cycle Timing. REFERENCE BYPASS Pin 3 (REF) should be bypassed with a 22µ F to 47µF tantalum capacitor. A rated working voltage of 2V or more is acceptable here. This pin is used to enhance the system accuracy of the internal reference circuit, and is not recommended for driving external signals. If there are important system reasons for using the ADS7800 reference externally, the output of pin 3 must be appropriately buffered. “HOT SOCKET” PRECAUTION Two separate +5V VS pins, 23 and 24, are used to minimize noise caused by digital transients. If one pin is powered and the other is not, the ADS7800 may “Latch Up” and draw excessive current. In normal operation, this is not a problem because both pins will be soldered together. However, during evaluation, incoming inspection, repair, etc., where the potential of a “Hot Socket” exists, care should be taken to power the ADS7800 only after it has been socketed. External Gain Adjust ±5V Input 100Ω +5V 1 ADS7800 R2 2 3 4 5 Bipolar Zero Adjust R1 10kΩ 10kΩ –15V 30.1kΩ 301Ω 6 7 FIGURE 11. ±5V Range With External Trims. ® 11 ADS7800 Next, although the data outputs are forced into a Hi-Z state during conversion, fast bus transients can still be capacitively coupled into the ADS7800. If the data bus experiences fast transients during conversion, these transients can be attenuated by adding a logic buffer to the data outputs. The BUSY output can be used to enable the buffer. Naturally, transients on the analog input signal are to be avoided, especially at times within ±20ns of R/C going LOW, when they may be trapped as part of the charge on the capacitor array. This requires careful layout of the circuit in front of the ADS7800. INPUT VOLTAGE RANGE AND LSB VALUES Input Voltage Range Defined As: Analog Input Connected to Pin Pin Connected to GND One Least Significant Bit (LSB) Finally, in multiplexed systems, the timing on when the multiplexer is switched may affect the analog performance of the system. In most applications, the multiplexer can be switched as soon as R/C goes LOW (with appropriate delays), but this may affect the conversion if the switched signal shows glitches or significant ringing at the ADS7800 input. Whenever possible, it is safer to wait until the conversion is completed before switching the multiplexer. The extremely fast acquisition time and conversion time of the ADS7800 make this practical in many applications. FSR/212 ±10V 1 2 20V/212 4.88mV ±5V 2 1 10V/212 2.44mV OUTPUT TRANSITION VALUES FFEH to FFFH 7FFH to 800H 000H to 001H +Full Scale Mid Scale (Bipolar Zero) –Full Scale +10V–3/2LSB +9.9927V 0V–1/2LSB –2.44mV –10V+1/2LSB –9.9976V +5V–3/2LSB +4.9963V 0V–1/2LSB –1.22mV –5V+1/2LSB –4.9988V TABLE IV. Input Voltages, Transition Values, and LSB Values. ® ADS7800 12