ADS7807PBG4

ADS7807 AD S 780 7 ADS 780 7 SBAS022C – NOVEMBER 1992 – REVISED FEBRUARY 2006 Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES q 35mW max POWER DISSIPATION q 50µW POWER-DOWN MODE q 25µs max ACQUISITION AND CONVERSION q ±1.5LSB max INL q DNL: 16 bits “No Missing Codes” q 86dB min SINAD WITH 1kHz INPUT q ±10V, 0V TO +5V, AND 0V TO +4V INPUT RANGES q SINGLE +5V SUPPLY OPERATION q PARALLEL AND SERIAL DATA OUTPUT q PIN-COMPATIBLE WITH THE 12-BIT ADS7806 q USES INTERNAL OR EXTERNAL REFERENCE q 0.3" DIP-28 AND SO-28 DESCRIPTION The ADS7807 is a low-power, 16-bit, sampling Analog-toDigital (A/D) converter using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, Successive Approximation Register (SAR) A/D converter with sample-and-hold, clock, reference, and microprocessor interface with parallel and serial output drivers. The ADS7807 can acquire and convert 16 bits to within ±1.5LSB in 25µs max while consuming only 35mW max. Laser trimmed scaling resistors provide standard industrial input ranges of ±10V and 0V to +5V. In addition, a 0V to +4V range allows development of complete single-supply systems. The ADS7807 is available in a 0.3" DIP-28 and SO-28, both fully specified for operation over the industrial –40°C to +85°C temperature range. Clock Successive Approximation Register and Control Logic R/C CS BYTE Power Down 40kΩ R1IN CDAC BUSY Parallel 20kΩ 40kΩ Comparator and Serial Data Serial Data Serial Data Clock 10kΩ R2IN CAP Out Parallel Data Buffer 6kΩ Internal +2.5V Ref Reference Power-Down 8 REF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1992-2006, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ........................................................................... ±12V .......................................................................... ±5.5V .................................. VANA + 0.3V to AGND2 – 0.3V ......................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND1, and AGND2 ............. ±0.3V VANA ....................................................................................................... 7V VDIG to VANA ...................................................................................... +0.3V VDIG ........................................................................................................ 7V Digital Inputs ............................................................. –0.3V to VDIG + 0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ............................................... +300°C Analog Inputs: R1IN R2IN CAP REF NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MINIMUM MAXIMUM SPECIFIED SIGNAL-TOINTEGRAL NO MISSING (NOISE + SPECIFIED LINEARITY CODE LEVEL DISTORTION) PACKAGE TEMPERATURE ERROR (LSB) (LSB) RATIO (DB) PACKAGE-LEAD DESIGNATOR(1) RANGE ±3 ±1.5 ±3 " ±1.5 " 15 16 15 " 16 " 83 86 83 " 86 " Dip-28 NT –40°C to +85°C PRODUCT ADS7807P ADS7807PB ADS7807U " ADS7807UB " PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY " SO-28 " " DW " " " " " ADS7807P ADS7807PB –40°C to +85°C ADS7807U " " " ADS7807UB " " " ADS7807P Tubes, 13 ADS7807PB Tubes, 13 ADS7807U Tubes, 28 ADS7807U/1K Tape and Reel, 1000 ADS7807UB Tubes, 28 ADS7807UB/1K Tape and Reel, 1000 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified. ADS7807P, U PARAMETER RESOLUTION ANALOG INPUT Voltage Ranges Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Gain Error Full-Scale Error(3,4) Full-Scale Error Drift Full-Scale Error(3,4) Full-Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Unipolar Zero Error(3) Unipolar Zero Error Drift Recovery Time to Rated Accuracy from Power-Down(5) Power-Supply Sensitivity (VDIG = VANA = VS) CONDITIONS MIN TYP MAX 16 ±10, 0 to +5, 0 to +4 (See Table I) 35 ✻ ✻ ✻ ✻ ±3 +3, –2 15 0.8 ±0.2 ±7 Ext. 2.5000V Ref Ext. 2.5000V Ref ±10V Range ±10V Range 0V to 5V, 0V to 4V Ranges 0V to 5V, 0V to 4V Ranges 2.2µF Capacitor to CAP +4.75V < VS < +5.25V ±0.5 ±0.5 ±0.5 1 16 ✻ ±0.1 ±5 ✻ ±10 ✻ ±3 ✻ ✻ ±8 ✻ ✻ ✻ ±1.5 +1.5, –1 MIN ADS7807PB, UB TYP MAX ✻ UNITS Bits V pF µs µs kHz LSB(1) LSB Bits LSB % % ppm/°C % ppm/°C mV ppm/°C mV ppm/°C ms LSB Acquire and Convert 40 20 25 ±0.5 ±0.5 ±0.25 ±0.25 2 ADS7807 www.ti.com SBAS022C ELECTRICAL CHARACTERISTICS (Cont.) At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified. ADS7807P, U PARAMETER AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Signal-to-Noise Usable Bandwidth(7) Full-Power Bandwidth (–3dB) SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Over-Voltage Recovery(8) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer.) Internal Reference Drift External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH(9) IIL IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance DIGITAL TIMING Bus Access Time Bus Relinquish Time POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation CONDITIONS fIN = 1kHz, ±10V fIN = 1kHz, ±10V fIN = 1kHz, ±10V –60dB Input fIN = 1kHz, ±10V MIN 90 83 83 TYP 100 –100 88 30 88 130 600 MAX MIN 96 –90 86 86 ADS7807PB, UB TYP ✻ ✻ ✻ 32 ✻ ✻ ✻ ✻ ✻ 5 750 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ MAX UNITS dB(6) dB dB dB dB kHz kHz –96 40 20 FS Step ns ps µs ns No Load 2.48 2.5 1 8 2.5 2.52 V µA ppm/°C V µA 2.3 External 2.5000V Ref 2.7 100 ✻ ✻ ✻ –0.3 +2.0 VIL = 0V VIH = 5V +0.8 VD + 0.3V ±10 ±10 ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA Parallel 16 bits in 2-bytes; Serial Binary Two’s Complement or Straight Binary ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VDIG High-Z State RL = 3.3kΩ, CL = 50pF RL = 3.3kΩ, CL = 10pF +0.4 +4 ±5 15 ✻ ✻ ✻ ✻ ✻ ✻ V V µA pF 83 83 ns ns Must be ≤ VANA +4.75 +4.75 VANA = VDIG = 5V, fS = 40kHz REFD HIGH PWRD and REFD HIGH –40 –55 –65 +5 +5 0.6 5.0 28 23 50 +5.25 +5.25 ✻ ✻ 35 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V mA mA mW mW µW °C °C °C °C/W °C/W TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (θJA) DIP SO ✻ Same specifications as ADS7807P, U. +85 +125 +150 75 75 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 305µV. (2) Typical rms noise at worst-case transition. (3) As measured with fixed resistors, see Figure 7b. Adjustable to zero with external potentiometer. (4) Full-scale error is the worst case of –Full-Scale or +Full-Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) This is the time delay after the ADS7807 is brought out of Power-Down mode until all internal settling occurs and the analog input is acquired to rated accuracy. A Convert command after this delay will yield accurate results. (6) All specifications in dB are referred to a full-scale input. (7) Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB. (8) Recovers to specified performance after 2 • FS input overvoltage. (9) The minimum VIH level for the DATACLK signal is 3V. ADS7807 SBAS022C www.ti.com 3 PIN DESCRIPTIONS PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME R1IN AGND1 R2IN CAP REF AGND2 SB/BTC EXT/INT D7 D6 D5 D4 D3 DGND D2 D1 D0 DATACLK SDATA TAG BYTE R/C CS BUSY PWRD REFD VANA VDIG DIGITAL I/O DESCRIPTION Analog Input. See Figure 7. Analog Sense Ground. Analog Input. See Figure 7. Reference Buffer Output. 2.2µF tantalum capacitor to ground. Reference Input/Output. 2.2µF tantalum capacitor to ground. Analog Ground Selects Straight Binary or Binary Two’s Complement for Output Data Format. External/Internal data clock select. Data Bit 7 if BYTE is HIGH. Data bit 15 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave unconnected when using serial output. Data Bit 6 if BYTE is HIGH. Data bit 14 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Data Bit 5 if BYTE is HIGH. Data bit 13 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Data Bit 4 if BYTE is HIGH. Data bit 12 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Data Bit 3 if BYTE is HIGH. Data bit 11 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Digital Ground Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH. Serial Output Synchronized to DATACLK Serial Input When Using an External Data Clock Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH) on parallel output pins. With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C enables the parallel output. Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same falling edge will start the transmission of serial data results from the previous conversion. At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs have been updated. PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active. REFD HIGH shuts down the internal reference. External reference will be required for conversions. Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors. Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA. I I O O O O O O O O I/O O I I I I O I I PIN CONFIGURATION Top View DIP, SO ANALOG INPUT RANGE ±10V 0V to 5V 0V to 4V CONNECT R1IN VIA 200Ω TO VIN AGND VIN CONNECT R2IN VIA 100Ω TO CAP VIN VIN IMPEDANCE 45.7kΩ 20.0kΩ 21.4kΩ R1IN AGND1 R2IN CAP REF AGND2 SB/BTC EXT/INT D7 1 2 3 4 5 6 7 ADS7807 8 9 28 VDIG 27 VANA 26 REFD 25 PWRD 24 BUSY 23 CS 22 R/C 21 BYTE 20 TAG 19 SDATA 18 DATACLK 17 D0 16 D1 15 D2 TABLE I. Input Range Connections. See Figure 7. D6 10 D5 11 D4 12 D3 13 DGND 14 4 ADS7807 www.ti.com SBAS022C TYPICAL CHARACTERISTICS At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified. FREQUENCY SPECTRUM (8192 Point FFT; fIN = 1kHz, 0dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 Frequency (kHz) 15 20 FREQUENCY SPECTRUM (8192 Point FFT; fIN = 15kHz, 0dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 Frequency (kHz) 15 20 Amplitude (dB) SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY (fIN = 0dB) 100 90 80 SINAD (dB) Amplitude (dB) SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY AND INPUT AMPLITUDE 100 90 80 70 SINAD (dB) 60 50 40 30 20 10 0 2 4 6 8 10 12 14 16 18 20 –60dB –20dB 0dB 70 60 50 40 30 20 10 100 1k 10k 100k 1M Input Signal Frequency (Hz) Input Signal Frequency (kHz) SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE (fIN = 1kHz, 0dB; fS = 10kHz to 40kHz) 100 AC PARAMETERS vs TEMPERATURE (fIN = 1kHz, 0dB) 110 SFDR, SINAD, and SNR (dB) 105 100 95 SNR 90 85 SINAD 80 THD –100 –105 –110 150 SFDR –80 –85 –90 –95 THD (dB) 95 10kHz SINAD (dB) 90 30kHz 20kHz 40kHz 85 80 75 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) –75 –50 –25 0 25 50 75 100 125 Temperature (°C) ADS7807 SBAS022C www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified. POWER-SUPPLY RIPPLE SENSITIVITY INL/DNL DEGRADATION PER LSB OF P-P RIPPLE Linearity Degradation (LSB/LSB) 3 2 1 0 –1 –2 –3 3 2 1 0 –1 –2 –3 1 16-Bit (LSBs) 10–1 All Codes INL 10–2 INL 10–3 16-Bit (LSBs) 10–4 DNL 10–5 101 102 103 104 105 106 107 All Codes DNL 0 8192 16384 24576 32768 40960 49152 Decimal Code 57344 65535 Power-Supply Ripple Frequency (Hz) ENDPOINT ERRORS (20V Bipolar Range) ENDPOINT ERRORS (Unipolar Ranges) mV From Ideal Percent From Ideal 0 –0.20 0.20 0 –0.20 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) +FS Error –FS Error Percent From Ideal 3 2 1 0 –1 –2 0.20 mV From Ideal BPZ Error 3 2 1 0 –1 –2 0.40 0.20 0 0.40 0.20 0 UPO Error +FS Error (4V Range) –FS Error (5V Range) Percent From Ideal Percent From Ideal –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.520 2.515 Internal Reference (V) Conversion Time (µs) CONVERSION TIME vs TEMPERATURE 19.4 2.510 2.505 2.500 2.495 2.490 2.485 2.480 –75 –50 –25 0 25 50 75 100 125 150 19.2 19 18.8 18.6 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) 6 ADS7807 www.ti.com SBAS022C BASIC OPERATION PARALLEL OUTPUT Figure 1a shows a basic circuit to operate the ADS7807 with a ±10V input range and parallel output. Taking R/C (pin 22) LOW for a minimum of 40ns (12µs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight Most Significant Bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the eight Least Significant Bits (LSBs) will be valid when BUSY rises. Data will be output in Binary Two’s Complement (BTC) format. BUSY going HIGH can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing the remaining byte to be read. All convert commands will be ignored while BUSY is LOW. The ADS7807 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section). output valid data from the previous conversion on SDATA (pin 19) synchronized to 16 clock pulses output on DATACLK (pin 18). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in BTC format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS7807 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section). STARTING A CONVERSION The combination of CS (pin 23) and R/C (pin 22) LOW for a minimum of 40ns puts the sample-and-hold of the ADS7807 in the hold state and starts conversion ‘n’. BUSY (pin 24) will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. CS and/ or R/C must go HIGH before BUSY goes HIGH, or a new conversion will be initiated without sufficient time to acquire a new signal. SERIAL OUTPUT Figure 1b shows a basic circuit to operate the ADS7807 with a ±10V input range and serial output. Taking R/C (pin 22) LOW for 40ns (12µs max) will initiate a conversion and Parallel Output 200Ω ±10V 66.5kΩ 100Ω + 1 2 3 4 2.2µF +5 6 7 ADS7807 8 9 10 11 12 13 14 21 20 28 27 26 25 BUSY 24 23 R/C 22 BYTE 40ns min Convert Pulse 0.1µF 10µF + + Serial Output 200Ω ±10V +5V 1 66.5kΩ 2 3 100Ω + 2.2µF + 28 27 26 25 24 23 22 ADS7807 21 20 19 18 0.1µF 10µF + + +5V +5V 4 5 6 7 8 +5V 2.2µF BUSY Convert Pulse R/C 2.2µF 19 18 17 16 15 NC(1) 40ns min SDATA DATACLK NC(1) 9 NC(1) 10 NC(1) 11 NC(1) 12 NC(1) 13 17 NC(1) 16 NC(1) 15 NC(1) Pin 21 B15 B14 B13 B12 B11 LOW (MSB) Pin 21 HIGH B7 B6 B5 B4 B3 B10 B9 B8 14 B2 B1 B0 (LSB) NOTE: (1) SDATA (pin 19) is always active. NOTE: (1) These pins should be left unconnected. They will be active when R/C is HIGH. FIGURE 1a. Basic ±10V Operation, both Parallel and Serial Output. FIGURE 1b. Basic ±10V Operation with Serial Output. ADS7807 SBAS022C www.ti.com 7 The ADS7807 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. Refer to Tables II and III for a summary of CS , R/C, and BUSY states, and Figures 2 through 6 for timing diagrams. CS 1 ↓ 0 0 ↓ ↓ 0 0 R/C X 0 ↓ 1 1 1 ↑ 0 BUSY X 1 1 ↑ 1 0 0 ↑ OPERATION None. Databus is in Hi-Z state. Initiates conversion ‘n’. Databus remains in Hi-Z state. Initiates conversion ‘n’. Databus enters Hi-Z state. Conversion ‘n’ completed. Valid data from conversion ‘n’ on the databus. Enables databus with valid data from conversion ‘n’. Enables databus with valid data from conversion ‘n – 1’(1). Conversion n in progress. Enables databus with valid data from conversion ‘n – 1’(1). Conversion ‘n’ in progress. New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. New convert commands ignored. Conversion ‘n’ in progress. CS and R/C are internally OR’ed and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion ‘n’, be sure the less critical input is LOW at least 10ns prior to the initiating input. If EXT/INT (pin 8) is LOW when initiating conversion ‘n’, serial data from conversion ‘n – 1’ will be output on SDATA (pin 19) following the start of conversion ‘n’. See Internal Data Clock in the Reading Data section. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. This will have no effect when using the internal data clock in the serial output mode. The parallel output and the serial output (only when using an external data clock), however, will be affected whenever R/C goes HIGH. Refer to the Reading Data section. READING DATA The ADS7807 outputs serial or parallel data in Straight Binary (SB) or Binary Two’s Complement data output format. If SB/BTC (pin 7) is HIGH, the output will be in SB format, and if LOW, the output will be in BTC format. Refer to Table IV for ideal output codes. The parallel output can be read without affecting the internal output registers; however, reading the data through the serial port will shift the internal output registers one bit per data X X 0 NOTE: (1) See Figures 2 and 3 for constraints on data valid from conversion ‘n – 1’. TABLE II. Control Functions When Using Parallel Output (DATACLK tied LOW, EXT/INT tied HIGH). CS ↓ 0 ↓ 0 ↓ ↓ 0 0 X R/C 0 ↓ 0 ↓ 1 1 ↑ 0 X BUSY 1 1 1 1 1 0 0 ↑ 0 EXT/INT 0 0 1 1 1 1 1 X X DATACLK Output Output Input Input Input Input Input X X OPERATION Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA. Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA. Initiates conversion ‘n’. Internal clock still runs conversion process. Initiates conversion ‘n’. Internal clock still runs conversion process. Conversion ‘n’ completed. Valid data from conversion ‘n’ clocked out on SDATA synchronized to external data clock. Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock. Conversion ‘n’ in progress. Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock. Conversion ‘n’ in progress. New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. New convert commands ignored. Conversion ‘n’ in progress. NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion ‘n – 1’. TABLE III. Control Functions When Using Serial Output. DESCRIPTION Full-Scale Range Least Significant Bit (LSB) ±10 305µV ANALOG INPUT 0V to 5V 76µV 0V to 4V 61µV DIGITAL OUTPUT BINARY TWO’S COMPLEMENT STRAIGHT BINARY (SB/BTC LOW) (SB/BTC HIGH) HEX BINARY CODE CODE 7FFF 0000 FFFF 8000 HEX BINARY CODE 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 CODE FFFF 8000 7FFF 0000 +Full-Scale (FS – 1LSB) Midscale One LSB Below Midscale –Full-Scale 9.999695V 0V –305µV –10V 4.999924V 2.5V 2.499924V 0V 3.999939V 2V 1.999939V 0V 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 TABLE IV. Output Codes and Ideal Input Voltages. 8 ADS7807 www.ti.com SBAS022C clock pulse. As a result, data can be read on the parallel port prior to reading the same data on the serial port, but data cannot be read through the serial port prior to reading the same data on the parallel port. PARALLEL OUTPUT (AFTER A CONVERSION) After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 24) will go HIGH. Valid data from conversion ‘n’ will be available on D7-D0 (pins 9-13 and 15-17). BUSY going high can be used to latch the data. Refer to Table V and Figures 2 and 3 for timing constraints. PARALLEL OUTPUT To use the parallel output, tie EXT/INT (pin 8) HIGH and DATACLK (pin 18) LOW. SDATA (pin 19) should be left unconnected. The parallel output will be active when R/C (pin 22) is HIGH and CS (pin 23) is LOW. Any other combination of CS and R/C will tri-state the parallel output. Valid conversion data can be read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is LOW, the 8 most significant bits will be valid with the MSB on D7. When BYTE is HIGH, the 8 least significant bits will be valid with the LSB on D0. BYTE can be toggled to read both bytes within one conversion cycle. Upon initial power up, the parallel output will contain indeterminate data. PARALLEL OUTPUT (DURING A CONVERSION) After conversion ‘n’ has been initiated, valid data from conversion ‘n – 1’ can be read and will be valid up to 12µs after the start of conversion ‘n’. Do not attempt to read data beyond 12µs after the start of conversion ‘n’ until BUSY (pin 24) goes HIGH; this may result in reading invalid data. Refer to Table V and Figures 2 and 3 for timing constraints. t1 R/C t3 BUSY t6 t7 MODE Acquire Convert t12 t11 Parallel Data Bus Previous High Byte Valid Hi-Z Previous High Byte Valid Previous Low Byte Valid t2 t9 BYTE t12 t12 t12 Not Valid t8 Acquire t4 t5 t1 t3 t6 Convert t12 t10 High Byte Valid Low Byte Valid Hi-Z t9 t12 High Byte Valid FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH). t21 R/C t1 CS t3 BUSY t21 t21 t21 t21 t21 t4 t21 BYTE t21 t21 t21 DATA BUS Hi-Z State High Byte t12 Hi-Z State t9 Low Byte t12 t9 Hi-Z State FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs. ADS7807 SBAS022C www.ti.com 9 SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t7 + t8 DESCRIPTION MIN TYP MAX UNITS 19 12 20 85 20 µs µs ns µs ns ns µs µs ns ns µs ns µs µs ns ns ns ns ns ns ns ns µs Convert Pulse Width 0.04 Data Valid Delay after R/C LOW BUSY Delay from Start of Conversion BUSY LOW BUSY Delay after End of Conversion Aperture Delay Conversion Time Acquisition Time Bus Relinquish Time 10 BUSY Delay after Data Valid 20 Previous Data Valid 12 after Start of Conversion Bus Access Time and BYTE Delay Start of Conversion to DATACLK Delay DATACLK Period Data Valid to DATACLK 20 HIGH Delay Data Valid after DATACLK 400 LOW Delay External DATACLK Period 100 External DATACLK LOW 40 External DATACLK HIGH 50 25 CS and R/C to External DATACLK Setup Time 10 R/C to CS Setup Time Valid Data after DATACLK HIGH 25 Throughput Time INTERNAL DATA CLOCK (During a Conversion) To use the internal data clock, tie EXT/INT (pin 8) LOW. The combination of R/C (pin 22) and CS (pin 23) LOW will initiate conversion ‘n’ and activate the internal data clock (typically 900kHz clock rate). The ADS7807 will output 16 bits of valid data, MSB first, from conversion ‘n-1’ on SDATA (pin 19), synchronized to 16 clock pulses output on DATACLK (pin 18). The data will be valid on both the rising and falling edges of the internal data clock. The rising edge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK will remain LOW until the next conversion is initiated, while SDATA will go to whatever logic level was input on TAG (pin 20) during the first clock pulse. Refer to Table VI and Figure 4. 19 90 40 19 20 5 83 60 19 83 1.4 1.1 75 600 EXTERNAL DATA CLOCK To use an external data clock, tie EXT/INT (pin 8) HIGH. The external data clock is not a conversion clock; it can only be used as a data clock. To enable the output mode of the ADS7807, CS (pin 23) must be LOW and R/C (pin 22) must be HIGH. DATACLK must be HIGH for 20% to 70% of the total data clock period; the clock rate can be between DC and 10MHz. Serial data from conversion ‘n’ can be output on SDATA (pin 19) after conversion ‘n’ is completed or during conversion ‘n + 1’. An obvious way to simplify control of the converter is to tie CS LOW and use R/C to initiate conversions. While this is perfectly acceptable, there is a possible problem when using an external data clock. At an indeterminate point from 12µs after the start of conversion ‘n’ until BUSY rises, the internal logic will shift the results of conversion ‘n’ into the output register. If CS is LOW, R/C HIGH, and the external clock is HIGH at this point, data will be lost. So, with CS LOW, either R/C and/or DATACLK must be LOW during this period to avoid losing valid data. 25 TABLE VI. Conversion and Data Timing. TA = –40°C to +85°C. SERIAL OUTPUT Data can be clocked out with the internal data clock or an external data clock. When using serial output, be careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these pins will come out of Hi-Z state whenever CS (pin 23) is LOW and R/C (pin 22) is HIGH. The serial output can not be tristated and is always active. Refer to the Applications Information section for specific serial interfaces. CS or R/C(1) t14 t13 1 2 t16 t15 MSB Valid SDATA (Results from previous conversion.) BUSY Bit 14 Valid Bit 13 Valid 3 t7 + t8 DATACLK 15 16 1 2 Bit 1 Valid LSB Valid MSB Valid Bit 14 Valid NOTE: (1) If controlling with CS , tie R/C LOW. Data bus pins will remain Hi-Z at all times. If controlling with R/C , tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected. FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW). 10 ADS7807 www.ti.com SBAS022C ADS7807 t17 t18 0 1 2 3 4 16 17 t19 18 t1 t22 t21 t20 t20 t3 t21 FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion. SBAS022C Bit 15 (MSB) Bit 14 Bit 1 EXTERNAL DATACLK CS R/C www.ti.com Tag 0 Tag 1 Tag 2 BUSY SDATA Bit 0 (LSB) Tag 0 Tag 1 TAG Tag 15 Tag 16 Tag 17 Tag 18 11 t17 t18 t19 EXTERNAL DATACLK t20 t22 t21 t20 R/C t1 t11 BUSY t3 CS DATA Bit 15 (MSB) Bit 0 (LSB) Tag 0 Tag 1 TAG Tag 0 Tag 1 Tag 16 Tag 17 Tag 18 FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion. EXTERNAL DATA CLOCK (After a Conversion) After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 24) will go HIGH. With CS LOW and R/C HIGH, valid data from conversion ‘n’ will be output on SDATA (pin 19) synchronized to the external data clock input on DATACLK (pin 18). The MSB will be valid on the first falling edge and the second rising edge of the external data clock. The LSB will be valid on the 16th falling edge and 17th rising edge of the data clock. TAG (pin 20) will input a bit of data for every external clock pulse. The first bit input on TAG will be valid on SDATA on the 17th falling edge and the 18th rising edge of DATACLK; the second input bit will be valid on the 18th falling edge and the 19th rising edge, etc. With a continuous data clock, TAG data will be output on SDATA until the internal output registers are updated with the results from the next conversion. Refer to Table VI and Figure 5. TAG FEATURE TAG (pin 20) inputs serial data synchronized to the external or internal data clock. When using an external data clock, the serial bit stream input on TAG will follow the LSB output on SDATA until the internal output register is updated with new conversion results. See Table V and Figures 5 and 6. The logic level input on TAG for the first rising edge of the internal data clock will be valid on SDATA after all 16 bits of valid data have been output. INPUT RANGES The ADS7807 offers three input ranges: standard ±10V and 0V-5V, and a 0V-4V range for complete, single-supply systems. See Figures 7a and 7b for the necessary circuit connections for implementing each input range and optional offset and gain adjust circuitry. Offset and full-scale error(1) specifications are tested with the fixed resistors, see Figure 7b. Adjustments for offset and gain are described in the Calibration section of this data sheet. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section). The input impedance, summarized in Table II, results from the combination of the internal resistor network (see the front page of this product data sheet) and the external resistors NOTE: (1) Full-scale error includes offset and gain errors measured at both +FS and –FS. EXTERNAL DATA CLOCK (During a Conversion) After conversion ‘n’ has been initiated, valid data from conversion ‘n – 1’ can be read and will be valid up to 12µs after the start of conversion ‘n’. Do not attempt to clock out data from 12µs after the start of conversion ‘n’ until BUSY (pin 24) rises; this will result in data loss. NOTE: For the best possible performance when using an external data clock, data should not be clocked out during a conversion. The switching noise of the asynchronous data clock can cause digital feedthrough degrading the converter’s performance. Refer to Table V and Figure 6. 12 ADS7807 www.ti.com SBAS022C used for each input range (see Figure 8). The input resistor divider network provides inherent over-voltage protection to at least ±5.5V for R2IN and ±12V for R1IN. Analog inputs above or below the expected range will yield either positive full-scale or negative full-scale digital outputs, respectively. Wrapping or folding over for analog inputs outside the nominal range will not occur. INPUT RANGE ±10V 0 to 5V 0 to 4V OFFSET ADJUST RANGE (mV) ±15 ±4 ±3 GAIN ADJUST RANGE (mV) ±60 ±30 ±30 TABLE VI. Offset and Gain Adjust Ranges for Hardware Calibration (see Figure 7a). are necessary. See the No Calibration section for more details on the external resistors. Refer to Table VIII for the range of offset and gain errors with and without the external resistors. CALIBRATION HARDWARE CALIBRATION To calibrate the offset and gain of the ADS7807 in hardware, install the resistors shown in Figure 7a. Table VI lists the hardware trim ranges relative to the input for each input range. NO CALIBRATION Figure 7b shows circuit connections. Note that the actual voltage dropped across the external resistors is at least two orders of magnitude lower than the voltage dropped across the internal resistor divider network. This should be consid- SOFTWARE CALIBRATION To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheet specifications for offset and gain, the resistors shown in Figure 7b ±10V 0V-5V 0V-4V 33.2kΩ 200Ω VIN 200Ω 1 R1IN 1 R1IN 1 200Ω VIN 2 R1IN 2 AGND1 33.2kΩ 2 AGND1 AGND1 3 100Ω 33.2kΩ 50kΩ 1MΩ 2.2µF +5V + 6 4 +5V 50kΩ 2.2µF + 5 R2IN VIN +5V 3 100Ω 4 2.2µF + 5 1MΩ 2.2µF + 6 R2IN 3 +5V 100Ω 4 50kΩ 50kΩ 2.2µF + 5 + 6 R2IN CAP CAP 50kΩ REF CAP 50kΩ AGND2 REF REF AGND2 1MΩ 2.2µF AGND2 FIGURE 7a. Circuit Diagrams (With Hardware Trim). ±10V 0V-5V 33.2kΩ 0V-4V 200Ω VIN 1 200Ω R1IN 33.2kΩ 1 R1IN 200Ω VIN 1 R1IN 2 66.5kΩ +5V 100Ω 4 2.2µF + 5 2.2µF + 6 AGND1 2 AGND1 2 AGND1 3 R2IN VIN 3 100Ω 4 2.2µF + 5 2.2µF + 6 R2IN 100Ω 3 R2IN CAP CAP 4 2.2µF + 5 2.2µF + 6 CAP REF REF REF AGND2 AGND2 AGND2 FIGURE 7b. Circuit Diagrams (Without Hardware Trim). ADS7807 SBAS022C www.ti.com 13 ered when choosing the accuracy and drift specifications of the external resistors. In most applications, 1% metal-film resistors will be sufficient. The external resistors, see Figure 7b, may not be necessary in some applications. These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Not using the external resistors will result in offset and gain errors in addition to those listed in the electrical characteristics section. Offset refers to the equivalent voltage of the digital output when converting with the input grounded. A positive gain error occurs when the equivalent output voltage of the digital output is larger than the analog input. Refer to Table VII for nominal ranges of gain and offset errors with and without the external resistors. Refer to Figure 8 for typical shifts in the transfer functions which occur when the external resistors are removed. OFFSET ERROR INPUT RANGE (V) ±10 0 to 5 0 to 4 WITH RESISTORS RANGE (mV) –10 ≤ BPZ ≤ 10 –3 ≤ UPO ≤ 3 –3 ≤ UPO ≤ 3 WITHOUT RESISTORS RANGE (mV) 0 ≤ BPZ ≤ 35 –12 ≤ UPO ≤ –3 –10.5 ≤ UPO ≤ –1.5 TYP (mV) 15 –7.5 –6 To further analyze the effects of removing any combination of the external resistors, consider Figure 9. The combination of the external and the internal resistors form a voltage divider which reduces the input signal to a 0.3125V to 2.8125V input range at the Capacitor Digital-to-Analog Converter (CDAC). The internal resistors are laser trimmed to high relative accuracy to meet full scale specifications. The actual input impedance of the internal resistor network looking into pin 1 or pin 3 however, is only accurate to ±20% due to process variations. This should be taken into account when determining the effects of removing the external resistors. REFERENCE The ADS7807 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed; REFD (pin 26) GAIN ERROR WITH RESISTORS RANGE (% FS) –0.4 ≤ G ≤ 0.4 0.15 ≤ G(1) ≤ 0.15 –0.4 ≤ G ≤ 0.4 0.15 ≤ G(1) ≤ 0.15 –0.4 ≤ G ≤ 0.4 –0.15 ≤ G(1) ≤ 0.15 WITHOUT RESISTORS RANGE (% FS) –0.3 ≤ G ≤ 0.5 –0.1 ≤ G(1) ≤ 0.2 –1.0 ≤ G ≤ 0.1 –0.55 ≤ G(1) ≤ –0.05 –1.0 ≤ G ≤ 0.1 –0.55 ≤ G(1) ≤ –0.05 TYP +0.05 +0.05 –0.2 –0.2 –0.2 –0.2 NOTE: (1) High Grade. TABLE VII. Range of Offset and Gain Errors With and Without External Resistors. (a) Bipolar (b) Unipolar Digital Output Digital Output +Full-Scale +Full-Scale Analog Input –Full-Scale Analog Input –Full-Scale Typical Transfer Functions With External Resistors Typical Transfer Functions Without External Resistors FIGURE 8. Typical Transfer Functions With and Without External Resistors. 14 ADS7807 www.ti.com SBAS022C 200Ω VIN 39.8kΩ CDAC (0.3125V to 2.8125V) 66.5kΩ +5V 100Ω 9.9kΩ 20kΩ 40kΩ +2.5V +2.5V 200Ω 39.8kΩ CDAC 33.2kΩ 100Ω VIN +2.5V 200Ω VIN 33.2kΩ 100Ω 9.9kΩ 20kΩ 40kΩ 39.8kΩ CDAC (0.3125V to 2.8125V) +2.5V 9.9kΩ 20kΩ 40kΩ (0.3125V to 2.8125V) +2.5V +2.5V FIGURE 9. Circuit Diagrams Showing External and Internal Resistors. tied HIGH will power-down the internal reference reducing the overall power consumption of the ADS7807 by approximately 5mW. The internal reference has approximately an 8ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = ±0.5% for low grade, ±0.25% for high grade). The ADS7807 also has an internal buffer for the reference voltage. Figure 10 shows characteristic impedances at the input and output of the buffer with all combinations of powerdown and reference down. ZCAP CAP (Pin 4) CDAC Buffer REF (Pin 5) ZREF Internal Reference REF REF (pin 5) is an input for an external reference or the output for the internal 2.5V reference. A 2.2µF tantalum capacitor should be connected as close as possible to the REF pin from ground. This capacitor and the output resistance of REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference, degrading the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads, as shown in Figure 10. The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full-scale range and the LSB size of the converter which can improve the SNR. PWRD 0 REFD 0 ZCAP (Ω) ZREF (Ω) 1 6k PWRD 0 REFD 1 1 100M PWRD 1 REFD 0 200 6k PWRD 1 REFD 1 200 100M FIGURE 10. Characteristic Impedances of Internal Buffer. CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2µF tantalum capacitor should be placed as close as possible to the CAP pin from ground to provide optimum switching currents for the CDAC throughout the conversion ADS7807 SBAS022C www.ti.com 15 cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor any smaller than 1µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2µF will have little affect on improving performance. See Figures 10 and 11. REFD REFD HIGH will power-down the internal 2.5V reference. All other analog circuitry, including the reference buffer, will be active. REFD should be HIGH when using an external reference to minimize power consumption and the loading effects on the external reference. See Figure 10 for the characteristic impedance of the reference buffer’s input for both REFD HIGH and LOW. The internal reference consumes approximately 5mW. 7000 6000 5000 4000 LAYOUT POWER For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the analog and digital grounds together. As noted in the electrical characteristics, the ADS7807 uses 90% of its power for the analog circuitry. The ADS7807 should be considered as an analog component. The +5V power for the A/D converter should be separate from the +5V used for the system’s digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5V source. µs 3000 2000 1000 0 0.1 1 10 100 “CAP” Pin Value (µF) FIGURE 11. Power-Down to Power-Up Time vs Capacitor Value on CAP. The output of the buffer is capable of driving up to 1mA of current to a DC load. Using an external buffer will allow the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This will cause performance degradation of the converter. REFERENCE AND POWER-DOWN The ADS7807 has analog power-down and reference power down capabilities via PWRD (pin 25) and REFD (pin 26), respectively. PWRD and REFD HIGH will power-down all analog circuitry maintaining data from the previous conversion in the internal registers, provided that the data has not already been shifted out through the serial port. Typical power consumption in this mode is 50µW. Power recovery is typically 1ms, using a 2.2µF capacitor connected to CAP. Figure 11 shows power-down to power-up recovery time relative to the capacitor value on CAP. With +5V applied to VDIG, the digital circuitry of the ADS7807 remains active at all times, regardless of PWRD and REFD states. GROUNDING Three ground pins are present on the ADS7807. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system’s digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the “system” ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. PWRD PWRD HIGH will power-down all of the analog circuitry except for the reference. Data from the previous conversion will be maintained in the internal registers and can still be read. With PWRD HIGH, a convert command yields meaningless data. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The 16 ADS7807 www.ti.com SBAS022C amount of charge injection due to the sampling FET switch on the ADS7807 is approximately 5% to 10% of the amount on similar A/D converters with the charge redistribution Digital-to-Analog Converter (DAC) CDAC architecture. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the drive capability on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application will be sufficient to drive the ADS7807. The resistive front end of the ADS7807 also provides a specified ±25V over-voltage protection. In most cases, this eliminates the need for external over-voltage protection circuitry. 173 581 176 INTERMEDIATE LATCHES The ADS7807 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversion, the tri-state outputs can be used to isolate the A/D converter from other peripherals on the same bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7807 has an internal LSB size of 38µV. Transients from fast switching signals on the parallel port, even when the A/D converter is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. 52 0 FFFDH FFFEH FFFFH 0000H 0001H 18 0002H 0 0003H FIGURE 12. Histogram of 1000 Conversions with Input Grounded. 5671 APPLICATIONS INFORMATION TRANSITION NOISE Apply a DC input to the ADS7807 and initiate 1000 conversions. The digital output of the converter will vary in output codes due to the internal noise of the ADS7807. This is true for all 16-bit SAR converters. The transition noise specification found in the electrical characteristics section is a statistical figure which represents the one sigma limit or rms value of these output codes. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal output code for the input voltage value. The ±1σ, ±2σ, and ±3σ distributions will represent 68.3%, 95.5%, and 99.7% of all codes. Multiplying TN by 6 will yield the ±3σ distribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the 5 code distribution when executing 1000 conversions. The ADS7807 has a TN of 0.8LSBs which yields 5 output codes for a ±3σ distribution. Figures 12 and 13 show 1000 and 10000 conversion histogram results. 438 18 FFFDH FFFEH FFFFH 0000H 0001H 182 0002H 0 0003H 2010 1681 176 FIGURE 13. Histogram of 10000 Conversions with Input Grounded. the number of averages. For example, averaging four conversion results will reduce the TN by 1/2 to 0.4LSBs. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging: for every decimation by 2, the signalto-noise ratio will improve 3dB. AVERAGING The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√Hz where n is ADS7807 SBAS022C www.ti.com 17 QSPI™ INTERFACING Figure 14 shows a simple interface between the ADS7807 and any QSPI equipped microcontroller. This interface assumes that the convert pulse does not originate from the microcontroller and that the ADS7807 is the only serial peripheral. Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line. When a transition from LOW to HIGH occurs on Slave Select (SS ) from BUSY (indicating the end of the current conversion), the port can be enabled. If this is not done, the microcontroller and the A/D converter may be “out-of-sync”. QSPI™ ADS7807 +5V PCS0 PCS1 SCK MISO R/C CS EXT/INT DATACLK D7 (MSB) CPOL = 0 CPHA = 0 BYTE QSPI is a registered trademark of Motorola. Convert Pulse FIGURE 15. QSPI Interface to the ADS7807. Processor Initiates Conversions. ADS7807 QSPI™ R/C PCS0/SS MOSI SCK BUSY SDATA DATACLK CS EXT/INT CPOL = 0 (Inactive State is LOW) CPHA = 1 (Data valid on falling edge) QSPI port is in slave mode. BYTE For both transfers, the DT register (delay after transfer) is used to cause a 19µs delay. The interface is also set up to wrap to the beginning of the queue. In this manner, the QSPI is a state machine which generates the appropriate timing for the ADS7807. This timing is thus locked to the crystal-based timing of the microcontroller and not interrupt driven. So, this interface is appropriate for both AC and DC measurements. For the fastest conversion rate, the baud rate should be set to 2 (4.19MHz SCK), DT set to 10, the first serial transfer set to 8 bits, the second set to 16 bits, and DSCK disabled (in the command control byte). This will allow for a 23kHz maximum conversion rate. For slower rates, DT should be increased. Do not slow SCK as this may increase the chance of affecting the conversion results or accidently initiating a second conversion during the first 8-bit transfer. In addition, CPOL and CPHA should be set to zero (SCK normally LOW and data captured on the rising edge). The command control byte for the 8-bit transfer should be set to 20H and for the 16-bit transfer to 61H. QSPI is a registered trademark of Motorola. FIGURE 14. QSPI Interface to the ADS7807. Figure 15 shows another interface between the ADS7807 and a QSPI equipped microcontroller which allows the microcontroller to give the convert pulses while also allowing multiple peripherals to be connected to the serial bus. This interface and the following discussion assume a master clock for the QSPI interface of 16.78MHz. Notice that the serial data input of the microcontroller is tied to the MSB (D7) of the ADS7807 instead of the serial output (SDATA). Using D7 instead of the serial port offers tri-state capability which allows other peripherals to be connected to the MISO pin. When communication is desired with those peripherals, PCS0 and PCS1 should be left HIGH; that will keep D7 tri-stated. In this configuration, the QSPI interface is actually set to do two different serial transfers. The first, an 8-bit transfer, causes PCS0 (R/C) and PCS1 (CS ) to go LOW, starting a conversion. The second, a 16-bit transfer, causes only PCS1 (CS ) to go LOW. This is when the valid data will be transferred. QSPI is a registered trademark of Motorola. SPI™ INTERFACE The SPI interface is generally only capable of 8-bit data transfers. For some microcontrollers with SPI interfaces, it might be possible to receive data in a similar manner as shown for the QSPI interface in Figure 14. The microcontroller will need to fetch the 8 most significant bits before the contents are overwritten by the least significant bits. A modified version of the QSPI interface shown in Figure 15 might be possible. For most microcontrollers with SPI interface, the automatic generation of the start-of-conversion pulse will be impossible and will have to be done with software. This will limit the interface to ‘DC’ applications due to the insufficient jitter performance of the convert pulse itself. SPI is a registered trademark of Motorola. 18 ADS7807 www.ti.com SBAS022C DSP56000 INTERFACING The DSP56000 serial interface has SPI compatibility mode with some enhancements. Figure 16 shows an interface between the ADS7807 and the DSP56000 which is very similar to the QSPI interface seen in Figure 14. As mentioned in the QSPI section, the DSP56000 must be programmed to enable the interface when a LOW to HIGH transition on SC1 is observed ( BUSY going HIGH at the end of conversion). The DSP56000 can also provide the convert pulse by including a monostable multi-vibrator, as seen in Figure 17. The receive and transmit sections of the interface are decoupled (asynchronous mode) and the transmit section is set to generate a word length frame sync every other transmit frame (frame rate divider set to 2). The prescale modulus should be set to 3. The monostable multi-vibrator in this circuit will provide varying pulse widths for the convert pulse. The pulse width will be determined by the external R and C values used with the multi-vibrator. The 74HCT123N data sheet shows that the pulse width is (0.7) RC. Choosing a pulse width as close to the minimum value specified in this data sheet will offer the best performance. See the Starting A Conversion section of this data sheet for details on the conversion pulse width. The maximum conversion rate for a 20.48MHz DSP56000 is exactly 40kHz. Note that this will not be the case for the ADS7806. See the ADS7806 data sheet (SBAS021B) for more information. Convert Pulse DSP56000 ADS7807 R/C SC1 SRD SCO BUSY SDATA DATACLK CS EXT/INT BYTE SYN = 0 (Asychronous) GCK = 1 (Gated clock) SCD1 = 0 (SC1 is an input) SHFD = 0 (Shift MSB first) WL1 = 1 WL0 = 0 (Word length = 16 bits) FIGURE 16. DSP56000 Interface to the ADS7807. DSP56000 +5V B1 74HCT123N R REXT1 C CEXT1 Q1 +5V SC2 CLR1 A1 ADS7807 R/C SC0 SRD DATACLK SDATA CS EXT/INT BYTE SYN = 0 (Asychronous) GCK = 1 (Gated clock) SCD2 = 1 (SC2 is an output) SHFD = 0 (Shift MSB first) WL1 = 1 WL0 = 0 (Word length = 16 bits) FIGURE 17. DSP56000 Interface to the ADS7807. Processor Initiates Conversions. ADS7807 SBAS022C www.ti.com 19 PACKAGE OPTION ADDENDUM www.ti.com 26-May-2008 PACKAGING INFORMATION Orderable Device ADS7807P ADS7807PB ADS7807PBG4 ADS7807PG4 ADS7807U ADS7807U/1K ADS7807U/1KE4 ADS7807U/1KG4 ADS7807UB ADS7807UB/1K ADS7807UB/1KE4 ADS7807UBE4 ADS7807UBG4 ADS7807UE4 (1) Status (1) NRND NRND NRND NRND NRND NRND NRND NRND NRND NRND NRND NRND NRND NRND Package Type PDIP PDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing NT NT NT NT DW DW DW DW DW DW DW DW DW DW Pins Package Eco Plan (2) Qty 28 28 28 28 28 28 28 28 28 28 28 28 28 28 13 13 13 13 20 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Cu NiPdAu Cu NiPdAu Cu NiPdAu Cu NiPdAu Cu NiPdAu Cu NiPdAu Cu NiPdAu Cu NiPdAu Cu NiPdAu Cu NiPdAu MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 20 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 20 20 20 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-May-2008 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SOIC SOIC SOIC DW DW DW 28 28 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 330.0 32.4 32.4 32.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 16.0 16.0 16.0 W Pin1 (mm) Quadrant 32.0 32.0 32.0 Q1 Q1 Q1 ADS7807U/1K ADS7807U/1KE4 ADS7807UB/1K 1000 1000 1000 11.35 11.35 11.35 18.67 18.67 18.67 3.1 3.1 3.1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device ADS7807U/1K ADS7807U/1KE4 ADS7807UB/1K Package Type SOIC SOIC SOIC Package Drawing DW DW DW Pins 28 28 28 SPQ 1000 1000 1000 Length (mm) 346.0 346.0 346.0 Width (mm) 346.0 346.0 346.0 Height (mm) 49.0 49.0 49.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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