ADS7808UBE4

ADS7808 ADS 7808 SBAS018A – JANUARY 1992 – REVISED SEPTEMBER 2003 12-Bit 10µs Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER FEATURES q q q q q q q q 100kHz SAMPLING RATE 72dB SINAD WITH 45kHz INPUT ±1/2 LSB INL AND DNL SIX SPECIFIED INPUT RANGES SERIAL OUTPUT SINGLE +5V SUPPLY OPERATION PIN-COMPATIBLE WITH 16-BIT ADS7809 USES INTERNAL OR EXTERNAL REFERENCE q 100mW MAX POWER DISSIPATION q 0.3" SO-20 q SIMPLE DSP INTERFACE DESCRIPTION The ADS7808 is a complete 12-bit sampling analog-to-digital using state-of-the-art CMOS structures. It contains a 12-bit capacitor-based SAR A/D with S/H, reference, clock, and a serial data interface. Data can be output using the internal clock, or can be synchronized to an external data clock. The ADS7808 also provides an output synchronization pulse for ease of use with standard DSP processors. The ADS7808 is specified at a 100kHz sampling rate, and specified over the full temperature range. Laser-trimmed scaling resistors provide various input ranges including ±10V and 0V to 5V, while an innovative design operates from a single +5V supply, with power dissipation under 100mW. The ADS7808 is available in a 0.3" SO-20, fully specified for operation over the industrial –40°C to +85°C range. R/C CS Power Down Successive Approximation Register and Control Logic Clock 20kΩ R1IN 10kΩ R2IN 5kΩ R3IN CAP Buffer 4kΩ REF Internal +2.5V Ref 20kΩ Comparator Serial Data Out Serial Data Data Clock BUSY CDAC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1992-2003, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) Analog Inputs: R1IN .......................................................................... ±25V R2IN .......................................................................... ±25V R3IN .......................................................................... ±25V CAP ..................................... VANA+0.3V to AGND2 –0.3V REF ....................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND2 ................................. ±0.3V VANA ...................................................................................................... 7V VDIG to VANA ....................................................................................... +0.3 VDIG ....................................................................................................... 7V Digital Inputs ............................................................. –0.3V to VDIG +0.3V Maximum Junction Temperature .................................................. +165°C Internal Power Dissipation ............................................................ 700mW Lead Temperature (soldering, 10s) .............................................. +300°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±0.9 " ±0.45 " MINIMUM SIGNAL-TOSPECIFIED (NOISE + DISTORTION) PACKAGE TEMPERATURE RATIO (DB) PACKAGE-LEAD DESIGNATOR(1) RANGE 70 " 72 " SO-20 " " " DW " " " –40°C to +85°C " " " PRODUCT ADS7808U " ADS7808UB " PACKAGE MARKING ADS7808U " ORDERING NUMBER ADS7808U ADS7808U/1K TRANSPORT MEDIA, QUANTITY Tube, 38 Tape and Reel, 1000 Tube, 38 Tape and Reel, 1000 ADS7808UB ADS7808UB " ADS7808UB/1K NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified. ADS7808U PARAMETER RESOLUTION ANALOG INPUT Voltage Ranges Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error(3,4) Full Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Unipolar Zero Error(3) CONDITIONS MIN TYP MAX 12 ±10V, 0V to 5V, etc. (See Table I) See Table I 35 ✻ ✻ ✻ ±0.9 ±0.9 Specified 0.1 ±7 Ext. 2.5000V Ref Ext. 2.5000V Ref Bipolar Ranges Bipolar Ranges 0V to 10V Range 0V to 4V Range 0V to 5V Range Unipolar Ranges 1µF Capacitor to CAP +4.75V < VD < +5.25V ±2 ±2 ±0.5 ±0.5 ±10 ±5 ±3 ±3 ✻ ✻ ±5 ✻ ✻ ±2 ✻ ✻ ✻ ✻ ✻ ±0.5 ✻ ±0.25 ±0.25 ±0.45 ±0.45 ✻ ✻ MIN ADS7808UB TYP MAX ✻ UNITS Bits pF µs µs kHz LSB(1) LSB LSB % ppm/°C % ppm/°C mV ppm/°C mV mV mV ppm/°C ms LSB 5.7 Acquire and Convert 100 8 10 Unipolar Zero Error Drift Recovery to Rated Accuracy after Power Down Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) ±2 1 fIN = fIN = fIN = fIN = 45kHz 45kHz 45kHz 45kHz 80 70 70 90 –90 73 73 250 ✻ –80 72 72 ✻ ✻ ✻ ✻ ✻ ✻ dB(5) dB dB dB kHz 2 ADS7808 www.ti.com SBAS018A ELECTRICAL CHARACTERISTICS (Cont.) At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified. ADS7808U PARAMETER SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer) External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH(8) IIL IIH DIGITAL OUTPUTS Data Format Data Coding Pipeline Delay Data Clock Internal (Output Only When Transmitting Data) External (Can Run Continually) VOL VOH Leakage Current Output Capacitance POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation: PWRD LOW PWRD HIGH TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (θJA) SO ✻ Specifications same as ADS7808U. NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures. (3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum VIH level for the DATACLK signal is 3V. CONDITIONS MIN TYP MAX MIN ADS7808UB TYP MAX UNITS FS Step 40 Sufficient to meet AC specs 2 150 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ns ns µs ns No Load 2.48 2.5 1 2.5 2.52 V µA V µA 2.3 Ext. 2.5000V Ref 2.7 100 ✻ ✻ ✻ –0.3 +2.0 VIL = 0V VIH = 5V +0.8 VD +0.3V ±10 ±10 ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA EXT/INT LOW Serial 12 bits Binary Two's Complement or Straight Binary Conversion results only available after completed conversion. Selectable for internal or external data clock 2.3 ✻ MHz EXT/INT HIGH ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VDIG High-Z State 0.1 10 +0.4 ✻ ✻ ✻ MHz V V µA pF +4 ±5 15 ✻ ✻ 15 Must be ≤ VANA +4.75 +4.75 +5 0.3 16 +5 +5.25 +5.25 ✻ ✻ ✻ ✻ ✻ ✻ ✻ VDIG = VANA = 5V, fS = 100kHz 50 100 ✻ ✻ ✻ ✻ ✻ ✻ V mA mA ✻ V mW µW °C °C °C –40 –55 –65 75 +85 +125 +150 ✻ ✻ ✻ °CW ADS7808 SBAS018A www.ti.com 3 PIN ASSIGNMENTS PIN # 1 2 3 4 5 6 7 8 9 NAME R1IN AGND1 R2IN R3IN CAP REF AGND2 SB/BTC EXT/INT DESCRIPTION Analog Input. See Table I and Figure 4 for input range connections. Analog Ground. Used internally as ground reference point. Minimal current flow. Analog Input. See Table I and Figure 4 for input range connections. Analog Input. See Table I and Figure 4 for input range connections. Reference Buffer Capacitor. 2.2µF Tantalum to ground. Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2µF Tantalum capacitor. Analog Ground. Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If LOW, data will be output in a Binary Two’s complement format. Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output on DATACLK. Digital Ground. Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK. Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW, DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions. Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the level of the TAG input when the conversion was started. Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12 DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3. Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of data from the previous conversion. Chip Select. Internally OR’ed with R/C. Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition. Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output shift register. Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF Tantalum capacitors. Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be ≤ VANA. 10 11 12 13 DGND SYNC DATACLK DATA 14 15 TAG R/C 16 17 18 19 20 CS BUSY PWRD VANA VDIG PIN CONFIGURATION ANALOG INPUT RANGE ±10V ±5V ±3.33 0V to 10V 0V to 5V 0V to 4V CONNECT R1IN VIA 200Ω TO VIN AGND VIN AGND AGND VIN CONNECT R2IN VIA 100Ω CONNECT R3IN TO TO AGND VIN VIN VIN AGND AGND CAP CAP CAP AGND VIN VIN R1IN AGND1 R2IN R3IN CAP REF AGND2 SB/BTC EXT/INT 1 2 3 4 5 6 7 8 9 ADS7808 20 VDIG 19 VANA 18 PWRD 17 BUSY 16 CS 15 R/C 14 TAG 13 DATA 12 DATACLK 11 SYNC IMPEDANCE 22.9kΩ 13.3kΩ 10.7kΩ 13.3kΩ 10.0kΩ 10.7kΩ TABLE I. Input Range Connections. See Figure 4 for complete information. DGND 10 4 ADS7808 www.ti.com SBAS018A SYMBOL t1 t2 t3 t4 t5 t6 t7 t6 + t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 DESCRIPTION Convert Pulse Width BUSY Delay BUSY LOW BUSY Delay after End of Conversion Aperture Delay Conversion Time Acquisition Time Throughput Time R/C LOW to DATACLK Delay DATACLK Period Data Valid to DATACLK HIGH Delay Data Valid after DATACLK LOW Delay External DATACLK Period External DATACLK HIGH External DATACLK LOW DATACLK HIGH Setup Time R/C to CS Setup Time SYNC Delay After DATACLK HIGH Data Valid Delay CS to Rising Edge Delay Data Available after CS LOW MIN 40 TYP MAX UNITS 4500 65 8 220 40 5.7 8 2 9 450 440 10 ns ns µs ns MODE Acquire ns µs µs µs ns ns ns ns ns ns ns t12 + 5 ns ns 35 55 ns ns ns µs CS, R/C BUSY t2 t1 t3 t4 t5 Convert t6 Acquire t7 FIGURE 1. Basic Conversion Timing. 20 100 100 20 30 20 10 15 25 25 4.5 75 125 TABLE II. Conversion and Data Timing TA = –40°C to +85°C. t8 R/C t9 DATACLK 1 2 t11 3 11 12 t10 SDATA t2 t3 BUSY MSB Valid Bit 10 Valid Bit 9 Valid Bit 1 Valid LSB Valid FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.) ADS7808 SBAS018A www.ti.com 5 SPECIFIC FUNCTION Initiate Conversion and Output Data Using Internal Clock CS 1>0 R/C 0 BUSY EXT/INT DATACLK PWRD 1 0 Output 0 SB/BTC x OPERATION Initiates conversion “n”. Data from conversion “n–1” clocked out on DATA synchronized to 12 clock pulses output on DATACLK. Initiates conversion “n”. Data from conversion “n–1” clocked out on DATA synchronized to 12 clock pulses output on DATACLK. Initiates conversion “n”. Initiates conversion “n”. Outputs a pulse on SYNC followed by data from conversion “n” clocked out synchronized to external DATACLK. Outputs a pulse on SYNC followed by data from conversion “n–1” clocked out synchronized to external DATACLK.(1) Conversion “n” in process. Outputs a pulse on SYNC followed by data from conversion “n–1” clocked out synchronized to external DATACLK .(1) Conversion “n” in process. CS or R/C must be HIGH or a new conversion will be initiated without time for acquisition. Analog circuitry powered. Conversion can proceed. Analog circuitry disabled. Data from previous conversion maintained in output registers. Serial data is output in Binary Two’s Complement format. Serial data is output in Straight Binary format. 0 1>0 1 0 Output 0 x Initiate Conversion and Output Data Using External Clock 1>0 0 1>0 0 1>0 1 1 1 1 1 1 1 Input Input Input 0 0 x x x x 1>0 1 0 1 Input 0 x 0 0>1 0 1 Input 0 x Incorrect Conversions Power Down 0 x x x 0 x x x x 0>1 x x x x x x x x x x x x x x 0 0 1 x x x x x 0 1 Selecting Output Format x NOTE: (1) See Figure 3b for constraints on previous data valid during conversion. Table III. Control Truth Table. DIGITAL OUTPUT BINARY TWO’S COMPLEMENT (SB/BTC LOW) DESCRIPTION Full-Scale Range Least Significant Bit (LSB) +Full Scale (FS – 1LSB) Midscale One LSB Below Midscale –Full Scale ±10 4.88mV ±5 2.44mV ANALOG INPUT ±3.33V 1.63mV 0V to 5V 0V to 10V 1.22mV 2.44mV 0V to 4V 0.98mV 3.99902V 2V 1.99902V 0V 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 7FF 000 FFF 800 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 FFF 800 7FF 000 HEX BINARY CODE CODE STRAIGHT BINARY (SB/BTC HIGH) HEX BINARY CODE CODE 9.99512V 4.99756V 3.33171V 0V –4.88mV –10V 0V –2.44mV –5V 0V –1.63mV –3.333333V 4.99878V 9.99756V 2.5V 5V 2.49878V 4.99756V 0V 0V Table IV. Output Codes and Ideal Input Voltages. 6 ADS7808 www.ti.com SBAS018A ADS7808 t12 t13 0 1 2 3 4 13 t14 14 t1 t15 t19 t16 t2 t16 t17 t12 t18 FIGURE 3a. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH). Read After Conversion. SBAS018A Bit 11 (MSB) Bit 10 Bit 1 Bit 0 (LSB) Tag 0 Tag 1 Tag 0 Tag 1 Tag 2 Tag 11 Tag 12 Tag 13 Tag 14 EXTERNAL DATACLK CS R/C www.ti.com BUSY SYNC DATA TAG Tag 15 7 Bit 0 (LSB) Bit 11 (MSB) t20 t12 t18 t14 t15 t12 t13 t1 EXTERNAL DATACLK t16 t2 t17 SYNC BUSY DATA FIGURE 3b. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH.) Read During Conversion (Previous Conversion Results). TAG CS R/C Tag 0 Tag 1 Tag 12 Tag 13 Tag 0 Tag 14 t19 Tag 1 Tag 15 8 ADS7808 www.ti.com SBAS018A Input Range 200Ω Without Trim With Trim (Adjust offset first at 0V, then adjust gain) 200Ω R1IN R1IN AGND1 100Ω VIN R2IN 33.2kΩ VIN 100Ω AGND1 R2IN 0V – 10V 33.2kΩ R3IN +5V 2.2µF +5V 50kΩ 576kΩ 50kΩ + 2.2µF + R3IN CAP + 2.2µF REF 2.2µF + AGND2 CAP REF AGND2 200Ω R1IN 200Ω R1IN AGND1 100Ω 33.2kΩ R2IN 33.2kΩ VIN +5V 100Ω AGND1 R2IN 0V – 5V VIN R3IN R3IN CAP + +5V CAP 50kΩ + 2.2µF 576kΩ REF 2.2µF + AGND2 2.2µF REF 2.2µF + AGND2 50kΩ 200Ω VIN R1IN 200Ω VIN R1IN AGND1 100Ω R2IN AGND1 100Ω R2IN 0V – 4V 33.2kΩ 2.2µF + R3IN R3IN +5V 33.2kΩ +5V 2.2µF 576kΩ 50kΩ 2.2µF + AGND2 + CAP CAP REF + 2.2µF AGND2 50kΩ REF FIGURE 4a. Offset/Gain Circuits for Unipolar Input Ranges. ADS7808 SBAS018A www.ti.com 9 Input Range Without Trim 200Ω VIN R1IN With Trim (Adjust offset first at 0V, then adjust gain) 200Ω VIN R1IN AGND1 100Ω R2IN 100Ω AGND1 R2IN +5V 33.2kΩ ±10V 33.2kΩ R3IN 50kΩ R3IN + 2.2µF CAP +5V 2.2µF 576kΩ 50kΩ 2.2µF + CAP REF 2.2µF + AGND2 REF + AGND2 200Ω R1IN 200Ω R1IN AGND1 100Ω 33.2kΩ VIN R2IN VIN 33.2kΩ R3IN +5V CAP + 2.2µF REF 2.2µF + 2.2µF AGND2 50kΩ 50kΩ + 2.2µF +5V 576kΩ + 100Ω AGND1 R2IN ±5V R3IN CAP REF AGND2 200Ω VIN 100Ω R1IN 200Ω VIN R1IN AGND1 100Ω AGND1 R2IN R2IN ±3.33V 33.2kΩ R3IN +5V 33.2kΩ 2.2µF +5V 50kΩ R3IN + CAP 576kΩ CAP + 2.2µF + 2.2µF REF 50kΩ + 2.2µF REF AGND2 AGND2 FIGURE 4b. Offset/Gain Circuits for Bipolar Input Ranges. 10 ADS7808 www.ti.com SBAS018A PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2007 PACKAGING INFORMATION Orderable Device ADS7808P ADS7808PB ADS7808U ADS7808U/1K ADS7808U/1KE4 ADS7808UB ADS7808UB/1KE4 ADS7808UBE4 ADS7808UBG4 ADS7808UE4 (1) Status (1) OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing N N DW DW DW DW DW DW DW DW Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 20 20 38 1000 TBD TBD Green (RoHS & no Sb/Br) Pb-Free (RoHS) Lead/Ball Finish Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Call TI Call TI Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR 1000 Green (RoHS & no Sb/Br) 38 1000 38 38 38 Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Pb-Free (RoHS) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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