ADS7816B

® ADS 781 6 OPS7816 A65 8 AD ADS7816 12-Bit High Speed Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q 200kHz SAMPLING RATE q MICRO POWER: 1.9mW at 200kHz 150µW at 12.5kHz q POWER DOWN: 3µA Max q 8-PIN MINI-DIP, SOIC, AND MSOP q DIFFERENTIAL INPUT q SERIAL INTERFACE DESCRIPTION The ADS7816 is a 12-bit, 200kHz sampling analogto-digital converter. It features low power operation with automatic power down, a synchronous serial interface, and a differential input. The reference voltage can be varied from 100mV to 5V, with a corresponding resolution from 24µV to 1.22mV. Low power, automatic power down, and small size make the ADS7816 ideal for battery operated systems or for systems where a large number of signals must be acquired simultaneously. It is also ideal for remote and/or isolated data acquisition. The ADS7816 is available in an 8-pin plastic mini-DIP, an 8-lead SOIC, or an 8-lead MSOP package. APPLICATIONS q BATTERY OPERATED SYSTEMS q REMOTE DATA ACQUISITION q ISOLATED DATA ACQUISITION SAR Control VREF DOUT +In CDAC –In S/H Amp Comparator Serial Interface DCLOCK CS/SHDN International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1355B Printed in U.S.A., March, 1997 SPECIFICATIONS At –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. ADS7816 PARAMETER ANALOG INPUT Full-Scale Input Span Absolute Input Voltage Capacitance Leakage Current SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Gain Error Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range REFERENCE INPUT Voltage Range Resistance Current Drain VIN = VIN = VIN = VIN = 5.0Vp-p 5.0Vp-p 5.0Vp-p 5.0Vp-p at at at at 1kHz 5kHz 1kHz 1kHz 0.1 CS = GND, fSAMPLE = 0Hz CS = VCC At Code 710h fSAMPLE = 12.5kHz CS = VCC 5 5 38 2.4 0.001 CMOS IIH = +5µA IIL = +5µA IOH = –250µA IOL = 250µA 3 –0.3 3.5 +VCC +0.3 0.8 0.4 Straight Binary 4.50 380 30 280 5.25 700 400 3 +85 T T T T T T T T T T T T T T T CONDITIONS MIN TYP MAX MIN T T T T T T 12 ±0.5 ±0.5 ±2 ±2 ±4 ±4 ±0.5 ±0.5 ±2 ±1 T T T ±0.5 ±0.25 ±1 ±0.75 T T ADS7816B TYP MAX T T T MIN T T T T T T ADS7816C TYP MAX T T T UNITS +In – (–In) +In –In 0 –0.2 –0.2 25 ±1 12 11 VREF VCC +0.2 +0.2 V V V pF µA Bits Bits LSB(1) LSB LSB LSB µVrms dB Clk Cycles Clk Cycles kHz dB dB dB dB 33 82 12 1.5 200 –84 –82 72 86 5 T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T 100 20 3 T T T T T T V GΩ GΩ µA µA µA DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format V V V V POWER SUPPLY REQUIREMENTS VCC Specified Performance Quiescent Current fSAMPLE = 12.5kHz(2, 3) fSAMPLE = 12.5kHz(3) Power Down CS = VCC, fSAMPLE = 0Hz TEMPERATURE RANGE Specified Performance T Specifications same as grade to the left. T T T T T V µA µA µA µA °C –40 NOTE: (1) LSB means Least Significant Bit, with VREF equal to +5V, one LSB is 1.22mV. (2) fCLK = 3.2MHz, CS = VCC for 251 clock cycles out of every 256. (3) See the Power Dissipation section for more information regarding lower sample rates. ® ADS7816 2 ABSOLUTE MAXIMUM RATINGS(1) +VCC ..................................................................................................... +6V Analog Input ........................................................... –0.3V to (+VCC + 0.3V) Logic Input ............................................................. –0.3V to (+VCC + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Reference Voltage .............................................................. +5.5V NOTE: (1) Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION VREF +In –In GND 1 2 ADS7816 3 4 8-Pin PDIP, 8-Lead SOIC, 8-Lead MSOP 8 7 6 5 +VCC DCLOCK DOUT CS/SHDN PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 NAME VREF +In –In GND CS/SHDN DOUT DCLOCK +VCC DESCRIPTION Reference Input. Non Inverting Input. Inverting Input. Connect to ground or to remote ground sense point. Ground. Chip Select when LOW, Shutdown Mode when HIGH. The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock synchronizes the serial data transfer and determines conversion speed. Power Supply. PACKAGE/ORDERING INFORMATION MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±2 ±2 ±2 ±2 ±2 ±2 ±1 ±1 ±1 MAXIMUM DIFFERENTIAL LINEARITY ERROR (LSB) ±2 ±2 ±2 ±1 ±1 ±1 ±0.75 ±0.75 ±0.75 PACKAGE DRAWING NUMBER(1) 006 182 337 006 182 337 006 182 337 PRODUCT ADS7816P ADS7816U ADS7816E ADS7816PB ADS7816UB ADS7816EB ADS7816PC ADS7816UC ADS7816EC TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C PACKAGE Plastic DIP SOIC MSOP Plastic DIP SOIC MSOP Plastic DIP SOIC MSOP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS7816 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified. CHANGE IN OFFSET vs REFERENCE VOLTAGE 5 4.5 CHANGE IN OFFSET vs TEMPERATURE 0.6 0.4 Delta from 25°C (LSB) Change in Offset (LSB) 4 3.5 3 2.5 2 1.5 1 0.5 0 1 2 3 Reference Voltage (V) 4 5 0.2 0 –0.2 –0.4 –0.6 –55 –40 –25 0 25 Temperature (°C) 70 85 CHANGE IN GAIN vs REFERENCE VOLTAGE 4 3.5 0.15 0.1 CHANGE IN GAIN vs TEMPERATURE Change in Gain (LSB) 3 2.5 2 1.5 1 0.5 0 1 2 3 Reference Voltage (V) 4 5 Delta from 25°C (LSB) 0.05 0 –0.05 –0.1 –0.15 –55 –40 –25 0 25 70 85 Temperature (°C) EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE 12 Effective Number of Bits (rms) 10 9 PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE 11.75 Peak-to-Peak Noise (LSB) 11.5 11.25 11 10.75 10.5 10.25 10 0.1 1 Reference Voltage (V) 10 8 7 6 5 4 3 2 1 0 0.1 1 Reference Voltage (V) 10 ® ADS7816 4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified. POWER SUPPLY REJECTION vs RIPPLE FREQUENCY 0 –10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 1 10 100 Ripple Frequency (kHz) 1000 10000 FREQUENCY SPECTRUM (2048 Point FFT; fIN = 9.9kHz, –0.5dB) Power Supply Rejection (dB) –20 –40 –50 –60 –70 –80 –90 Amplitude (dB) –30 0 25 50 Frequency (kHz) 75 100 SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs FREQUENCY 100 Spurious Free Dynamic Range and Signal-to-Noise Ratio (dB) Total Harmonic Distortion (dB) 0 TOTAL HARMONIC DISTORTION vs FREQUENCY –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 90 80 70 60 50 40 30 20 10 0 1 Spurious Free Dynamic Range Signal-to-Noise Ratio 10 Frequency (kHz) 100 1 10 Frequency (kHz) 100 SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY 100 SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL Signal-to-(Noise Ratio Plus Distortion) (dB) 1 10 Frequency (kHz) 100 80 70 60 50 40 30 20 10 0 –40 –35 –30 –25 –20 –15 Input Level (dB) –10 –5 0 Signal-to-(Noise + Distortion) (dB) 90 80 70 60 50 40 30 20 10 0 ® 5 ADS7816 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified. INTEGRAL LINEARITY ERROR vs CODE 1.00 DIFFERENTIAL LINEARITY ERROR vs CODE 1.00 Differential Linearity Error (LSB) Integral Linearity Error (LSB) 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 2048 Code 4095 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 2048 Code 4095 CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE 0.10 10 INPUT LEAKAGE CURRENT vs TEMPERATURE Delta from +5V Reference (LSB) 0.05 0.00 –0.05 –0.10 –0.15 –0.20 1 2 3 Reference Voltage (V) 4 5 Change in Integral Linearity (LSB) Change in Differential Linearity (LSB) Leakage Current (nA) 1 0.1 0.01 –55 –40 –25 0 25 70 85 Temperature (°C) SUPPLY CURRENT vs TEMPERATURE 450 400 fSAMPLE = 200kHz POWER DOWN SUPPLY CURRENT vs TEMPERATURE 3 2.5 Supply Current (µA) Supply Current (µA) 350 300 250 200 150 –55 –40 –25 0 25 70 85 Temperature (°C) fSAMPLE = 12.5kHz 2 1.5 1 0.5 0 –55 –40 –25 0 25 70 85 Temperature (°C) ® ADS7816 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified. REFERENCE CURRENT vs SAMPLE RATE (Code = 710h) 40 35 55 50 REFERENCE CURRENT vs TEMPERATURE (Code = 710h) Reference Current (µA) 30 25 20 15 10 5 Reference Current (µA) 45 40 35 30 25 0 0 40 80 120 160 200 Sample Rate (kHz) –55 –40 –25 0 25 70 85 Temperature (°C) CHANGE IN INTEGRAL LINEARITY and DIFFERENTIAL LINEARITY vs SAMPLE RATE 1.5 Delta from fSAMPLE = 200kHz (LSB) 1.0 Change in Integral Linearity (LSB) 0.5 0 Change in Differential Linearity (LSB) –0.5 0 100 200 300 400 500 Sample Rate (kHz) ® 7 ADS7816 THEORY OF OPERATION The ADS7816 is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6µ CMOS process. The architecture and process allow the ADS7816 to acquire and convert an analog signal at up to 200,000 conversions per second while consuming very little power. The ADS7816 requires an external reference, an external clock, and a single +5V power source. The external reference can be any voltage between 100mV and VCC. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS7816. The external clock can vary between 10kHz (625Hz throughput) and 3.2MHz (200kHz throughput). The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 150ns. The minimum clock frequency is set by the leakage on the capacitors internal to the ADS7816. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS7816 after the conversion is complete and to obtain the serial data least significant bit first. See the Digital Interface section for more information. to a 12-bit settling level within 1.5 clock cycles. When the converter goes into the hold mode or while it is in the power down mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –In input should not exceed GND ±200mV. The +In input should always remain within the range of GND –200mV to VCC +200mV. Outside of these ranges, the converter’s linearity may not meet specifications. REFERENCE INPUT The external reference sets the analog input range. The ADS7816 will operate with a reference in the range of 100mV to VCC. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. The typical performance curves of “Change in Offset vs Reference Voltage” and “Change in Gain vs Reference Voltage” provide more information. The noise inherent in the converter will also appear to increase with lower LSB size. With a 5V reference, the internal noise of the converter typically contributes only 0.16 LSB peak-to-peak of potential error to the output code. When the external reference is 100mV, the potential error contribution from the internal noise will be 50 times larger— 8 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult the typical performance curves “Effective Number of Bits vs Reference Voltage” and “Peak-to-Peak Noise vs Reference Voltage.” The effective number of bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 • ENOB +1.76. With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. The current that must be provided by the external reference will depend on the conversion result. The current is lowest at full-scale (FFFh) and is typically 25µA at a 200kHz conversion rate (25°C). For the same conditions, the current will increase as the input approaches zero, reaching 50µA at an output result of 000h. The current does not increase linearly, but depends, to some degree, on the bit pattern of the digital output. ANALOG INPUT The +In and –In input pins allow for a differential input signal. Unlike some converters of this type, the –In input is not resampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between +In and –In is captured on the internal capacitor array. The range of the –In input is limited to ±200mV. Because of this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the –In input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power down mode. Essentially, the current into the ADS7816 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) ® ADS7816 8 The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce the overall current drain from the reference. The reference current changes only slightly with temperature. See the curves, “Reference Current vs Sample Rate” and “Reference Current vs Temperature” in the Typical Performance Curves section for more information. value for one clock period. For the next 12 DCLOCK periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data but in a least significant bit first format. After the most significant bit (B11) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. DIGITAL INTERFACE SERIAL INTERFACE The ADS7816 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface as shown in Figure 1 and Table I. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 1.5 to 2.0 clock periods of the conversion cycle are used to sample the input signal. After the second falling DCLOCK edge, DOUT is enabled and will output a LOW SYMBOL tSMPL tCONV tCYC tCSD tSUCS thDO tdDO tdis ten tf tr DESCRIPTION Analog Input Sample TIme Conversion Time Throughput Rate CS Falling to DCLOCK LOW CS Falling to DCLOCK Rising DCLOCK Falling to Current DOUT Not Valid DCLOCK Falling to Next DOUT Valid CS Rising to DOUT Tri-State DCLOCK Falling to DOUT Enabled DOUT Fall Time DOUT Rise Time MIN 1.5 TYP MAX 2.0 UNITS Clk Cycles Clk Cycles kHz ns ns ns 12 200 0 30 15 85 25 50 70 60 150 50 100 100 100 ns ns ns ns ns TABLE I. Timing Specifications –40°C to +85°C. tCYC CS/SHDN tSUCS DCLOCK tCSD DOUT HI-Z NULL BIT NULL BIT POWER DOWN HI-Z B8 B7 B6 B5 B4 B3 B2 B1 B0(1) tSMPL B11 B10 B9 (MSB) B11 B10 B9 B8 tCONV tDATA Note: (1) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output LSB-First data then followed with zeroes indefinitely. tCYC CS/SHDN tSUCS DCLOCK tCSD DOUT HI-Z NULL BIT HI-Z B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 (2) POWER DOWN tSMPL B11 B10 B9 (MSB) tCONV tDATA Note: (2) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output zeroes indefinitely. tDATA: During this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes. FIGURE 1. ADS7816 Basic Timing Diagrams. ® 9 ADS7816 1.4V 3kΩ DOUT 100pF CLOAD Test Point DOUT tr tf VOH VOL Load Circuit for tdDO, tr, and tf Voltage Waveforms for DOUT Rise and Fall TImes tr, and tf Test Point DCLOCK VIL tdDO DOUT thDO Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden VOH VOL DOUT 3kΩ 100pF CLOAD VCC tdis Waveform 2, ten tdis Waveform 1 CS/SHDN VIH CS/SHDN DOUT Waveform 1(1) tdis DOUT Waveform 2(2) Voltage Waveforms for tdis 90% DCLOCK 1 2 10% DOUT ten VOL B11 NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Voltage Waveforms for ten FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I. DATA FORMAT The output data from the ADS7816 is in Straight Binary format as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS7816 to convert at up to a 200kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS7816 scales directly with conversion rate. The first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS7816 is in power down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see Figure 1). Ideally, each conversion should occur as quickly as possible, preferably, at a 3.2MHz clock rate. This way, the converter spends the longest possible time in the power down mode. This is very important as the DESCRIPTION Full Scale Range Least Significant Bit (LSB) Full Scale Midscale Midscale – 1 LSB Zero ANALOG VALUE VREF VREF/4096 VREF –1 LSB VREF/2 VREF/2 – 1 LSB 0V DIGITAL OUTPUT: STRAIGHT BINARY BINARY CODE 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 HEX CODE FFF 800 7FF 000 Table II. Ideal Input Voltages and Output Codes. ® ADS7816 10 Supply Current (µA) converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components) but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power down mode is entered. Figure 3 shows the current consumption of the ADS7816 versus sample rate. For this graph, the converter is clocked at 3.2MHz regardless of the sample rate—CS is HIGH for the remaining sample period. Figure 4 also shows current consumption versus sample rate. However, in this case, the DCLOCK period is 1/16th of the sample period—CS is HIGH for one DCLOCK cycle out of every 16. There is an important distinction between the power down mode that is entered after a conversion is complete and the full power down mode which is enabled when CS is HIGH. While both power down the analog section, the digital section is powered down only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH. See Figure 5 for more information. By lowering the reference voltage, the ADS7816 requires less current to completely charge its internal capacitors on both the analog input and the reference input. This reduction in power dissipation should be weighed carefully against the resulting increase in noise, offset, and gain error as outlined in the Reference section. The power dissipation of the ADS7816 is reduced roughly 10% when the reference voltage and input range are changed from 5V to 100mV. SHORT CYCLING 1000 100 10 TA = 25°C VCC = VREF = +5V fCLK = 3.2MHz 1 1 10 100 1000 Sample Rate (kHz) FIGURE 3. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Directly with Sample Rate. 1000 Supply Current (µA) 100 10 TA = 25°C VCC = VREF = +5V fCLK = 16 • fSAMPLE 1 Another way of saving power is to utilize the CS signal to short cycle the conversion. Because the ADS7816 places the latest data bit on the DOUT line as it is generated, the converter can easily be short cycled. This term means that the conversion can be terminated at any time. For example, if only 8-bits of the conversion result are needed, then the conversion can be terminated (by pulling CS HIGH) after the 8th bit has been clocked out. This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 12-bit conversion result may not be needed. If so, the conversion can be terminated after the first n-bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system, as they spend more time in the power down mode. 1 10 100 1000 Sample Rate (kHz) FIGURE 4. Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate. 60 50 TA = 25°C VCC = VREF = +5V fCLK = 16 • fSAMPLE Supply Current (µA) 40 30 20 10 0 1 10 100 CS LOW (GND) CS = HIGH (VCC) 1000 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7816 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At 200kHz conversion rate, the ADS7816 makes a bit decision every 312ns. That is, for each subsequent bit deci- Sample Rate (kHz) FIGURE 5. Shutdown Current is Considerably Lower with CS HIGH than when CS is LOW. ® 11 ADS7816 sion, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 12-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter’s DCLOCK signal—as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS7816 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the ADS7816 package as possible. In addition, a 1 to 10µF capacitor and a 10Ω series resistor may be used to lowpass filter a noisy supply. The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to lowpass filter the reference voltage. If the reference voltage originates from an op amp, be careful that the opamp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS7816 draws very little current from the reference on average, there are higher instantaneous current demands placed on the external reference circuitry. Also, keep in mind that the ADS7816 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50Hz or 60Hz), can be difficult to remove. The GND pin on the ADS7816 should be placed on a clean ground point. In many cases, this will be the “analog” ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. The –In input pin should be connected directly to ground. In those cases where the ADS7816 is a large distance from the signal source and/or the circuit environment contains large EMI or RFI sources, the –In input should be connected to the ground nearest the signal source. This should be done with a signal trace that is adjacent to the +In input trace. If appropriate, coax cable or twisted-pair wire can be used. APPLICATION CIRCUITS Figures 6, 7, and 8 show some typical application circuits for the ADS7816. Figure 6 uses an ADS7816 and a multiplexer to provide for a flexible data acquisition circuit. A resistor string provides for various voltages at the multiplexer input. The selected voltage is buffered and driven into VREF. As shown in Figure 6, the input range of the ADS7816 is programmable to 100mV, 200mV, 300mV, or 400mV. The 100mV range would be useful for sensors such as the thermocouple shown. Figure 7 is more complex variation of Figure 6 with increased flexibility. In this circuit, a digital signal processor designed for audio applications is put to use in running three ADS7816s and a DAC56. The DAC56 provides a variable voltage for VREF —enabling the input range of the ADS7816s to be programmed from 100mV to 3V. +5V +5V +5V R8 46kΩ R7 10Ω OPA237 0.4V R9 1kΩ 0.3V C1 10µF MUX R10 1kΩ 0.2V R11 1kΩ 0.1V R12 1kΩ D1 R1 150kΩ R3 500kΩ R2 59kΩ R6 1MΩ C3 0.1µF VREF C2 0.1µF U2 DCLOCK ADS7816 DOUT CS/SHDN U1 R5 500Ω C5 0.1µF µP 3-Wire Interface U4 A0 A1 TC1 Thermocouple TC2 TC3 C4 10µF R4 1kΩ U3 ISO Thermal Block FIGURE 6. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7816. ® ADS7816 12 DSP56004 ADS7816 + VREF 10µF 0.1µF +In –In CS DOUT DCLOCK WST SDO0 SDO1 SDO2 SCKT ADS7816 + VREF 10µF 0.1µF +In –In CS DOUT DCLOCK SCKR SDI0 SDI1 WSR Serial Audio Interface ADS7816 + VREF 10µF 0.1µF +In –In 10Ω 10Ω 10Ω CS DOUT DCLOCK SCK/SCL MISO/SDA MOSI/HA0 HREQ SS/HA2 Serial Host Interface DAC56 VOUT LE CLK DATA FIGURE 7. Flexible Data Acquisition System. +5V 5Ω to 10Ω + 1µF to 10µF ADS7816 VREF 0.1µF +In –In GND CS DOUT DCLOCK VCC + 1µF to 10µF Microcontroller FIGURE 8. Basic Data Acquisition System. The ADS7816s and the DSP56004 can all be placed into a power down mode. Or, the DSP56004 can run the ADS7816s at a full 3.2MHz clock rate while on-board software enables the ADS7816s as needed. With additional glue logic, the DSP56004 could be used to run multiple DAC56s or provide CS controls for each of the three ADS7816s. Figure 8 shows a basic data acquisition system. The ADS7816 input range is 0V to 5V, as the reference input is connected directly to the +5V supply. The 5Ω to 10Ω resistor and 1µF to 10µF capacitor filter the microcontroller “noise” on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of the noise. ® 13 ADS7816